1 |
578 |
jeremybenn |
/* Coldfire C Header File
|
2 |
|
|
* Copyright Freescale Semiconductor Inc
|
3 |
|
|
* All rights reserved.
|
4 |
|
|
*
|
5 |
|
|
* 2008/04/17 Revision: 0.2
|
6 |
|
|
*
|
7 |
|
|
* (c) Copyright UNIS, spol. s r.o. 1997-2008
|
8 |
|
|
* UNIS, spol. s r.o.
|
9 |
|
|
* Jundrovska 33
|
10 |
|
|
* 624 00 Brno
|
11 |
|
|
* Czech Republic
|
12 |
|
|
* http : www.processorexpert.com
|
13 |
|
|
* mail : info@processorexpert.com
|
14 |
|
|
*/
|
15 |
|
|
|
16 |
|
|
#ifndef __MCF52259_PAD_H__
|
17 |
|
|
#define __MCF52259_PAD_H__
|
18 |
|
|
|
19 |
|
|
|
20 |
|
|
/*********************************************************************
|
21 |
|
|
*
|
22 |
|
|
* Common GPIO
|
23 |
|
|
*
|
24 |
|
|
*********************************************************************/
|
25 |
|
|
|
26 |
|
|
/* Register read/write macros */
|
27 |
|
|
#define MCF_PAD_PSRR0 (*(vuint32*)(0x40100078))
|
28 |
|
|
#define MCF_PAD_PDSR0 (*(vuint32*)(0x4010007C))
|
29 |
|
|
#define MCF_PAD_PSRR1 (*(vuint32*)(0x40100080))
|
30 |
|
|
#define MCF_PAD_PSRR2 (*(vuint16*)(0x40100086))
|
31 |
|
|
#define MCF_PAD_PDSR1 (*(vuint32*)(0x40100088))
|
32 |
|
|
#define MCF_PAD_PDSR2 (*(vuint16*)(0x4010008E))
|
33 |
|
|
|
34 |
|
|
|
35 |
|
|
/* Bit definitions and macros for MCF_PAD_PSRR0 */
|
36 |
|
|
#define MCF_PAD_PSRR0_PSRR0 (0x1)
|
37 |
|
|
#define MCF_PAD_PSRR0_PSRR1 (0x2)
|
38 |
|
|
#define MCF_PAD_PSRR0_PSRR2 (0x4)
|
39 |
|
|
#define MCF_PAD_PSRR0_PSRR3 (0x8)
|
40 |
|
|
#define MCF_PAD_PSRR0_PSRR4 (0x10)
|
41 |
|
|
#define MCF_PAD_PSRR0_PSRR5 (0x20)
|
42 |
|
|
#define MCF_PAD_PSRR0_PSRR6 (0x40)
|
43 |
|
|
#define MCF_PAD_PSRR0_PSRR7 (0x80)
|
44 |
|
|
#define MCF_PAD_PSRR0_PSRR8 (0x100)
|
45 |
|
|
#define MCF_PAD_PSRR0_PSRR9 (0x200)
|
46 |
|
|
#define MCF_PAD_PSRR0_PSRR10 (0x400)
|
47 |
|
|
#define MCF_PAD_PSRR0_PSRR11 (0x800)
|
48 |
|
|
#define MCF_PAD_PSRR0_PSRR12 (0x1000)
|
49 |
|
|
#define MCF_PAD_PSRR0_PSRR13 (0x2000)
|
50 |
|
|
#define MCF_PAD_PSRR0_PSRR14 (0x4000)
|
51 |
|
|
#define MCF_PAD_PSRR0_PSRR15 (0x8000)
|
52 |
|
|
#define MCF_PAD_PSRR0_PSRR16 (0x10000)
|
53 |
|
|
#define MCF_PAD_PSRR0_PSRR17 (0x20000)
|
54 |
|
|
#define MCF_PAD_PSRR0_PSRR18 (0x40000)
|
55 |
|
|
#define MCF_PAD_PSRR0_PSRR19 (0x80000)
|
56 |
|
|
#define MCF_PAD_PSRR0_PSRR20 (0x100000)
|
57 |
|
|
#define MCF_PAD_PSRR0_PSRR21 (0x200000)
|
58 |
|
|
#define MCF_PAD_PSRR0_PSRR22 (0x400000)
|
59 |
|
|
#define MCF_PAD_PSRR0_PSRR23 (0x800000)
|
60 |
|
|
#define MCF_PAD_PSRR0_PSRR24 (0x1000000)
|
61 |
|
|
#define MCF_PAD_PSRR0_PSRR25 (0x2000000)
|
62 |
|
|
#define MCF_PAD_PSRR0_PSRR26 (0x4000000)
|
63 |
|
|
#define MCF_PAD_PSRR0_PSRR27 (0x8000000)
|
64 |
|
|
#define MCF_PAD_PSRR0_PSRR28 (0x10000000)
|
65 |
|
|
#define MCF_PAD_PSRR0_PSRR29 (0x20000000)
|
66 |
|
|
#define MCF_PAD_PSRR0_PSRR30 (0x40000000)
|
67 |
|
|
#define MCF_PAD_PSRR0_PSRR31 (0x80000000)
|
68 |
|
|
|
69 |
|
|
/* Bit definitions and macros for MCF_PAD_PDSR0 */
|
70 |
|
|
#define MCF_PAD_PDSR0_PDSR0 (0x1)
|
71 |
|
|
#define MCF_PAD_PDSR0_PDSR1 (0x2)
|
72 |
|
|
#define MCF_PAD_PDSR0_PDSR2 (0x4)
|
73 |
|
|
#define MCF_PAD_PDSR0_PDSR3 (0x8)
|
74 |
|
|
#define MCF_PAD_PDSR0_PDSR4 (0x10)
|
75 |
|
|
#define MCF_PAD_PDSR0_PDSR5 (0x20)
|
76 |
|
|
#define MCF_PAD_PDSR0_PDSR6 (0x40)
|
77 |
|
|
#define MCF_PAD_PDSR0_PDSR7 (0x80)
|
78 |
|
|
#define MCF_PAD_PDSR0_PDSR8 (0x100)
|
79 |
|
|
#define MCF_PAD_PDSR0_PDSR9 (0x200)
|
80 |
|
|
#define MCF_PAD_PDSR0_PDSR10 (0x400)
|
81 |
|
|
#define MCF_PAD_PDSR0_PDSR11 (0x800)
|
82 |
|
|
#define MCF_PAD_PDSR0_PDSR12 (0x1000)
|
83 |
|
|
#define MCF_PAD_PDSR0_PDSR13 (0x2000)
|
84 |
|
|
#define MCF_PAD_PDSR0_PDSR14 (0x4000)
|
85 |
|
|
#define MCF_PAD_PDSR0_PDSR15 (0x8000)
|
86 |
|
|
#define MCF_PAD_PDSR0_PDSR16 (0x10000)
|
87 |
|
|
#define MCF_PAD_PDSR0_PDSR17 (0x20000)
|
88 |
|
|
#define MCF_PAD_PDSR0_PDSR18 (0x40000)
|
89 |
|
|
#define MCF_PAD_PDSR0_PDSR19 (0x80000)
|
90 |
|
|
#define MCF_PAD_PDSR0_PDSR20 (0x100000)
|
91 |
|
|
#define MCF_PAD_PDSR0_PDSR21 (0x200000)
|
92 |
|
|
#define MCF_PAD_PDSR0_PDSR22 (0x400000)
|
93 |
|
|
#define MCF_PAD_PDSR0_PDSR23 (0x800000)
|
94 |
|
|
#define MCF_PAD_PDSR0_PDSR24 (0x1000000)
|
95 |
|
|
#define MCF_PAD_PDSR0_PDSR25 (0x2000000)
|
96 |
|
|
#define MCF_PAD_PDSR0_PDSR26 (0x4000000)
|
97 |
|
|
#define MCF_PAD_PDSR0_PDSR27 (0x8000000)
|
98 |
|
|
#define MCF_PAD_PDSR0_PDSR28 (0x10000000)
|
99 |
|
|
#define MCF_PAD_PDSR0_PDSR29 (0x20000000)
|
100 |
|
|
#define MCF_PAD_PDSR0_PDSR30 (0x40000000)
|
101 |
|
|
#define MCF_PAD_PDSR0_PDSR31 (0x80000000)
|
102 |
|
|
|
103 |
|
|
/* Bit definitions and macros for MCF_PAD_PSRR1 */
|
104 |
|
|
#define MCF_PAD_PSRR1_PSRR32 (0x1)
|
105 |
|
|
#define MCF_PAD_PSRR1_PSRR33 (0x2)
|
106 |
|
|
#define MCF_PAD_PSRR1_PSRR34 (0x4)
|
107 |
|
|
#define MCF_PAD_PSRR1_PSRR35 (0x8)
|
108 |
|
|
#define MCF_PAD_PSRR1_PSRR36 (0x10)
|
109 |
|
|
#define MCF_PAD_PSRR1_PSRR37 (0x20)
|
110 |
|
|
#define MCF_PAD_PSRR1_PSRR38 (0x40)
|
111 |
|
|
#define MCF_PAD_PSRR1_PSRR39 (0x80)
|
112 |
|
|
#define MCF_PAD_PSRR1_PSRR40 (0x100)
|
113 |
|
|
#define MCF_PAD_PSRR1_PSRR41 (0x200)
|
114 |
|
|
#define MCF_PAD_PSRR1_PSRR42 (0x400)
|
115 |
|
|
#define MCF_PAD_PSRR1_PSRR43 (0x800)
|
116 |
|
|
#define MCF_PAD_PSRR1_PSRR44 (0x1000)
|
117 |
|
|
#define MCF_PAD_PSRR1_PSRR45 (0x2000)
|
118 |
|
|
#define MCF_PAD_PSRR1_PSRR46 (0x4000)
|
119 |
|
|
#define MCF_PAD_PSRR1_PSRR47 (0x8000)
|
120 |
|
|
#define MCF_PAD_PSRR1_PSRR48 (0x10000)
|
121 |
|
|
#define MCF_PAD_PSRR1_PSRR49 (0x20000)
|
122 |
|
|
#define MCF_PAD_PSRR1_PSRR50 (0x40000)
|
123 |
|
|
#define MCF_PAD_PSRR1_PSRR51 (0x80000)
|
124 |
|
|
#define MCF_PAD_PSRR1_PSRR52 (0x100000)
|
125 |
|
|
#define MCF_PAD_PSRR1_PSRR53 (0x200000)
|
126 |
|
|
#define MCF_PAD_PSRR1_PSRR54 (0x400000)
|
127 |
|
|
#define MCF_PAD_PSRR1_PSRR55 (0x800000)
|
128 |
|
|
#define MCF_PAD_PSRR1_PSRR56 (0x1000000)
|
129 |
|
|
#define MCF_PAD_PSRR1_PSRR57 (0x2000000)
|
130 |
|
|
#define MCF_PAD_PSRR1_PSRR58 (0x4000000)
|
131 |
|
|
#define MCF_PAD_PSRR1_PSRR59 (0x8000000)
|
132 |
|
|
#define MCF_PAD_PSRR1_PSRR60 (0x10000000)
|
133 |
|
|
#define MCF_PAD_PSRR1_PSRR61 (0x20000000)
|
134 |
|
|
#define MCF_PAD_PSRR1_PSRR62 (0x40000000)
|
135 |
|
|
#define MCF_PAD_PSRR1_PSRR63 (0x80000000)
|
136 |
|
|
|
137 |
|
|
/* Bit definitions and macros for MCF_PAD_PSRR2 */
|
138 |
|
|
#define MCF_PAD_PSRR2_PSRR64 (0x1)
|
139 |
|
|
#define MCF_PAD_PSRR2_PSRR65 (0x2)
|
140 |
|
|
#define MCF_PAD_PSRR2_PSRR66 (0x4)
|
141 |
|
|
#define MCF_PAD_PSRR2_PSRR67 (0x8)
|
142 |
|
|
#define MCF_PAD_PSRR2_PSRR68 (0x10)
|
143 |
|
|
#define MCF_PAD_PSRR2_PSRR69 (0x20)
|
144 |
|
|
#define MCF_PAD_PSRR2_PSRR70 (0x40)
|
145 |
|
|
#define MCF_PAD_PSRR2_PSRR71 (0x80)
|
146 |
|
|
#define MCF_PAD_PSRR2_PSRR72 (0x100)
|
147 |
|
|
#define MCF_PAD_PSRR2_PSRR73 (0x200)
|
148 |
|
|
#define MCF_PAD_PSRR2_PSRR74 (0x400)
|
149 |
|
|
#define MCF_PAD_PSRR2_PSRR75 (0x800)
|
150 |
|
|
#define MCF_PAD_PSRR2_PSRR76 (0x1000)
|
151 |
|
|
#define MCF_PAD_PSRR2_PSRR77 (0x2000)
|
152 |
|
|
#define MCF_PAD_PSRR2_PSRR78 (0x4000)
|
153 |
|
|
#define MCF_PAD_PSRR2_PSRR79 (0x8000)
|
154 |
|
|
|
155 |
|
|
/* Bit definitions and macros for MCF_PAD_PDSR1 */
|
156 |
|
|
#define MCF_PAD_PDSR1_PDSR32 (0x1)
|
157 |
|
|
#define MCF_PAD_PDSR1_PDSR33 (0x2)
|
158 |
|
|
#define MCF_PAD_PDSR1_PDSR34 (0x4)
|
159 |
|
|
#define MCF_PAD_PDSR1_PDSR35 (0x8)
|
160 |
|
|
#define MCF_PAD_PDSR1_PDSR36 (0x10)
|
161 |
|
|
#define MCF_PAD_PDSR1_PDSR37 (0x20)
|
162 |
|
|
#define MCF_PAD_PDSR1_PDSR38 (0x40)
|
163 |
|
|
#define MCF_PAD_PDSR1_PDSR39 (0x80)
|
164 |
|
|
#define MCF_PAD_PDSR1_PDSR40 (0x100)
|
165 |
|
|
#define MCF_PAD_PDSR1_PDSR41 (0x200)
|
166 |
|
|
#define MCF_PAD_PDSR1_PDSR42 (0x400)
|
167 |
|
|
#define MCF_PAD_PDSR1_PDSR43 (0x800)
|
168 |
|
|
#define MCF_PAD_PDSR1_PDSR44 (0x1000)
|
169 |
|
|
#define MCF_PAD_PDSR1_PDSR45 (0x2000)
|
170 |
|
|
#define MCF_PAD_PDSR1_PDSR46 (0x4000)
|
171 |
|
|
#define MCF_PAD_PDSR1_PDSR47 (0x8000)
|
172 |
|
|
#define MCF_PAD_PDSR1_PDSR48 (0x10000)
|
173 |
|
|
#define MCF_PAD_PDSR1_PDSR49 (0x20000)
|
174 |
|
|
#define MCF_PAD_PDSR1_PDSR50 (0x40000)
|
175 |
|
|
#define MCF_PAD_PDSR1_PDSR51 (0x80000)
|
176 |
|
|
#define MCF_PAD_PDSR1_PDSR52 (0x100000)
|
177 |
|
|
#define MCF_PAD_PDSR1_PDSR53 (0x200000)
|
178 |
|
|
#define MCF_PAD_PDSR1_PDSR54 (0x400000)
|
179 |
|
|
#define MCF_PAD_PDSR1_PDSR55 (0x800000)
|
180 |
|
|
#define MCF_PAD_PDSR1_PDSR56 (0x1000000)
|
181 |
|
|
#define MCF_PAD_PDSR1_PDSR57 (0x2000000)
|
182 |
|
|
#define MCF_PAD_PDSR1_PDSR58 (0x4000000)
|
183 |
|
|
#define MCF_PAD_PDSR1_PDSR59 (0x8000000)
|
184 |
|
|
#define MCF_PAD_PDSR1_PDSR60 (0x10000000)
|
185 |
|
|
#define MCF_PAD_PDSR1_PDSR61 (0x20000000)
|
186 |
|
|
#define MCF_PAD_PDSR1_PDSR62 (0x40000000)
|
187 |
|
|
#define MCF_PAD_PDSR1_PDSR63 (0x80000000)
|
188 |
|
|
|
189 |
|
|
/* Bit definitions and macros for MCF_PAD_PDSR2 */
|
190 |
|
|
#define MCF_PAD_PDSR2_PDSR64 (0x1)
|
191 |
|
|
#define MCF_PAD_PDSR2_PDSR65 (0x2)
|
192 |
|
|
#define MCF_PAD_PDSR2_PDSR66 (0x4)
|
193 |
|
|
#define MCF_PAD_PDSR2_PDSR67 (0x8)
|
194 |
|
|
#define MCF_PAD_PDSR2_PDSR68 (0x10)
|
195 |
|
|
#define MCF_PAD_PDSR2_PDSR69 (0x20)
|
196 |
|
|
#define MCF_PAD_PDSR2_PDSR70 (0x40)
|
197 |
|
|
#define MCF_PAD_PDSR2_PDSR71 (0x80)
|
198 |
|
|
#define MCF_PAD_PDSR2_PDSR72 (0x100)
|
199 |
|
|
#define MCF_PAD_PDSR2_PDSR73 (0x200)
|
200 |
|
|
#define MCF_PAD_PDSR2_PDSR74 (0x400)
|
201 |
|
|
#define MCF_PAD_PDSR2_PDSR75 (0x800)
|
202 |
|
|
#define MCF_PAD_PDSR2_PDSR76 (0x1000)
|
203 |
|
|
#define MCF_PAD_PDSR2_PDSR77 (0x2000)
|
204 |
|
|
#define MCF_PAD_PDSR2_PDSR78 (0x4000)
|
205 |
|
|
#define MCF_PAD_PDSR2_PDSR79 (0x8000)
|
206 |
|
|
|
207 |
|
|
|
208 |
|
|
#endif /* __MCF52259_PAD_H__ */
|