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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [Freescale_Headers/] [MCF52259_RCM.h] - Blame information for rev 675

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Line No. Rev Author Line
1 578 jeremybenn 
/* Coldfire C Header File
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 * Copyright Freescale Semiconductor Inc
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 * All rights reserved.
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 *
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 * 2008/04/17 Revision: 0.2
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 *
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 * (c) Copyright UNIS, spol. s r.o. 1997-2008
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 * UNIS, spol. s r.o.
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 * Jundrovska 33
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 * 624 00 Brno
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 * Czech Republic
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 * http      : www.processorexpert.com
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 * mail      : info@processorexpert.com
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 */
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#ifndef __MCF52259_RCM_H__
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#define __MCF52259_RCM_H__
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/*********************************************************************
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*
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* Reset Controller Module (RCM)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_RCM_RCR                          (*(vuint8 *)(0x40110000))
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#define MCF_RCM_RSR                          (*(vuint8 *)(0x40110001))
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/* Bit definitions and macros for MCF_RCM_RCR */
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#define MCF_RCM_RCR_LVDE                     (0x1)
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#define MCF_RCM_RCR_LVDRE                    (0x4)
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#define MCF_RCM_RCR_LVDIE                    (0x8)
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#define MCF_RCM_RCR_LVDF                     (0x10)
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#define MCF_RCM_RCR_FRCRSTOUT                (0x40)
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#define MCF_RCM_RCR_SOFTRST                  (0x80)
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/* Bit definitions and macros for MCF_RCM_RSR */
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#define MCF_RCM_RSR_LOL                      (0x1)
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#define MCF_RCM_RSR_LOC                      (0x2)
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#define MCF_RCM_RSR_EXT                      (0x4)
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#define MCF_RCM_RSR_POR                      (0x8)
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#define MCF_RCM_RSR_WDR                      (0x10)
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#define MCF_RCM_RSR_SOFT                     (0x20)
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#define MCF_RCM_RSR_LVD                      (0x40)
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#endif /* __MCF52259_RCM_H__ */

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