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jeremybenn |
/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2008/02/26 Revision: 0.1
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*
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* (c) Copyright UNIS, spol. s r.o. 1997-2008
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* UNIS, spol. s r.o.
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* Jundrovska 33
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* 624 00 Brno
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* Czech Republic
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* http : www.processorexpert.com
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* mail : info@processorexpert.com
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*/
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#ifndef __MCF52259_TMR_H__
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#define __MCF52259_TMR_H__
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/*********************************************************************
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*
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* Timer Module (TMR)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_TMR0_TMR (*(vuint16*)(0x40000400))
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#define MCF_TMR0_TRR (*(vuint16*)(0x40000404))
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#define MCF_TMR0_TCR (*(vuint16*)(0x40000408))
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#define MCF_TMR0_TCN (*(vuint16*)(0x4000040C))
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#define MCF_TMR0_TER (*(vuint8 *)(0x40000411))
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#define MCF_TMR1_TMR (*(vuint16*)(0x40000440))
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#define MCF_TMR1_TRR (*(vuint16*)(0x40000444))
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#define MCF_TMR1_TCR (*(vuint16*)(0x40000448))
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#define MCF_TMR1_TCN (*(vuint16*)(0x4000044C))
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#define MCF_TMR1_TER (*(vuint8 *)(0x40000451))
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#define MCF_TMR2_TMR (*(vuint16*)(0x40000480))
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#define MCF_TMR2_TRR (*(vuint16*)(0x40000484))
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#define MCF_TMR2_TCR (*(vuint16*)(0x40000488))
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#define MCF_TMR2_TCN (*(vuint16*)(0x4000048C))
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#define MCF_TMR2_TER (*(vuint8 *)(0x40000491))
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#define MCF_TMR3_TMR (*(vuint16*)(0x400004C0))
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#define MCF_TMR3_TRR (*(vuint16*)(0x400004C4))
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#define MCF_TMR3_TCR (*(vuint16*)(0x400004C8))
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#define MCF_TMR3_TCN (*(vuint16*)(0x400004CC))
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#define MCF_TMR3_TER (*(vuint8 *)(0x400004D1))
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#define MCF_TMR_TMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40)))
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#define MCF_TMR_TRR(x) (*(vuint16*)(0x40000404 + ((x)*0x40)))
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#define MCF_TMR_TCR(x) (*(vuint16*)(0x40000408 + ((x)*0x40)))
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#define MCF_TMR_TCN(x) (*(vuint16*)(0x4000040C + ((x)*0x40)))
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#define MCF_TMR_TER(x) (*(vuint8 *)(0x40000411 + ((x)*0x40)))
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/* Bit definitions and macros for MCF_TMR_TMR */
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#define MCF_TMR_TMR_RST (0x1)
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#define MCF_TMR_TMR_CLK(x) (((x)&0x3)<<0x1)
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#define MCF_TMR_TMR_CLK_STOP (0)
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#define MCF_TMR_TMR_CLK_SYSCLK (0x2)
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#define MCF_TMR_TMR_CLK_DIV16 (0x4)
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#define MCF_TMR_TMR_CLK_TIN (0x6)
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#define MCF_TMR_TMR_FRR (0x8)
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#define MCF_TMR_TMR_ORI (0x10)
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#define MCF_TMR_TMR_OM (0x20)
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#define MCF_TMR_TMR_CE(x) (((x)&0x3)<<0x6)
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#define MCF_TMR_TMR_CE_NONE (0)
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#define MCF_TMR_TMR_CE_RISE (0x40)
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#define MCF_TMR_TMR_CE_FALL (0x80)
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#define MCF_TMR_TMR_CE_ANY (0xC0)
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#define MCF_TMR_TMR_PS(x) (((x)&0xFF)<<0x8)
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/* Bit definitions and macros for MCF_TMR_TRR */
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#define MCF_TMR_TRR_REF(x) (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_TMR_TCR */
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#define MCF_TMR_TCR_CAP(x) (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_TMR_TCN */
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#define MCF_TMR_TCN_COUNT(x) (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_TMR_TER */
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#define MCF_TMR_TER_CAP (0x1)
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#define MCF_TMR_TER_REF (0x2)
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#endif /* __MCF52259_TMR_H__ */
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