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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [cfg/] [mcf5225xEVB_PnE.cfg] - Blame information for rev 578

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Line No. Rev Author Line
1 578 jeremybenn
ResetHalt
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; Set VBR to the beginning of what will be SRAM
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; VBR is an absolute CPU register
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writecontrolreg 0x0801 0x20000000
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; Set RAMBAR1 (SRAM)
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writecontrolreg 0x0C05 0x20000021
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; Set FLASHBAR (Flash)
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writecontrolreg 0x0C04 0x00000061
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; Enable PST[3:0] signals
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writemem.b 0x40100074 0x0F

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