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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [cfg/] [mcf5225xEVB_PnE.cfg] - Blame information for rev 578

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ResetHalt
 
; Set VBR to the beginning of what will be SRAM
; VBR is an absolute CPU register
writecontrolreg 0x0801 0x20000000
 
; Set RAMBAR1 (SRAM)
writecontrolreg 0x0C05 0x20000021
 
; Set FLASHBAR (Flash)
writecontrolreg 0x0C04 0x00000061
 
; Enable PST[3:0] signals
writemem.b 0x40100074 0x0F

Line No.	Rev	Author	Line
1	578	jeremybenn	`ResetHalt`
2
3			`; Set VBR to the beginning of what will be SRAM`
4			`; VBR is an absolute CPU register`
5			`writecontrolreg 0x0801 0x20000000`
6
7			`; Set RAMBAR1 (SRAM)`
8			`writecontrolreg 0x0C05 0x20000021`
9
10			`; Set FLASHBAR (Flash)`
11			`writecontrolreg 0x0C04 0x00000061`
12
13			`; Enable PST[3:0] signals`
14			`writemem.b 0x40100074 0x0F`

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [cfg/] [mcf5225xEVB_PnE.cfg] - Blame information for rev 578