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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [cpu/] [mcf5225x_sysinit.c] - Blame information for rev 607

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Line No. Rev Author Line
1 578 jeremybenn 
/*
2 
 * File:                sysinit.c
3 
 * Purpose:             Reset configuration of the M52259EVB
4 
 *
5 
 * License:     All software covered by license agreement in -
6 
 *              docs/Freescale_Software_License.pdf
7 
 */
8 
 
9 
#include "common.h"
10 
 
11 
/********************************************************************/
12 
 
13 
void mcf5225x_init(void);
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void mcf5225x_wtm_init(void);
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void mcf5225x_pll_init(void);
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void mcf5225x_uart_init(void);
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void mcf5225x_scm_init(void);
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void mcf5225x_gpio_init(void);
19 
 
20 
/********************************************************************/
21 
void
22 
mcf5225x_init(void)
23 
{
24 
        register uint32 n;
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        register uint8 *dp, *sp;
26 
 
27 
 
28 
    /*
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     * Allow interrupts from ABORT, SW1, SW2 (IRQ[1,5,7])
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     * and USB (IRQ[2,6])
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     */
32 
 
33 
 
34 
    /* Enable IRQ signals on the port */
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    MCF_GPIO_PNQPAR = 0
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        | MCF_GPIO_PNQPAR_IRQ1_IRQ1
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        | MCF_GPIO_PNQPAR_IRQ5_IRQ5
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        | MCF_GPIO_PNQPAR_IRQ7_IRQ7;
39 
 
40 
    /* Set EPORT to look for falling edges */
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    MCF_EPORT_EPPAR = 0
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        | MCF_EPORT_EPPAR_EPPA1_FALLING
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        | MCF_EPORT_EPPAR_EPPA2_FALLING
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        | MCF_EPORT_EPPAR_EPPA5_FALLING
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        | MCF_EPORT_EPPAR_EPPA6_FALLING
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        | MCF_EPORT_EPPAR_EPPA7_FALLING;
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48 
    /* Clear any currently triggered events on the EPORT  */
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    MCF_EPORT_EPIER = 0
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        | MCF_EPORT_EPIER_EPIE1
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        | MCF_EPORT_EPIER_EPIE2
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        | MCF_EPORT_EPIER_EPIE5
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        | MCF_EPORT_EPIER_EPIE6
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        | MCF_EPORT_EPIER_EPIE7;
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56 
    /* Enable interrupts in the interrupt controller */
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    MCF_INTC0_IMRL &= ~(0
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        | MCF_INTC_IMRL_INT_MASK1
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        | MCF_INTC_IMRL_INT_MASK2
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        | MCF_INTC_IMRL_INT_MASK5
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        | MCF_INTC_IMRL_INT_MASK6
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        | MCF_INTC_IMRL_INT_MASK7
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        | MCF_INTC_IMRL_MASKALL);
64 
 
65 
 
66 
        /* Enable debug */
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        MCF_GPIO_PDDPAR = 0x0F;
68 
 
69 
        /* Set real time clock freq */
70 
 
71 
        MCF_CLOCK_RTCCR = 48000000;
72 
 
73 
        /* Copy the vector table to RAM */
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        if (__VECTOR_RAM != VECTOR_TABLE)
75 
        {
76 
                for (n = 0; n < 256; n++)
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                        __VECTOR_RAM[n] = VECTOR_TABLE[n];
78 
 
79 
                mcf5xxx_wr_vbr((uint32)__VECTOR_RAM);
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        }
81 
 
82 
        /*
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         * Move initialized data from ROM to RAM.
84 
         */
85 
        if (__DATA_ROM != __DATA_RAM)
86 
        {
87 
                dp = (uint8 *)__DATA_RAM;
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                sp = (uint8 *)__DATA_ROM;
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                n = (uint32)(__DATA_END - __DATA_RAM);
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                while (n--)
91 
                        *dp++ = *sp++;
92 
        }
93 
 
94 
        /*
95 
         * Zero uninitialized data
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         */
97 
        if (__BSS_START != __BSS_END)
98 
        {
99 
                sp = (uint8 *)__BSS_START;
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                n = (uint32)(__BSS_END - __BSS_START);
101 
                while (n--)
102 
                        *sp++ = 0;
103 
        }
104 
        mcf5225x_wtm_init();
105 
 
106 
        mcf5225x_pll_init();
107 
        mcf5225x_scm_init();
108 
        mcf5225x_uart_init();
109 
}
110 
/********************************************************************/
111 
void
112 
mcf5225x_wtm_init(void)
113 
{
114 
        /*
115 
         * Disable Software Watchdog Timer
116 
         */
117 
        MCF_SCM_CWCR = 0;
118 
}
119 
/********************************************************************/
120 
void
121 
mcf5225x_pll_init(void)
122 
{
123 
        /*Required if booting with internal relaxation oscillator & pll off, clkmod[1:0]=00 & xtal=1 */
124 
#ifndef OMIT_OCLR_CONFIGURATION
125 
        MCF_CLOCK_OCLR = 0xC0;   //turn on crystal
126 
        MCF_CLOCK_CCLR = 0x00;    //switch to crystal
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    MCF_CLOCK_OCHR = 0x00; //turn off relaxation osc
128 
#endif
129 
 
130 
        /* The PLL pre divider - 48MHz / 6 = 8MHz */
131 
        MCF_CLOCK_CCHR =0x05;
132 
 
133 
 
134 
        /* The PLL pre-divider affects this!!!
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         * Multiply 48Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz
136 
         */
137 
 
138 
        MCF_CLOCK_SYNCR &= ~(MCF_CLOCK_SYNCR_PLLEN);
139 
 
140 
    MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_CLKSRC | MCF_CLOCK_SYNCR_PLLMODE;
141 
 
142 
        //80
143 
        MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_RFD(0);
144 
        //64
145 
        //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(0);
146 
        //16
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        //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(2);
148 
        //8
149 
        //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(3);
150 
        //1
151 
        //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(6);
152 
 
153 
        MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_PLLEN;
154 
 
155 
 
156 
        while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
157 
        {
158 
        }
159 
}
160 
/********************************************************************/
161 
void
162 
mcf5225x_scm_init(void)
163 
{
164 
        /*
165 
         * Enable on-chip modules to access internal SRAM
166 
         */
167 
        MCF_SCM_RAMBAR = (0
168 
                | MCF_SCM_RAMBAR_BA(SRAM_ADDRESS)
169 
                | MCF_SCM_RAMBAR_BDE);
170 
}
171 
/********************************************************************/
172 
void
173 
mcf5225x_gpio_init(void)
174 
{
175 
        /*
176 
         * Initialize Port TA to enable Axcel control
177 
         */
178 
        MCF_GPIO_PTAPAR = 0x00;
179 
        MCF_GPIO_DDRTA  = 0x0F;
180 
        MCF_GPIO_PORTTA = 0x04;
181 
 
182 
}
183 
/********************************************************************/
184 
void
185 
mcf5225x_uart_init(void)
186 
{
187 
        /*
188 
         * Initialize all three UARTs for serial communications
189 
         */
190 
 
191 
        register uint16 ubgs;
192 
 
193 
        /*
194 
         * Set Port UA to initialize URXD0/UTXD0
195 
         */
196 
    MCF_GPIO_PUAPAR = 0
197 
        | MCF_GPIO_PUAPAR_URXD0_URXD0
198 
        | MCF_GPIO_PUAPAR_UTXD0_UTXD0;
199 
 
200 
    MCF_GPIO_PUBPAR = 0
201 
        | MCF_GPIO_PUBPAR_URXD1_URXD1
202 
        | MCF_GPIO_PUBPAR_UTXD1_UTXD1;
203 
 
204 
    MCF_GPIO_PUCPAR = 0
205 
        | MCF_GPIO_PUCPAR_URXD2_URXD2
206 
        | MCF_GPIO_PUCPAR_UTXD2_UTXD2;
207 
 
208 
        /*
209 
         * Reset Transmitter
210 
         */
211 
        MCF_UART0_UCR = MCF_UART_UCR_RESET_TX;
212 
        MCF_UART1_UCR = MCF_UART_UCR_RESET_TX;
213 
        MCF_UART2_UCR = MCF_UART_UCR_RESET_TX;
214 
 
215 
        /*
216 
         * Reset Receiver
217 
         */
218 
        MCF_UART0_UCR = MCF_UART_UCR_RESET_RX;
219 
        MCF_UART1_UCR = MCF_UART_UCR_RESET_RX;
220 
        MCF_UART2_UCR = MCF_UART_UCR_RESET_RX;
221 
 
222 
        /*
223 
         * Reset Mode Register
224 
         */
225 
        MCF_UART0_UCR = MCF_UART_UCR_RESET_MR;
226 
        MCF_UART1_UCR = MCF_UART_UCR_RESET_MR;
227 
        MCF_UART2_UCR = MCF_UART_UCR_RESET_MR;
228 
 
229 
        /*
230 
         * No parity, 8-bits per character
231 
         */
232 
        MCF_UART0_UMR1 = (0
233 
                | MCF_UART_UMR_PM_NONE
234 
                | MCF_UART_UMR_BC_8 );
235 
        MCF_UART1_UMR1 = (0
236 
                | MCF_UART_UMR_PM_NONE
237 
                | MCF_UART_UMR_BC_8 );
238 
        MCF_UART2_UMR1 = (0
239 
                | MCF_UART_UMR_PM_NONE
240 
                | MCF_UART_UMR_BC_8 );
241 
 
242 
        /*
243 
         * No echo or loopback, 1 stop bit
244 
         */
245 
        MCF_UART0_UMR2 = (0
246 
                | MCF_UART_UMR_CM_NORMAL
247 
                | MCF_UART_UMR_SB_STOP_BITS_1);
248 
        MCF_UART1_UMR2 = (0
249 
                | MCF_UART_UMR_CM_NORMAL
250 
                | MCF_UART_UMR_SB_STOP_BITS_1);
251 
        MCF_UART2_UMR2 = (0
252 
                | MCF_UART_UMR_CM_NORMAL
253 
                | MCF_UART_UMR_SB_STOP_BITS_1);
254 
 
255 
        /*
256 
         * Set Rx and Tx baud by SYSTEM CLOCK
257 
         */
258 
        MCF_UART0_UCSR = (0
259 
                | MCF_UART_UCSR_RCS_SYS_CLK
260 
                | MCF_UART_UCSR_TCS_SYS_CLK);
261 
        MCF_UART1_UCSR = (0
262 
                | MCF_UART_UCSR_RCS_SYS_CLK
263 
                | MCF_UART_UCSR_TCS_SYS_CLK);
264 
        MCF_UART2_UCSR = (0
265 
                | MCF_UART_UCSR_RCS_SYS_CLK
266 
                | MCF_UART_UCSR_TCS_SYS_CLK);
267 
 
268 
        /*
269 
         * Mask all UART interrupts
270 
         */
271 
        MCF_UART0_UIMR = 0;
272 
        MCF_UART1_UIMR = 0;
273 
        MCF_UART2_UIMR = 0;
274 
 
275 
        /*
276 
         * Calculate baud settings
277 
         */
278 
        ubgs = (uint16)((SYSTEM_CLOCK*1000000)/(UART_BAUD * 32));
279 
 
280 
        MCF_UART0_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
281 
        MCF_UART0_UBG2 = (uint8)(ubgs & 0x00FF);
282 
        MCF_UART1_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
283 
        MCF_UART1_UBG2 = (uint8)(ubgs & 0x00FF);
284 
        MCF_UART2_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
285 
        MCF_UART2_UBG2 = (uint8)(ubgs & 0x00FF);
286 
 
287 
        /*
288 
         * Enable receiver and transmitter
289 
         */
290 
        MCF_UART0_UCR = (0
291 
                | MCF_UART_UCR_TX_ENABLED
292 
                | MCF_UART_UCR_RX_ENABLED);
293 
        MCF_UART1_UCR = (0
294 
                | MCF_UART_UCR_TX_ENABLED
295 
                | MCF_UART_UCR_RX_ENABLED);
296 
        MCF_UART2_UCR = (0
297 
                | MCF_UART_UCR_TX_ENABLED
298 
                | MCF_UART_UCR_RX_ENABLED);
299 
 
300 
}
301 
/********************************************************************/

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