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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [cpu/] [mcf5225x_sysinit.c] - Blame information for rev 609

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Line No. Rev Author Line
1 578 jeremybenn
/*
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 * File:                sysinit.c
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 * Purpose:             Reset configuration of the M52259EVB
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 *
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 * License:     All software covered by license agreement in -
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 *              docs/Freescale_Software_License.pdf
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 */
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#include "common.h"
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/********************************************************************/
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void mcf5225x_init(void);
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void mcf5225x_wtm_init(void);
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void mcf5225x_pll_init(void);
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void mcf5225x_uart_init(void);
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void mcf5225x_scm_init(void);
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void mcf5225x_gpio_init(void);
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/********************************************************************/
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void
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mcf5225x_init(void)
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{
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        register uint32 n;
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        register uint8 *dp, *sp;
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    /*
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     * Allow interrupts from ABORT, SW1, SW2 (IRQ[1,5,7])
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     * and USB (IRQ[2,6])
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     */
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    /* Enable IRQ signals on the port */
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    MCF_GPIO_PNQPAR = 0
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        | MCF_GPIO_PNQPAR_IRQ1_IRQ1
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        | MCF_GPIO_PNQPAR_IRQ5_IRQ5
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        | MCF_GPIO_PNQPAR_IRQ7_IRQ7;
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    /* Set EPORT to look for falling edges */
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    MCF_EPORT_EPPAR = 0
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        | MCF_EPORT_EPPAR_EPPA1_FALLING
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        | MCF_EPORT_EPPAR_EPPA2_FALLING
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        | MCF_EPORT_EPPAR_EPPA5_FALLING
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        | MCF_EPORT_EPPAR_EPPA6_FALLING
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        | MCF_EPORT_EPPAR_EPPA7_FALLING;
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    /* Clear any currently triggered events on the EPORT  */
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    MCF_EPORT_EPIER = 0
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        | MCF_EPORT_EPIER_EPIE1
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        | MCF_EPORT_EPIER_EPIE2
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        | MCF_EPORT_EPIER_EPIE5
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        | MCF_EPORT_EPIER_EPIE6
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        | MCF_EPORT_EPIER_EPIE7;
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    /* Enable interrupts in the interrupt controller */
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    MCF_INTC0_IMRL &= ~(0
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        | MCF_INTC_IMRL_INT_MASK1
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        | MCF_INTC_IMRL_INT_MASK2
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        | MCF_INTC_IMRL_INT_MASK5
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        | MCF_INTC_IMRL_INT_MASK6
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        | MCF_INTC_IMRL_INT_MASK7
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        | MCF_INTC_IMRL_MASKALL);
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        /* Enable debug */
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        MCF_GPIO_PDDPAR = 0x0F;
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        /* Set real time clock freq */
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        MCF_CLOCK_RTCCR = 48000000;
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        /* Copy the vector table to RAM */
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        if (__VECTOR_RAM != VECTOR_TABLE)
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        {
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                for (n = 0; n < 256; n++)
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                        __VECTOR_RAM[n] = VECTOR_TABLE[n];
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                mcf5xxx_wr_vbr((uint32)__VECTOR_RAM);
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        }
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        /*
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         * Move initialized data from ROM to RAM.
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         */
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        if (__DATA_ROM != __DATA_RAM)
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        {
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                dp = (uint8 *)__DATA_RAM;
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                sp = (uint8 *)__DATA_ROM;
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                n = (uint32)(__DATA_END - __DATA_RAM);
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                while (n--)
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                        *dp++ = *sp++;
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        }
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        /*
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         * Zero uninitialized data
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         */
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        if (__BSS_START != __BSS_END)
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        {
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                sp = (uint8 *)__BSS_START;
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                n = (uint32)(__BSS_END - __BSS_START);
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                while (n--)
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                        *sp++ = 0;
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        }
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        mcf5225x_wtm_init();
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        mcf5225x_pll_init();
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        mcf5225x_scm_init();
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        mcf5225x_uart_init();
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}
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/********************************************************************/
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void
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mcf5225x_wtm_init(void)
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{
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        /*
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         * Disable Software Watchdog Timer
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         */
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        MCF_SCM_CWCR = 0;
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}
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/********************************************************************/
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void
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mcf5225x_pll_init(void)
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{
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        /*Required if booting with internal relaxation oscillator & pll off, clkmod[1:0]=00 & xtal=1 */
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#ifndef OMIT_OCLR_CONFIGURATION
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        MCF_CLOCK_OCLR = 0xC0;   //turn on crystal
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        MCF_CLOCK_CCLR = 0x00;    //switch to crystal 
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    MCF_CLOCK_OCHR = 0x00; //turn off relaxation osc
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#endif
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        /* The PLL pre divider - 48MHz / 6 = 8MHz */
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        MCF_CLOCK_CCHR =0x05;
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        /* The PLL pre-divider affects this!!!
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         * Multiply 48Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz
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         */
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        MCF_CLOCK_SYNCR &= ~(MCF_CLOCK_SYNCR_PLLEN);
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    MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_CLKSRC | MCF_CLOCK_SYNCR_PLLMODE;
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        //80
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        MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_RFD(0);
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        //64
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        //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(0);
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        //16
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        //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(2);
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        //8
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        //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(3);
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        //1
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        //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(6);
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        MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_PLLEN;
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        while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
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        {
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        }
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}
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/********************************************************************/
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void
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mcf5225x_scm_init(void)
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{
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        /*
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         * Enable on-chip modules to access internal SRAM
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         */
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        MCF_SCM_RAMBAR = (0
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                | MCF_SCM_RAMBAR_BA(SRAM_ADDRESS)
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                | MCF_SCM_RAMBAR_BDE);
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}
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/********************************************************************/
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void
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mcf5225x_gpio_init(void)
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{
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        /*
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         * Initialize Port TA to enable Axcel control
177
         */
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        MCF_GPIO_PTAPAR = 0x00;
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        MCF_GPIO_DDRTA  = 0x0F;
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        MCF_GPIO_PORTTA = 0x04;
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182
}
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/********************************************************************/
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void
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mcf5225x_uart_init(void)
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{
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        /*
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         * Initialize all three UARTs for serial communications
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         */
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        register uint16 ubgs;
192
 
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        /*
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         * Set Port UA to initialize URXD0/UTXD0
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         */
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    MCF_GPIO_PUAPAR = 0
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        | MCF_GPIO_PUAPAR_URXD0_URXD0
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        | MCF_GPIO_PUAPAR_UTXD0_UTXD0;
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    MCF_GPIO_PUBPAR = 0
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        | MCF_GPIO_PUBPAR_URXD1_URXD1
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        | MCF_GPIO_PUBPAR_UTXD1_UTXD1;
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    MCF_GPIO_PUCPAR = 0
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        | MCF_GPIO_PUCPAR_URXD2_URXD2
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        | MCF_GPIO_PUCPAR_UTXD2_UTXD2;
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        /*
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         * Reset Transmitter
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         */
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        MCF_UART0_UCR = MCF_UART_UCR_RESET_TX;
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        MCF_UART1_UCR = MCF_UART_UCR_RESET_TX;
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        MCF_UART2_UCR = MCF_UART_UCR_RESET_TX;
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        /*
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         * Reset Receiver
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         */
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        MCF_UART0_UCR = MCF_UART_UCR_RESET_RX;
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        MCF_UART1_UCR = MCF_UART_UCR_RESET_RX;
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        MCF_UART2_UCR = MCF_UART_UCR_RESET_RX;
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        /*
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         * Reset Mode Register
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         */
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        MCF_UART0_UCR = MCF_UART_UCR_RESET_MR;
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        MCF_UART1_UCR = MCF_UART_UCR_RESET_MR;
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        MCF_UART2_UCR = MCF_UART_UCR_RESET_MR;
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        /*
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         * No parity, 8-bits per character
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         */
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        MCF_UART0_UMR1 = (0
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                | MCF_UART_UMR_PM_NONE
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                | MCF_UART_UMR_BC_8 );
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        MCF_UART1_UMR1 = (0
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                | MCF_UART_UMR_PM_NONE
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                | MCF_UART_UMR_BC_8 );
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        MCF_UART2_UMR1 = (0
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                | MCF_UART_UMR_PM_NONE
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                | MCF_UART_UMR_BC_8 );
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        /*
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         * No echo or loopback, 1 stop bit
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         */
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        MCF_UART0_UMR2 = (0
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                | MCF_UART_UMR_CM_NORMAL
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                | MCF_UART_UMR_SB_STOP_BITS_1);
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        MCF_UART1_UMR2 = (0
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                | MCF_UART_UMR_CM_NORMAL
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                | MCF_UART_UMR_SB_STOP_BITS_1);
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        MCF_UART2_UMR2 = (0
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                | MCF_UART_UMR_CM_NORMAL
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                | MCF_UART_UMR_SB_STOP_BITS_1);
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255
        /*
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         * Set Rx and Tx baud by SYSTEM CLOCK
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         */
258
        MCF_UART0_UCSR = (0
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                | MCF_UART_UCSR_RCS_SYS_CLK
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                | MCF_UART_UCSR_TCS_SYS_CLK);
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        MCF_UART1_UCSR = (0
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                | MCF_UART_UCSR_RCS_SYS_CLK
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                | MCF_UART_UCSR_TCS_SYS_CLK);
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        MCF_UART2_UCSR = (0
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                | MCF_UART_UCSR_RCS_SYS_CLK
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                | MCF_UART_UCSR_TCS_SYS_CLK);
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        /*
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         * Mask all UART interrupts
270
         */
271
        MCF_UART0_UIMR = 0;
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        MCF_UART1_UIMR = 0;
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        MCF_UART2_UIMR = 0;
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        /*
276
         * Calculate baud settings
277
         */
278
        ubgs = (uint16)((SYSTEM_CLOCK*1000000)/(UART_BAUD * 32));
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280
        MCF_UART0_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
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        MCF_UART0_UBG2 = (uint8)(ubgs & 0x00FF);
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        MCF_UART1_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
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        MCF_UART1_UBG2 = (uint8)(ubgs & 0x00FF);
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        MCF_UART2_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
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        MCF_UART2_UBG2 = (uint8)(ubgs & 0x00FF);
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        /*
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         * Enable receiver and transmitter
289
         */
290
        MCF_UART0_UCR = (0
291
                | MCF_UART_UCR_TX_ENABLED
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                | MCF_UART_UCR_RX_ENABLED);
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        MCF_UART1_UCR = (0
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                | MCF_UART_UCR_TX_ENABLED
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                | MCF_UART_UCR_RX_ENABLED);
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        MCF_UART2_UCR = (0
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                | MCF_UART_UCR_TX_ENABLED
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                | MCF_UART_UCR_RX_ENABLED);
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300
}
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/********************************************************************/

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