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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [cpu/] [mcf5xxx.c] - Blame information for rev 578

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Line No. Rev Author Line
1 578 jeremybenn 
/*
2 
 * File:    mcf5xxx.c
3 
 * Purpose: Generic high-level routines for generic ColdFire processors
4 
 *
5 
 * Notes:
6 
 *
7 
 * License:     All software covered by license agreement in -
8 
 *              docs/Freescale_Software_License.pdf
9 
 */
10 
 
11 
#include "common.h"
12 
 
13 
/********************************************************************/
14 
 
15 
#define EXCEPTFMT  "%s -- PC = %#08X\n"
16 
 
17 
/********************************************************************/
18 
/*
19 
 * This is the exception handler for all defined exceptions.  Most
20 
 * exceptions do nothing, but some of the more important ones are
21 
 * handled to some extent.
22 
 *
23 
 * Called by asm_exception_handler
24 
 */
25 
void
26 
mcf5xxx_exception_handler (void *framep)
27 
{
28 
    switch (MCF5XXX_RD_SF_FORMAT(framep))
29 
    {
30 
        case 4:
31 
        case 5:
32 
        case 6:
33 
        case 7:
34 
            break;
35 
        default:
36 
            printf(EXCEPTFMT,"Illegal stack type", MCF5XXX_SF_PC(framep));
37 
            break;
38 
    }
39 
 
40 
    switch (MCF5XXX_RD_SF_VECTOR(framep))
41 
    {
42 
        case 2:
43 
            printf(EXCEPTFMT, "Access Error", MCF5XXX_SF_PC(framep));
44 
            switch (MCF5XXX_RD_SF_FS(framep))
45 
            {
46 
                case 4:
47 
                    printf("Error on instruction fetch\n");
48 
                    break;
49 
                case 8:
50 
                    printf("Error on operand write\n");
51 
                    break;
52 
                case 9:
53 
                    printf("Attempted write to write-protected space\n");
54 
                    break;
55 
                case 12:
56 
                    printf("Error on operand read\n");
57 
                    break;
58 
                default:
59 
                    printf("Reserved Fault Status Encoding\n");
60 
                    break;
61 
            }
62 
            break;
63 
        case 3:
64 
            printf(EXCEPTFMT, "Address Error", MCF5XXX_SF_PC(framep));
65 
            switch (MCF5XXX_RD_SF_FS(framep))
66 
            {
67 
                case 4:
68 
                    printf("Error on instruction fetch\n");
69 
                    break;
70 
                case 8:
71 
                    printf("Error on operand write\n");
72 
                    break;
73 
                case 9:
74 
                    printf("Attempted write to write-protected space\n");
75 
                    break;
76 
                case 12:
77 
                    printf("Error on operand read\n");
78 
                    break;
79 
                default:
80 
                    printf("Reserved Fault Status Encoding\n");
81 
                    break;
82 
            }
83 
            break;
84 
        case 4:
85 
            printf(EXCEPTFMT, "Illegal instruction", MCF5XXX_SF_PC(framep));
86 
            break;
87 
        case 8:
88 
            printf(EXCEPTFMT, "Privilege violation", MCF5XXX_SF_PC(framep));
89 
            break;
90 
        case 9:
91 
            printf(EXCEPTFMT, "Trace Exception", MCF5XXX_SF_PC(framep));
92 
            break;
93 
        case 10:
94 
            printf(EXCEPTFMT, "Unimplemented A-Line Instruction", \
95 
                MCF5XXX_SF_PC(framep));
96 
            break;
97 
        case 11:
98 
            printf(EXCEPTFMT, "Unimplemented F-Line Instruction", \
99 
                MCF5XXX_SF_PC(framep));
100 
            break;
101 
        case 12:
102 
            printf(EXCEPTFMT, "Debug Interrupt", MCF5XXX_SF_PC(framep));
103 
            break;
104 
        case 14:
105 
            printf(EXCEPTFMT, "Format Error", MCF5XXX_SF_PC(framep));
106 
            break;
107 
        case 15:
108 
            printf(EXCEPTFMT, "Unitialized Interrupt", MCF5XXX_SF_PC(framep));
109 
            break;
110 
        case 24:
111 
            printf(EXCEPTFMT, "Spurious Interrupt", MCF5XXX_SF_PC(framep));
112 
            break;
113 
        case 25:
114 
        case 26:
115 
        case 27:
116 
        case 28:
117 
        case 29:
118 
        case 30:
119 
        case 31:
120 
            printf("Autovector interrupt level %d\n",
121 
                MCF5XXX_RD_SF_VECTOR(framep) - 24);
122 
            break;
123 
        case 32:
124 
        case 33:
125 
        case 34:
126 
        case 35:
127 
        case 36:
128 
        case 37:
129 
        case 38:
130 
        case 39:
131 
        case 40:
132 
        case 41:
133 
        case 42:
134 
        case 43:
135 
        case 44:
136 
        case 45:
137 
        case 46:
138 
        case 47:
139 
            printf("TRAP #%d\n", MCF5XXX_RD_SF_VECTOR(framep) - 32);
140 
            break;
141 
        case 5:
142 
        case 6:
143 
        case 7:
144 
        case 13:
145 
        case 16:
146 
        case 17:
147 
        case 18:
148 
        case 19:
149 
        case 20:
150 
        case 21:
151 
        case 22:
152 
        case 23:
153 
        case 48:
154 
        case 49:
155 
        case 50:
156 
        case 51:
157 
        case 52:
158 
        case 53:
159 
        case 54:
160 
        case 55:
161 
        case 56:
162 
        case 57:
163 
        case 58:
164 
        case 59:
165 
        case 60:
166 
        case 61:
167 
        case 62:
168 
        case 63:
169 
            printf("Reserved: #%d\n", MCF5XXX_RD_SF_VECTOR(framep));
170 
            break;
171 
        default:
172 
            cpu_handle_interrupt(MCF5XXX_RD_SF_VECTOR(framep));
173 
            break;
174 
    }
175 
}
176 
 
177 
/********************************************************************/
178 
/*
179 
 * Interpret the reset values of D0 and D1
180 
 *
181 
 * Parameters:
182 
 *  d0  - the reset value of data register zero
183 
 *  d1  - the reset value of data register one
184 
 */
185 
void
186 
mcf5xxx_interpret_d0d1(int d0, int d1)
187 
{
188 
#ifdef DEBUG_PRINT
189 
    printf("\nColdFire Core Configuration:\n");
190 
    printf("----------------------------\n");
191 
    printf("Processor Family       %#02x\n",MCF5XXX_D0_PF(d0));
192 
    printf("ColdFire Core Version: %d\n",MCF5XXX_D0_VER(d0));
193 
    printf("Processor Revision:    %d\n",MCF5XXX_D0_REV(d1));
194 
    printf("Bus Width:             ");
195 
    switch (MCF5XXX_D1_BUSW(d1))
196 
    {
197 
        case 0:
198 
            printf("32-bit\n");
199 
            break;
200 
        default:
201 
            printf("Reserved\n");
202 
    }
203 
    printf("ISA Version:           ");
204 
    switch (MCF5XXX_D0_ISA(d0))
205 
    {
206 
        case 0:
207 
            printf("A\n");
208 
            break;
209 
        case 1:
210 
            printf("B\n");
211 
            break;
212 
        case 2:
213 
            printf("C\n");
214 
            break;
215 
        case 8:
216 
            printf("A+\n");
217 
            break;
218 
        default:
219 
            printf("Reserved\n");
220 
    }
221 
    printf("Debug Version:         ");
222 
    switch (MCF5XXX_D0_DEBUG(d0))
223 
    {
224 
        case 0:
225 
            printf("A\n");
226 
            break;
227 
        case 1:
228 
            printf("B\n");
229 
            break;
230 
        case 2:
231 
            printf("C\n");
232 
            break;
233 
        case 3:
234 
            printf("D\n");
235 
            break;
236 
        case 4:
237 
            printf("E\n");
238 
            break;
239 
        case 9:
240 
            printf("B+\n");
241 
            break;
242 
        default :
243 
            printf("Reserved\n");
244 
    }
245 
    printf("MAC:                   %s\n", MCF5XXX_D0_MAC(d0) ? "Yes" : "No");
246 
    printf("DIV:                   %s\n", MCF5XXX_D0_DIV(d0) ? "Yes" : "No");
247 
    printf("EMAC:                  %s\n", MCF5XXX_D0_EMAC(d0) ? "Yes" : "No");
248 
    printf("FPU:                   %s\n", MCF5XXX_D0_FPU(d0) ? "Yes" : "No");
249 
    printf("MMU:                   %s\n", MCF5XXX_D0_MMU(d0) ? "Yes" : "No");
250 
    printf("RAM Bank 0 Size:       ");
251 
    switch (MCF5XXX_D1_RAM0SIZ(d1))
252 
    {
253 
        case 0:
254 
        case 1:
255 
        case 2:
256 
        case 3:
257 
            printf("None\n");
258 
            break;
259 
        case 4:
260 
            printf("4KB\n");
261 
            break;
262 
        case 5:
263 
            printf("8KB\n");
264 
            break;
265 
        case 6:
266 
            printf("16KB\n");
267 
            break;
268 
        case 7:
269 
            printf("32KB\n");
270 
            break;
271 
        case 8:
272 
            printf("64KB\n");
273 
            break;
274 
        case 9:
275 
            printf("128KB\n");
276 
            break;
277 
        case 10:
278 
            printf("256KB\n");
279 
            break;
280 
        case 11:
281 
            printf("512KB\n");
282 
            break;
283 
        default:
284 
            printf("Reserved\n");
285 
    }
286 
    printf("RAM Bank 1 Size:       ");
287 
    switch (MCF5XXX_D1_RAM1SIZ(d1))
288 
    {
289 
        case 0:
290 
        case 1:
291 
        case 2:
292 
        case 3:
293 
            printf("None\n");
294 
            break;
295 
        case 4:
296 
            printf("4KB\n");
297 
            break;
298 
        case 5:
299 
            printf("8KB\n");
300 
            break;
301 
        case 6:
302 
            printf("16KB\n");
303 
            break;
304 
        case 7:
305 
            printf("32KB\n");
306 
            break;
307 
        case 8:
308 
            printf("64KB\n");
309 
            break;
310 
        case 9:
311 
            printf("128KB\n");
312 
            break;
313 
        case 10:
314 
            printf("256KB\n");
315 
            break;
316 
        case 11:
317 
            printf("512KB\n");
318 
            break;
319 
        default:
320 
            printf("Reserved\n");
321 
    }
322 
    printf("ROM Bank 0 Size:       ");
323 
    switch (MCF5XXX_D1_ROM0SIZ(d1))
324 
    {
325 
        case 0:
326 
        case 1:
327 
        case 2:
328 
        case 3:
329 
            printf("None\n");
330 
            break;
331 
        case 4:
332 
            printf("4KB\n");
333 
            break;
334 
        case 5:
335 
            printf("8KB\n");
336 
            break;
337 
        case 6:
338 
            printf("16KB\n");
339 
            break;
340 
        case 7:
341 
            printf("32KB\n");
342 
            break;
343 
        case 8:
344 
            printf("64KB\n");
345 
            break;
346 
        case 9:
347 
            printf("128KB\n");
348 
        default:
349 
            printf("Reserved\n");
350 
    }
351 
    printf("ROM Bank 1 Size:       ");
352 
    switch (MCF5XXX_D1_ROM1SIZ(d1))
353 
    {
354 
        case 0:
355 
        case 1:
356 
        case 2:
357 
        case 3:
358 
            printf("None\n");
359 
            break;
360 
        case 4:
361 
            printf("4KB\n");
362 
            break;
363 
        case 5:
364 
            printf("8KB\n");
365 
            break;
366 
        case 6:
367 
            printf("16KB\n");
368 
            break;
369 
        case 7:
370 
            printf("32KB\n");
371 
            break;
372 
        case 8:
373 
            printf("64KB\n");
374 
            break;
375 
        case 9:
376 
            printf("128KB\n");
377 
        default:
378 
            printf("Reserved\n");
379 
    }
380 
    printf("Cache Line Size:       ");
381 
    switch (MCF5XXX_D1_CL(d1))
382 
    {
383 
        case 0:
384 
            printf("16-byte\n");
385 
            break;
386 
        default:
387 
            printf("Reserved\n");
388 
    }
389 
    printf("I-Cache Associativity: ");
390 
    switch (MCF5XXX_D1_ICA(d1))
391 
    {
392 
        case 0:
393 
            printf("Four-way\n");
394 
            break;
395 
        case 1:
396 
            printf("Direct mapped\n");
397 
            break;
398 
        default:
399 
            printf("Reserved\n");
400 
    }
401 
    printf("D-Cache Associativity: ");
402 
    switch (MCF5XXX_D1_DCA(d1))
403 
    {
404 
        case 0:
405 
            printf("Four-way\n");
406 
            break;
407 
        case 1:
408 
            printf("Direct mapped\n");
409 
            break;
410 
        default:
411 
            printf("Reserved\n");
412 
    }
413 
    printf("I-Cache Size:          ");
414 
    switch (MCF5XXX_D1_ICSIZ(d1))
415 
    {
416 
        case 0:
417 
            printf("None\n");
418 
            break;
419 
        case 1:
420 
            printf("512B\n");
421 
            break;
422 
        case 2:
423 
            printf("1KB\n");
424 
            break;
425 
        case 3:
426 
            printf("2KB\n");
427 
            break;
428 
        case 4:
429 
            printf("4KB\n");
430 
            break;
431 
        case 5:
432 
            printf("8KB\n");
433 
            break;
434 
        case 6:
435 
            printf("16KB\n");
436 
            break;
437 
        case 7:
438 
            printf("32KB\n");
439 
            break;
440 
        case 8:
441 
            printf("64KB\n");
442 
            break;
443 
        default:
444 
            printf("Reserved\n");
445 
    }
446 
    printf("D-Cache Size:          ");
447 
    switch (MCF5XXX_D1_DCSIZ(d1))
448 
    {
449 
        case 0:
450 
            printf("None\n");
451 
            break;
452 
        case 1:
453 
            printf("512B\n");
454 
            break;
455 
        case 2:
456 
            printf("1KB\n");
457 
            break;
458 
        case 3:
459 
            printf("2KB\n");
460 
            break;
461 
        case 4:
462 
            printf("4KB\n");
463 
            break;
464 
        case 5:
465 
            printf("8KB\n");
466 
            break;
467 
        case 6:
468 
            printf("16KB\n");
469 
            break;
470 
        case 7:
471 
            printf("32KB\n");
472 
            break;
473 
        case 8:
474 
            printf("64KB\n");
475 
            break;
476 
        default:
477 
            printf("Reserved\n");
478 
    }
479 
    printf("\n");
480 
#else
481 
        /* Remove compiler warnings. */
482 
        ( void ) d0;
483 
        ( void ) d1;
484 
#endif
485 
}
486 
 
487 
/********************************************************************/
488 
void
489 
mcf5xxx_irq_enable (void)
490 
{
491 
    asm_set_ipl(0);
492 
}
493 
/********************************************************************/
494 
void
495 
mcf5xxx_irq_disable (void)
496 
{
497 
    asm_set_ipl(7);
498 
}
499 
/********************************************************************/
500 
/*
501 
 * Write new interrupt vector handler into the vector table
502 
 * Return previous handler address
503 
 */
504 
 
505 
ADDRESS
506 
mcf5xxx_set_handler (int vector, ADDRESS new_handler)
507 
{
508 
    ADDRESS old_handler;
509 
    extern uint32 __VECTOR_RAM[];
510 
 
511 
    old_handler = (ADDRESS) __VECTOR_RAM[vector];
512 
    __VECTOR_RAM[vector] = (uint32)new_handler;
513 
    return old_handler;
514 
}
515 
 
516 
/********************************************************************/

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