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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [cpu/] [mcf5xxx_lo.s] - Blame information for rev 578

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Line No. Rev Author Line
1 578 jeremybenn 
/*
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 * File:    mcf5xxx.s
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 * Purpose: Lowest level routines for all ColdFire processors.
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 *
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 * Notes:
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 *
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 * License:     All software covered by license agreement in -
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 *              docs/Freescale_Software_License.pdf
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 */
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#define mcf5xxx_exception_handler   _mcf5xxx_exception_handler
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    .extern mcf5xxx_exception_handler
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    .global asm_exception_handler
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    .global _asm_exception_handler
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    .global asm_set_ipl
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    .global _asm_set_ipl
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    .global mcf5xxx_exe_wdebug
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    .global _mcf5xxx_exe_wdebug
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   .global mcf5xxx_move_line   //added by Mac
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   .global _mcf5xxx_move_line   //added by Mac
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    .global mcf5xxx_wr_cacr
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    .global _mcf5xxx_wr_cacr
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    .global mcf5xxx_wr_asid
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    .global _mcf5xxx_wr_asid
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    .global mcf5xxx_wr_acr0
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    .global _mcf5xxx_wr_acr0
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    .global mcf5xxx_wr_acr1
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    .global _mcf5xxx_wr_acr1
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    .global mcf5xxx_wr_acr2
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    .global _mcf5xxx_wr_acr2
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    .global mcf5xxx_wr_acr3
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    .global _mcf5xxx_wr_acr3
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    .global mcf5xxx_wr_mmubar
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    .global _mcf5xxx_wr_mmubar
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    .global mcf5xxx_wr_other_a7
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    .global _mcf5xxx_wr_other_a7
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    .global mcf5xxx_wr_vbr
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    .global _mcf5xxx_wr_vbr
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    .global mcf5xxx_wr_macsr
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    .global _mcf5xxx_wr_macsr
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    .global mcf5xxx_wr_mask
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    .global _mcf5xxx_wr_mask
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    .global mcf5xxx_wr_acc0
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    .global _mcf5xxx_wr_acc0
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    .global mcf5xxx_wr_accext01
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    .global _mcf5xxx_wr_accext01
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    .global mcf5xxx_wr_accext23
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    .global _mcf5xxx_wr_accext23
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    .global mcf5xxx_wr_acc1
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    .global _mcf5xxx_wr_acc1
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    .global mcf5xxx_wr_acc2
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    .global _mcf5xxx_wr_acc2
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    .global mcf5xxx_wr_acc3
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    .global _mcf5xxx_wr_acc3
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    .global mcf5xxx_wr_sr
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    .global _mcf5xxx_wr_sr
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    .global mcf5xxx_wr_pc
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    .global _mcf5xxx_wr_pc
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    .global mcf5xxx_wr_rombar0
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    .global _mcf5xxx_wr_rombar0
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    .global mcf5xxx_wr_rombar1
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    .global _mcf5xxx_wr_rombar1
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    .global mcf5xxx_wr_rambar0
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    .global _mcf5xxx_wr_rambar0
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    .global mcf5xxx_wr_rambar1
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    .global _mcf5xxx_wr_rambar1
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    .global mcf5xxx_wr_mpcr
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    .global _mcf5xxx_wr_mpcr
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    .global mcf5xxx_wr_secmbar
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    .global _mcf5xxx_wr_secmbar
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    .global mcf5xxx_wr_mbar
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    .global _mcf5xxx_wr_mbar
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    .text
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78 
/********************************************************************
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 * This routine is the lowest-level exception handler.
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 */
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asm_exception_handler:
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_asm_exception_handler:
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    lea     -16(SP),SP
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    movem.l D0-D1/A0-A1,(SP)
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    lea     16(SP),A1
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    move.l  A1,-(SP)
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    jsr     mcf5xxx_exception_handler
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    lea     4(SP),SP
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    movem.l (SP),D0-D1/A0-A1
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    lea     16(SP),SP
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    rte
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94 
/********************************************************************/
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/*
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 * This routines changes the IPL to the value passed into the routine.
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 * It also returns the old IPL value back.
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 * Calling convention from C:
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 *   old_ipl = asm_set_ipl(new_ipl);
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 * For the Diab Data C compiler, it passes return value thru D0.
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 * Note that only the least significant three bits of the passed
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 * value are used.
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 */
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asm_set_ipl:
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_asm_set_ipl:
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    link    A6,#-8
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    movem.l D6-D7,(SP)
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    move.w  SR,D7       /* current sr    */
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    move.l  D7,D0       /* prepare return value  */
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    andi.l  #0x0700,D0  /* mask out IPL  */
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    lsr.l   #8,D0       /* IPL   */
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    move.l  8(A6),D6    /* get argument  */
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    andi.l  #0x07,D6        /* least significant three bits  */
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    lsl.l   #8,D6       /* move over to make mask    */
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    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
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    or.l    D6,D7           /* place new IPL in sr   */
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    move.w  D7,SR
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124 
    movem.l (SP),D6-D7
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    lea     8(SP),SP
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    unlk    A6
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    rts
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129 
/********************************************************************/
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/*
131 
 * These routines execute special ColdFire instructions
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 */
133 
 
134 
mcf5xxx_exe_wdebug:
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_mcf5xxx_exe_wdebug:
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    move.l   4(sp),a0
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    wdebug.l (a0)
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    rts
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140 
 mcf5xxx_move_line:
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_mcf5xxx_move_line:
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    lea.l   -24(sp),sp
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    movem.l d0-d3/a0-a1,(sp)
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    movea.l 28(sp),a0       /* source in a0 */
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    movea.l 32(sp),a1       /* destination in a1 */
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    movem.l (a0),d0-d3      /* move line from source */
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    movem.l d0-d3,(a1)      /* move line to destination */
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    movem.l (sp),d0-d3/a0-a1
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    lea.l   24(sp),sp
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    rts
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152 
 
153 
/********************************************************************/
154 
/*
155 
 * These routines write to the special purpose registers in the ColdFire
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 * core.  Since these registers are write-only in the supervisor model,
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 * no corresponding read routines exist.
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 */
159 
 
160 
mcf5xxx_wr_sr:
161 
_mcf5xxx_wr_sr:
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    move.l  4(SP),D0
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    move.w  D0,SR
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    rts
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166 
mcf5xxx_wr_cacr:
167 
_mcf5xxx_wr_cacr:
168 
    move.l  4(SP),D0
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    .long   0x4e7b0002      /* movec d0,cacr */
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    nop
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    rts
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173 
mcf5xxx_wr_asid:
174 
_mcf5xxx_wr_asid:
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    move.l  4(SP),D0
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    .long   0x4e7b0003      /* movec d0,asid */
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    nop
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    rts
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180 
mcf5xxx_wr_acr0:
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_mcf5xxx_wr_acr0:
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    move.l  4(SP),D0
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    .long   0x4e7b0004      /* movec d0,ACR0 */
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    nop
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    rts
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187 
mcf5xxx_wr_acr1:
188 
_mcf5xxx_wr_acr1:
189 
    move.l  4(SP),D0
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    .long   0x4e7b0005      /* movec d0,ACR1 */
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    nop
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    rts
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194 
mcf5xxx_wr_acr2:
195 
_mcf5xxx_wr_acr2:
196 
    move.l  4(SP),D0
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    .long   0x4e7b0006      /* movec d0,ACR2 */
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    nop
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    rts
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201 
mcf5xxx_wr_acr3:
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_mcf5xxx_wr_acr3:
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    move.l  4(SP),D0
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    .long   0x4e7b0007      /* movec d0,ACR3 */
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    nop
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    rts
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208 
mcf5xxx_wr_mmubar:
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_mcf5xxx_wr_mmubar:
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    move.l  4(SP),D0
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    .long   0x4e7b0008      /* movec d0,MBAR */
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    nop
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    rts
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215 
mcf5xxx_wr_other_a7:
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_mcf5xxx_wr_other_a7:
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    move.l  4(SP),D0
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    .long   0x4e7b0800      /* movec d0,OTHER_A7 */
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    nop
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    rts
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222 
mcf5xxx_wr_vbr:
223 
_mcf5xxx_wr_vbr:
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    move.l  4(SP),D0
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    .long   0x4e7b0801      /* movec d0,VBR */
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    nop
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    rts
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229 
mcf5xxx_wr_macsr:
230 
_mcf5xxx_wr_macsr:
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    move.l  4(SP),D0
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    .long   0x4e7b0804      /* movec d0,MACSR */
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    nop
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    rts
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236 
mcf5xxx_wr_mask:
237 
_mcf5xxx_wr_mask:
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    move.l  4(SP),D0
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    .long   0x4e7b0805      /* movec d0,MASK */
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    nop
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    rts
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243 
mcf5xxx_wr_acc0:
244 
_mcf5xxx_wr_acc0:
245 
    move.l  4(SP),D0
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    .long   0x4e7b0806      /* movec d0,ACC0 */
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    nop
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    rts
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250 
mcf5xxx_wr_accext01:
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_mcf5xxx_wr_accext01:
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    move.l  4(SP),D0
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    .long   0x4e7b0807      /* movec d0,ACCEXT01 */
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    nop
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    rts
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257 
mcf5xxx_wr_accext23:
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_mcf5xxx_wr_accext23:
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    move.l  4(SP),D0
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    .long   0x4e7b0808      /* movec d0,ACCEXT23 */
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    nop
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    rts
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264 
mcf5xxx_wr_acc1:
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_mcf5xxx_wr_acc1:
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    move.l  4(SP),D0
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    .long   0x4e7b0809      /* movec d0,ACC1 */
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    nop
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    rts
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mcf5xxx_wr_acc2:
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_mcf5xxx_wr_acc2:
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    move.l  4(SP),D0
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    .long   0x4e7b080A      /* movec d0,ACC2 */
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    nop
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    rts
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278 
mcf5xxx_wr_acc3:
279 
_mcf5xxx_wr_acc3:
280 
    move.l  4(SP),D0
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    .long   0x4e7b080B      /* movec d0,ACC3 */
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    nop
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    rts
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285 
mcf5xxx_wr_pc:
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_mcf5xxx_wr_pc:
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    move.l  4(SP),D0
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    .long   0x4e7b080F      /* movec d0,PC */
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    nop
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    rts
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292 
mcf5xxx_wr_rombar0:
293 
_mcf5xxx_wr_rombar0:
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    move.l  4(SP),D0
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    .long   0x4e7b0C00      /* movec d0,ROMBAR0 */
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    nop
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    rts
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299 
mcf5xxx_wr_rombar1:
300 
_mcf5xxx_wr_rombar1:
301 
    move.l  4(SP),D0
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    .long   0x4e7b0C01      /* movec d0,ROMBAR1 */
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    nop
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    rts
305 
 
306 
mcf5xxx_wr_rambar0:
307 
_mcf5xxx_wr_rambar0:
308 
    move.l  4(SP),D0
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    .long   0x4e7b0C04      /* movec d0,RAMBAR0 */
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    nop
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    rts
312 
 
313 
mcf5xxx_wr_rambar1:
314 
_mcf5xxx_wr_rambar1:
315 
    move.l  4(SP),D0
316 
    .long   0x4e7b0C05      /* movec d0,RAMBAR1 */
317 
    nop
318 
    rts
319 
 
320 
mcf5xxx_wr_mpcr:
321 
_mcf5xxx_wr_mpcr:
322 
    move.l  4(SP),D0
323 
    .long   0x4e7b0C0C      /* movec d0,MPCR */
324 
    nop
325 
    rts
326 
 
327 
mcf5xxx_wr_secmbar:
328 
_mcf5xxx_wr_secmbar:
329 
    move.l  4(SP),D0
330 
    .long   0x4e7b0C0E      /* movec d0,MBAR1   */
331 
    nop
332 
    rts
333 
 
334 
mcf5xxx_wr_mbar:
335 
_mcf5xxx_wr_mbar:
336 
    move.l  4(SP),D0
337 
    .long   0x4e7b0C0F      /* movec d0,MBAR0   */
338 
    nop
339 
    rts
340 
 
341 
/********************************************************************/
342 
    .end

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