OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [cpu/] [mcf5xxx_lo.s] - Blame information for rev 773

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 jeremybenn 
/*
2 
 * File:    mcf5xxx.s
3 
 * Purpose: Lowest level routines for all ColdFire processors.
4 
 *
5 
 * Notes:
6 
 *
7 
 * License:     All software covered by license agreement in -
8 
 *              docs/Freescale_Software_License.pdf
9 
 */
10 
 
11 
#define mcf5xxx_exception_handler   _mcf5xxx_exception_handler
12 
 
13 
    .extern mcf5xxx_exception_handler
14 
 
15 
    .global asm_exception_handler
16 
    .global _asm_exception_handler
17 
    .global asm_set_ipl
18 
    .global _asm_set_ipl
19 
    .global mcf5xxx_exe_wdebug
20 
    .global _mcf5xxx_exe_wdebug
21 
   .global mcf5xxx_move_line   //added by Mac
22 
   .global _mcf5xxx_move_line   //added by Mac
23 
    .global mcf5xxx_wr_cacr
24 
    .global _mcf5xxx_wr_cacr
25 
    .global mcf5xxx_wr_asid
26 
    .global _mcf5xxx_wr_asid
27 
    .global mcf5xxx_wr_acr0
28 
    .global _mcf5xxx_wr_acr0
29 
    .global mcf5xxx_wr_acr1
30 
    .global _mcf5xxx_wr_acr1
31 
    .global mcf5xxx_wr_acr2
32 
    .global _mcf5xxx_wr_acr2
33 
    .global mcf5xxx_wr_acr3
34 
    .global _mcf5xxx_wr_acr3
35 
    .global mcf5xxx_wr_mmubar
36 
    .global _mcf5xxx_wr_mmubar
37 
    .global mcf5xxx_wr_other_a7
38 
    .global _mcf5xxx_wr_other_a7
39 
    .global mcf5xxx_wr_vbr
40 
    .global _mcf5xxx_wr_vbr
41 
    .global mcf5xxx_wr_macsr
42 
    .global _mcf5xxx_wr_macsr
43 
    .global mcf5xxx_wr_mask
44 
    .global _mcf5xxx_wr_mask
45 
    .global mcf5xxx_wr_acc0
46 
    .global _mcf5xxx_wr_acc0
47 
    .global mcf5xxx_wr_accext01
48 
    .global _mcf5xxx_wr_accext01
49 
    .global mcf5xxx_wr_accext23
50 
    .global _mcf5xxx_wr_accext23
51 
    .global mcf5xxx_wr_acc1
52 
    .global _mcf5xxx_wr_acc1
53 
    .global mcf5xxx_wr_acc2
54 
    .global _mcf5xxx_wr_acc2
55 
    .global mcf5xxx_wr_acc3
56 
    .global _mcf5xxx_wr_acc3
57 
    .global mcf5xxx_wr_sr
58 
    .global _mcf5xxx_wr_sr
59 
    .global mcf5xxx_wr_pc
60 
    .global _mcf5xxx_wr_pc
61 
    .global mcf5xxx_wr_rombar0
62 
    .global _mcf5xxx_wr_rombar0
63 
    .global mcf5xxx_wr_rombar1
64 
    .global _mcf5xxx_wr_rombar1
65 
    .global mcf5xxx_wr_rambar0
66 
    .global _mcf5xxx_wr_rambar0
67 
    .global mcf5xxx_wr_rambar1
68 
    .global _mcf5xxx_wr_rambar1
69 
    .global mcf5xxx_wr_mpcr
70 
    .global _mcf5xxx_wr_mpcr
71 
    .global mcf5xxx_wr_secmbar
72 
    .global _mcf5xxx_wr_secmbar
73 
    .global mcf5xxx_wr_mbar
74 
    .global _mcf5xxx_wr_mbar
75 
 
76 
    .text
77 
 
78 
/********************************************************************
79 
 * This routine is the lowest-level exception handler.
80 
 */
81 
 
82 
asm_exception_handler:
83 
_asm_exception_handler:
84 
    lea     -16(SP),SP
85 
    movem.l D0-D1/A0-A1,(SP)
86 
    lea     16(SP),A1
87 
    move.l  A1,-(SP)
88 
    jsr     mcf5xxx_exception_handler
89 
    lea     4(SP),SP
90 
    movem.l (SP),D0-D1/A0-A1
91 
    lea     16(SP),SP
92 
    rte
93 
 
94 
/********************************************************************/
95 
/*
96 
 * This routines changes the IPL to the value passed into the routine.
97 
 * It also returns the old IPL value back.
98 
 * Calling convention from C:
99 
 *   old_ipl = asm_set_ipl(new_ipl);
100 
 * For the Diab Data C compiler, it passes return value thru D0.
101 
 * Note that only the least significant three bits of the passed
102 
 * value are used.
103 
 */
104 
 
105 
asm_set_ipl:
106 
_asm_set_ipl:
107 
    link    A6,#-8
108 
    movem.l D6-D7,(SP)
109 
 
110 
    move.w  SR,D7       /* current sr    */
111 
 
112 
    move.l  D7,D0       /* prepare return value  */
113 
    andi.l  #0x0700,D0  /* mask out IPL  */
114 
    lsr.l   #8,D0       /* IPL   */
115 
 
116 
    move.l  8(A6),D6    /* get argument  */
117 
    andi.l  #0x07,D6        /* least significant three bits  */
118 
    lsl.l   #8,D6       /* move over to make mask    */
119 
 
120 
    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
121 
    or.l    D6,D7           /* place new IPL in sr   */
122 
    move.w  D7,SR
123 
 
124 
    movem.l (SP),D6-D7
125 
    lea     8(SP),SP
126 
    unlk    A6
127 
    rts
128 
 
129 
/********************************************************************/
130 
/*
131 
 * These routines execute special ColdFire instructions
132 
 */
133 
 
134 
mcf5xxx_exe_wdebug:
135 
_mcf5xxx_exe_wdebug:
136 
    move.l   4(sp),a0
137 
    wdebug.l (a0)
138 
    rts
139 
 
140 
 mcf5xxx_move_line:
141 
_mcf5xxx_move_line:
142 
    lea.l   -24(sp),sp
143 
    movem.l d0-d3/a0-a1,(sp)
144 
    movea.l 28(sp),a0       /* source in a0 */
145 
    movea.l 32(sp),a1       /* destination in a1 */
146 
    movem.l (a0),d0-d3      /* move line from source */
147 
    movem.l d0-d3,(a1)      /* move line to destination */
148 
    movem.l (sp),d0-d3/a0-a1
149 
    lea.l   24(sp),sp
150 
    rts
151 
 
152 
 
153 
/********************************************************************/
154 
/*
155 
 * These routines write to the special purpose registers in the ColdFire
156 
 * core.  Since these registers are write-only in the supervisor model,
157 
 * no corresponding read routines exist.
158 
 */
159 
 
160 
mcf5xxx_wr_sr:
161 
_mcf5xxx_wr_sr:
162 
    move.l  4(SP),D0
163 
    move.w  D0,SR
164 
    rts
165 
 
166 
mcf5xxx_wr_cacr:
167 
_mcf5xxx_wr_cacr:
168 
    move.l  4(SP),D0
169 
    .long   0x4e7b0002      /* movec d0,cacr */
170 
    nop
171 
    rts
172 
 
173 
mcf5xxx_wr_asid:
174 
_mcf5xxx_wr_asid:
175 
    move.l  4(SP),D0
176 
    .long   0x4e7b0003      /* movec d0,asid */
177 
    nop
178 
    rts
179 
 
180 
mcf5xxx_wr_acr0:
181 
_mcf5xxx_wr_acr0:
182 
    move.l  4(SP),D0
183 
    .long   0x4e7b0004      /* movec d0,ACR0 */
184 
    nop
185 
    rts
186 
 
187 
mcf5xxx_wr_acr1:
188 
_mcf5xxx_wr_acr1:
189 
    move.l  4(SP),D0
190 
    .long   0x4e7b0005      /* movec d0,ACR1 */
191 
    nop
192 
    rts
193 
 
194 
mcf5xxx_wr_acr2:
195 
_mcf5xxx_wr_acr2:
196 
    move.l  4(SP),D0
197 
    .long   0x4e7b0006      /* movec d0,ACR2 */
198 
    nop
199 
    rts
200 
 
201 
mcf5xxx_wr_acr3:
202 
_mcf5xxx_wr_acr3:
203 
    move.l  4(SP),D0
204 
    .long   0x4e7b0007      /* movec d0,ACR3 */
205 
    nop
206 
    rts
207 
 
208 
mcf5xxx_wr_mmubar:
209 
_mcf5xxx_wr_mmubar:
210 
    move.l  4(SP),D0
211 
    .long   0x4e7b0008      /* movec d0,MBAR */
212 
    nop
213 
    rts
214 
 
215 
mcf5xxx_wr_other_a7:
216 
_mcf5xxx_wr_other_a7:
217 
    move.l  4(SP),D0
218 
    .long   0x4e7b0800      /* movec d0,OTHER_A7 */
219 
    nop
220 
    rts
221 
 
222 
mcf5xxx_wr_vbr:
223 
_mcf5xxx_wr_vbr:
224 
    move.l  4(SP),D0
225 
    .long   0x4e7b0801      /* movec d0,VBR */
226 
    nop
227 
    rts
228 
 
229 
mcf5xxx_wr_macsr:
230 
_mcf5xxx_wr_macsr:
231 
    move.l  4(SP),D0
232 
    .long   0x4e7b0804      /* movec d0,MACSR */
233 
    nop
234 
    rts
235 
 
236 
mcf5xxx_wr_mask:
237 
_mcf5xxx_wr_mask:
238 
    move.l  4(SP),D0
239 
    .long   0x4e7b0805      /* movec d0,MASK */
240 
    nop
241 
    rts
242 
 
243 
mcf5xxx_wr_acc0:
244 
_mcf5xxx_wr_acc0:
245 
    move.l  4(SP),D0
246 
    .long   0x4e7b0806      /* movec d0,ACC0 */
247 
    nop
248 
    rts
249 
 
250 
mcf5xxx_wr_accext01:
251 
_mcf5xxx_wr_accext01:
252 
    move.l  4(SP),D0
253 
    .long   0x4e7b0807      /* movec d0,ACCEXT01 */
254 
    nop
255 
    rts
256 
 
257 
mcf5xxx_wr_accext23:
258 
_mcf5xxx_wr_accext23:
259 
    move.l  4(SP),D0
260 
    .long   0x4e7b0808      /* movec d0,ACCEXT23 */
261 
    nop
262 
    rts
263 
 
264 
mcf5xxx_wr_acc1:
265 
_mcf5xxx_wr_acc1:
266 
    move.l  4(SP),D0
267 
    .long   0x4e7b0809      /* movec d0,ACC1 */
268 
    nop
269 
    rts
270 
 
271 
mcf5xxx_wr_acc2:
272 
_mcf5xxx_wr_acc2:
273 
    move.l  4(SP),D0
274 
    .long   0x4e7b080A      /* movec d0,ACC2 */
275 
    nop
276 
    rts
277 
 
278 
mcf5xxx_wr_acc3:
279 
_mcf5xxx_wr_acc3:
280 
    move.l  4(SP),D0
281 
    .long   0x4e7b080B      /* movec d0,ACC3 */
282 
    nop
283 
    rts
284 
 
285 
mcf5xxx_wr_pc:
286 
_mcf5xxx_wr_pc:
287 
    move.l  4(SP),D0
288 
    .long   0x4e7b080F      /* movec d0,PC */
289 
    nop
290 
    rts
291 
 
292 
mcf5xxx_wr_rombar0:
293 
_mcf5xxx_wr_rombar0:
294 
    move.l  4(SP),D0
295 
    .long   0x4e7b0C00      /* movec d0,ROMBAR0 */
296 
    nop
297 
    rts
298 
 
299 
mcf5xxx_wr_rombar1:
300 
_mcf5xxx_wr_rombar1:
301 
    move.l  4(SP),D0
302 
    .long   0x4e7b0C01      /* movec d0,ROMBAR1 */
303 
    nop
304 
    rts
305 
 
306 
mcf5xxx_wr_rambar0:
307 
_mcf5xxx_wr_rambar0:
308 
    move.l  4(SP),D0
309 
    .long   0x4e7b0C04      /* movec d0,RAMBAR0 */
310 
    nop
311 
    rts
312 
 
313 
mcf5xxx_wr_rambar1:
314 
_mcf5xxx_wr_rambar1:
315 
    move.l  4(SP),D0
316 
    .long   0x4e7b0C05      /* movec d0,RAMBAR1 */
317 
    nop
318 
    rts
319 
 
320 
mcf5xxx_wr_mpcr:
321 
_mcf5xxx_wr_mpcr:
322 
    move.l  4(SP),D0
323 
    .long   0x4e7b0C0C      /* movec d0,MPCR */
324 
    nop
325 
    rts
326 
 
327 
mcf5xxx_wr_secmbar:
328 
_mcf5xxx_wr_secmbar:
329 
    move.l  4(SP),D0
330 
    .long   0x4e7b0C0E      /* movec d0,MBAR1   */
331 
    nop
332 
    rts
333 
 
334 
mcf5xxx_wr_mbar:
335 
_mcf5xxx_wr_mbar:
336 
    move.l  4(SP),D0
337 
    .long   0x4e7b0C0F      /* movec d0,MBAR0   */
338 
    nop
339 
    rts
340 
 
341 
/********************************************************************/
342 
    .end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.