OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [lcf/] [MCF52259_INTERNAL_FLASH.lcf] - Blame information for rev 728

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 jeremybenn
#  NOTE: The debugger uses the Illegal Instruction Vector to stop.
2
#  A small subroutine is written at the location VBR+0x408-VBR+0x40B
3
#  to handle the exception.  The Illegal Instruction Vector in
4
#  the the vector table at VBR+0x10 is then pointed to it.  When the
5
#  debugger encounters an illegal instruction, it jumps to this
6
#  subroutine, which ends with an RTE, then exits.
7
#  Do not overwrite this area of memory otherwise the debugger may not
8
#  exit properly.
9
# */
10
 
11
MEMORY
12
{
13
        vectorflash(RX) : ORIGIN = 0x00000000, LENGTH = 0x00000418
14
 
15
    flash   (RX)   : ORIGIN = 0x00000420, LENGTH = 0x0007FC00
16
        vectorram(RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000400
17
        sram    (RWX)  : ORIGIN = 0x20000400, LENGTH = 0x0000FA00
18
        ipsbar  (RWX)  : ORIGIN = 0x40000000, LENGTH = 0x0
19
}
20
 
21
SECTIONS
22
{
23
        .ipsbar  : {} > ipsbar
24
 
25
        .vectorflash :
26
        {
27
                mcf5225x_vectors.s (.text)
28
    } > vectorflash
29
 
30
        .flash :
31
        {
32
                *(.text)
33
                .                          = ALIGN(0x10);
34
                *(.rodata)
35
 
36
                ___DATA_ROM        = .;
37
    } > flash
38
 
39
    .data : AT(___DATA_ROM)
40
        {
41
                ___DATA_RAM    = . ;
42
 
43
        *(.exception)
44
                .              = ALIGN(0x10);
45
                __exception_table_start__ = .;
46
            EXCEPTION
47
                __exception_table_end__   = .;
48
 
49
                ___sinit__     = .;
50
            STATICINIT
51
 
52
        *(.data)
53
        *(.relocate_code)
54
                .              = ALIGN (0x10);
55
                ___DATA_END    = .;
56
 
57
                __START_SDATA  = .;
58
        *(.sdata)
59
 
60
                .              = ALIGN (0x10);
61
                __END_SDATA    = .;
62
 
63
                __SDA_BASE     = .;
64
                .              = ALIGN(0x10);
65
        } > sram
66
 
67
        .bss :
68
        {
69
                . = ALIGN(0x10);
70
                __START_SBSS = .;
71
                *(.sbss)
72
                *(SCOMMON)
73
                __END_SBSS   = .;
74
 
75
                . = ALIGN(0x10);
76
                __START_BSS  = .;
77
                *(.bss)
78
                *(COMMON)
79
                __END_BSS    = .;
80
        ___BSS_START = __START_SBSS;
81
        ___BSS_END   = __END_BSS;
82
        . = ALIGN(0x10);
83
 
84
        } >> sram
85
 
86
        ___FLASH                = ADDR(.vectorflash);
87
        ___FLASH_SIZE   = 0x00080000;
88
        ___SRAM                 = 0x20000400;
89
        ___SRAM_SIZE    = 0x0000FC00;
90
 
91
        ___VECTOR_RAM   = 0x20000000;
92
        ___IPSBAR               = ADDR(.ipsbar);
93
 
94
    ___SP_SIZE      = 0x200;
95
        ___HEAP_START   = .;
96
        ___HEAP_END             = ___SRAM + ___SRAM_SIZE - ___SP_SIZE;
97
        ___SP_END               = ___HEAP_END;
98
        ___SP_INIT              = ___SP_END + ___SP_SIZE;
99
 
100
        ___heap_addr    = ___HEAP_START;
101
        ___heap_size    = ___HEAP_END - ___HEAP_START ;
102
        __SP_INIT               = ___SP_INIT;
103
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.