OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF5282_Eclipse/] [RTOSDemo/] [MCF5282/] [MCF5282_PIT.h] - Blame information for rev 587

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
2
 * Copyright Freescale Semiconductor Inc
3
 * All rights reserved.
4
 *
5
 * 2007/03/19 Revision: 0.9
6
 */
7
 
8
#ifndef __MCF5282_PIT_H__
9
#define __MCF5282_PIT_H__
10
 
11
 
12
/*********************************************************************
13
*
14
* Programmable Interrupt Timer (PIT)
15
*
16
*********************************************************************/
17
 
18
/* Register read/write macros */
19
#define MCF_PIT0_PCSR                        (*(vuint16*)(&__IPSBAR[0x150000]))
20
#define MCF_PIT0_PMR                         (*(vuint16*)(&__IPSBAR[0x150002]))
21
#define MCF_PIT0_PCNTR                       (*(vuint16*)(&__IPSBAR[0x150004]))
22
 
23
#define MCF_PIT1_PCSR                        (*(vuint16*)(&__IPSBAR[0x160000]))
24
#define MCF_PIT1_PMR                         (*(vuint16*)(&__IPSBAR[0x160002]))
25
#define MCF_PIT1_PCNTR                       (*(vuint16*)(&__IPSBAR[0x160004]))
26
 
27
#define MCF_PIT2_PCSR                        (*(vuint16*)(&__IPSBAR[0x170000]))
28
#define MCF_PIT2_PMR                         (*(vuint16*)(&__IPSBAR[0x170002]))
29
#define MCF_PIT2_PCNTR                       (*(vuint16*)(&__IPSBAR[0x170004]))
30
 
31
#define MCF_PIT3_PCSR                        (*(vuint16*)(&__IPSBAR[0x180000]))
32
#define MCF_PIT3_PMR                         (*(vuint16*)(&__IPSBAR[0x180002]))
33
#define MCF_PIT3_PCNTR                       (*(vuint16*)(&__IPSBAR[0x180004]))
34
 
35
#define MCF_PIT_PCSR(x)                      (*(vuint16*)(&__IPSBAR[0x150000 + ((x)*0x10000)]))
36
#define MCF_PIT_PMR(x)                       (*(vuint16*)(&__IPSBAR[0x150002 + ((x)*0x10000)]))
37
#define MCF_PIT_PCNTR(x)                     (*(vuint16*)(&__IPSBAR[0x150004 + ((x)*0x10000)]))
38
 
39
 
40
/* Bit definitions and macros for MCF_PIT_PCSR */
41
#define MCF_PIT_PCSR_EN                      (0x1)
42
#define MCF_PIT_PCSR_RLD                     (0x2)
43
#define MCF_PIT_PCSR_PIF                     (0x4)
44
#define MCF_PIT_PCSR_PIE                     (0x8)
45
#define MCF_PIT_PCSR_OVW                     (0x10)
46
#define MCF_PIT_PCSR_HALTED                  (0x20)
47
#define MCF_PIT_PCSR_DOZE                    (0x40)
48
#define MCF_PIT_PCSR_PRE(x)                  (((x)&0xF)<<0x8)
49
 
50
/* Bit definitions and macros for MCF_PIT_PMR */
51
#define MCF_PIT_PMR_PM(x)                    (((x)&0xFFFF)<<0)
52
 
53
/* Bit definitions and macros for MCF_PIT_PCNTR */
54
#define MCF_PIT_PCNTR_PC(x)                  (((x)&0xFFFF)<<0)
55
 
56
 
57
#endif /* __MCF5282_PIT_H__ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.