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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF5282_Eclipse/] [RTOSDemo/] [MCF5282/] [MCF5282_PMM.h] - Blame information for rev 597

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Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
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 * Copyright Freescale Semiconductor Inc
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 * All rights reserved.
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 *
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 * 2007/03/19 Revision: 0.9
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 */
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#ifndef __MCF5282_PMM_H__
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#define __MCF5282_PMM_H__
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/*********************************************************************
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*
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* Power Management (PMM)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_PMM_LPICR                        (*(vuint8 *)(&__IPSBAR[0x12]))
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#define MCF_PMM_LPCR                         (*(vuint8 *)(&__IPSBAR[0x110007]))
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/* Bit definitions and macros for MCF_PMM_LPICR */
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#define MCF_PMM_LPICR_XLPM_IPL(x)            (((x)&0x7)<<0x4)
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#define MCF_PMM_LPICR_ENBSTOP                (0x80)
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/* Bit definitions and macros for MCF_PMM_LPCR */
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#define MCF_PMM_LPCR_LVDSE                   (0x2)
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#define MCF_PMM_LPCR_STPMD(x)                (((x)&0x3)<<0x3)
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#define MCF_PMM_LPCR_STPMD_SYS_DISABLED      (0)
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#define MCF_PMM_LPCR_STPMD_SYS_CLKOUT_DISABLED (0x8)
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#define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED  (0x10)
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#define MCF_PMM_LPCR_STPMD_ALL_DISABLED      (0x18)
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#define MCF_PMM_LPCR_LPMD(x)                 (((x)&0x3)<<0x6)
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#define MCF_PMM_LPCR_LPMD_RUN                (0)
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#define MCF_PMM_LPCR_LPMD_DOZE               (0x40)
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#define MCF_PMM_LPCR_LPMD_WAIT               (0x80)
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#define MCF_PMM_LPCR_LPMD_STOP               (0xC0)
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#endif /* __MCF5282_PMM_H__ */

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