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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF5282_Eclipse/] [RTOSDemo/] [MCF5282/] [MCF5282_QSPI.h] - Blame information for rev 867

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Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
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 * Copyright Freescale Semiconductor Inc
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 * All rights reserved.
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 *
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 * 2007/03/19 Revision: 0.9
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 */
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#ifndef __MCF5282_QSPI_H__
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#define __MCF5282_QSPI_H__
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/*********************************************************************
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*
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* Queued Serial Peripheral Interface (QSPI)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_QSPI_QMR                         (*(vuint16*)(&__IPSBAR[0x340]))
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#define MCF_QSPI_QDLYR                       (*(vuint16*)(&__IPSBAR[0x344]))
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#define MCF_QSPI_QWR                         (*(vuint16*)(&__IPSBAR[0x348]))
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#define MCF_QSPI_QIR                         (*(vuint16*)(&__IPSBAR[0x34C]))
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#define MCF_QSPI_QAR                         (*(vuint16*)(&__IPSBAR[0x350]))
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#define MCF_QSPI_QDR                         (*(vuint16*)(&__IPSBAR[0x354]))
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/* Bit definitions and macros for MCF_QSPI_QMR */
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#define MCF_QSPI_QMR_BAUD(x)                 (((x)&0xFF)<<0)
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#define MCF_QSPI_QMR_CPHA                    (0x100)
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#define MCF_QSPI_QMR_CPOL                    (0x200)
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#define MCF_QSPI_QMR_BITS(x)                 (((x)&0xF)<<0xA)
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#define MCF_QSPI_QMR_DOHIE                   (0x4000)
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#define MCF_QSPI_QMR_MSTR                    (0x8000)
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/* Bit definitions and macros for MCF_QSPI_QDLYR */
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#define MCF_QSPI_QDLYR_DTL(x)                (((x)&0xFF)<<0)
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#define MCF_QSPI_QDLYR_QCD(x)                (((x)&0x7F)<<0x8)
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#define MCF_QSPI_QDLYR_SPE                   (0x8000)
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/* Bit definitions and macros for MCF_QSPI_QWR */
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#define MCF_QSPI_QWR_NEWQP(x)                (((x)&0xF)<<0)
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#define MCF_QSPI_QWR_CPTQP(x)                (((x)&0xF)<<0x4)
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#define MCF_QSPI_QWR_ENDQP(x)                (((x)&0xF)<<0x8)
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#define MCF_QSPI_QWR_CSIV                    (0x1000)
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#define MCF_QSPI_QWR_WRTO                    (0x2000)
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#define MCF_QSPI_QWR_WREN                    (0x4000)
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#define MCF_QSPI_QWR_HALT                    (0x8000)
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/* Bit definitions and macros for MCF_QSPI_QIR */
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#define MCF_QSPI_QIR_SPIF                    (0x1)
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#define MCF_QSPI_QIR_ABRT                    (0x4)
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#define MCF_QSPI_QIR_WCEF                    (0x8)
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#define MCF_QSPI_QIR_SPIFE                   (0x100)
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#define MCF_QSPI_QIR_ABRTE                   (0x400)
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#define MCF_QSPI_QIR_WCEFE                   (0x800)
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#define MCF_QSPI_QIR_ABRTL                   (0x1000)
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#define MCF_QSPI_QIR_ABRTB                   (0x4000)
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#define MCF_QSPI_QIR_WCEFB                   (0x8000)
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/* Bit definitions and macros for MCF_QSPI_QAR */
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#define MCF_QSPI_QAR_ADDR(x)                 (((x)&0x3F)<<0)
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#define MCF_QSPI_QAR_TRANS                   (0)
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#define MCF_QSPI_QAR_RECV                    (0x10)
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#define MCF_QSPI_QAR_CMD                     (0x20)
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/* Bit definitions and macros for MCF_QSPI_QDR */
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#define MCF_QSPI_QDR_DATA(x)                 (((x)&0xFFFF)<<0)
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#define MCF_QSPI_QDR_CONT                    (0x8000)
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#define MCF_QSPI_QDR_BITSE                   (0x4000)
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#define MCF_QSPI_QDR_DT                      (0x2000)
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#define MCF_QSPI_QDR_DSCK                    (0x1000)
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#define MCF_QSPI_QDR_QSPI_CS3                (0x800)
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#define MCF_QSPI_QDR_QSPI_CS2                (0x400)
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#define MCF_QSPI_QDR_QSPI_CS1                (0x200)
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#define MCF_QSPI_QDR_QSPI_CS0                (0x100)
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#endif /* __MCF5282_QSPI_H__ */

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