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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF5282_Eclipse/] [RTOSDemo/] [MCF5282/] [MCF5282_RCM.h] - Blame information for rev 797

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Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
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 * Copyright Freescale Semiconductor Inc
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 * All rights reserved.
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 *
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 * 2007/03/19 Revision: 0.9
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 */
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#ifndef __MCF5282_RCM_H__
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#define __MCF5282_RCM_H__
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/*********************************************************************
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*
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* Reset Controller Module (RCM)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_RCM_RCR                          (*(vuint8 *)(&__IPSBAR[0x110000]))
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#define MCF_RCM_RSR                          (*(vuint8 *)(&__IPSBAR[0x110001]))
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/* Bit definitions and macros for MCF_RCM_RCR */
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#define MCF_RCM_RCR_LVDE                     (0x1)
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#define MCF_RCM_RCR_LVDRE                    (0x4)
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#define MCF_RCM_RCR_LVDIE                    (0x8)
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#define MCF_RCM_RCR_LVDF                     (0x10)
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#define MCF_RCM_RCR_FRCRSTOUT                (0x40)
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#define MCF_RCM_RCR_SOFTRST                  (0x80)
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/* Bit definitions and macros for MCF_RCM_RSR */
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#define MCF_RCM_RSR_LOL                      (0x1)
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#define MCF_RCM_RSR_LOC                      (0x2)
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#define MCF_RCM_RSR_EXT                      (0x4)
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#define MCF_RCM_RSR_POR                      (0x8)
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#define MCF_RCM_RSR_WDR                      (0x10)
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#define MCF_RCM_RSR_SOFT                     (0x20)
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#define MCF_RCM_RSR_LVD                      (0x40)
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#endif /* __MCF5282_RCM_H__ */

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