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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF5282_Eclipse/] [RTOSDemo/] [MCF5282/] [MCF5282_WTM.h] - Blame information for rev 867

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Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
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 * Copyright Freescale Semiconductor Inc
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 * All rights reserved.
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 *
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 * 2007/03/19 Revision: 0.9
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 */
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#ifndef __MCF5282_WTM_H__
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#define __MCF5282_WTM_H__
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/*********************************************************************
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*
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* Watchdog Timer Module (WTM)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_WTM_WCR                          (*(vuint16*)(&__IPSBAR[0x140000]))
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#define MCF_WTM_WMR                          (*(vuint16*)(&__IPSBAR[0x140002]))
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#define MCF_WTM_WCNTR                        (*(vuint16*)(&__IPSBAR[0x140004]))
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#define MCF_WTM_WSR                          (*(vuint16*)(&__IPSBAR[0x140006]))
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/* Bit definitions and macros for MCF_WTM_WCR */
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#define MCF_WTM_WCR_EN                       (0x1)
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#define MCF_WTM_WCR_HALTED                   (0x2)
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#define MCF_WTM_WCR_DOZE                     (0x4)
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#define MCF_WTM_WCR_WAIT                     (0x8)
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/* Bit definitions and macros for MCF_WTM_WMR */
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#define MCF_WTM_WMR_WM(x)                    (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_WTM_WCNTR */
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#define MCF_WTM_WCNTR_WC(x)                  (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_WTM_WSR */
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#define MCF_WTM_WSR_WS(x)                    (((x)&0xFFFF)<<0)
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#endif /* __MCF5282_WTM_H__ */

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