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1 608 jeremybenn
//  ----------------------------------------------------------------------------
2
//          ATMEL Microcontroller Software Support  -  ROUSSET  -
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//  ----------------------------------------------------------------------------
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//  Copyright (c) 2006, Atmel Corporation
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// 
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//  All rights reserved.
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// 
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//  Redistribution and use in source and binary forms, with or without
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//  modification, are permitted provided that the following conditions are met:
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// 
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//  - Redistributions of source code must retain the above copyright notice,
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//  this list of conditions and the disclaimer below.
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// 
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//  - Redistributions in binary form must reproduce the above copyright notice,
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//  this list of conditions and the disclaimer below in the documentation and/or
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//  other materials provided with the distribution. 
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// 
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//  Atmel's name may not be used to endorse or promote products derived from
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//  this software without specific prior written permission. 
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//  
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//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//  ----------------------------------------------------------------------------
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// File Name           : AT91SAM9XE512.h
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// Object              : AT91SAM9XE512 definitions
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// Generated           : AT91 SW Application Group  02/13/2008 (18:25:59)
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// 
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// CVS Reference       : /AT91SAM9XE512.pl/1.16/Wed Jan 30 14:02:22 2008//
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// CVS Reference       : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008//
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// CVS Reference       : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007//
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// CVS Reference       : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007//
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// CVS Reference       : /PMC_SAM9262.pl/1.4/Mon Mar  7 18:03:13 2005//
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// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
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// CVS Reference       : /HSDRAMC1_6100A.pl/1.2/Mon Aug  9 10:52:25 2004//
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// CVS Reference       : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
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// CVS Reference       : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
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// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
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// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
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// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
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// CVS Reference       : /RSTC_6098A.pl/1.3/Thu Nov  4 13:57:00 2004//
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// CVS Reference       : /SHDWC_6122A.pl/1.3/Wed Oct  6 14:16:58 2004//
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// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
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// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
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// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
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// CVS Reference       : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006//
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// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
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// CVS Reference       : /MCI_6101E.pl/1.1/Fri Jun  3 13:20:23 2005//
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// CVS Reference       : /TWI_6061B.pl/1.2/Fri Aug  4 08:53:02 2006//
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// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
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// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
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// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
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// CVS Reference       : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
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// CVS Reference       : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//
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// CVS Reference       : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
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// CVS Reference       : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//
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// CVS Reference       : /HECC_6143A.pl/1.1/Wed Feb  9 17:16:57 2005//
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// CVS Reference       : /ISI_xxxxx.pl/1.3/Thu Mar  3 11:11:48 2005//
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//  ----------------------------------------------------------------------------
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68
#ifndef AT91SAM9XE512_H
69
#define AT91SAM9XE512_H
70
 
71
#ifndef __ASSEMBLY__
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typedef volatile unsigned int AT91_REG;// Hardware register definition
73
#define AT91_CAST(a) (a)
74
#else
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#define AT91_CAST(a)
76
#endif
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78
// *****************************************************************************
79
//              SOFTWARE API DEFINITION  FOR System Peripherals
80
// *****************************************************************************
81
#ifndef __ASSEMBLY__
82
typedef struct _AT91S_SYS {
83
        AT91_REG         Reserved0[2560];       // 
84
        AT91_REG         ECC_CR;        //  ECC reset register
85
        AT91_REG         ECC_MR;        //  ECC Page size register
86
        AT91_REG         ECC_SR;        //  ECC Status register
87
        AT91_REG         ECC_PR;        //  ECC Parity register
88
        AT91_REG         ECC_NPR;       //  ECC Parity N register
89
        AT91_REG         Reserved1[58];         // 
90
        AT91_REG         ECC_VR;        //  ECC Version register
91
        AT91_REG         Reserved2[64];         // 
92
        AT91_REG         SDRAMC_MR;     // SDRAM Controller Mode Register
93
        AT91_REG         SDRAMC_TR;     // SDRAM Controller Refresh Timer Register
94
        AT91_REG         SDRAMC_CR;     // SDRAM Controller Configuration Register
95
        AT91_REG         SDRAMC_HSR;    // SDRAM Controller High Speed Register
96
        AT91_REG         SDRAMC_LPR;    // SDRAM Controller Low Power Register
97
        AT91_REG         SDRAMC_IER;    // SDRAM Controller Interrupt Enable Register
98
        AT91_REG         SDRAMC_IDR;    // SDRAM Controller Interrupt Disable Register
99
        AT91_REG         SDRAMC_IMR;    // SDRAM Controller Interrupt Mask Register
100
        AT91_REG         SDRAMC_ISR;    // SDRAM Controller Interrupt Mask Register
101
        AT91_REG         SDRAMC_MDR;    // SDRAM Memory Device Register
102
        AT91_REG         Reserved3[118];        // 
103
        AT91_REG         SMC_SETUP0;    //  Setup Register for CS 0
104
        AT91_REG         SMC_PULSE0;    //  Pulse Register for CS 0
105
        AT91_REG         SMC_CYCLE0;    //  Cycle Register for CS 0
106
        AT91_REG         SMC_CTRL0;     //  Control Register for CS 0
107
        AT91_REG         SMC_SETUP1;    //  Setup Register for CS 1
108
        AT91_REG         SMC_PULSE1;    //  Pulse Register for CS 1
109
        AT91_REG         SMC_CYCLE1;    //  Cycle Register for CS 1
110
        AT91_REG         SMC_CTRL1;     //  Control Register for CS 1
111
        AT91_REG         SMC_SETUP2;    //  Setup Register for CS 2
112
        AT91_REG         SMC_PULSE2;    //  Pulse Register for CS 2
113
        AT91_REG         SMC_CYCLE2;    //  Cycle Register for CS 2
114
        AT91_REG         SMC_CTRL2;     //  Control Register for CS 2
115
        AT91_REG         SMC_SETUP3;    //  Setup Register for CS 3
116
        AT91_REG         SMC_PULSE3;    //  Pulse Register for CS 3
117
        AT91_REG         SMC_CYCLE3;    //  Cycle Register for CS 3
118
        AT91_REG         SMC_CTRL3;     //  Control Register for CS 3
119
        AT91_REG         SMC_SETUP4;    //  Setup Register for CS 4
120
        AT91_REG         SMC_PULSE4;    //  Pulse Register for CS 4
121
        AT91_REG         SMC_CYCLE4;    //  Cycle Register for CS 4
122
        AT91_REG         SMC_CTRL4;     //  Control Register for CS 4
123
        AT91_REG         SMC_SETUP5;    //  Setup Register for CS 5
124
        AT91_REG         SMC_PULSE5;    //  Pulse Register for CS 5
125
        AT91_REG         SMC_CYCLE5;    //  Cycle Register for CS 5
126
        AT91_REG         SMC_CTRL5;     //  Control Register for CS 5
127
        AT91_REG         SMC_SETUP6;    //  Setup Register for CS 6
128
        AT91_REG         SMC_PULSE6;    //  Pulse Register for CS 6
129
        AT91_REG         SMC_CYCLE6;    //  Cycle Register for CS 6
130
        AT91_REG         SMC_CTRL6;     //  Control Register for CS 6
131
        AT91_REG         SMC_SETUP7;    //  Setup Register for CS 7
132
        AT91_REG         SMC_PULSE7;    //  Pulse Register for CS 7
133
        AT91_REG         SMC_CYCLE7;    //  Cycle Register for CS 7
134
        AT91_REG         SMC_CTRL7;     //  Control Register for CS 7
135
        AT91_REG         Reserved4[96];         // 
136
        AT91_REG         MATRIX_MCFG0;  //  Master Configuration Register 0 (ram96k)     
137
        AT91_REG         MATRIX_MCFG1;  //  Master Configuration Register 1 (rom)    
138
        AT91_REG         MATRIX_MCFG2;  //  Master Configuration Register 2 (hperiphs) 
139
        AT91_REG         MATRIX_MCFG3;  //  Master Configuration Register 3 (ebi)
140
        AT91_REG         MATRIX_MCFG4;  //  Master Configuration Register 4 (bridge)    
141
        AT91_REG         MATRIX_MCFG5;  //  Master Configuration Register 5 (mailbox)    
142
        AT91_REG         MATRIX_MCFG6;  //  Master Configuration Register 6 (ram16k)  
143
        AT91_REG         MATRIX_MCFG7;  //  Master Configuration Register 7 (teak_prog)     
144
        AT91_REG         Reserved5[8];  // 
145
        AT91_REG         MATRIX_SCFG0;  //  Slave Configuration Register 0 (ram96k)     
146
        AT91_REG         MATRIX_SCFG1;  //  Slave Configuration Register 1 (rom)    
147
        AT91_REG         MATRIX_SCFG2;  //  Slave Configuration Register 2 (hperiphs) 
148
        AT91_REG         MATRIX_SCFG3;  //  Slave Configuration Register 3 (ebi)
149
        AT91_REG         MATRIX_SCFG4;  //  Slave Configuration Register 4 (bridge)    
150
        AT91_REG         Reserved6[11];         // 
151
        AT91_REG         MATRIX_PRAS0;  //  PRAS0 (ram0) 
152
        AT91_REG         MATRIX_PRBS0;  //  PRBS0 (ram0) 
153
        AT91_REG         MATRIX_PRAS1;  //  PRAS1 (ram1) 
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        AT91_REG         MATRIX_PRBS1;  //  PRBS1 (ram1) 
155
        AT91_REG         MATRIX_PRAS2;  //  PRAS2 (ram2) 
156
        AT91_REG         MATRIX_PRBS2;  //  PRBS2 (ram2) 
157
        AT91_REG         MATRIX_PRAS3;  //  PRAS3 : usb_dev_hs
158
        AT91_REG         MATRIX_PRBS3;  //  PRBS3 : usb_dev_hs
159
        AT91_REG         MATRIX_PRAS4;  //  PRAS4 : ebi
160
        AT91_REG         MATRIX_PRBS4;  //  PRBS4 : ebi
161
        AT91_REG         Reserved7[22];         // 
162
        AT91_REG         MATRIX_MRCR;   //  Master Remp Control Register 
163
        AT91_REG         Reserved8[6];  // 
164
        AT91_REG         CCFG_EBICSA;   //  EBI Chip Select Assignement Register
165
        AT91_REG         Reserved9[3];  // 
166
        AT91_REG         MATRIX_TEAKCFG;        //  Slave 7 (teak_prog) Special Function Register
167
        AT91_REG         Reserved10[51];        // 
168
        AT91_REG         CCFG_MATRIXVERSION;    //  Version Register
169
        AT91_REG         AIC_SMR[32];   // Source Mode Register
170
        AT91_REG         AIC_SVR[32];   // Source Vector Register
171
        AT91_REG         AIC_IVR;       // IRQ Vector Register
172
        AT91_REG         AIC_FVR;       // FIQ Vector Register
173
        AT91_REG         AIC_ISR;       // Interrupt Status Register
174
        AT91_REG         AIC_IPR;       // Interrupt Pending Register
175
        AT91_REG         AIC_IMR;       // Interrupt Mask Register
176
        AT91_REG         AIC_CISR;      // Core Interrupt Status Register
177
        AT91_REG         Reserved11[2];         // 
178
        AT91_REG         AIC_IECR;      // Interrupt Enable Command Register
179
        AT91_REG         AIC_IDCR;      // Interrupt Disable Command Register
180
        AT91_REG         AIC_ICCR;      // Interrupt Clear Command Register
181
        AT91_REG         AIC_ISCR;      // Interrupt Set Command Register
182
        AT91_REG         AIC_EOICR;     // End of Interrupt Command Register
183
        AT91_REG         AIC_SPU;       // Spurious Vector Register
184
        AT91_REG         AIC_DCR;       // Debug Control Register (Protect)
185
        AT91_REG         Reserved12[1];         // 
186
        AT91_REG         AIC_FFER;      // Fast Forcing Enable Register
187
        AT91_REG         AIC_FFDR;      // Fast Forcing Disable Register
188
        AT91_REG         AIC_FFSR;      // Fast Forcing Status Register
189
        AT91_REG         Reserved13[45];        // 
190
        AT91_REG         DBGU_CR;       // Control Register
191
        AT91_REG         DBGU_MR;       // Mode Register
192
        AT91_REG         DBGU_IER;      // Interrupt Enable Register
193
        AT91_REG         DBGU_IDR;      // Interrupt Disable Register
194
        AT91_REG         DBGU_IMR;      // Interrupt Mask Register
195
        AT91_REG         DBGU_CSR;      // Channel Status Register
196
        AT91_REG         DBGU_RHR;      // Receiver Holding Register
197
        AT91_REG         DBGU_THR;      // Transmitter Holding Register
198
        AT91_REG         DBGU_BRGR;     // Baud Rate Generator Register
199
        AT91_REG         Reserved14[7];         // 
200
        AT91_REG         DBGU_CIDR;     // Chip ID Register
201
        AT91_REG         DBGU_EXID;     // Chip ID Extension Register
202
        AT91_REG         DBGU_FNTR;     // Force NTRST Register
203
        AT91_REG         Reserved15[45];        // 
204
        AT91_REG         DBGU_RPR;      // Receive Pointer Register
205
        AT91_REG         DBGU_RCR;      // Receive Counter Register
206
        AT91_REG         DBGU_TPR;      // Transmit Pointer Register
207
        AT91_REG         DBGU_TCR;      // Transmit Counter Register
208
        AT91_REG         DBGU_RNPR;     // Receive Next Pointer Register
209
        AT91_REG         DBGU_RNCR;     // Receive Next Counter Register
210
        AT91_REG         DBGU_TNPR;     // Transmit Next Pointer Register
211
        AT91_REG         DBGU_TNCR;     // Transmit Next Counter Register
212
        AT91_REG         DBGU_PTCR;     // PDC Transfer Control Register
213
        AT91_REG         DBGU_PTSR;     // PDC Transfer Status Register
214
        AT91_REG         Reserved16[54];        // 
215
        AT91_REG         PIOA_PER;      // PIO Enable Register
216
        AT91_REG         PIOA_PDR;      // PIO Disable Register
217
        AT91_REG         PIOA_PSR;      // PIO Status Register
218
        AT91_REG         Reserved17[1];         // 
219
        AT91_REG         PIOA_OER;      // Output Enable Register
220
        AT91_REG         PIOA_ODR;      // Output Disable Registerr
221
        AT91_REG         PIOA_OSR;      // Output Status Register
222
        AT91_REG         Reserved18[1];         // 
223
        AT91_REG         PIOA_IFER;     // Input Filter Enable Register
224
        AT91_REG         PIOA_IFDR;     // Input Filter Disable Register
225
        AT91_REG         PIOA_IFSR;     // Input Filter Status Register
226
        AT91_REG         Reserved19[1];         // 
227
        AT91_REG         PIOA_SODR;     // Set Output Data Register
228
        AT91_REG         PIOA_CODR;     // Clear Output Data Register
229
        AT91_REG         PIOA_ODSR;     // Output Data Status Register
230
        AT91_REG         PIOA_PDSR;     // Pin Data Status Register
231
        AT91_REG         PIOA_IER;      // Interrupt Enable Register
232
        AT91_REG         PIOA_IDR;      // Interrupt Disable Register
233
        AT91_REG         PIOA_IMR;      // Interrupt Mask Register
234
        AT91_REG         PIOA_ISR;      // Interrupt Status Register
235
        AT91_REG         PIOA_MDER;     // Multi-driver Enable Register
236
        AT91_REG         PIOA_MDDR;     // Multi-driver Disable Register
237
        AT91_REG         PIOA_MDSR;     // Multi-driver Status Register
238
        AT91_REG         Reserved20[1];         // 
239
        AT91_REG         PIOA_PPUDR;    // Pull-up Disable Register
240
        AT91_REG         PIOA_PPUER;    // Pull-up Enable Register
241
        AT91_REG         PIOA_PPUSR;    // Pull-up Status Register
242
        AT91_REG         Reserved21[1];         // 
243
        AT91_REG         PIOA_ASR;      // Select A Register
244
        AT91_REG         PIOA_BSR;      // Select B Register
245
        AT91_REG         PIOA_ABSR;     // AB Select Status Register
246
        AT91_REG         Reserved22[9];         // 
247
        AT91_REG         PIOA_OWER;     // Output Write Enable Register
248
        AT91_REG         PIOA_OWDR;     // Output Write Disable Register
249
        AT91_REG         PIOA_OWSR;     // Output Write Status Register
250
        AT91_REG         Reserved23[213];       // 
251
        AT91_REG         PIOB_PER;      // PIO Enable Register
252
        AT91_REG         PIOB_PDR;      // PIO Disable Register
253
        AT91_REG         PIOB_PSR;      // PIO Status Register
254
        AT91_REG         Reserved24[1];         // 
255
        AT91_REG         PIOB_OER;      // Output Enable Register
256
        AT91_REG         PIOB_ODR;      // Output Disable Registerr
257
        AT91_REG         PIOB_OSR;      // Output Status Register
258
        AT91_REG         Reserved25[1];         // 
259
        AT91_REG         PIOB_IFER;     // Input Filter Enable Register
260
        AT91_REG         PIOB_IFDR;     // Input Filter Disable Register
261
        AT91_REG         PIOB_IFSR;     // Input Filter Status Register
262
        AT91_REG         Reserved26[1];         // 
263
        AT91_REG         PIOB_SODR;     // Set Output Data Register
264
        AT91_REG         PIOB_CODR;     // Clear Output Data Register
265
        AT91_REG         PIOB_ODSR;     // Output Data Status Register
266
        AT91_REG         PIOB_PDSR;     // Pin Data Status Register
267
        AT91_REG         PIOB_IER;      // Interrupt Enable Register
268
        AT91_REG         PIOB_IDR;      // Interrupt Disable Register
269
        AT91_REG         PIOB_IMR;      // Interrupt Mask Register
270
        AT91_REG         PIOB_ISR;      // Interrupt Status Register
271
        AT91_REG         PIOB_MDER;     // Multi-driver Enable Register
272
        AT91_REG         PIOB_MDDR;     // Multi-driver Disable Register
273
        AT91_REG         PIOB_MDSR;     // Multi-driver Status Register
274
        AT91_REG         Reserved27[1];         // 
275
        AT91_REG         PIOB_PPUDR;    // Pull-up Disable Register
276
        AT91_REG         PIOB_PPUER;    // Pull-up Enable Register
277
        AT91_REG         PIOB_PPUSR;    // Pull-up Status Register
278
        AT91_REG         Reserved28[1];         // 
279
        AT91_REG         PIOB_ASR;      // Select A Register
280
        AT91_REG         PIOB_BSR;      // Select B Register
281
        AT91_REG         PIOB_ABSR;     // AB Select Status Register
282
        AT91_REG         Reserved29[9];         // 
283
        AT91_REG         PIOB_OWER;     // Output Write Enable Register
284
        AT91_REG         PIOB_OWDR;     // Output Write Disable Register
285
        AT91_REG         PIOB_OWSR;     // Output Write Status Register
286
        AT91_REG         Reserved30[85];        // 
287
        AT91_REG         PIOC_PER;      // PIO Enable Register
288
        AT91_REG         PIOC_PDR;      // PIO Disable Register
289
        AT91_REG         PIOC_PSR;      // PIO Status Register
290
        AT91_REG         Reserved31[1];         // 
291
        AT91_REG         PIOC_OER;      // Output Enable Register
292
        AT91_REG         PIOC_ODR;      // Output Disable Registerr
293
        AT91_REG         PIOC_OSR;      // Output Status Register
294
        AT91_REG         Reserved32[1];         // 
295
        AT91_REG         PIOC_IFER;     // Input Filter Enable Register
296
        AT91_REG         PIOC_IFDR;     // Input Filter Disable Register
297
        AT91_REG         PIOC_IFSR;     // Input Filter Status Register
298
        AT91_REG         Reserved33[1];         // 
299
        AT91_REG         PIOC_SODR;     // Set Output Data Register
300
        AT91_REG         PIOC_CODR;     // Clear Output Data Register
301
        AT91_REG         PIOC_ODSR;     // Output Data Status Register
302
        AT91_REG         PIOC_PDSR;     // Pin Data Status Register
303
        AT91_REG         PIOC_IER;      // Interrupt Enable Register
304
        AT91_REG         PIOC_IDR;      // Interrupt Disable Register
305
        AT91_REG         PIOC_IMR;      // Interrupt Mask Register
306
        AT91_REG         PIOC_ISR;      // Interrupt Status Register
307
        AT91_REG         PIOC_MDER;     // Multi-driver Enable Register
308
        AT91_REG         PIOC_MDDR;     // Multi-driver Disable Register
309
        AT91_REG         PIOC_MDSR;     // Multi-driver Status Register
310
        AT91_REG         Reserved34[1];         // 
311
        AT91_REG         PIOC_PPUDR;    // Pull-up Disable Register
312
        AT91_REG         PIOC_PPUER;    // Pull-up Enable Register
313
        AT91_REG         PIOC_PPUSR;    // Pull-up Status Register
314
        AT91_REG         Reserved35[1];         // 
315
        AT91_REG         PIOC_ASR;      // Select A Register
316
        AT91_REG         PIOC_BSR;      // Select B Register
317
        AT91_REG         PIOC_ABSR;     // AB Select Status Register
318
        AT91_REG         Reserved36[9];         // 
319
        AT91_REG         PIOC_OWER;     // Output Write Enable Register
320
        AT91_REG         PIOC_OWDR;     // Output Write Disable Register
321
        AT91_REG         PIOC_OWSR;     // Output Write Status Register
322
        AT91_REG         Reserved37[85];        // 
323
        AT91_REG         PMC_SCER;      // System Clock Enable Register
324
        AT91_REG         PMC_SCDR;      // System Clock Disable Register
325
        AT91_REG         PMC_SCSR;      // System Clock Status Register
326
        AT91_REG         Reserved38[1];         // 
327
        AT91_REG         PMC_PCER;      // Peripheral Clock Enable Register
328
        AT91_REG         PMC_PCDR;      // Peripheral Clock Disable Register
329
        AT91_REG         PMC_PCSR;      // Peripheral Clock Status Register
330
        AT91_REG         Reserved39[1];         // 
331
        AT91_REG         PMC_MOR;       // Main Oscillator Register
332
        AT91_REG         PMC_MCFR;      // Main Clock  Frequency Register
333
        AT91_REG         PMC_PLLAR;     // PLL A Register
334
        AT91_REG         PMC_PLLBR;     // PLL B Register
335
        AT91_REG         PMC_MCKR;      // Master Clock Register
336
        AT91_REG         Reserved40[3];         // 
337
        AT91_REG         PMC_PCKR[8];   // Programmable Clock Register
338
        AT91_REG         PMC_IER;       // Interrupt Enable Register
339
        AT91_REG         PMC_IDR;       // Interrupt Disable Register
340
        AT91_REG         PMC_SR;        // Status Register
341
        AT91_REG         PMC_IMR;       // Interrupt Mask Register
342
        AT91_REG         Reserved41[36];        // 
343
        AT91_REG         RSTC_RCR;      // Reset Control Register
344
        AT91_REG         RSTC_RSR;      // Reset Status Register
345
        AT91_REG         RSTC_RMR;      // Reset Mode Register
346
        AT91_REG         Reserved42[1];         // 
347
        AT91_REG         SHDWC_SHCR;    // Shut Down Control Register
348
        AT91_REG         SHDWC_SHMR;    // Shut Down Mode Register
349
        AT91_REG         SHDWC_SHSR;    // Shut Down Status Register
350
        AT91_REG         Reserved43[1];         // 
351
        AT91_REG         RTTC_RTMR;     // Real-time Mode Register
352
        AT91_REG         RTTC_RTAR;     // Real-time Alarm Register
353
        AT91_REG         RTTC_RTVR;     // Real-time Value Register
354
        AT91_REG         RTTC_RTSR;     // Real-time Status Register
355
        AT91_REG         PITC_PIMR;     // Period Interval Mode Register
356
        AT91_REG         PITC_PISR;     // Period Interval Status Register
357
        AT91_REG         PITC_PIVR;     // Period Interval Value Register
358
        AT91_REG         PITC_PIIR;     // Period Interval Image Register
359
        AT91_REG         WDTC_WDCR;     // Watchdog Control Register
360
        AT91_REG         WDTC_WDMR;     // Watchdog Mode Register
361
        AT91_REG         WDTC_WDSR;     // Watchdog Status Register
362
        AT91_REG         Reserved44[1];         // 
363
        AT91_REG         SYS_GPBR[4];   // General Purpose Register
364
} AT91S_SYS, *AT91PS_SYS;
365
#else
366
#define SYS_GPBR        (AT91_CAST(AT91_REG *)  0x00003D50) // (SYS_GPBR) General Purpose Register
367
 
368
#endif
369
// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- 
370
#define AT91C_GPBR_GPRV       (0x0 <<  0) // (SYS) General Purpose Register Value
371
 
372
// *****************************************************************************
373
//              SOFTWARE API DEFINITION  FOR External Bus Interface
374
// *****************************************************************************
375
#ifndef __ASSEMBLY__
376
typedef struct _AT91S_EBI {
377
        AT91_REG         EBI_DUMMY;     // Dummy register - Do not use
378
} AT91S_EBI, *AT91PS_EBI;
379
#else
380
#define EBI_DUMMY       (AT91_CAST(AT91_REG *)  0x00000000) // (EBI_DUMMY) Dummy register - Do not use
381
 
382
#endif
383
 
384
// *****************************************************************************
385
//              SOFTWARE API DEFINITION  FOR Error Correction Code controller
386
// *****************************************************************************
387
#ifndef __ASSEMBLY__
388
typedef struct _AT91S_ECC {
389
        AT91_REG         ECC_CR;        //  ECC reset register
390
        AT91_REG         ECC_MR;        //  ECC Page size register
391
        AT91_REG         ECC_SR;        //  ECC Status register
392
        AT91_REG         ECC_PR;        //  ECC Parity register
393
        AT91_REG         ECC_NPR;       //  ECC Parity N register
394
        AT91_REG         Reserved0[58];         // 
395
        AT91_REG         ECC_VR;        //  ECC Version register
396
} AT91S_ECC, *AT91PS_ECC;
397
#else
398
#define ECC_CR          (AT91_CAST(AT91_REG *)  0x00000000) // (ECC_CR)  ECC reset register
399
#define ECC_MR          (AT91_CAST(AT91_REG *)  0x00000004) // (ECC_MR)  ECC Page size register
400
#define ECC_SR          (AT91_CAST(AT91_REG *)  0x00000008) // (ECC_SR)  ECC Status register
401
#define ECC_PR          (AT91_CAST(AT91_REG *)  0x0000000C) // (ECC_PR)  ECC Parity register
402
#define ECC_NPR         (AT91_CAST(AT91_REG *)  0x00000010) // (ECC_NPR)  ECC Parity N register
403
#define ECC_VR          (AT91_CAST(AT91_REG *)  0x000000FC) // (ECC_VR)  ECC Version register
404
 
405
#endif
406
// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- 
407
#define AT91C_ECC_RST         (0x1 <<  0) // (ECC) ECC reset parity
408
// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- 
409
#define AT91C_ECC_PAGE_SIZE   (0x3 <<  0) // (ECC) Nand Flash page size
410
// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- 
411
#define AT91C_ECC_RECERR      (0x1 <<  0) // (ECC) ECC error
412
#define AT91C_ECC_ECCERR      (0x1 <<  1) // (ECC) ECC single error
413
#define AT91C_ECC_MULERR      (0x1 <<  2) // (ECC) ECC_MULERR
414
// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- 
415
#define AT91C_ECC_BITADDR     (0xF <<  0) // (ECC) Bit address error
416
#define AT91C_ECC_WORDADDR    (0xFFF <<  4) // (ECC) address of the failing bit
417
// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- 
418
#define AT91C_ECC_NPARITY     (0xFFFF <<  0) // (ECC) ECC parity N 
419
// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- 
420
#define AT91C_ECC_VR          (0xF <<  0) // (ECC) ECC version register
421
 
422
// *****************************************************************************
423
//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface
424
// *****************************************************************************
425
#ifndef __ASSEMBLY__
426
typedef struct _AT91S_SDRAMC {
427
        AT91_REG         SDRAMC_MR;     // SDRAM Controller Mode Register
428
        AT91_REG         SDRAMC_TR;     // SDRAM Controller Refresh Timer Register
429
        AT91_REG         SDRAMC_CR;     // SDRAM Controller Configuration Register
430
        AT91_REG         SDRAMC_HSR;    // SDRAM Controller High Speed Register
431
        AT91_REG         SDRAMC_LPR;    // SDRAM Controller Low Power Register
432
        AT91_REG         SDRAMC_IER;    // SDRAM Controller Interrupt Enable Register
433
        AT91_REG         SDRAMC_IDR;    // SDRAM Controller Interrupt Disable Register
434
        AT91_REG         SDRAMC_IMR;    // SDRAM Controller Interrupt Mask Register
435
        AT91_REG         SDRAMC_ISR;    // SDRAM Controller Interrupt Mask Register
436
        AT91_REG         SDRAMC_MDR;    // SDRAM Memory Device Register
437
} AT91S_SDRAMC, *AT91PS_SDRAMC;
438
#else
439
#define SDRAMC_MR       (AT91_CAST(AT91_REG *)  0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
440
#define SDRAMC_TR       (AT91_CAST(AT91_REG *)  0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
441
#define SDRAMC_CR       (AT91_CAST(AT91_REG *)  0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
442
#define SDRAMC_HSR      (AT91_CAST(AT91_REG *)  0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
443
#define SDRAMC_LPR      (AT91_CAST(AT91_REG *)  0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
444
#define SDRAMC_IER      (AT91_CAST(AT91_REG *)  0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
445
#define SDRAMC_IDR      (AT91_CAST(AT91_REG *)  0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
446
#define SDRAMC_IMR      (AT91_CAST(AT91_REG *)  0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
447
#define SDRAMC_ISR      (AT91_CAST(AT91_REG *)  0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
448
#define SDRAMC_MDR      (AT91_CAST(AT91_REG *)  0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
449
 
450
#endif
451
// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- 
452
#define AT91C_SDRAMC_MODE     (0xF <<  0) // (SDRAMC) Mode
453
#define         AT91C_SDRAMC_MODE_NORMAL_CMD           (0x0) // (SDRAMC) Normal Mode
454
#define         AT91C_SDRAMC_MODE_NOP_CMD              (0x1) // (SDRAMC) Issue a NOP Command at every access
455
#define         AT91C_SDRAMC_MODE_PRCGALL_CMD          (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
456
#define         AT91C_SDRAMC_MODE_LMR_CMD              (0x3) // (SDRAMC) Issue a Load Mode Register at every access
457
#define         AT91C_SDRAMC_MODE_RFSH_CMD             (0x4) // (SDRAMC) Issue a Refresh
458
#define         AT91C_SDRAMC_MODE_EXT_LMR_CMD          (0x5) // (SDRAMC) Issue an Extended Load Mode Register
459
#define         AT91C_SDRAMC_MODE_DEEP_CMD             (0x6) // (SDRAMC) Enter Deep Power Mode
460
// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- 
461
#define AT91C_SDRAMC_COUNT    (0xFFF <<  0) // (SDRAMC) Refresh Counter
462
// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- 
463
#define AT91C_SDRAMC_NC       (0x3 <<  0) // (SDRAMC) Number of Column Bits
464
#define         AT91C_SDRAMC_NC_8                    (0x0) // (SDRAMC) 8 Bits
465
#define         AT91C_SDRAMC_NC_9                    (0x1) // (SDRAMC) 9 Bits
466
#define         AT91C_SDRAMC_NC_10                   (0x2) // (SDRAMC) 10 Bits
467
#define         AT91C_SDRAMC_NC_11                   (0x3) // (SDRAMC) 11 Bits
468
#define AT91C_SDRAMC_NR       (0x3 <<  2) // (SDRAMC) Number of Row Bits
469
#define         AT91C_SDRAMC_NR_11                   (0x0 <<  2) // (SDRAMC) 11 Bits
470
#define         AT91C_SDRAMC_NR_12                   (0x1 <<  2) // (SDRAMC) 12 Bits
471
#define         AT91C_SDRAMC_NR_13                   (0x2 <<  2) // (SDRAMC) 13 Bits
472
#define AT91C_SDRAMC_NB       (0x1 <<  4) // (SDRAMC) Number of Banks
473
#define         AT91C_SDRAMC_NB_2_BANKS              (0x0 <<  4) // (SDRAMC) 2 banks
474
#define         AT91C_SDRAMC_NB_4_BANKS              (0x1 <<  4) // (SDRAMC) 4 banks
475
#define AT91C_SDRAMC_CAS      (0x3 <<  5) // (SDRAMC) CAS Latency
476
#define         AT91C_SDRAMC_CAS_2                    (0x2 <<  5) // (SDRAMC) 2 cycles
477
#define         AT91C_SDRAMC_CAS_3                    (0x3 <<  5) // (SDRAMC) 3 cycles
478
#define AT91C_SDRAMC_DBW      (0x1 <<  7) // (SDRAMC) Data Bus Width
479
#define         AT91C_SDRAMC_DBW_32_BITS              (0x0 <<  7) // (SDRAMC) 32 Bits datas bus
480
#define         AT91C_SDRAMC_DBW_16_BITS              (0x1 <<  7) // (SDRAMC) 16 Bits datas bus
481
#define AT91C_SDRAMC_TWR      (0xF <<  8) // (SDRAMC) Number of Write Recovery Time Cycles
482
#define         AT91C_SDRAMC_TWR_0                    (0x0 <<  8) // (SDRAMC) Value :  0
483
#define         AT91C_SDRAMC_TWR_1                    (0x1 <<  8) // (SDRAMC) Value :  1
484
#define         AT91C_SDRAMC_TWR_2                    (0x2 <<  8) // (SDRAMC) Value :  2
485
#define         AT91C_SDRAMC_TWR_3                    (0x3 <<  8) // (SDRAMC) Value :  3
486
#define         AT91C_SDRAMC_TWR_4                    (0x4 <<  8) // (SDRAMC) Value :  4
487
#define         AT91C_SDRAMC_TWR_5                    (0x5 <<  8) // (SDRAMC) Value :  5
488
#define         AT91C_SDRAMC_TWR_6                    (0x6 <<  8) // (SDRAMC) Value :  6
489
#define         AT91C_SDRAMC_TWR_7                    (0x7 <<  8) // (SDRAMC) Value :  7
490
#define         AT91C_SDRAMC_TWR_8                    (0x8 <<  8) // (SDRAMC) Value :  8
491
#define         AT91C_SDRAMC_TWR_9                    (0x9 <<  8) // (SDRAMC) Value :  9
492
#define         AT91C_SDRAMC_TWR_10                   (0xA <<  8) // (SDRAMC) Value : 10
493
#define         AT91C_SDRAMC_TWR_11                   (0xB <<  8) // (SDRAMC) Value : 11
494
#define         AT91C_SDRAMC_TWR_12                   (0xC <<  8) // (SDRAMC) Value : 12
495
#define         AT91C_SDRAMC_TWR_13                   (0xD <<  8) // (SDRAMC) Value : 13
496
#define         AT91C_SDRAMC_TWR_14                   (0xE <<  8) // (SDRAMC) Value : 14
497
#define         AT91C_SDRAMC_TWR_15                   (0xF <<  8) // (SDRAMC) Value : 15
498
#define AT91C_SDRAMC_TRC      (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
499
#define         AT91C_SDRAMC_TRC_0                    (0x0 << 12) // (SDRAMC) Value :  0
500
#define         AT91C_SDRAMC_TRC_1                    (0x1 << 12) // (SDRAMC) Value :  1
501
#define         AT91C_SDRAMC_TRC_2                    (0x2 << 12) // (SDRAMC) Value :  2
502
#define         AT91C_SDRAMC_TRC_3                    (0x3 << 12) // (SDRAMC) Value :  3
503
#define         AT91C_SDRAMC_TRC_4                    (0x4 << 12) // (SDRAMC) Value :  4
504
#define         AT91C_SDRAMC_TRC_5                    (0x5 << 12) // (SDRAMC) Value :  5
505
#define         AT91C_SDRAMC_TRC_6                    (0x6 << 12) // (SDRAMC) Value :  6
506
#define         AT91C_SDRAMC_TRC_7                    (0x7 << 12) // (SDRAMC) Value :  7
507
#define         AT91C_SDRAMC_TRC_8                    (0x8 << 12) // (SDRAMC) Value :  8
508
#define         AT91C_SDRAMC_TRC_9                    (0x9 << 12) // (SDRAMC) Value :  9
509
#define         AT91C_SDRAMC_TRC_10                   (0xA << 12) // (SDRAMC) Value : 10
510
#define         AT91C_SDRAMC_TRC_11                   (0xB << 12) // (SDRAMC) Value : 11
511
#define         AT91C_SDRAMC_TRC_12                   (0xC << 12) // (SDRAMC) Value : 12
512
#define         AT91C_SDRAMC_TRC_13                   (0xD << 12) // (SDRAMC) Value : 13
513
#define         AT91C_SDRAMC_TRC_14                   (0xE << 12) // (SDRAMC) Value : 14
514
#define         AT91C_SDRAMC_TRC_15                   (0xF << 12) // (SDRAMC) Value : 15
515
#define AT91C_SDRAMC_TRP      (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
516
#define         AT91C_SDRAMC_TRP_0                    (0x0 << 16) // (SDRAMC) Value :  0
517
#define         AT91C_SDRAMC_TRP_1                    (0x1 << 16) // (SDRAMC) Value :  1
518
#define         AT91C_SDRAMC_TRP_2                    (0x2 << 16) // (SDRAMC) Value :  2
519
#define         AT91C_SDRAMC_TRP_3                    (0x3 << 16) // (SDRAMC) Value :  3
520
#define         AT91C_SDRAMC_TRP_4                    (0x4 << 16) // (SDRAMC) Value :  4
521
#define         AT91C_SDRAMC_TRP_5                    (0x5 << 16) // (SDRAMC) Value :  5
522
#define         AT91C_SDRAMC_TRP_6                    (0x6 << 16) // (SDRAMC) Value :  6
523
#define         AT91C_SDRAMC_TRP_7                    (0x7 << 16) // (SDRAMC) Value :  7
524
#define         AT91C_SDRAMC_TRP_8                    (0x8 << 16) // (SDRAMC) Value :  8
525
#define         AT91C_SDRAMC_TRP_9                    (0x9 << 16) // (SDRAMC) Value :  9
526
#define         AT91C_SDRAMC_TRP_10                   (0xA << 16) // (SDRAMC) Value : 10
527
#define         AT91C_SDRAMC_TRP_11                   (0xB << 16) // (SDRAMC) Value : 11
528
#define         AT91C_SDRAMC_TRP_12                   (0xC << 16) // (SDRAMC) Value : 12
529
#define         AT91C_SDRAMC_TRP_13                   (0xD << 16) // (SDRAMC) Value : 13
530
#define         AT91C_SDRAMC_TRP_14                   (0xE << 16) // (SDRAMC) Value : 14
531
#define         AT91C_SDRAMC_TRP_15                   (0xF << 16) // (SDRAMC) Value : 15
532
#define AT91C_SDRAMC_TRCD     (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
533
#define         AT91C_SDRAMC_TRCD_0                    (0x0 << 20) // (SDRAMC) Value :  0
534
#define         AT91C_SDRAMC_TRCD_1                    (0x1 << 20) // (SDRAMC) Value :  1
535
#define         AT91C_SDRAMC_TRCD_2                    (0x2 << 20) // (SDRAMC) Value :  2
536
#define         AT91C_SDRAMC_TRCD_3                    (0x3 << 20) // (SDRAMC) Value :  3
537
#define         AT91C_SDRAMC_TRCD_4                    (0x4 << 20) // (SDRAMC) Value :  4
538
#define         AT91C_SDRAMC_TRCD_5                    (0x5 << 20) // (SDRAMC) Value :  5
539
#define         AT91C_SDRAMC_TRCD_6                    (0x6 << 20) // (SDRAMC) Value :  6
540
#define         AT91C_SDRAMC_TRCD_7                    (0x7 << 20) // (SDRAMC) Value :  7
541
#define         AT91C_SDRAMC_TRCD_8                    (0x8 << 20) // (SDRAMC) Value :  8
542
#define         AT91C_SDRAMC_TRCD_9                    (0x9 << 20) // (SDRAMC) Value :  9
543
#define         AT91C_SDRAMC_TRCD_10                   (0xA << 20) // (SDRAMC) Value : 10
544
#define         AT91C_SDRAMC_TRCD_11                   (0xB << 20) // (SDRAMC) Value : 11
545
#define         AT91C_SDRAMC_TRCD_12                   (0xC << 20) // (SDRAMC) Value : 12
546
#define         AT91C_SDRAMC_TRCD_13                   (0xD << 20) // (SDRAMC) Value : 13
547
#define         AT91C_SDRAMC_TRCD_14                   (0xE << 20) // (SDRAMC) Value : 14
548
#define         AT91C_SDRAMC_TRCD_15                   (0xF << 20) // (SDRAMC) Value : 15
549
#define AT91C_SDRAMC_TRAS     (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
550
#define         AT91C_SDRAMC_TRAS_0                    (0x0 << 24) // (SDRAMC) Value :  0
551
#define         AT91C_SDRAMC_TRAS_1                    (0x1 << 24) // (SDRAMC) Value :  1
552
#define         AT91C_SDRAMC_TRAS_2                    (0x2 << 24) // (SDRAMC) Value :  2
553
#define         AT91C_SDRAMC_TRAS_3                    (0x3 << 24) // (SDRAMC) Value :  3
554
#define         AT91C_SDRAMC_TRAS_4                    (0x4 << 24) // (SDRAMC) Value :  4
555
#define         AT91C_SDRAMC_TRAS_5                    (0x5 << 24) // (SDRAMC) Value :  5
556
#define         AT91C_SDRAMC_TRAS_6                    (0x6 << 24) // (SDRAMC) Value :  6
557
#define         AT91C_SDRAMC_TRAS_7                    (0x7 << 24) // (SDRAMC) Value :  7
558
#define         AT91C_SDRAMC_TRAS_8                    (0x8 << 24) // (SDRAMC) Value :  8
559
#define         AT91C_SDRAMC_TRAS_9                    (0x9 << 24) // (SDRAMC) Value :  9
560
#define         AT91C_SDRAMC_TRAS_10                   (0xA << 24) // (SDRAMC) Value : 10
561
#define         AT91C_SDRAMC_TRAS_11                   (0xB << 24) // (SDRAMC) Value : 11
562
#define         AT91C_SDRAMC_TRAS_12                   (0xC << 24) // (SDRAMC) Value : 12
563
#define         AT91C_SDRAMC_TRAS_13                   (0xD << 24) // (SDRAMC) Value : 13
564
#define         AT91C_SDRAMC_TRAS_14                   (0xE << 24) // (SDRAMC) Value : 14
565
#define         AT91C_SDRAMC_TRAS_15                   (0xF << 24) // (SDRAMC) Value : 15
566
#define AT91C_SDRAMC_TXSR     (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
567
#define         AT91C_SDRAMC_TXSR_0                    (0x0 << 28) // (SDRAMC) Value :  0
568
#define         AT91C_SDRAMC_TXSR_1                    (0x1 << 28) // (SDRAMC) Value :  1
569
#define         AT91C_SDRAMC_TXSR_2                    (0x2 << 28) // (SDRAMC) Value :  2
570
#define         AT91C_SDRAMC_TXSR_3                    (0x3 << 28) // (SDRAMC) Value :  3
571
#define         AT91C_SDRAMC_TXSR_4                    (0x4 << 28) // (SDRAMC) Value :  4
572
#define         AT91C_SDRAMC_TXSR_5                    (0x5 << 28) // (SDRAMC) Value :  5
573
#define         AT91C_SDRAMC_TXSR_6                    (0x6 << 28) // (SDRAMC) Value :  6
574
#define         AT91C_SDRAMC_TXSR_7                    (0x7 << 28) // (SDRAMC) Value :  7
575
#define         AT91C_SDRAMC_TXSR_8                    (0x8 << 28) // (SDRAMC) Value :  8
576
#define         AT91C_SDRAMC_TXSR_9                    (0x9 << 28) // (SDRAMC) Value :  9
577
#define         AT91C_SDRAMC_TXSR_10                   (0xA << 28) // (SDRAMC) Value : 10
578
#define         AT91C_SDRAMC_TXSR_11                   (0xB << 28) // (SDRAMC) Value : 11
579
#define         AT91C_SDRAMC_TXSR_12                   (0xC << 28) // (SDRAMC) Value : 12
580
#define         AT91C_SDRAMC_TXSR_13                   (0xD << 28) // (SDRAMC) Value : 13
581
#define         AT91C_SDRAMC_TXSR_14                   (0xE << 28) // (SDRAMC) Value : 14
582
#define         AT91C_SDRAMC_TXSR_15                   (0xF << 28) // (SDRAMC) Value : 15
583
// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- 
584
#define AT91C_SDRAMC_DA       (0x1 <<  0) // (SDRAMC) Decode Cycle Enable Bit
585
#define         AT91C_SDRAMC_DA_DISABLE              (0x0) // (SDRAMC) Disable Decode Cycle
586
#define         AT91C_SDRAMC_DA_ENABLE               (0x1) // (SDRAMC) Enable Decode Cycle
587
// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- 
588
#define AT91C_SDRAMC_LPCB     (0x3 <<  0) // (SDRAMC) Low-power Configurations
589
#define         AT91C_SDRAMC_LPCB_DISABLE              (0x0) // (SDRAMC) Disable Low Power Features
590
#define         AT91C_SDRAMC_LPCB_SELF_REFRESH         (0x1) // (SDRAMC) Enable SELF_REFRESH
591
#define         AT91C_SDRAMC_LPCB_POWER_DOWN           (0x2) // (SDRAMC) Enable POWER_DOWN
592
#define         AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN      (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
593
#define AT91C_SDRAMC_PASR     (0x7 <<  4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
594
#define AT91C_SDRAMC_TCSR     (0x3 <<  8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
595
#define AT91C_SDRAMC_DS       (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
596
#define AT91C_SDRAMC_TIMEOUT  (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
597
#define         AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES         (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
598
#define         AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES        (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
599
#define         AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES       (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
600
// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- 
601
#define AT91C_SDRAMC_RES      (0x1 <<  0) // (SDRAMC) Refresh Error Status
602
// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- 
603
// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- 
604
// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- 
605
// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- 
606
#define AT91C_SDRAMC_MD       (0x3 <<  0) // (SDRAMC) Memory Device Type
607
#define         AT91C_SDRAMC_MD_SDRAM                (0x0) // (SDRAMC) SDRAM Mode
608
#define         AT91C_SDRAMC_MD_LOW_POWER_SDRAM      (0x1) // (SDRAMC) SDRAM Low Power Mode
609
 
610
// *****************************************************************************
611
//              SOFTWARE API DEFINITION  FOR Static Memory Controller Interface
612
// *****************************************************************************
613
#ifndef __ASSEMBLY__
614
typedef struct _AT91S_SMC {
615
        AT91_REG         SMC_SETUP0;    //  Setup Register for CS 0
616
        AT91_REG         SMC_PULSE0;    //  Pulse Register for CS 0
617
        AT91_REG         SMC_CYCLE0;    //  Cycle Register for CS 0
618
        AT91_REG         SMC_CTRL0;     //  Control Register for CS 0
619
        AT91_REG         SMC_SETUP1;    //  Setup Register for CS 1
620
        AT91_REG         SMC_PULSE1;    //  Pulse Register for CS 1
621
        AT91_REG         SMC_CYCLE1;    //  Cycle Register for CS 1
622
        AT91_REG         SMC_CTRL1;     //  Control Register for CS 1
623
        AT91_REG         SMC_SETUP2;    //  Setup Register for CS 2
624
        AT91_REG         SMC_PULSE2;    //  Pulse Register for CS 2
625
        AT91_REG         SMC_CYCLE2;    //  Cycle Register for CS 2
626
        AT91_REG         SMC_CTRL2;     //  Control Register for CS 2
627
        AT91_REG         SMC_SETUP3;    //  Setup Register for CS 3
628
        AT91_REG         SMC_PULSE3;    //  Pulse Register for CS 3
629
        AT91_REG         SMC_CYCLE3;    //  Cycle Register for CS 3
630
        AT91_REG         SMC_CTRL3;     //  Control Register for CS 3
631
        AT91_REG         SMC_SETUP4;    //  Setup Register for CS 4
632
        AT91_REG         SMC_PULSE4;    //  Pulse Register for CS 4
633
        AT91_REG         SMC_CYCLE4;    //  Cycle Register for CS 4
634
        AT91_REG         SMC_CTRL4;     //  Control Register for CS 4
635
        AT91_REG         SMC_SETUP5;    //  Setup Register for CS 5
636
        AT91_REG         SMC_PULSE5;    //  Pulse Register for CS 5
637
        AT91_REG         SMC_CYCLE5;    //  Cycle Register for CS 5
638
        AT91_REG         SMC_CTRL5;     //  Control Register for CS 5
639
        AT91_REG         SMC_SETUP6;    //  Setup Register for CS 6
640
        AT91_REG         SMC_PULSE6;    //  Pulse Register for CS 6
641
        AT91_REG         SMC_CYCLE6;    //  Cycle Register for CS 6
642
        AT91_REG         SMC_CTRL6;     //  Control Register for CS 6
643
        AT91_REG         SMC_SETUP7;    //  Setup Register for CS 7
644
        AT91_REG         SMC_PULSE7;    //  Pulse Register for CS 7
645
        AT91_REG         SMC_CYCLE7;    //  Cycle Register for CS 7
646
        AT91_REG         SMC_CTRL7;     //  Control Register for CS 7
647
} AT91S_SMC, *AT91PS_SMC;
648
#else
649
#define SETUP0          (AT91_CAST(AT91_REG *)  0x00000000) // (SETUP0)  Setup Register for CS 0
650
#define PULSE0          (AT91_CAST(AT91_REG *)  0x00000004) // (PULSE0)  Pulse Register for CS 0
651
#define CYCLE0          (AT91_CAST(AT91_REG *)  0x00000008) // (CYCLE0)  Cycle Register for CS 0
652
#define CTRL0           (AT91_CAST(AT91_REG *)  0x0000000C) // (CTRL0)  Control Register for CS 0
653
#define SETUP1          (AT91_CAST(AT91_REG *)  0x00000010) // (SETUP1)  Setup Register for CS 1
654
#define PULSE1          (AT91_CAST(AT91_REG *)  0x00000014) // (PULSE1)  Pulse Register for CS 1
655
#define CYCLE1          (AT91_CAST(AT91_REG *)  0x00000018) // (CYCLE1)  Cycle Register for CS 1
656
#define CTRL1           (AT91_CAST(AT91_REG *)  0x0000001C) // (CTRL1)  Control Register for CS 1
657
#define SETUP2          (AT91_CAST(AT91_REG *)  0x00000020) // (SETUP2)  Setup Register for CS 2
658
#define PULSE2          (AT91_CAST(AT91_REG *)  0x00000024) // (PULSE2)  Pulse Register for CS 2
659
#define CYCLE2          (AT91_CAST(AT91_REG *)  0x00000028) // (CYCLE2)  Cycle Register for CS 2
660
#define CTRL2           (AT91_CAST(AT91_REG *)  0x0000002C) // (CTRL2)  Control Register for CS 2
661
#define SETUP3          (AT91_CAST(AT91_REG *)  0x00000030) // (SETUP3)  Setup Register for CS 3
662
#define PULSE3          (AT91_CAST(AT91_REG *)  0x00000034) // (PULSE3)  Pulse Register for CS 3
663
#define CYCLE3          (AT91_CAST(AT91_REG *)  0x00000038) // (CYCLE3)  Cycle Register for CS 3
664
#define CTRL3           (AT91_CAST(AT91_REG *)  0x0000003C) // (CTRL3)  Control Register for CS 3
665
#define SETUP4          (AT91_CAST(AT91_REG *)  0x00000040) // (SETUP4)  Setup Register for CS 4
666
#define PULSE4          (AT91_CAST(AT91_REG *)  0x00000044) // (PULSE4)  Pulse Register for CS 4
667
#define CYCLE4          (AT91_CAST(AT91_REG *)  0x00000048) // (CYCLE4)  Cycle Register for CS 4
668
#define CTRL4           (AT91_CAST(AT91_REG *)  0x0000004C) // (CTRL4)  Control Register for CS 4
669
#define SETUP5          (AT91_CAST(AT91_REG *)  0x00000050) // (SETUP5)  Setup Register for CS 5
670
#define PULSE5          (AT91_CAST(AT91_REG *)  0x00000054) // (PULSE5)  Pulse Register for CS 5
671
#define CYCLE5          (AT91_CAST(AT91_REG *)  0x00000058) // (CYCLE5)  Cycle Register for CS 5
672
#define CTRL5           (AT91_CAST(AT91_REG *)  0x0000005C) // (CTRL5)  Control Register for CS 5
673
#define SETUP6          (AT91_CAST(AT91_REG *)  0x00000060) // (SETUP6)  Setup Register for CS 6
674
#define PULSE6          (AT91_CAST(AT91_REG *)  0x00000064) // (PULSE6)  Pulse Register for CS 6
675
#define CYCLE6          (AT91_CAST(AT91_REG *)  0x00000068) // (CYCLE6)  Cycle Register for CS 6
676
#define CTRL6           (AT91_CAST(AT91_REG *)  0x0000006C) // (CTRL6)  Control Register for CS 6
677
#define SETUP7          (AT91_CAST(AT91_REG *)  0x00000070) // (SETUP7)  Setup Register for CS 7
678
#define PULSE7          (AT91_CAST(AT91_REG *)  0x00000074) // (PULSE7)  Pulse Register for CS 7
679
#define CYCLE7          (AT91_CAST(AT91_REG *)  0x00000078) // (CYCLE7)  Cycle Register for CS 7
680
#define CTRL7           (AT91_CAST(AT91_REG *)  0x0000007C) // (CTRL7)  Control Register for CS 7
681
 
682
#endif
683
// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- 
684
#define AT91C_SMC_NWESETUP    (0x3F <<  0) // (SMC) NWE Setup Length
685
#define AT91C_SMC_NCSSETUPWR  (0x3F <<  8) // (SMC) NCS Setup Length in WRite Access
686
#define AT91C_SMC_NRDSETUP    (0x3F << 16) // (SMC) NRD Setup Length
687
#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
688
// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- 
689
#define AT91C_SMC_NWEPULSE    (0x7F <<  0) // (SMC) NWE Pulse Length
690
#define AT91C_SMC_NCSPULSEWR  (0x7F <<  8) // (SMC) NCS Pulse Length in WRite Access
691
#define AT91C_SMC_NRDPULSE    (0x7F << 16) // (SMC) NRD Pulse Length
692
#define AT91C_SMC_NCSPULSERD  (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
693
// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- 
694
#define AT91C_SMC_NWECYCLE    (0x1FF <<  0) // (SMC) Total Write Cycle Length
695
#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) // (SMC) Total Read Cycle Length
696
// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- 
697
#define AT91C_SMC_READMODE    (0x1 <<  0) // (SMC) Read Mode
698
#define AT91C_SMC_WRITEMODE   (0x1 <<  1) // (SMC) Write Mode
699
#define AT91C_SMC_NWAITM      (0x3 <<  4) // (SMC) NWAIT Mode
700
#define         AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  4) // (SMC) External NWAIT disabled.
701
#define         AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  4) // (SMC) External NWAIT enabled in frozen mode.
702
#define         AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  4) // (SMC) External NWAIT enabled in ready mode.
703
#define AT91C_SMC_BAT         (0x1 <<  8) // (SMC) Byte Access Type
704
#define         AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
705
#define         AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
706
#define AT91C_SMC_DBW         (0x3 << 12) // (SMC) Data Bus Width
707
#define         AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) // (SMC) 8 bits.
708
#define         AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) // (SMC) 16 bits.
709
#define         AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
710
#define AT91C_SMC_TDF         (0xF << 16) // (SMC) Data Float Time.
711
#define AT91C_SMC_TDFEN       (0x1 << 20) // (SMC) TDF Enabled.
712
#define AT91C_SMC_PMEN        (0x1 << 24) // (SMC) Page Mode Enabled.
713
#define AT91C_SMC_PS          (0x3 << 28) // (SMC) Page Size
714
#define         AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) // (SMC) 4 bytes.
715
#define         AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) // (SMC) 8 bytes.
716
#define         AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) // (SMC) 16 bytes.
717
#define         AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
718
// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- 
719
// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- 
720
// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- 
721
// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- 
722
// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- 
723
// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- 
724
// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- 
725
// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- 
726
// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- 
727
// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- 
728
// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- 
729
// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- 
730
// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- 
731
// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- 
732
// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- 
733
// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- 
734
// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- 
735
// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- 
736
// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- 
737
// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- 
738
// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- 
739
// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- 
740
// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- 
741
// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- 
742
// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- 
743
// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- 
744
// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- 
745
// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- 
746
 
747
// *****************************************************************************
748
//              SOFTWARE API DEFINITION  FOR AHB Matrix Interface
749
// *****************************************************************************
750
#ifndef __ASSEMBLY__
751
typedef struct _AT91S_MATRIX {
752
        AT91_REG         MATRIX_MCFG0;  //  Master Configuration Register 0 (ram96k)     
753
        AT91_REG         MATRIX_MCFG1;  //  Master Configuration Register 1 (rom)    
754
        AT91_REG         MATRIX_MCFG2;  //  Master Configuration Register 2 (hperiphs) 
755
        AT91_REG         MATRIX_MCFG3;  //  Master Configuration Register 3 (ebi)
756
        AT91_REG         MATRIX_MCFG4;  //  Master Configuration Register 4 (bridge)    
757
        AT91_REG         MATRIX_MCFG5;  //  Master Configuration Register 5 (mailbox)    
758
        AT91_REG         MATRIX_MCFG6;  //  Master Configuration Register 6 (ram16k)  
759
        AT91_REG         MATRIX_MCFG7;  //  Master Configuration Register 7 (teak_prog)     
760
        AT91_REG         Reserved0[8];  // 
761
        AT91_REG         MATRIX_SCFG0;  //  Slave Configuration Register 0 (ram96k)     
762
        AT91_REG         MATRIX_SCFG1;  //  Slave Configuration Register 1 (rom)    
763
        AT91_REG         MATRIX_SCFG2;  //  Slave Configuration Register 2 (hperiphs) 
764
        AT91_REG         MATRIX_SCFG3;  //  Slave Configuration Register 3 (ebi)
765
        AT91_REG         MATRIX_SCFG4;  //  Slave Configuration Register 4 (bridge)    
766
        AT91_REG         Reserved1[11];         // 
767
        AT91_REG         MATRIX_PRAS0;  //  PRAS0 (ram0) 
768
        AT91_REG         MATRIX_PRBS0;  //  PRBS0 (ram0) 
769
        AT91_REG         MATRIX_PRAS1;  //  PRAS1 (ram1) 
770
        AT91_REG         MATRIX_PRBS1;  //  PRBS1 (ram1) 
771
        AT91_REG         MATRIX_PRAS2;  //  PRAS2 (ram2) 
772
        AT91_REG         MATRIX_PRBS2;  //  PRBS2 (ram2) 
773
        AT91_REG         MATRIX_PRAS3;  //  PRAS3 : usb_dev_hs
774
        AT91_REG         MATRIX_PRBS3;  //  PRBS3 : usb_dev_hs
775
        AT91_REG         MATRIX_PRAS4;  //  PRAS4 : ebi
776
        AT91_REG         MATRIX_PRBS4;  //  PRBS4 : ebi
777
        AT91_REG         Reserved2[22];         // 
778
        AT91_REG         MATRIX_MRCR;   //  Master Remp Control Register 
779
        AT91_REG         Reserved3[6];  // 
780
        AT91_REG         MATRIX_EBI;    //  Slave 3 (ebi) Special Function Register
781
        AT91_REG         Reserved4[3];  // 
782
        AT91_REG         MATRIX_TEAKCFG;        //  Slave 7 (teak_prog) Special Function Register
783
        AT91_REG         Reserved5[51];         // 
784
        AT91_REG         MATRIX_VERSION;        //  Version Register
785
} AT91S_MATRIX, *AT91PS_MATRIX;
786
#else
787
#define MATRIX_MCFG0    (AT91_CAST(AT91_REG *)  0x00000000) // (MATRIX_MCFG0)  Master Configuration Register 0 (ram96k)     
788
#define MATRIX_MCFG1    (AT91_CAST(AT91_REG *)  0x00000004) // (MATRIX_MCFG1)  Master Configuration Register 1 (rom)    
789
#define MATRIX_MCFG2    (AT91_CAST(AT91_REG *)  0x00000008) // (MATRIX_MCFG2)  Master Configuration Register 2 (hperiphs) 
790
#define MATRIX_MCFG3    (AT91_CAST(AT91_REG *)  0x0000000C) // (MATRIX_MCFG3)  Master Configuration Register 3 (ebi)
791
#define MATRIX_MCFG4    (AT91_CAST(AT91_REG *)  0x00000010) // (MATRIX_MCFG4)  Master Configuration Register 4 (bridge)    
792
#define MATRIX_MCFG5    (AT91_CAST(AT91_REG *)  0x00000014) // (MATRIX_MCFG5)  Master Configuration Register 5 (mailbox)    
793
#define MATRIX_MCFG6    (AT91_CAST(AT91_REG *)  0x00000018) // (MATRIX_MCFG6)  Master Configuration Register 6 (ram16k)  
794
#define MATRIX_MCFG7    (AT91_CAST(AT91_REG *)  0x0000001C) // (MATRIX_MCFG7)  Master Configuration Register 7 (teak_prog)     
795
#define MATRIX_SCFG0    (AT91_CAST(AT91_REG *)  0x00000040) // (MATRIX_SCFG0)  Slave Configuration Register 0 (ram96k)     
796
#define MATRIX_SCFG1    (AT91_CAST(AT91_REG *)  0x00000044) // (MATRIX_SCFG1)  Slave Configuration Register 1 (rom)    
797
#define MATRIX_SCFG2    (AT91_CAST(AT91_REG *)  0x00000048) // (MATRIX_SCFG2)  Slave Configuration Register 2 (hperiphs) 
798
#define MATRIX_SCFG3    (AT91_CAST(AT91_REG *)  0x0000004C) // (MATRIX_SCFG3)  Slave Configuration Register 3 (ebi)
799
#define MATRIX_SCFG4    (AT91_CAST(AT91_REG *)  0x00000050) // (MATRIX_SCFG4)  Slave Configuration Register 4 (bridge)    
800
#define MATRIX_PRAS0    (AT91_CAST(AT91_REG *)  0x00000080) // (MATRIX_PRAS0)  PRAS0 (ram0) 
801
#define MATRIX_PRBS0    (AT91_CAST(AT91_REG *)  0x00000084) // (MATRIX_PRBS0)  PRBS0 (ram0) 
802
#define MATRIX_PRAS1    (AT91_CAST(AT91_REG *)  0x00000088) // (MATRIX_PRAS1)  PRAS1 (ram1) 
803
#define MATRIX_PRBS1    (AT91_CAST(AT91_REG *)  0x0000008C) // (MATRIX_PRBS1)  PRBS1 (ram1) 
804
#define MATRIX_PRAS2    (AT91_CAST(AT91_REG *)  0x00000090) // (MATRIX_PRAS2)  PRAS2 (ram2) 
805
#define MATRIX_PRBS2    (AT91_CAST(AT91_REG *)  0x00000094) // (MATRIX_PRBS2)  PRBS2 (ram2) 
806
#define MATRIX_PRAS3    (AT91_CAST(AT91_REG *)  0x00000098) // (MATRIX_PRAS3)  PRAS3 : usb_dev_hs
807
#define MATRIX_PRBS3    (AT91_CAST(AT91_REG *)  0x0000009C) // (MATRIX_PRBS3)  PRBS3 : usb_dev_hs
808
#define MATRIX_PRAS4    (AT91_CAST(AT91_REG *)  0x000000A0) // (MATRIX_PRAS4)  PRAS4 : ebi
809
#define MATRIX_PRBS4    (AT91_CAST(AT91_REG *)  0x000000A4) // (MATRIX_PRBS4)  PRBS4 : ebi
810
#define MATRIX_MRCR     (AT91_CAST(AT91_REG *)  0x00000100) // (MATRIX_MRCR)  Master Remp Control Register 
811
#define MATRIX_EBI      (AT91_CAST(AT91_REG *)  0x0000011C) // (MATRIX_EBI)  Slave 3 (ebi) Special Function Register
812
#define MATRIX_TEAKCFG  (AT91_CAST(AT91_REG *)  0x0000012C) // (MATRIX_TEAKCFG)  Slave 7 (teak_prog) Special Function Register
813
#define MATRIX_VERSION  (AT91_CAST(AT91_REG *)  0x000001FC) // (MATRIX_VERSION)  Version Register
814
 
815
#endif
816
// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- 
817
#define AT91C_MATRIX_SLOT_CYCLE (0xFF <<  0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
818
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
819
#define         AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
820
#define         AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
821
#define         AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
822
#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
823
#define         AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
824
#define         AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
825
#define         AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
826
#define         AT91C_MATRIX_FIXED_DEFMSTR0_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
827
#define         AT91C_MATRIX_FIXED_DEFMSTR0_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
828
// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- 
829
#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
830
#define         AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
831
#define         AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
832
#define         AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
833
#define         AT91C_MATRIX_FIXED_DEFMSTR1_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
834
#define         AT91C_MATRIX_FIXED_DEFMSTR1_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
835
// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- 
836
#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
837
#define         AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
838
#define         AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
839
// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- 
840
#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
841
#define         AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
842
#define         AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
843
#define         AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
844
#define         AT91C_MATRIX_FIXED_DEFMSTR3_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
845
#define         AT91C_MATRIX_FIXED_DEFMSTR3_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
846
// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- 
847
#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
848
#define         AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
849
#define         AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
850
#define         AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
851
// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- 
852
#define AT91C_MATRIX_M0PR     (0x3 <<  0) // (MATRIX) ARM926EJ-S Instruction priority
853
#define AT91C_MATRIX_M1PR     (0x3 <<  4) // (MATRIX) ARM926EJ-S Data priority
854
#define AT91C_MATRIX_M2PR     (0x3 <<  8) // (MATRIX) PDC priority
855
#define AT91C_MATRIX_M3PR     (0x3 << 12) // (MATRIX) LCDC priority
856
#define AT91C_MATRIX_M4PR     (0x3 << 16) // (MATRIX) 2DGC priority
857
#define AT91C_MATRIX_M5PR     (0x3 << 20) // (MATRIX) ISI priority
858
#define AT91C_MATRIX_M6PR     (0x3 << 24) // (MATRIX) DMA priority
859
#define AT91C_MATRIX_M7PR     (0x3 << 28) // (MATRIX) EMAC priority
860
// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- 
861
#define AT91C_MATRIX_M8PR     (0x3 <<  0) // (MATRIX) USB priority
862
// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- 
863
// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- 
864
// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- 
865
// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- 
866
// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- 
867
// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- 
868
// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- 
869
// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- 
870
// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- 
871
#define AT91C_MATRIX_RCA926I  (0x1 <<  0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
872
#define AT91C_MATRIX_RCA926D  (0x1 <<  1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
873
// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register -------- 
874
#define AT91C_MATRIX_CS1A     (0x1 <<  1) // (MATRIX) Chip Select 1 Assignment
875
#define         AT91C_MATRIX_CS1A_SMC                  (0x0 <<  1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
876
#define         AT91C_MATRIX_CS1A_SDRAMC               (0x1 <<  1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
877
#define AT91C_MATRIX_CS3A     (0x1 <<  3) // (MATRIX) Chip Select 3 Assignment
878
#define         AT91C_MATRIX_CS3A_SMC                  (0x0 <<  3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
879
#define         AT91C_MATRIX_CS3A_SM                   (0x1 <<  3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
880
#define AT91C_MATRIX_CS4A     (0x1 <<  4) // (MATRIX) Chip Select 4 Assignment
881
#define         AT91C_MATRIX_CS4A_SMC                  (0x0 <<  4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
882
#define         AT91C_MATRIX_CS4A_CF                   (0x1 <<  4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
883
#define AT91C_MATRIX_CS5A     (0x1 <<  5) // (MATRIX) Chip Select 5 Assignment
884
#define         AT91C_MATRIX_CS5A_SMC                  (0x0 <<  5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
885
#define         AT91C_MATRIX_CS5A_CF                   (0x1 <<  5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
886
#define AT91C_MATRIX_DBPUC    (0x1 <<  8) // (MATRIX) Data Bus Pull-up Configuration
887
// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register -------- 
888
#define AT91C_TEAK_PROGRAM_ACCESS (0x1 <<  0) // (MATRIX) TEAK program memory access from AHB
889
#define         AT91C_TEAK_PROGRAM_ACCESS_DISABLED             (0x0) // (MATRIX) TEAK program access disabled
890
#define         AT91C_TEAK_PROGRAM_ACCESS_ENABLED              (0x1) // (MATRIX) TEAK program access enabled
891
#define AT91C_TEAK_BOOT       (0x1 <<  1) // (MATRIX) TEAK program start from boot routine
892
#define         AT91C_TEAK_BOOT_DISABLED             (0x0 <<  1) // (MATRIX) TEAK program starts from boot routine disabled
893
#define         AT91C_TEAK_BOOT_ENABLED              (0x1 <<  1) // (MATRIX) TEAK program starts from boot routine enabled
894
#define AT91C_TEAK_NRESET     (0x1 <<  2) // (MATRIX) active low TEAK reset
895
#define         AT91C_TEAK_NRESET_ENABLED              (0x0 <<  2) // (MATRIX) active low TEAK reset enabled
896
#define         AT91C_TEAK_NRESET_DISABLED             (0x1 <<  2) // (MATRIX) active low TEAK reset disabled
897
#define AT91C_TEAK_LVECTORP   (0x3FFFF << 14) // (MATRIX) boot routine start address
898
 
899
// *****************************************************************************
900
//              SOFTWARE API DEFINITION  FOR Chip Configuration Registers
901
// *****************************************************************************
902
#ifndef __ASSEMBLY__
903
typedef struct _AT91S_CCFG {
904
        AT91_REG         Reserved0[3];  // 
905
        AT91_REG         CCFG_EBICSA;   //  EBI Chip Select Assignement Register
906
        AT91_REG         Reserved1[55];         // 
907
        AT91_REG         CCFG_MATRIXVERSION;    //  Version Register
908
} AT91S_CCFG, *AT91PS_CCFG;
909
#else
910
#define CCFG_EBICSA     (AT91_CAST(AT91_REG *)  0x0000000C) // (CCFG_EBICSA)  EBI Chip Select Assignement Register
911
#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *)       0x000000EC) // (CCFG_MATRIXVERSION)  Version Register
912
 
913
#endif
914
// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register -------- 
915
#define AT91C_EBI_CS1A        (0x1 <<  1) // (CCFG) Chip Select 1 Assignment
916
#define         AT91C_EBI_CS1A_SMC                  (0x0 <<  1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
917
#define         AT91C_EBI_CS1A_SDRAMC               (0x1 <<  1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
918
#define AT91C_EBI_CS3A        (0x1 <<  3) // (CCFG) Chip Select 3 Assignment
919
#define         AT91C_EBI_CS3A_SMC                  (0x0 <<  3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
920
#define         AT91C_EBI_CS3A_SM                   (0x1 <<  3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
921
#define AT91C_EBI_CS4A        (0x1 <<  4) // (CCFG) Chip Select 4 Assignment
922
#define         AT91C_EBI_CS4A_SMC                  (0x0 <<  4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
923
#define         AT91C_EBI_CS4A_CF                   (0x1 <<  4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
924
#define AT91C_EBI_CS5A        (0x1 <<  5) // (CCFG) Chip Select 5 Assignment
925
#define         AT91C_EBI_CS5A_SMC                  (0x0 <<  5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
926
#define         AT91C_EBI_CS5A_CF                   (0x1 <<  5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
927
#define AT91C_EBI_DBPUC       (0x1 <<  8) // (CCFG) Data Bus Pull-up Configuration
928
#define AT91C_EBI_SUPPLY      (0x1 << 16) // (CCFG) EBI supply selection
929
 
930
// *****************************************************************************
931
//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
932
// *****************************************************************************
933
#ifndef __ASSEMBLY__
934
typedef struct _AT91S_PDC {
935
        AT91_REG         PDC_RPR;       // Receive Pointer Register
936
        AT91_REG         PDC_RCR;       // Receive Counter Register
937
        AT91_REG         PDC_TPR;       // Transmit Pointer Register
938
        AT91_REG         PDC_TCR;       // Transmit Counter Register
939
        AT91_REG         PDC_RNPR;      // Receive Next Pointer Register
940
        AT91_REG         PDC_RNCR;      // Receive Next Counter Register
941
        AT91_REG         PDC_TNPR;      // Transmit Next Pointer Register
942
        AT91_REG         PDC_TNCR;      // Transmit Next Counter Register
943
        AT91_REG         PDC_PTCR;      // PDC Transfer Control Register
944
        AT91_REG         PDC_PTSR;      // PDC Transfer Status Register
945
} AT91S_PDC, *AT91PS_PDC;
946
#else
947
#define PDC_RPR         (AT91_CAST(AT91_REG *)  0x00000000) // (PDC_RPR) Receive Pointer Register
948
#define PDC_RCR         (AT91_CAST(AT91_REG *)  0x00000004) // (PDC_RCR) Receive Counter Register
949
#define PDC_TPR         (AT91_CAST(AT91_REG *)  0x00000008) // (PDC_TPR) Transmit Pointer Register
950
#define PDC_TCR         (AT91_CAST(AT91_REG *)  0x0000000C) // (PDC_TCR) Transmit Counter Register
951
#define PDC_RNPR        (AT91_CAST(AT91_REG *)  0x00000010) // (PDC_RNPR) Receive Next Pointer Register
952
#define PDC_RNCR        (AT91_CAST(AT91_REG *)  0x00000014) // (PDC_RNCR) Receive Next Counter Register
953
#define PDC_TNPR        (AT91_CAST(AT91_REG *)  0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
954
#define PDC_TNCR        (AT91_CAST(AT91_REG *)  0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
955
#define PDC_PTCR        (AT91_CAST(AT91_REG *)  0x00000020) // (PDC_PTCR) PDC Transfer Control Register
956
#define PDC_PTSR        (AT91_CAST(AT91_REG *)  0x00000024) // (PDC_PTSR) PDC Transfer Status Register
957
 
958
#endif
959
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
960
#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
961
#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
962
#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
963
#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
964
// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
965
 
966
// *****************************************************************************
967
//              SOFTWARE API DEFINITION  FOR Debug Unit
968
// *****************************************************************************
969
#ifndef __ASSEMBLY__
970
typedef struct _AT91S_DBGU {
971
        AT91_REG         DBGU_CR;       // Control Register
972
        AT91_REG         DBGU_MR;       // Mode Register
973
        AT91_REG         DBGU_IER;      // Interrupt Enable Register
974
        AT91_REG         DBGU_IDR;      // Interrupt Disable Register
975
        AT91_REG         DBGU_IMR;      // Interrupt Mask Register
976
        AT91_REG         DBGU_CSR;      // Channel Status Register
977
        AT91_REG         DBGU_RHR;      // Receiver Holding Register
978
        AT91_REG         DBGU_THR;      // Transmitter Holding Register
979
        AT91_REG         DBGU_BRGR;     // Baud Rate Generator Register
980
        AT91_REG         Reserved0[7];  // 
981
        AT91_REG         DBGU_CIDR;     // Chip ID Register
982
        AT91_REG         DBGU_EXID;     // Chip ID Extension Register
983
        AT91_REG         DBGU_FNTR;     // Force NTRST Register
984
        AT91_REG         Reserved1[45];         // 
985
        AT91_REG         DBGU_RPR;      // Receive Pointer Register
986
        AT91_REG         DBGU_RCR;      // Receive Counter Register
987
        AT91_REG         DBGU_TPR;      // Transmit Pointer Register
988
        AT91_REG         DBGU_TCR;      // Transmit Counter Register
989
        AT91_REG         DBGU_RNPR;     // Receive Next Pointer Register
990
        AT91_REG         DBGU_RNCR;     // Receive Next Counter Register
991
        AT91_REG         DBGU_TNPR;     // Transmit Next Pointer Register
992
        AT91_REG         DBGU_TNCR;     // Transmit Next Counter Register
993
        AT91_REG         DBGU_PTCR;     // PDC Transfer Control Register
994
        AT91_REG         DBGU_PTSR;     // PDC Transfer Status Register
995
} AT91S_DBGU, *AT91PS_DBGU;
996
#else
997
#define DBGU_CR         (AT91_CAST(AT91_REG *)  0x00000000) // (DBGU_CR) Control Register
998
#define DBGU_MR         (AT91_CAST(AT91_REG *)  0x00000004) // (DBGU_MR) Mode Register
999
#define DBGU_IER        (AT91_CAST(AT91_REG *)  0x00000008) // (DBGU_IER) Interrupt Enable Register
1000
#define DBGU_IDR        (AT91_CAST(AT91_REG *)  0x0000000C) // (DBGU_IDR) Interrupt Disable Register
1001
#define DBGU_IMR        (AT91_CAST(AT91_REG *)  0x00000010) // (DBGU_IMR) Interrupt Mask Register
1002
#define DBGU_CSR        (AT91_CAST(AT91_REG *)  0x00000014) // (DBGU_CSR) Channel Status Register
1003
#define DBGU_RHR        (AT91_CAST(AT91_REG *)  0x00000018) // (DBGU_RHR) Receiver Holding Register
1004
#define DBGU_THR        (AT91_CAST(AT91_REG *)  0x0000001C) // (DBGU_THR) Transmitter Holding Register
1005
#define DBGU_BRGR       (AT91_CAST(AT91_REG *)  0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
1006
#define DBGU_CIDR       (AT91_CAST(AT91_REG *)  0x00000040) // (DBGU_CIDR) Chip ID Register
1007
#define DBGU_EXID       (AT91_CAST(AT91_REG *)  0x00000044) // (DBGU_EXID) Chip ID Extension Register
1008
#define DBGU_FNTR       (AT91_CAST(AT91_REG *)  0x00000048) // (DBGU_FNTR) Force NTRST Register
1009
 
1010
#endif
1011
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
1012
#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
1013
#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
1014
#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
1015
#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
1016
#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
1017
#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
1018
#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
1019
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
1020
#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
1021
#define         AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
1022
#define         AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
1023
#define         AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
1024
#define         AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
1025
#define         AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
1026
#define         AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
1027
#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
1028
#define         AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
1029
#define         AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
1030
#define         AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
1031
#define         AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
1032
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
1033
#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
1034
#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
1035
#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
1036
#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
1037
#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
1038
#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
1039
#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
1040
#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
1041
#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
1042
#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
1043
#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
1044
#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
1045
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
1046
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
1047
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
1048
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
1049
#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
1050
 
1051
// *****************************************************************************
1052
//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
1053
// *****************************************************************************
1054
#ifndef __ASSEMBLY__
1055
typedef struct _AT91S_AIC {
1056
        AT91_REG         AIC_SMR[32];   // Source Mode Register
1057
        AT91_REG         AIC_SVR[32];   // Source Vector Register
1058
        AT91_REG         AIC_IVR;       // IRQ Vector Register
1059
        AT91_REG         AIC_FVR;       // FIQ Vector Register
1060
        AT91_REG         AIC_ISR;       // Interrupt Status Register
1061
        AT91_REG         AIC_IPR;       // Interrupt Pending Register
1062
        AT91_REG         AIC_IMR;       // Interrupt Mask Register
1063
        AT91_REG         AIC_CISR;      // Core Interrupt Status Register
1064
        AT91_REG         Reserved0[2];  // 
1065
        AT91_REG         AIC_IECR;      // Interrupt Enable Command Register
1066
        AT91_REG         AIC_IDCR;      // Interrupt Disable Command Register
1067
        AT91_REG         AIC_ICCR;      // Interrupt Clear Command Register
1068
        AT91_REG         AIC_ISCR;      // Interrupt Set Command Register
1069
        AT91_REG         AIC_EOICR;     // End of Interrupt Command Register
1070
        AT91_REG         AIC_SPU;       // Spurious Vector Register
1071
        AT91_REG         AIC_DCR;       // Debug Control Register (Protect)
1072
        AT91_REG         Reserved1[1];  // 
1073
        AT91_REG         AIC_FFER;      // Fast Forcing Enable Register
1074
        AT91_REG         AIC_FFDR;      // Fast Forcing Disable Register
1075
        AT91_REG         AIC_FFSR;      // Fast Forcing Status Register
1076
} AT91S_AIC, *AT91PS_AIC;
1077
#else
1078
#define AIC_SMR         (AT91_CAST(AT91_REG *)  0x00000000) // (AIC_SMR) Source Mode Register
1079
#define AIC_SVR         (AT91_CAST(AT91_REG *)  0x00000080) // (AIC_SVR) Source Vector Register
1080
#define AIC_IVR         (AT91_CAST(AT91_REG *)  0x00000100) // (AIC_IVR) IRQ Vector Register
1081
#define AIC_FVR         (AT91_CAST(AT91_REG *)  0x00000104) // (AIC_FVR) FIQ Vector Register
1082
#define AIC_ISR         (AT91_CAST(AT91_REG *)  0x00000108) // (AIC_ISR) Interrupt Status Register
1083
#define AIC_IPR         (AT91_CAST(AT91_REG *)  0x0000010C) // (AIC_IPR) Interrupt Pending Register
1084
#define AIC_IMR         (AT91_CAST(AT91_REG *)  0x00000110) // (AIC_IMR) Interrupt Mask Register
1085
#define AIC_CISR        (AT91_CAST(AT91_REG *)  0x00000114) // (AIC_CISR) Core Interrupt Status Register
1086
#define AIC_IECR        (AT91_CAST(AT91_REG *)  0x00000120) // (AIC_IECR) Interrupt Enable Command Register
1087
#define AIC_IDCR        (AT91_CAST(AT91_REG *)  0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
1088
#define AIC_ICCR        (AT91_CAST(AT91_REG *)  0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
1089
#define AIC_ISCR        (AT91_CAST(AT91_REG *)  0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
1090
#define AIC_EOICR       (AT91_CAST(AT91_REG *)  0x00000130) // (AIC_EOICR) End of Interrupt Command Register
1091
#define AIC_SPU         (AT91_CAST(AT91_REG *)  0x00000134) // (AIC_SPU) Spurious Vector Register
1092
#define AIC_DCR         (AT91_CAST(AT91_REG *)  0x00000138) // (AIC_DCR) Debug Control Register (Protect)
1093
#define AIC_FFER        (AT91_CAST(AT91_REG *)  0x00000140) // (AIC_FFER) Fast Forcing Enable Register
1094
#define AIC_FFDR        (AT91_CAST(AT91_REG *)  0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
1095
#define AIC_FFSR        (AT91_CAST(AT91_REG *)  0x00000148) // (AIC_FFSR) Fast Forcing Status Register
1096
 
1097
#endif
1098
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
1099
#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
1100
#define         AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
1101
#define         AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
1102
#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
1103
#define         AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
1104
#define         AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
1105
#define         AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
1106
#define         AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
1107
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
1108
#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
1109
#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
1110
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
1111
#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
1112
#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
1113
 
1114
// *****************************************************************************
1115
//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
1116
// *****************************************************************************
1117
#ifndef __ASSEMBLY__
1118
typedef struct _AT91S_PIO {
1119
        AT91_REG         PIO_PER;       // PIO Enable Register
1120
        AT91_REG         PIO_PDR;       // PIO Disable Register
1121
        AT91_REG         PIO_PSR;       // PIO Status Register
1122
        AT91_REG         Reserved0[1];  // 
1123
        AT91_REG         PIO_OER;       // Output Enable Register
1124
        AT91_REG         PIO_ODR;       // Output Disable Registerr
1125
        AT91_REG         PIO_OSR;       // Output Status Register
1126
        AT91_REG         Reserved1[1];  // 
1127
        AT91_REG         PIO_IFER;      // Input Filter Enable Register
1128
        AT91_REG         PIO_IFDR;      // Input Filter Disable Register
1129
        AT91_REG         PIO_IFSR;      // Input Filter Status Register
1130
        AT91_REG         Reserved2[1];  // 
1131
        AT91_REG         PIO_SODR;      // Set Output Data Register
1132
        AT91_REG         PIO_CODR;      // Clear Output Data Register
1133
        AT91_REG         PIO_ODSR;      // Output Data Status Register
1134
        AT91_REG         PIO_PDSR;      // Pin Data Status Register
1135
        AT91_REG         PIO_IER;       // Interrupt Enable Register
1136
        AT91_REG         PIO_IDR;       // Interrupt Disable Register
1137
        AT91_REG         PIO_IMR;       // Interrupt Mask Register
1138
        AT91_REG         PIO_ISR;       // Interrupt Status Register
1139
        AT91_REG         PIO_MDER;      // Multi-driver Enable Register
1140
        AT91_REG         PIO_MDDR;      // Multi-driver Disable Register
1141
        AT91_REG         PIO_MDSR;      // Multi-driver Status Register
1142
        AT91_REG         Reserved3[1];  // 
1143
        AT91_REG         PIO_PPUDR;     // Pull-up Disable Register
1144
        AT91_REG         PIO_PPUER;     // Pull-up Enable Register
1145
        AT91_REG         PIO_PPUSR;     // Pull-up Status Register
1146
        AT91_REG         Reserved4[1];  // 
1147
        AT91_REG         PIO_ASR;       // Select A Register
1148
        AT91_REG         PIO_BSR;       // Select B Register
1149
        AT91_REG         PIO_ABSR;      // AB Select Status Register
1150
        AT91_REG         Reserved5[9];  // 
1151
        AT91_REG         PIO_OWER;      // Output Write Enable Register
1152
        AT91_REG         PIO_OWDR;      // Output Write Disable Register
1153
        AT91_REG         PIO_OWSR;      // Output Write Status Register
1154
} AT91S_PIO, *AT91PS_PIO;
1155
#else
1156
#define PIO_PER         (AT91_CAST(AT91_REG *)  0x00000000) // (PIO_PER) PIO Enable Register
1157
#define PIO_PDR         (AT91_CAST(AT91_REG *)  0x00000004) // (PIO_PDR) PIO Disable Register
1158
#define PIO_PSR         (AT91_CAST(AT91_REG *)  0x00000008) // (PIO_PSR) PIO Status Register
1159
#define PIO_OER         (AT91_CAST(AT91_REG *)  0x00000010) // (PIO_OER) Output Enable Register
1160
#define PIO_ODR         (AT91_CAST(AT91_REG *)  0x00000014) // (PIO_ODR) Output Disable Registerr
1161
#define PIO_OSR         (AT91_CAST(AT91_REG *)  0x00000018) // (PIO_OSR) Output Status Register
1162
#define PIO_IFER        (AT91_CAST(AT91_REG *)  0x00000020) // (PIO_IFER) Input Filter Enable Register
1163
#define PIO_IFDR        (AT91_CAST(AT91_REG *)  0x00000024) // (PIO_IFDR) Input Filter Disable Register
1164
#define PIO_IFSR        (AT91_CAST(AT91_REG *)  0x00000028) // (PIO_IFSR) Input Filter Status Register
1165
#define PIO_SODR        (AT91_CAST(AT91_REG *)  0x00000030) // (PIO_SODR) Set Output Data Register
1166
#define PIO_CODR        (AT91_CAST(AT91_REG *)  0x00000034) // (PIO_CODR) Clear Output Data Register
1167
#define PIO_ODSR        (AT91_CAST(AT91_REG *)  0x00000038) // (PIO_ODSR) Output Data Status Register
1168
#define PIO_PDSR        (AT91_CAST(AT91_REG *)  0x0000003C) // (PIO_PDSR) Pin Data Status Register
1169
#define PIO_IER         (AT91_CAST(AT91_REG *)  0x00000040) // (PIO_IER) Interrupt Enable Register
1170
#define PIO_IDR         (AT91_CAST(AT91_REG *)  0x00000044) // (PIO_IDR) Interrupt Disable Register
1171
#define PIO_IMR         (AT91_CAST(AT91_REG *)  0x00000048) // (PIO_IMR) Interrupt Mask Register
1172
#define PIO_ISR         (AT91_CAST(AT91_REG *)  0x0000004C) // (PIO_ISR) Interrupt Status Register
1173
#define PIO_MDER        (AT91_CAST(AT91_REG *)  0x00000050) // (PIO_MDER) Multi-driver Enable Register
1174
#define PIO_MDDR        (AT91_CAST(AT91_REG *)  0x00000054) // (PIO_MDDR) Multi-driver Disable Register
1175
#define PIO_MDSR        (AT91_CAST(AT91_REG *)  0x00000058) // (PIO_MDSR) Multi-driver Status Register
1176
#define PIO_PPUDR       (AT91_CAST(AT91_REG *)  0x00000060) // (PIO_PPUDR) Pull-up Disable Register
1177
#define PIO_PPUER       (AT91_CAST(AT91_REG *)  0x00000064) // (PIO_PPUER) Pull-up Enable Register
1178
#define PIO_PPUSR       (AT91_CAST(AT91_REG *)  0x00000068) // (PIO_PPUSR) Pull-up Status Register
1179
#define PIO_ASR         (AT91_CAST(AT91_REG *)  0x00000070) // (PIO_ASR) Select A Register
1180
#define PIO_BSR         (AT91_CAST(AT91_REG *)  0x00000074) // (PIO_BSR) Select B Register
1181
#define PIO_ABSR        (AT91_CAST(AT91_REG *)  0x00000078) // (PIO_ABSR) AB Select Status Register
1182
#define PIO_OWER        (AT91_CAST(AT91_REG *)  0x000000A0) // (PIO_OWER) Output Write Enable Register
1183
#define PIO_OWDR        (AT91_CAST(AT91_REG *)  0x000000A4) // (PIO_OWDR) Output Write Disable Register
1184
#define PIO_OWSR        (AT91_CAST(AT91_REG *)  0x000000A8) // (PIO_OWSR) Output Write Status Register
1185
 
1186
#endif
1187
 
1188
// *****************************************************************************
1189
//              SOFTWARE API DEFINITION  FOR Embedded Flash Controller 2.0
1190
// *****************************************************************************
1191
#ifndef __ASSEMBLY__
1192
typedef struct _AT91S_EFC {
1193
        AT91_REG         EFC_FMR;       // EFC Flash Mode Register
1194
        AT91_REG         EFC_FCR;       // EFC Flash Command Register
1195
        AT91_REG         EFC_FSR;       // EFC Flash Status Register
1196
        AT91_REG         EFC_FRR;       // EFC Flash Result Register
1197
        AT91_REG         EFC_FVR;       // EFC Flash Version Register
1198
} AT91S_EFC, *AT91PS_EFC;
1199
#else
1200
#define EFC_FMR         (AT91_CAST(AT91_REG *)  0x00000000) // (EFC_FMR) EFC Flash Mode Register
1201
#define EFC_FCR         (AT91_CAST(AT91_REG *)  0x00000004) // (EFC_FCR) EFC Flash Command Register
1202
#define EFC_FSR         (AT91_CAST(AT91_REG *)  0x00000008) // (EFC_FSR) EFC Flash Status Register
1203
#define EFC_FRR         (AT91_CAST(AT91_REG *)  0x0000000C) // (EFC_FRR) EFC Flash Result Register
1204
#define EFC_FVR         (AT91_CAST(AT91_REG *)  0x00000010) // (EFC_FVR) EFC Flash Version Register
1205
 
1206
#endif
1207
// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- 
1208
#define AT91C_EFC_FRDY        (0x1 <<  0) // (EFC) Ready Interrupt Enable
1209
#define AT91C_EFC_FWS         (0xF <<  8) // (EFC) Flash Wait State.
1210
#define         AT91C_EFC_FWS_0WS                  (0x0 <<  8) // (EFC) 0 Wait State
1211
#define         AT91C_EFC_FWS_1WS                  (0x1 <<  8) // (EFC) 1 Wait State
1212
#define         AT91C_EFC_FWS_2WS                  (0x2 <<  8) // (EFC) 2 Wait States
1213
#define         AT91C_EFC_FWS_3WS                  (0x3 <<  8) // (EFC) 3 Wait States
1214
// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- 
1215
#define AT91C_EFC_FCMD        (0xFF <<  0) // (EFC) Flash Command
1216
#define         AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor
1217
#define         AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page
1218
#define         AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock
1219
#define         AT91C_EFC_FCMD_EWP                  (0x3) // (EFC) Erase Page and Write Page
1220
#define         AT91C_EFC_FCMD_EWPL                 (0x4) // (EFC) Erase Page and Write Page then Lock
1221
#define         AT91C_EFC_FCMD_EA                   (0x5) // (EFC) Erase All
1222
#define         AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase Plane
1223
#define         AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase Pages
1224
#define         AT91C_EFC_FCMD_SLB                  (0x8) // (EFC) Set Lock Bit
1225
#define         AT91C_EFC_FCMD_CLB                  (0x9) // (EFC) Clear Lock Bit
1226
#define         AT91C_EFC_FCMD_GLB                  (0xA) // (EFC) Get Lock Bit
1227
#define         AT91C_EFC_FCMD_SFB                  (0xB) // (EFC) Set Fuse Bit
1228
#define         AT91C_EFC_FCMD_CFB                  (0xC) // (EFC) Clear Fuse Bit
1229
#define         AT91C_EFC_FCMD_GFB                  (0xD) // (EFC) Get Fuse Bit
1230
#define AT91C_EFC_FARG        (0xFFFF <<  8) // (EFC) Flash Command Argument
1231
#define AT91C_EFC_FKEY        (0xFF << 24) // (EFC) Flash Writing Protection Key
1232
// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- 
1233
#define AT91C_EFC_FRDY_S      (0x1 <<  0) // (EFC) Flash Ready Status
1234
#define AT91C_EFC_FCMDE       (0x1 <<  1) // (EFC) Flash Command Error Status
1235
#define AT91C_EFC_LOCKE       (0x1 <<  2) // (EFC) Flash Lock Error Status
1236
// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- 
1237
#define AT91C_EFC_FVALUE      (0x0 <<  0) // (EFC) Flash Result Value
1238
 
1239
// *****************************************************************************
1240
//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
1241
// *****************************************************************************
1242
#ifndef __ASSEMBLY__
1243
typedef struct _AT91S_CKGR {
1244
        AT91_REG         CKGR_MOR;      // Main Oscillator Register
1245
        AT91_REG         CKGR_MCFR;     // Main Clock  Frequency Register
1246
        AT91_REG         CKGR_PLLAR;    // PLL A Register
1247
        AT91_REG         CKGR_PLLBR;    // PLL B Register
1248
} AT91S_CKGR, *AT91PS_CKGR;
1249
#else
1250
#define CKGR_MOR        (AT91_CAST(AT91_REG *)  0x00000000) // (CKGR_MOR) Main Oscillator Register
1251
#define CKGR_MCFR       (AT91_CAST(AT91_REG *)  0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
1252
#define CKGR_PLLAR      (AT91_CAST(AT91_REG *)  0x00000008) // (CKGR_PLLAR) PLL A Register
1253
#define CKGR_PLLBR      (AT91_CAST(AT91_REG *)  0x0000000C) // (CKGR_PLLBR) PLL B Register
1254
 
1255
#endif
1256
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
1257
#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
1258
#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
1259
#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
1260
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
1261
#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
1262
#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
1263
// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- 
1264
#define AT91C_CKGR_DIVA       (0xFF <<  0) // (CKGR) Divider A Selected
1265
#define         AT91C_CKGR_DIVA_0                    (0x0) // (CKGR) Divider A output is 0
1266
#define         AT91C_CKGR_DIVA_BYPASS               (0x1) // (CKGR) Divider A is bypassed
1267
#define AT91C_CKGR_PLLACOUNT  (0x3F <<  8) // (CKGR) PLL A Counter
1268
#define AT91C_CKGR_OUTA       (0x3 << 14) // (CKGR) PLL A Output Frequency Range
1269
#define         AT91C_CKGR_OUTA_0                    (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
1270
#define         AT91C_CKGR_OUTA_1                    (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
1271
#define         AT91C_CKGR_OUTA_2                    (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
1272
#define         AT91C_CKGR_OUTA_3                    (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
1273
#define AT91C_CKGR_MULA       (0x7FF << 16) // (CKGR) PLL A Multiplier
1274
#define AT91C_CKGR_SRCA       (0x1 << 29) // (CKGR) 
1275
// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- 
1276
#define AT91C_CKGR_DIVB       (0xFF <<  0) // (CKGR) Divider B Selected
1277
#define         AT91C_CKGR_DIVB_0                    (0x0) // (CKGR) Divider B output is 0
1278
#define         AT91C_CKGR_DIVB_BYPASS               (0x1) // (CKGR) Divider B is bypassed
1279
#define AT91C_CKGR_PLLBCOUNT  (0x3F <<  8) // (CKGR) PLL B Counter
1280
#define AT91C_CKGR_OUTB       (0x3 << 14) // (CKGR) PLL B Output Frequency Range
1281
#define         AT91C_CKGR_OUTB_0                    (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
1282
#define         AT91C_CKGR_OUTB_1                    (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
1283
#define         AT91C_CKGR_OUTB_2                    (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
1284
#define         AT91C_CKGR_OUTB_3                    (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
1285
#define AT91C_CKGR_MULB       (0x7FF << 16) // (CKGR) PLL B Multiplier
1286
#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
1287
#define         AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
1288
#define         AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
1289
#define         AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
1290
 
1291
// *****************************************************************************
1292
//              SOFTWARE API DEFINITION  FOR Power Management Controler
1293
// *****************************************************************************
1294
#ifndef __ASSEMBLY__
1295
typedef struct _AT91S_PMC {
1296
        AT91_REG         PMC_SCER;      // System Clock Enable Register
1297
        AT91_REG         PMC_SCDR;      // System Clock Disable Register
1298
        AT91_REG         PMC_SCSR;      // System Clock Status Register
1299
        AT91_REG         Reserved0[1];  // 
1300
        AT91_REG         PMC_PCER;      // Peripheral Clock Enable Register
1301
        AT91_REG         PMC_PCDR;      // Peripheral Clock Disable Register
1302
        AT91_REG         PMC_PCSR;      // Peripheral Clock Status Register
1303
        AT91_REG         Reserved1[1];  // 
1304
        AT91_REG         PMC_MOR;       // Main Oscillator Register
1305
        AT91_REG         PMC_MCFR;      // Main Clock  Frequency Register
1306
        AT91_REG         PMC_PLLAR;     // PLL A Register
1307
        AT91_REG         PMC_PLLBR;     // PLL B Register
1308
        AT91_REG         PMC_MCKR;      // Master Clock Register
1309
        AT91_REG         Reserved2[3];  // 
1310
        AT91_REG         PMC_PCKR[8];   // Programmable Clock Register
1311
        AT91_REG         PMC_IER;       // Interrupt Enable Register
1312
        AT91_REG         PMC_IDR;       // Interrupt Disable Register
1313
        AT91_REG         PMC_SR;        // Status Register
1314
        AT91_REG         PMC_IMR;       // Interrupt Mask Register
1315
} AT91S_PMC, *AT91PS_PMC;
1316
#else
1317
#define PMC_SCER        (AT91_CAST(AT91_REG *)  0x00000000) // (PMC_SCER) System Clock Enable Register
1318
#define PMC_SCDR        (AT91_CAST(AT91_REG *)  0x00000004) // (PMC_SCDR) System Clock Disable Register
1319
#define PMC_SCSR        (AT91_CAST(AT91_REG *)  0x00000008) // (PMC_SCSR) System Clock Status Register
1320
#define PMC_PCER        (AT91_CAST(AT91_REG *)  0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
1321
#define PMC_PCDR        (AT91_CAST(AT91_REG *)  0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
1322
#define PMC_PCSR        (AT91_CAST(AT91_REG *)  0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
1323
#define PMC_MCKR        (AT91_CAST(AT91_REG *)  0x00000030) // (PMC_MCKR) Master Clock Register
1324
#define PMC_PCKR        (AT91_CAST(AT91_REG *)  0x00000040) // (PMC_PCKR) Programmable Clock Register
1325
#define PMC_IER         (AT91_CAST(AT91_REG *)  0x00000060) // (PMC_IER) Interrupt Enable Register
1326
#define PMC_IDR         (AT91_CAST(AT91_REG *)  0x00000064) // (PMC_IDR) Interrupt Disable Register
1327
#define PMC_SR          (AT91_CAST(AT91_REG *)  0x00000068) // (PMC_SR) Status Register
1328
#define PMC_IMR         (AT91_CAST(AT91_REG *)  0x0000006C) // (PMC_IMR) Interrupt Mask Register
1329
 
1330
#endif
1331
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
1332
#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
1333
#define AT91C_PMC_OTG         (0x1 <<  5) // (PMC) USB OTG Clock
1334
#define AT91C_PMC_UHP         (0x1 <<  6) // (PMC) USB Host Port Clock
1335
#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
1336
#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
1337
#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
1338
#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
1339
#define AT91C_PMC_PCK3        (0x1 << 11) // (PMC) Programmable Clock Output
1340
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
1341
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
1342
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
1343
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
1344
// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- 
1345
// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- 
1346
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
1347
#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
1348
#define         AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
1349
#define         AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
1350
#define         AT91C_PMC_CSS_PLLA_CLK             (0x2) // (PMC) Clock from PLL A is selected
1351
#define         AT91C_PMC_CSS_PLLB_CLK             (0x3) // (PMC) Clock from PLL B is selected
1352
#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
1353
#define         AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
1354
#define         AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
1355
#define         AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
1356
#define         AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
1357
#define         AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
1358
#define         AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
1359
#define         AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
1360
#define AT91C_PMC_MDIV        (0x3 <<  8) // (PMC) Master Clock Division
1361
#define         AT91C_PMC_MDIV_1                    (0x0 <<  8) // (PMC) The master clock and the processor clock are the same
1362
#define         AT91C_PMC_MDIV_2                    (0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock
1363
#define         AT91C_PMC_MDIV_3                    (0x2 <<  8) // (PMC) The processor clock is four times faster than the master clock
1364
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
1365
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
1366
#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
1367
#define AT91C_PMC_LOCKA       (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask
1368
#define AT91C_PMC_LOCKB       (0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask
1369
#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) Master Clock Status/Enable/Disable/Mask
1370
#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
1371
#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
1372
#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
1373
#define AT91C_PMC_PCK3RDY     (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
1374
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
1375
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
1376
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
1377
 
1378
// *****************************************************************************
1379
//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
1380
// *****************************************************************************
1381
#ifndef __ASSEMBLY__
1382
typedef struct _AT91S_RSTC {
1383
        AT91_REG         RSTC_RCR;      // Reset Control Register
1384
        AT91_REG         RSTC_RSR;      // Reset Status Register
1385
        AT91_REG         RSTC_RMR;      // Reset Mode Register
1386
} AT91S_RSTC, *AT91PS_RSTC;
1387
#else
1388
#define RSTC_RCR        (AT91_CAST(AT91_REG *)  0x00000000) // (RSTC_RCR) Reset Control Register
1389
#define RSTC_RSR        (AT91_CAST(AT91_REG *)  0x00000004) // (RSTC_RSR) Reset Status Register
1390
#define RSTC_RMR        (AT91_CAST(AT91_REG *)  0x00000008) // (RSTC_RMR) Reset Mode Register
1391
 
1392
#endif
1393
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
1394
#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
1395
#define AT91C_RSTC_ICERST     (0x1 <<  1) // (RSTC) ICE Interface Reset
1396
#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
1397
#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
1398
#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
1399
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
1400
#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
1401
#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
1402
#define         AT91C_RSTC_RSTTYP_GENERAL              (0x0 <<  8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
1403
#define         AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
1404
#define         AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
1405
#define         AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
1406
#define         AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
1407
#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
1408
#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
1409
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
1410
#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
1411
#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
1412
#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Enable
1413
 
1414
// *****************************************************************************
1415
//              SOFTWARE API DEFINITION  FOR Shut Down Controller Interface
1416
// *****************************************************************************
1417
#ifndef __ASSEMBLY__
1418
typedef struct _AT91S_SHDWC {
1419
        AT91_REG         SHDWC_SHCR;    // Shut Down Control Register
1420
        AT91_REG         SHDWC_SHMR;    // Shut Down Mode Register
1421
        AT91_REG         SHDWC_SHSR;    // Shut Down Status Register
1422
} AT91S_SHDWC, *AT91PS_SHDWC;
1423
#else
1424
#define SHDWC_SHCR      (AT91_CAST(AT91_REG *)  0x00000000) // (SHDWC_SHCR) Shut Down Control Register
1425
#define SHDWC_SHMR      (AT91_CAST(AT91_REG *)  0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
1426
#define SHDWC_SHSR      (AT91_CAST(AT91_REG *)  0x00000008) // (SHDWC_SHSR) Shut Down Status Register
1427
 
1428
#endif
1429
// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- 
1430
#define AT91C_SHDWC_SHDW      (0x1 <<  0) // (SHDWC) Processor Reset
1431
#define AT91C_SHDWC_KEY       (0xFF << 24) // (SHDWC) Shut down KEY Password
1432
// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- 
1433
#define AT91C_SHDWC_WKMODE0   (0x3 <<  0) // (SHDWC) Wake Up 0 Mode Selection
1434
#define         AT91C_SHDWC_WKMODE0_NONE                 (0x0) // (SHDWC) None. No detection is performed on the wake up input.
1435
#define         AT91C_SHDWC_WKMODE0_HIGH                 (0x1) // (SHDWC) High Level.
1436
#define         AT91C_SHDWC_WKMODE0_LOW                  (0x2) // (SHDWC) Low Level.
1437
#define         AT91C_SHDWC_WKMODE0_ANYLEVEL             (0x3) // (SHDWC) Any level change.
1438
#define AT91C_SHDWC_CPTWK0    (0xF <<  4) // (SHDWC) Counter On Wake Up 0
1439
#define AT91C_SHDWC_WKMODE1   (0x3 <<  8) // (SHDWC) Wake Up 1 Mode Selection
1440
#define         AT91C_SHDWC_WKMODE1_NONE                 (0x0 <<  8) // (SHDWC) None. No detection is performed on the wake up input.
1441
#define         AT91C_SHDWC_WKMODE1_HIGH                 (0x1 <<  8) // (SHDWC) High Level.
1442
#define         AT91C_SHDWC_WKMODE1_LOW                  (0x2 <<  8) // (SHDWC) Low Level.
1443
#define         AT91C_SHDWC_WKMODE1_ANYLEVEL             (0x3 <<  8) // (SHDWC) Any level change.
1444
#define AT91C_SHDWC_CPTWK1    (0xF << 12) // (SHDWC) Counter On Wake Up 1
1445
#define AT91C_SHDWC_RTTWKEN   (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
1446
#define AT91C_SHDWC_RTCWKEN   (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable
1447
// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- 
1448
#define AT91C_SHDWC_WAKEUP0   (0x1 <<  0) // (SHDWC) Wake Up 0 Status
1449
#define AT91C_SHDWC_WAKEUP1   (0x1 <<  1) // (SHDWC) Wake Up 1 Status
1450
#define AT91C_SHDWC_FWKUP     (0x1 <<  2) // (SHDWC) Force Wake Up Status
1451
#define AT91C_SHDWC_RTTWK     (0x1 << 16) // (SHDWC) Real Time Timer wake Up
1452
#define AT91C_SHDWC_RTCWK     (0x1 << 17) // (SHDWC) Real Time Clock wake Up
1453
 
1454
// *****************************************************************************
1455
//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
1456
// *****************************************************************************
1457
#ifndef __ASSEMBLY__
1458
typedef struct _AT91S_RTTC {
1459
        AT91_REG         RTTC_RTMR;     // Real-time Mode Register
1460
        AT91_REG         RTTC_RTAR;     // Real-time Alarm Register
1461
        AT91_REG         RTTC_RTVR;     // Real-time Value Register
1462
        AT91_REG         RTTC_RTSR;     // Real-time Status Register
1463
} AT91S_RTTC, *AT91PS_RTTC;
1464
#else
1465
#define RTTC_RTMR       (AT91_CAST(AT91_REG *)  0x00000000) // (RTTC_RTMR) Real-time Mode Register
1466
#define RTTC_RTAR       (AT91_CAST(AT91_REG *)  0x00000004) // (RTTC_RTAR) Real-time Alarm Register
1467
#define RTTC_RTVR       (AT91_CAST(AT91_REG *)  0x00000008) // (RTTC_RTVR) Real-time Value Register
1468
#define RTTC_RTSR       (AT91_CAST(AT91_REG *)  0x0000000C) // (RTTC_RTSR) Real-time Status Register
1469
 
1470
#endif
1471
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
1472
#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
1473
#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
1474
#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
1475
#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
1476
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
1477
#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
1478
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
1479
#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
1480
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
1481
#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
1482
#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
1483
 
1484
// *****************************************************************************
1485
//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
1486
// *****************************************************************************
1487
#ifndef __ASSEMBLY__
1488
typedef struct _AT91S_PITC {
1489
        AT91_REG         PITC_PIMR;     // Period Interval Mode Register
1490
        AT91_REG         PITC_PISR;     // Period Interval Status Register
1491
        AT91_REG         PITC_PIVR;     // Period Interval Value Register
1492
        AT91_REG         PITC_PIIR;     // Period Interval Image Register
1493
} AT91S_PITC, *AT91PS_PITC;
1494
#else
1495
#define PITC_PIMR       (AT91_CAST(AT91_REG *)  0x00000000) // (PITC_PIMR) Period Interval Mode Register
1496
#define PITC_PISR       (AT91_CAST(AT91_REG *)  0x00000004) // (PITC_PISR) Period Interval Status Register
1497
#define PITC_PIVR       (AT91_CAST(AT91_REG *)  0x00000008) // (PITC_PIVR) Period Interval Value Register
1498
#define PITC_PIIR       (AT91_CAST(AT91_REG *)  0x0000000C) // (PITC_PIIR) Period Interval Image Register
1499
 
1500
#endif
1501
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
1502
#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
1503
#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
1504
#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
1505
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
1506
#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
1507
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
1508
#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
1509
#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
1510
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
1511
 
1512
// *****************************************************************************
1513
//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
1514
// *****************************************************************************
1515
#ifndef __ASSEMBLY__
1516
typedef struct _AT91S_WDTC {
1517
        AT91_REG         WDTC_WDCR;     // Watchdog Control Register
1518
        AT91_REG         WDTC_WDMR;     // Watchdog Mode Register
1519
        AT91_REG         WDTC_WDSR;     // Watchdog Status Register
1520
} AT91S_WDTC, *AT91PS_WDTC;
1521
#else
1522
#define WDTC_WDCR       (AT91_CAST(AT91_REG *)  0x00000000) // (WDTC_WDCR) Watchdog Control Register
1523
#define WDTC_WDMR       (AT91_CAST(AT91_REG *)  0x00000004) // (WDTC_WDMR) Watchdog Mode Register
1524
#define WDTC_WDSR       (AT91_CAST(AT91_REG *)  0x00000008) // (WDTC_WDSR) Watchdog Status Register
1525
 
1526
#endif
1527
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
1528
#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
1529
#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
1530
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
1531
#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
1532
#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
1533
#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
1534
#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
1535
#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
1536
#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
1537
#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
1538
#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
1539
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
1540
#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
1541
#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
1542
 
1543
// *****************************************************************************
1544
//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
1545
// *****************************************************************************
1546
#ifndef __ASSEMBLY__
1547
typedef struct _AT91S_TC {
1548
        AT91_REG         TC_CCR;        // Channel Control Register
1549
        AT91_REG         TC_CMR;        // Channel Mode Register (Capture Mode / Waveform Mode)
1550
        AT91_REG         Reserved0[2];  // 
1551
        AT91_REG         TC_CV;         // Counter Value
1552
        AT91_REG         TC_RA;         // Register A
1553
        AT91_REG         TC_RB;         // Register B
1554
        AT91_REG         TC_RC;         // Register C
1555
        AT91_REG         TC_SR;         // Status Register
1556
        AT91_REG         TC_IER;        // Interrupt Enable Register
1557
        AT91_REG         TC_IDR;        // Interrupt Disable Register
1558
        AT91_REG         TC_IMR;        // Interrupt Mask Register
1559
} AT91S_TC, *AT91PS_TC;
1560
#else
1561
#define TC_CCR          (AT91_CAST(AT91_REG *)  0x00000000) // (TC_CCR) Channel Control Register
1562
#define TC_CMR          (AT91_CAST(AT91_REG *)  0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
1563
#define TC_CV           (AT91_CAST(AT91_REG *)  0x00000010) // (TC_CV) Counter Value
1564
#define TC_RA           (AT91_CAST(AT91_REG *)  0x00000014) // (TC_RA) Register A
1565
#define TC_RB           (AT91_CAST(AT91_REG *)  0x00000018) // (TC_RB) Register B
1566
#define TC_RC           (AT91_CAST(AT91_REG *)  0x0000001C) // (TC_RC) Register C
1567
#define TC_SR           (AT91_CAST(AT91_REG *)  0x00000020) // (TC_SR) Status Register
1568
#define TC_IER          (AT91_CAST(AT91_REG *)  0x00000024) // (TC_IER) Interrupt Enable Register
1569
#define TC_IDR          (AT91_CAST(AT91_REG *)  0x00000028) // (TC_IDR) Interrupt Disable Register
1570
#define TC_IMR          (AT91_CAST(AT91_REG *)  0x0000002C) // (TC_IMR) Interrupt Mask Register
1571
 
1572
#endif
1573
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
1574
#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
1575
#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
1576
#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
1577
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
1578
#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
1579
#define         AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
1580
#define         AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
1581
#define         AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
1582
#define         AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
1583
#define         AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
1584
#define         AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
1585
#define         AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
1586
#define         AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
1587
#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
1588
#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
1589
#define         AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
1590
#define         AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
1591
#define         AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
1592
#define         AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
1593
#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
1594
#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
1595
#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
1596
#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
1597
#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
1598
#define         AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
1599
#define         AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
1600
#define         AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
1601
#define         AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
1602
#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
1603
#define         AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
1604
#define         AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
1605
#define         AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
1606
#define         AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
1607
#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
1608
#define         AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
1609
#define         AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
1610
#define         AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
1611
#define         AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
1612
#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
1613
#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
1614
#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
1615
#define         AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
1616
#define         AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
1617
#define         AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
1618
#define         AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
1619
#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
1620
#define AT91C_TC_WAVE         (0x1 << 15) // (TC) 
1621
#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
1622
#define         AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
1623
#define         AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
1624
#define         AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
1625
#define         AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
1626
#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
1627
#define         AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
1628
#define         AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
1629
#define         AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
1630
#define         AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
1631
#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
1632
#define         AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
1633
#define         AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
1634
#define         AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
1635
#define         AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
1636
#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
1637
#define         AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
1638
#define         AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
1639
#define         AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
1640
#define         AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
1641
#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
1642
#define         AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
1643
#define         AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
1644
#define         AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
1645
#define         AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
1646
#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
1647
#define         AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
1648
#define         AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
1649
#define         AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
1650
#define         AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
1651
#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
1652
#define         AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
1653
#define         AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
1654
#define         AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
1655
#define         AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
1656
#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
1657
#define         AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
1658
#define         AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
1659
#define         AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
1660
#define         AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
1661
#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
1662
#define         AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
1663
#define         AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
1664
#define         AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
1665
#define         AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
1666
#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
1667
#define         AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
1668
#define         AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
1669
#define         AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
1670
#define         AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
1671
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
1672
#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
1673
#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
1674
#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
1675
#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
1676
#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
1677
#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
1678
#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
1679
#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
1680
#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
1681
#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
1682
#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
1683
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
1684
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
1685
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
1686
 
1687
// *****************************************************************************
1688
//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
1689
// *****************************************************************************
1690
#ifndef __ASSEMBLY__
1691
typedef struct _AT91S_TCB {
1692
        AT91S_TC         TCB_TC0;       // TC Channel 0
1693
        AT91_REG         Reserved0[4];  // 
1694
        AT91S_TC         TCB_TC1;       // TC Channel 1
1695
        AT91_REG         Reserved1[4];  // 
1696
        AT91S_TC         TCB_TC2;       // TC Channel 2
1697
        AT91_REG         Reserved2[4];  // 
1698
        AT91_REG         TCB_BCR;       // TC Block Control Register
1699
        AT91_REG         TCB_BMR;       // TC Block Mode Register
1700
} AT91S_TCB, *AT91PS_TCB;
1701
#else
1702
#define TCB_BCR         (AT91_CAST(AT91_REG *)  0x000000C0) // (TCB_BCR) TC Block Control Register
1703
#define TCB_BMR         (AT91_CAST(AT91_REG *)  0x000000C4) // (TCB_BMR) TC Block Mode Register
1704
 
1705
#endif
1706
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
1707
#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
1708
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
1709
#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
1710
#define         AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
1711
#define         AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
1712
#define         AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
1713
#define         AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
1714
#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
1715
#define         AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
1716
#define         AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
1717
#define         AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
1718
#define         AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
1719
#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
1720
#define         AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
1721
#define         AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
1722
#define         AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
1723
#define         AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
1724
 
1725
// *****************************************************************************
1726
//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
1727
// *****************************************************************************
1728
#ifndef __ASSEMBLY__
1729
typedef struct _AT91S_MCI {
1730
        AT91_REG         MCI_CR;        // MCI Control Register
1731
        AT91_REG         MCI_MR;        // MCI Mode Register
1732
        AT91_REG         MCI_DTOR;      // MCI Data Timeout Register
1733
        AT91_REG         MCI_SDCR;      // MCI SD Card Register
1734
        AT91_REG         MCI_ARGR;      // MCI Argument Register
1735
        AT91_REG         MCI_CMDR;      // MCI Command Register
1736
        AT91_REG         MCI_BLKR;      // MCI Block Register
1737
        AT91_REG         Reserved0[1];  // 
1738
        AT91_REG         MCI_RSPR[4];   // MCI Response Register
1739
        AT91_REG         MCI_RDR;       // MCI Receive Data Register
1740
        AT91_REG         MCI_TDR;       // MCI Transmit Data Register
1741
        AT91_REG         Reserved1[2];  // 
1742
        AT91_REG         MCI_SR;        // MCI Status Register
1743
        AT91_REG         MCI_IER;       // MCI Interrupt Enable Register
1744
        AT91_REG         MCI_IDR;       // MCI Interrupt Disable Register
1745
        AT91_REG         MCI_IMR;       // MCI Interrupt Mask Register
1746
        AT91_REG         Reserved2[43];         // 
1747
        AT91_REG         MCI_VR;        // MCI Version Register
1748
        AT91_REG         MCI_RPR;       // Receive Pointer Register
1749
        AT91_REG         MCI_RCR;       // Receive Counter Register
1750
        AT91_REG         MCI_TPR;       // Transmit Pointer Register
1751
        AT91_REG         MCI_TCR;       // Transmit Counter Register
1752
        AT91_REG         MCI_RNPR;      // Receive Next Pointer Register
1753
        AT91_REG         MCI_RNCR;      // Receive Next Counter Register
1754
        AT91_REG         MCI_TNPR;      // Transmit Next Pointer Register
1755
        AT91_REG         MCI_TNCR;      // Transmit Next Counter Register
1756
        AT91_REG         MCI_PTCR;      // PDC Transfer Control Register
1757
        AT91_REG         MCI_PTSR;      // PDC Transfer Status Register
1758
} AT91S_MCI, *AT91PS_MCI;
1759
#else
1760
#define MCI_CR          (AT91_CAST(AT91_REG *)  0x00000000) // (MCI_CR) MCI Control Register
1761
#define MCI_MR          (AT91_CAST(AT91_REG *)  0x00000004) // (MCI_MR) MCI Mode Register
1762
#define MCI_DTOR        (AT91_CAST(AT91_REG *)  0x00000008) // (MCI_DTOR) MCI Data Timeout Register
1763
#define MCI_SDCR        (AT91_CAST(AT91_REG *)  0x0000000C) // (MCI_SDCR) MCI SD Card Register
1764
#define MCI_ARGR        (AT91_CAST(AT91_REG *)  0x00000010) // (MCI_ARGR) MCI Argument Register
1765
#define MCI_CMDR        (AT91_CAST(AT91_REG *)  0x00000014) // (MCI_CMDR) MCI Command Register
1766
#define MCI_BLKR        (AT91_CAST(AT91_REG *)  0x00000018) // (MCI_BLKR) MCI Block Register
1767
#define MCI_RSPR        (AT91_CAST(AT91_REG *)  0x00000020) // (MCI_RSPR) MCI Response Register
1768
#define MCI_RDR         (AT91_CAST(AT91_REG *)  0x00000030) // (MCI_RDR) MCI Receive Data Register
1769
#define MCI_TDR         (AT91_CAST(AT91_REG *)  0x00000034) // (MCI_TDR) MCI Transmit Data Register
1770
#define MCI_SR          (AT91_CAST(AT91_REG *)  0x00000040) // (MCI_SR) MCI Status Register
1771
#define MCI_IER         (AT91_CAST(AT91_REG *)  0x00000044) // (MCI_IER) MCI Interrupt Enable Register
1772
#define MCI_IDR         (AT91_CAST(AT91_REG *)  0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
1773
#define MCI_IMR         (AT91_CAST(AT91_REG *)  0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
1774
#define MCI_VR          (AT91_CAST(AT91_REG *)  0x000000FC) // (MCI_VR) MCI Version Register
1775
 
1776
#endif
1777
// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 
1778
#define AT91C_MCI_MCIEN       (0x1 <<  0) // (MCI) Multimedia Interface Enable
1779
#define AT91C_MCI_MCIDIS      (0x1 <<  1) // (MCI) Multimedia Interface Disable
1780
#define AT91C_MCI_PWSEN       (0x1 <<  2) // (MCI) Power Save Mode Enable
1781
#define AT91C_MCI_PWSDIS      (0x1 <<  3) // (MCI) Power Save Mode Disable
1782
#define AT91C_MCI_SWRST       (0x1 <<  7) // (MCI) MCI Software reset
1783
// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 
1784
#define AT91C_MCI_CLKDIV      (0xFF <<  0) // (MCI) Clock Divider
1785
#define AT91C_MCI_PWSDIV      (0x7 <<  8) // (MCI) Power Saving Divider
1786
#define AT91C_MCI_RDPROOF     (0x1 << 11) // (MCI) Read Proof Enable
1787
#define AT91C_MCI_WRPROOF     (0x1 << 12) // (MCI) Write Proof Enable
1788
#define AT91C_MCI_PDCFBYTE    (0x1 << 13) // (MCI) PDC Force Byte Transfer
1789
#define AT91C_MCI_PDCPADV     (0x1 << 14) // (MCI) PDC Padding Value
1790
#define AT91C_MCI_PDCMODE     (0x1 << 15) // (MCI) PDC Oriented Mode
1791
#define AT91C_MCI_BLKLEN      (0xFFFF << 16) // (MCI) Data Block Length
1792
// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 
1793
#define AT91C_MCI_DTOCYC      (0xF <<  0) // (MCI) Data Timeout Cycle Number
1794
#define AT91C_MCI_DTOMUL      (0x7 <<  4) // (MCI) Data Timeout Multiplier
1795
#define         AT91C_MCI_DTOMUL_1                    (0x0 <<  4) // (MCI) DTOCYC x 1
1796
#define         AT91C_MCI_DTOMUL_16                   (0x1 <<  4) // (MCI) DTOCYC x 16
1797
#define         AT91C_MCI_DTOMUL_128                  (0x2 <<  4) // (MCI) DTOCYC x 128
1798
#define         AT91C_MCI_DTOMUL_256                  (0x3 <<  4) // (MCI) DTOCYC x 256
1799
#define         AT91C_MCI_DTOMUL_1024                 (0x4 <<  4) // (MCI) DTOCYC x 1024
1800
#define         AT91C_MCI_DTOMUL_4096                 (0x5 <<  4) // (MCI) DTOCYC x 4096
1801
#define         AT91C_MCI_DTOMUL_65536                (0x6 <<  4) // (MCI) DTOCYC x 65536
1802
#define         AT91C_MCI_DTOMUL_1048576              (0x7 <<  4) // (MCI) DTOCYC x 1048576
1803
// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 
1804
#define AT91C_MCI_SCDSEL      (0x3 <<  0) // (MCI) SD Card Selector
1805
#define AT91C_MCI_SCDBUS      (0x1 <<  7) // (MCI) SDCard/SDIO Bus Width
1806
// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 
1807
#define AT91C_MCI_CMDNB       (0x3F <<  0) // (MCI) Command Number
1808
#define AT91C_MCI_RSPTYP      (0x3 <<  6) // (MCI) Response Type
1809
#define         AT91C_MCI_RSPTYP_NO                   (0x0 <<  6) // (MCI) No response
1810
#define         AT91C_MCI_RSPTYP_48                   (0x1 <<  6) // (MCI) 48-bit response
1811
#define         AT91C_MCI_RSPTYP_136                  (0x2 <<  6) // (MCI) 136-bit response
1812
#define AT91C_MCI_SPCMD       (0x7 <<  8) // (MCI) Special CMD
1813
#define         AT91C_MCI_SPCMD_NONE                 (0x0 <<  8) // (MCI) Not a special CMD
1814
#define         AT91C_MCI_SPCMD_INIT                 (0x1 <<  8) // (MCI) Initialization CMD
1815
#define         AT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) // (MCI) Synchronized CMD
1816
#define         AT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) // (MCI) Interrupt command
1817
#define         AT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) // (MCI) Interrupt response
1818
#define AT91C_MCI_OPDCMD      (0x1 << 11) // (MCI) Open Drain Command
1819
#define AT91C_MCI_MAXLAT      (0x1 << 12) // (MCI) Maximum Latency for Command to respond
1820
#define AT91C_MCI_TRCMD       (0x3 << 16) // (MCI) Transfer CMD
1821
#define         AT91C_MCI_TRCMD_NO                   (0x0 << 16) // (MCI) No transfer
1822
#define         AT91C_MCI_TRCMD_START                (0x1 << 16) // (MCI) Start transfer
1823
#define         AT91C_MCI_TRCMD_STOP                 (0x2 << 16) // (MCI) Stop transfer
1824
#define AT91C_MCI_TRDIR       (0x1 << 18) // (MCI) Transfer Direction
1825
#define AT91C_MCI_TRTYP       (0x7 << 19) // (MCI) Transfer Type
1826
#define         AT91C_MCI_TRTYP_BLOCK                (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
1827
#define         AT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
1828
#define         AT91C_MCI_TRTYP_STREAM               (0x2 << 19) // (MCI) MMC Stream transfer type
1829
#define         AT91C_MCI_TRTYP_SDIO_BYTE            (0x4 << 19) // (MCI) SDIO Byte transfer type
1830
#define         AT91C_MCI_TRTYP_SDIO_BLOCK           (0x5 << 19) // (MCI) SDIO Block transfer type
1831
#define AT91C_MCI_IOSPCMD     (0x3 << 24) // (MCI) SDIO Special Command
1832
#define         AT91C_MCI_IOSPCMD_NONE                 (0x0 << 24) // (MCI) NOT a special command
1833
#define         AT91C_MCI_IOSPCMD_SUSPEND              (0x1 << 24) // (MCI) SDIO Suspend Command
1834
#define         AT91C_MCI_IOSPCMD_RESUME               (0x2 << 24) // (MCI) SDIO Resume Command
1835
// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- 
1836
#define AT91C_MCI_BCNT        (0xFFFF <<  0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
1837
// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 
1838
#define AT91C_MCI_CMDRDY      (0x1 <<  0) // (MCI) Command Ready flag
1839
#define AT91C_MCI_RXRDY       (0x1 <<  1) // (MCI) RX Ready flag
1840
#define AT91C_MCI_TXRDY       (0x1 <<  2) // (MCI) TX Ready flag
1841
#define AT91C_MCI_BLKE        (0x1 <<  3) // (MCI) Data Block Transfer Ended flag
1842
#define AT91C_MCI_DTIP        (0x1 <<  4) // (MCI) Data Transfer in Progress flag
1843
#define AT91C_MCI_NOTBUSY     (0x1 <<  5) // (MCI) Data Line Not Busy flag
1844
#define AT91C_MCI_ENDRX       (0x1 <<  6) // (MCI) End of RX Buffer flag
1845
#define AT91C_MCI_ENDTX       (0x1 <<  7) // (MCI) End of TX Buffer flag
1846
#define AT91C_MCI_SDIOIRQA    (0x1 <<  8) // (MCI) SDIO Interrupt for Slot A
1847
#define AT91C_MCI_SDIOIRQB    (0x1 <<  9) // (MCI) SDIO Interrupt for Slot B
1848
#define AT91C_MCI_SDIOIRQC    (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
1849
#define AT91C_MCI_SDIOIRQD    (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
1850
#define AT91C_MCI_RXBUFF      (0x1 << 14) // (MCI) RX Buffer Full flag
1851
#define AT91C_MCI_TXBUFE      (0x1 << 15) // (MCI) TX Buffer Empty flag
1852
#define AT91C_MCI_RINDE       (0x1 << 16) // (MCI) Response Index Error flag
1853
#define AT91C_MCI_RDIRE       (0x1 << 17) // (MCI) Response Direction Error flag
1854
#define AT91C_MCI_RCRCE       (0x1 << 18) // (MCI) Response CRC Error flag
1855
#define AT91C_MCI_RENDE       (0x1 << 19) // (MCI) Response End Bit Error flag
1856
#define AT91C_MCI_RTOE        (0x1 << 20) // (MCI) Response Time-out Error flag
1857
#define AT91C_MCI_DCRCE       (0x1 << 21) // (MCI) data CRC Error flag
1858
#define AT91C_MCI_DTOE        (0x1 << 22) // (MCI) Data timeout Error flag
1859
#define AT91C_MCI_OVRE        (0x1 << 30) // (MCI) Overrun flag
1860
#define AT91C_MCI_UNRE        (0x1 << 31) // (MCI) Underrun flag
1861
// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 
1862
// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 
1863
// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 
1864
 
1865
// *****************************************************************************
1866
//              SOFTWARE API DEFINITION  FOR Two-wire Interface
1867
// *****************************************************************************
1868
#ifndef __ASSEMBLY__
1869
typedef struct _AT91S_TWI {
1870
        AT91_REG         TWI_CR;        // Control Register
1871
        AT91_REG         TWI_MMR;       // Master Mode Register
1872
        AT91_REG         TWI_SMR;       // Slave Mode Register
1873
        AT91_REG         TWI_IADR;      // Internal Address Register
1874
        AT91_REG         TWI_CWGR;      // Clock Waveform Generator Register
1875
        AT91_REG         Reserved0[3];  // 
1876
        AT91_REG         TWI_SR;        // Status Register
1877
        AT91_REG         TWI_IER;       // Interrupt Enable Register
1878
        AT91_REG         TWI_IDR;       // Interrupt Disable Register
1879
        AT91_REG         TWI_IMR;       // Interrupt Mask Register
1880
        AT91_REG         TWI_RHR;       // Receive Holding Register
1881
        AT91_REG         TWI_THR;       // Transmit Holding Register
1882
        AT91_REG         Reserved1[50];         // 
1883
        AT91_REG         TWI_RPR;       // Receive Pointer Register
1884
        AT91_REG         TWI_RCR;       // Receive Counter Register
1885
        AT91_REG         TWI_TPR;       // Transmit Pointer Register
1886
        AT91_REG         TWI_TCR;       // Transmit Counter Register
1887
        AT91_REG         TWI_RNPR;      // Receive Next Pointer Register
1888
        AT91_REG         TWI_RNCR;      // Receive Next Counter Register
1889
        AT91_REG         TWI_TNPR;      // Transmit Next Pointer Register
1890
        AT91_REG         TWI_TNCR;      // Transmit Next Counter Register
1891
        AT91_REG         TWI_PTCR;      // PDC Transfer Control Register
1892
        AT91_REG         TWI_PTSR;      // PDC Transfer Status Register
1893
} AT91S_TWI, *AT91PS_TWI;
1894
#else
1895
#define TWI_CR          (AT91_CAST(AT91_REG *)  0x00000000) // (TWI_CR) Control Register
1896
#define TWI_MMR         (AT91_CAST(AT91_REG *)  0x00000004) // (TWI_MMR) Master Mode Register
1897
#define TWI_SMR         (AT91_CAST(AT91_REG *)  0x00000008) // (TWI_SMR) Slave Mode Register
1898
#define TWI_IADR        (AT91_CAST(AT91_REG *)  0x0000000C) // (TWI_IADR) Internal Address Register
1899
#define TWI_CWGR        (AT91_CAST(AT91_REG *)  0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
1900
#define TWI_SR          (AT91_CAST(AT91_REG *)  0x00000020) // (TWI_SR) Status Register
1901
#define TWI_IER         (AT91_CAST(AT91_REG *)  0x00000024) // (TWI_IER) Interrupt Enable Register
1902
#define TWI_IDR         (AT91_CAST(AT91_REG *)  0x00000028) // (TWI_IDR) Interrupt Disable Register
1903
#define TWI_IMR         (AT91_CAST(AT91_REG *)  0x0000002C) // (TWI_IMR) Interrupt Mask Register
1904
#define TWI_RHR         (AT91_CAST(AT91_REG *)  0x00000030) // (TWI_RHR) Receive Holding Register
1905
#define TWI_THR         (AT91_CAST(AT91_REG *)  0x00000034) // (TWI_THR) Transmit Holding Register
1906
 
1907
#endif
1908
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
1909
#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
1910
#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
1911
#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
1912
#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
1913
#define AT91C_TWI_SVEN        (0x1 <<  4) // (TWI) TWI Slave mode Enabled
1914
#define AT91C_TWI_SVDIS       (0x1 <<  5) // (TWI) TWI Slave mode Disabled
1915
#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
1916
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
1917
#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
1918
#define         AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
1919
#define         AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
1920
#define         AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
1921
#define         AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
1922
#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
1923
#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
1924
// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
1925
#define AT91C_TWI_SADR        (0x7F << 16) // (TWI) Slave Address
1926
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
1927
#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
1928
#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
1929
#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
1930
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
1931
#define AT91C_TWI_TXCOMP_SLAVE (0x1 <<  0) // (TWI) Transmission Completed
1932
#define AT91C_TWI_TXCOMP_MASTER (0x1 <<  0) // (TWI) Transmission Completed
1933
#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
1934
#define AT91C_TWI_TXRDY_MASTER (0x1 <<  2) // (TWI) Transmit holding register ReaDY
1935
#define AT91C_TWI_TXRDY_SLAVE (0x1 <<  2) // (TWI) Transmit holding register ReaDY
1936
#define AT91C_TWI_SVREAD      (0x1 <<  3) // (TWI) Slave READ (used only in Slave mode)
1937
#define AT91C_TWI_SVACC       (0x1 <<  4) // (TWI) Slave ACCess (used only in Slave mode)
1938
#define AT91C_TWI_GACC        (0x1 <<  5) // (TWI) General Call ACcess (used only in Slave mode)
1939
#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
1940
#define AT91C_TWI_NACK_SLAVE  (0x1 <<  8) // (TWI) Not Acknowledged
1941
#define AT91C_TWI_NACK_MASTER (0x1 <<  8) // (TWI) Not Acknowledged
1942
#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 <<  9) // (TWI) Arbitration Lost (used only in Multimaster mode)
1943
#define AT91C_TWI_SCLWS       (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
1944
#define AT91C_TWI_EOSACC      (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
1945
#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI) End of Receiver Transfer
1946
#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI) End of Receiver Transfer
1947
#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI) RXBUFF Interrupt
1948
#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI) TXBUFE Interrupt
1949
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
1950
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
1951
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
1952
 
1953
// *****************************************************************************
1954
//              SOFTWARE API DEFINITION  FOR Usart
1955
// *****************************************************************************
1956
#ifndef __ASSEMBLY__
1957
typedef struct _AT91S_USART {
1958
        AT91_REG         US_CR;         // Control Register
1959
        AT91_REG         US_MR;         // Mode Register
1960
        AT91_REG         US_IER;        // Interrupt Enable Register
1961
        AT91_REG         US_IDR;        // Interrupt Disable Register
1962
        AT91_REG         US_IMR;        // Interrupt Mask Register
1963
        AT91_REG         US_CSR;        // Channel Status Register
1964
        AT91_REG         US_RHR;        // Receiver Holding Register
1965
        AT91_REG         US_THR;        // Transmitter Holding Register
1966
        AT91_REG         US_BRGR;       // Baud Rate Generator Register
1967
        AT91_REG         US_RTOR;       // Receiver Time-out Register
1968
        AT91_REG         US_TTGR;       // Transmitter Time-guard Register
1969
        AT91_REG         Reserved0[5];  // 
1970
        AT91_REG         US_FIDI;       // FI_DI_Ratio Register
1971
        AT91_REG         US_NER;        // Nb Errors Register
1972
        AT91_REG         Reserved1[1];  // 
1973
        AT91_REG         US_IF;         // IRDA_FILTER Register
1974
        AT91_REG         Reserved2[44];         // 
1975
        AT91_REG         US_RPR;        // Receive Pointer Register
1976
        AT91_REG         US_RCR;        // Receive Counter Register
1977
        AT91_REG         US_TPR;        // Transmit Pointer Register
1978
        AT91_REG         US_TCR;        // Transmit Counter Register
1979
        AT91_REG         US_RNPR;       // Receive Next Pointer Register
1980
        AT91_REG         US_RNCR;       // Receive Next Counter Register
1981
        AT91_REG         US_TNPR;       // Transmit Next Pointer Register
1982
        AT91_REG         US_TNCR;       // Transmit Next Counter Register
1983
        AT91_REG         US_PTCR;       // PDC Transfer Control Register
1984
        AT91_REG         US_PTSR;       // PDC Transfer Status Register
1985
} AT91S_USART, *AT91PS_USART;
1986
#else
1987
#define US_CR           (AT91_CAST(AT91_REG *)  0x00000000) // (US_CR) Control Register
1988
#define US_MR           (AT91_CAST(AT91_REG *)  0x00000004) // (US_MR) Mode Register
1989
#define US_IER          (AT91_CAST(AT91_REG *)  0x00000008) // (US_IER) Interrupt Enable Register
1990
#define US_IDR          (AT91_CAST(AT91_REG *)  0x0000000C) // (US_IDR) Interrupt Disable Register
1991
#define US_IMR          (AT91_CAST(AT91_REG *)  0x00000010) // (US_IMR) Interrupt Mask Register
1992
#define US_CSR          (AT91_CAST(AT91_REG *)  0x00000014) // (US_CSR) Channel Status Register
1993
#define US_RHR          (AT91_CAST(AT91_REG *)  0x00000018) // (US_RHR) Receiver Holding Register
1994
#define US_THR          (AT91_CAST(AT91_REG *)  0x0000001C) // (US_THR) Transmitter Holding Register
1995
#define US_BRGR         (AT91_CAST(AT91_REG *)  0x00000020) // (US_BRGR) Baud Rate Generator Register
1996
#define US_RTOR         (AT91_CAST(AT91_REG *)  0x00000024) // (US_RTOR) Receiver Time-out Register
1997
#define US_TTGR         (AT91_CAST(AT91_REG *)  0x00000028) // (US_TTGR) Transmitter Time-guard Register
1998
#define US_FIDI         (AT91_CAST(AT91_REG *)  0x00000040) // (US_FIDI) FI_DI_Ratio Register
1999
#define US_NER          (AT91_CAST(AT91_REG *)  0x00000044) // (US_NER) Nb Errors Register
2000
#define US_IF           (AT91_CAST(AT91_REG *)  0x0000004C) // (US_IF) IRDA_FILTER Register
2001
 
2002
#endif
2003
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
2004
#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
2005
#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
2006
#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
2007
#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
2008
#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
2009
#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
2010
#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
2011
#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
2012
#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
2013
#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
2014
#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
2015
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
2016
#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
2017
#define         AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
2018
#define         AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
2019
#define         AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
2020
#define         AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
2021
#define         AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
2022
#define         AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
2023
#define         AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
2024
#define         AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
2025
#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
2026
#define         AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
2027
#define         AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
2028
#define         AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
2029
#define         AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
2030
#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
2031
#define         AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
2032
#define         AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
2033
#define         AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
2034
#define         AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
2035
#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
2036
#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
2037
#define         AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
2038
#define         AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
2039
#define         AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
2040
#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
2041
#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
2042
#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
2043
#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
2044
#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
2045
#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
2046
#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
2047
#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
2048
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
2049
#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
2050
#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
2051
#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
2052
#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
2053
#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
2054
#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
2055
#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
2056
#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
2057
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
2058
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
2059
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
2060
#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
2061
#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
2062
#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
2063
#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
2064
 
2065
// *****************************************************************************
2066
//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
2067
// *****************************************************************************
2068
#ifndef __ASSEMBLY__
2069
typedef struct _AT91S_SSC {
2070
        AT91_REG         SSC_CR;        // Control Register
2071
        AT91_REG         SSC_CMR;       // Clock Mode Register
2072
        AT91_REG         Reserved0[2];  // 
2073
        AT91_REG         SSC_RCMR;      // Receive Clock ModeRegister
2074
        AT91_REG         SSC_RFMR;      // Receive Frame Mode Register
2075
        AT91_REG         SSC_TCMR;      // Transmit Clock Mode Register
2076
        AT91_REG         SSC_TFMR;      // Transmit Frame Mode Register
2077
        AT91_REG         SSC_RHR;       // Receive Holding Register
2078
        AT91_REG         SSC_THR;       // Transmit Holding Register
2079
        AT91_REG         Reserved1[2];  // 
2080
        AT91_REG         SSC_RSHR;      // Receive Sync Holding Register
2081
        AT91_REG         SSC_TSHR;      // Transmit Sync Holding Register
2082
        AT91_REG         Reserved2[2];  // 
2083
        AT91_REG         SSC_SR;        // Status Register
2084
        AT91_REG         SSC_IER;       // Interrupt Enable Register
2085
        AT91_REG         SSC_IDR;       // Interrupt Disable Register
2086
        AT91_REG         SSC_IMR;       // Interrupt Mask Register
2087
        AT91_REG         Reserved3[44];         // 
2088
        AT91_REG         SSC_RPR;       // Receive Pointer Register
2089
        AT91_REG         SSC_RCR;       // Receive Counter Register
2090
        AT91_REG         SSC_TPR;       // Transmit Pointer Register
2091
        AT91_REG         SSC_TCR;       // Transmit Counter Register
2092
        AT91_REG         SSC_RNPR;      // Receive Next Pointer Register
2093
        AT91_REG         SSC_RNCR;      // Receive Next Counter Register
2094
        AT91_REG         SSC_TNPR;      // Transmit Next Pointer Register
2095
        AT91_REG         SSC_TNCR;      // Transmit Next Counter Register
2096
        AT91_REG         SSC_PTCR;      // PDC Transfer Control Register
2097
        AT91_REG         SSC_PTSR;      // PDC Transfer Status Register
2098
} AT91S_SSC, *AT91PS_SSC;
2099
#else
2100
#define SSC_CR          (AT91_CAST(AT91_REG *)  0x00000000) // (SSC_CR) Control Register
2101
#define SSC_CMR         (AT91_CAST(AT91_REG *)  0x00000004) // (SSC_CMR) Clock Mode Register
2102
#define SSC_RCMR        (AT91_CAST(AT91_REG *)  0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
2103
#define SSC_RFMR        (AT91_CAST(AT91_REG *)  0x00000014) // (SSC_RFMR) Receive Frame Mode Register
2104
#define SSC_TCMR        (AT91_CAST(AT91_REG *)  0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
2105
#define SSC_TFMR        (AT91_CAST(AT91_REG *)  0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
2106
#define SSC_RHR         (AT91_CAST(AT91_REG *)  0x00000020) // (SSC_RHR) Receive Holding Register
2107
#define SSC_THR         (AT91_CAST(AT91_REG *)  0x00000024) // (SSC_THR) Transmit Holding Register
2108
#define SSC_RSHR        (AT91_CAST(AT91_REG *)  0x00000030) // (SSC_RSHR) Receive Sync Holding Register
2109
#define SSC_TSHR        (AT91_CAST(AT91_REG *)  0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
2110
#define SSC_SR          (AT91_CAST(AT91_REG *)  0x00000040) // (SSC_SR) Status Register
2111
#define SSC_IER         (AT91_CAST(AT91_REG *)  0x00000044) // (SSC_IER) Interrupt Enable Register
2112
#define SSC_IDR         (AT91_CAST(AT91_REG *)  0x00000048) // (SSC_IDR) Interrupt Disable Register
2113
#define SSC_IMR         (AT91_CAST(AT91_REG *)  0x0000004C) // (SSC_IMR) Interrupt Mask Register
2114
 
2115
#endif
2116
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
2117
#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
2118
#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
2119
#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
2120
#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
2121
#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
2122
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
2123
#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
2124
#define         AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
2125
#define         AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
2126
#define         AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
2127
#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
2128
#define         AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
2129
#define         AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
2130
#define         AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
2131
#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
2132
#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
2133
#define         AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
2134
#define         AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
2135
#define         AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
2136
#define         AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
2137
#define         AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
2138
#define         AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
2139
#define         AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
2140
#define         AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
2141
#define         AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
2142
#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
2143
#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
2144
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
2145
#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
2146
#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
2147
#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
2148
#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
2149
#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
2150
#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
2151
#define         AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
2152
#define         AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
2153
#define         AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
2154
#define         AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
2155
#define         AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
2156
#define         AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
2157
#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
2158
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
2159
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
2160
#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
2161
#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
2162
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
2163
#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
2164
#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
2165
#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
2166
#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
2167
#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
2168
#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
2169
#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
2170
#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
2171
#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
2172
#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
2173
#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
2174
#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
2175
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
2176
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
2177
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
2178
 
2179
// *****************************************************************************
2180
//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
2181
// *****************************************************************************
2182
#ifndef __ASSEMBLY__
2183
typedef struct _AT91S_SPI {
2184
        AT91_REG         SPI_CR;        // Control Register
2185
        AT91_REG         SPI_MR;        // Mode Register
2186
        AT91_REG         SPI_RDR;       // Receive Data Register
2187
        AT91_REG         SPI_TDR;       // Transmit Data Register
2188
        AT91_REG         SPI_SR;        // Status Register
2189
        AT91_REG         SPI_IER;       // Interrupt Enable Register
2190
        AT91_REG         SPI_IDR;       // Interrupt Disable Register
2191
        AT91_REG         SPI_IMR;       // Interrupt Mask Register
2192
        AT91_REG         Reserved0[4];  // 
2193
        AT91_REG         SPI_CSR[4];    // Chip Select Register
2194
        AT91_REG         Reserved1[48];         // 
2195
        AT91_REG         SPI_RPR;       // Receive Pointer Register
2196
        AT91_REG         SPI_RCR;       // Receive Counter Register
2197
        AT91_REG         SPI_TPR;       // Transmit Pointer Register
2198
        AT91_REG         SPI_TCR;       // Transmit Counter Register
2199
        AT91_REG         SPI_RNPR;      // Receive Next Pointer Register
2200
        AT91_REG         SPI_RNCR;      // Receive Next Counter Register
2201
        AT91_REG         SPI_TNPR;      // Transmit Next Pointer Register
2202
        AT91_REG         SPI_TNCR;      // Transmit Next Counter Register
2203
        AT91_REG         SPI_PTCR;      // PDC Transfer Control Register
2204
        AT91_REG         SPI_PTSR;      // PDC Transfer Status Register
2205
} AT91S_SPI, *AT91PS_SPI;
2206
#else
2207
#define SPI_CR          (AT91_CAST(AT91_REG *)  0x00000000) // (SPI_CR) Control Register
2208
#define SPI_MR          (AT91_CAST(AT91_REG *)  0x00000004) // (SPI_MR) Mode Register
2209
#define SPI_RDR         (AT91_CAST(AT91_REG *)  0x00000008) // (SPI_RDR) Receive Data Register
2210
#define SPI_TDR         (AT91_CAST(AT91_REG *)  0x0000000C) // (SPI_TDR) Transmit Data Register
2211
#define SPI_SR          (AT91_CAST(AT91_REG *)  0x00000010) // (SPI_SR) Status Register
2212
#define SPI_IER         (AT91_CAST(AT91_REG *)  0x00000014) // (SPI_IER) Interrupt Enable Register
2213
#define SPI_IDR         (AT91_CAST(AT91_REG *)  0x00000018) // (SPI_IDR) Interrupt Disable Register
2214
#define SPI_IMR         (AT91_CAST(AT91_REG *)  0x0000001C) // (SPI_IMR) Interrupt Mask Register
2215
#define SPI_CSR         (AT91_CAST(AT91_REG *)  0x00000030) // (SPI_CSR) Chip Select Register
2216
 
2217
#endif
2218
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
2219
#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
2220
#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
2221
#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
2222
#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
2223
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
2224
#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
2225
#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
2226
#define         AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
2227
#define         AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
2228
#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
2229
#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
2230
#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
2231
#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
2232
#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
2233
#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
2234
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
2235
#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
2236
#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
2237
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
2238
#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
2239
#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
2240
// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
2241
#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
2242
#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
2243
#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
2244
#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
2245
#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
2246
#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
2247
#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
2248
#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
2249
#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
2250
#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
2251
#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
2252
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
2253
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
2254
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
2255
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
2256
#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
2257
#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
2258
#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
2259
#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
2260
#define         AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
2261
#define         AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
2262
#define         AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
2263
#define         AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
2264
#define         AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
2265
#define         AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
2266
#define         AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
2267
#define         AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
2268
#define         AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
2269
#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
2270
#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
2271
#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
2272
 
2273
// *****************************************************************************
2274
//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
2275
// *****************************************************************************
2276
#ifndef __ASSEMBLY__
2277
typedef struct _AT91S_ADC {
2278
        AT91_REG         ADC_CR;        // ADC Control Register
2279
        AT91_REG         ADC_MR;        // ADC Mode Register
2280
        AT91_REG         Reserved0[2];  // 
2281
        AT91_REG         ADC_CHER;      // ADC Channel Enable Register
2282
        AT91_REG         ADC_CHDR;      // ADC Channel Disable Register
2283
        AT91_REG         ADC_CHSR;      // ADC Channel Status Register
2284
        AT91_REG         ADC_SR;        // ADC Status Register
2285
        AT91_REG         ADC_LCDR;      // ADC Last Converted Data Register
2286
        AT91_REG         ADC_IER;       // ADC Interrupt Enable Register
2287
        AT91_REG         ADC_IDR;       // ADC Interrupt Disable Register
2288
        AT91_REG         ADC_IMR;       // ADC Interrupt Mask Register
2289
        AT91_REG         ADC_CDR0;      // ADC Channel Data Register 0
2290
        AT91_REG         ADC_CDR1;      // ADC Channel Data Register 1
2291
        AT91_REG         ADC_CDR2;      // ADC Channel Data Register 2
2292
        AT91_REG         ADC_CDR3;      // ADC Channel Data Register 3
2293
        AT91_REG         ADC_CDR4;      // ADC Channel Data Register 4
2294
        AT91_REG         ADC_CDR5;      // ADC Channel Data Register 5
2295
        AT91_REG         ADC_CDR6;      // ADC Channel Data Register 6
2296
        AT91_REG         ADC_CDR7;      // ADC Channel Data Register 7
2297
        AT91_REG         Reserved1[44];         // 
2298
        AT91_REG         ADC_RPR;       // Receive Pointer Register
2299
        AT91_REG         ADC_RCR;       // Receive Counter Register
2300
        AT91_REG         ADC_TPR;       // Transmit Pointer Register
2301
        AT91_REG         ADC_TCR;       // Transmit Counter Register
2302
        AT91_REG         ADC_RNPR;      // Receive Next Pointer Register
2303
        AT91_REG         ADC_RNCR;      // Receive Next Counter Register
2304
        AT91_REG         ADC_TNPR;      // Transmit Next Pointer Register
2305
        AT91_REG         ADC_TNCR;      // Transmit Next Counter Register
2306
        AT91_REG         ADC_PTCR;      // PDC Transfer Control Register
2307
        AT91_REG         ADC_PTSR;      // PDC Transfer Status Register
2308
} AT91S_ADC, *AT91PS_ADC;
2309
#else
2310
#define ADC_CR          (AT91_CAST(AT91_REG *)  0x00000000) // (ADC_CR) ADC Control Register
2311
#define ADC_MR          (AT91_CAST(AT91_REG *)  0x00000004) // (ADC_MR) ADC Mode Register
2312
#define ADC_CHER        (AT91_CAST(AT91_REG *)  0x00000010) // (ADC_CHER) ADC Channel Enable Register
2313
#define ADC_CHDR        (AT91_CAST(AT91_REG *)  0x00000014) // (ADC_CHDR) ADC Channel Disable Register
2314
#define ADC_CHSR        (AT91_CAST(AT91_REG *)  0x00000018) // (ADC_CHSR) ADC Channel Status Register
2315
#define ADC_SR          (AT91_CAST(AT91_REG *)  0x0000001C) // (ADC_SR) ADC Status Register
2316
#define ADC_LCDR        (AT91_CAST(AT91_REG *)  0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
2317
#define ADC_IER         (AT91_CAST(AT91_REG *)  0x00000024) // (ADC_IER) ADC Interrupt Enable Register
2318
#define ADC_IDR         (AT91_CAST(AT91_REG *)  0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
2319
#define ADC_IMR         (AT91_CAST(AT91_REG *)  0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
2320
#define ADC_CDR0        (AT91_CAST(AT91_REG *)  0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
2321
#define ADC_CDR1        (AT91_CAST(AT91_REG *)  0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
2322
#define ADC_CDR2        (AT91_CAST(AT91_REG *)  0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
2323
#define ADC_CDR3        (AT91_CAST(AT91_REG *)  0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
2324
#define ADC_CDR4        (AT91_CAST(AT91_REG *)  0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
2325
#define ADC_CDR5        (AT91_CAST(AT91_REG *)  0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
2326
#define ADC_CDR6        (AT91_CAST(AT91_REG *)  0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
2327
#define ADC_CDR7        (AT91_CAST(AT91_REG *)  0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
2328
 
2329
#endif
2330
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
2331
#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
2332
#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
2333
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
2334
#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
2335
#define         AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
2336
#define         AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
2337
#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
2338
#define         AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
2339
#define         AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
2340
#define         AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
2341
#define         AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
2342
#define         AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
2343
#define         AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
2344
#define         AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
2345
#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
2346
#define         AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
2347
#define         AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
2348
#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
2349
#define         AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
2350
#define         AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
2351
#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
2352
#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
2353
#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
2354
// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
2355
#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
2356
#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
2357
#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
2358
#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
2359
#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
2360
#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
2361
#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
2362
#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
2363
// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
2364
// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
2365
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
2366
#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
2367
#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
2368
#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
2369
#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
2370
#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
2371
#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
2372
#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
2373
#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
2374
#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
2375
#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
2376
#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
2377
#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
2378
#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
2379
#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
2380
#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
2381
#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
2382
#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
2383
#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
2384
#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
2385
#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
2386
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
2387
#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
2388
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
2389
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
2390
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
2391
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
2392
#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
2393
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
2394
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
2395
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
2396
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
2397
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
2398
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
2399
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
2400
 
2401
// *****************************************************************************
2402
//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
2403
// *****************************************************************************
2404
#ifndef __ASSEMBLY__
2405
typedef struct _AT91S_EMAC {
2406
        AT91_REG         EMAC_NCR;      // Network Control Register
2407
        AT91_REG         EMAC_NCFGR;    // Network Configuration Register
2408
        AT91_REG         EMAC_NSR;      // Network Status Register
2409
        AT91_REG         Reserved0[2];  // 
2410
        AT91_REG         EMAC_TSR;      // Transmit Status Register
2411
        AT91_REG         EMAC_RBQP;     // Receive Buffer Queue Pointer
2412
        AT91_REG         EMAC_TBQP;     // Transmit Buffer Queue Pointer
2413
        AT91_REG         EMAC_RSR;      // Receive Status Register
2414
        AT91_REG         EMAC_ISR;      // Interrupt Status Register
2415
        AT91_REG         EMAC_IER;      // Interrupt Enable Register
2416
        AT91_REG         EMAC_IDR;      // Interrupt Disable Register
2417
        AT91_REG         EMAC_IMR;      // Interrupt Mask Register
2418
        AT91_REG         EMAC_MAN;      // PHY Maintenance Register
2419
        AT91_REG         EMAC_PTR;      // Pause Time Register
2420
        AT91_REG         EMAC_PFR;      // Pause Frames received Register
2421
        AT91_REG         EMAC_FTO;      // Frames Transmitted OK Register
2422
        AT91_REG         EMAC_SCF;      // Single Collision Frame Register
2423
        AT91_REG         EMAC_MCF;      // Multiple Collision Frame Register
2424
        AT91_REG         EMAC_FRO;      // Frames Received OK Register
2425
        AT91_REG         EMAC_FCSE;     // Frame Check Sequence Error Register
2426
        AT91_REG         EMAC_ALE;      // Alignment Error Register
2427
        AT91_REG         EMAC_DTF;      // Deferred Transmission Frame Register
2428
        AT91_REG         EMAC_LCOL;     // Late Collision Register
2429
        AT91_REG         EMAC_ECOL;     // Excessive Collision Register
2430
        AT91_REG         EMAC_TUND;     // Transmit Underrun Error Register
2431
        AT91_REG         EMAC_CSE;      // Carrier Sense Error Register
2432
        AT91_REG         EMAC_RRE;      // Receive Ressource Error Register
2433
        AT91_REG         EMAC_ROV;      // Receive Overrun Errors Register
2434
        AT91_REG         EMAC_RSE;      // Receive Symbol Errors Register
2435
        AT91_REG         EMAC_ELE;      // Excessive Length Errors Register
2436
        AT91_REG         EMAC_RJA;      // Receive Jabbers Register
2437
        AT91_REG         EMAC_USF;      // Undersize Frames Register
2438
        AT91_REG         EMAC_STE;      // SQE Test Error Register
2439
        AT91_REG         EMAC_RLE;      // Receive Length Field Mismatch Register
2440
        AT91_REG         EMAC_TPF;      // Transmitted Pause Frames Register
2441
        AT91_REG         EMAC_HRB;      // Hash Address Bottom[31:0]
2442
        AT91_REG         EMAC_HRT;      // Hash Address Top[63:32]
2443
        AT91_REG         EMAC_SA1L;     // Specific Address 1 Bottom, First 4 bytes
2444
        AT91_REG         EMAC_SA1H;     // Specific Address 1 Top, Last 2 bytes
2445
        AT91_REG         EMAC_SA2L;     // Specific Address 2 Bottom, First 4 bytes
2446
        AT91_REG         EMAC_SA2H;     // Specific Address 2 Top, Last 2 bytes
2447
        AT91_REG         EMAC_SA3L;     // Specific Address 3 Bottom, First 4 bytes
2448
        AT91_REG         EMAC_SA3H;     // Specific Address 3 Top, Last 2 bytes
2449
        AT91_REG         EMAC_SA4L;     // Specific Address 4 Bottom, First 4 bytes
2450
        AT91_REG         EMAC_SA4H;     // Specific Address 4 Top, Last 2 bytes
2451
        AT91_REG         EMAC_TID;      // Type ID Checking Register
2452
        AT91_REG         EMAC_TPQ;      // Transmit Pause Quantum Register
2453
        AT91_REG         EMAC_USRIO;    // USER Input/Output Register
2454
        AT91_REG         EMAC_WOL;      // Wake On LAN Register
2455
        AT91_REG         Reserved1[13];         // 
2456
        AT91_REG         EMAC_REV;      // Revision Register
2457
} AT91S_EMAC, *AT91PS_EMAC;
2458
#else
2459
#define EMAC_NCR        (AT91_CAST(AT91_REG *)  0x00000000) // (EMAC_NCR) Network Control Register
2460
#define EMAC_NCFGR      (AT91_CAST(AT91_REG *)  0x00000004) // (EMAC_NCFGR) Network Configuration Register
2461
#define EMAC_NSR        (AT91_CAST(AT91_REG *)  0x00000008) // (EMAC_NSR) Network Status Register
2462
#define EMAC_TSR        (AT91_CAST(AT91_REG *)  0x00000014) // (EMAC_TSR) Transmit Status Register
2463
#define EMAC_RBQP       (AT91_CAST(AT91_REG *)  0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
2464
#define EMAC_TBQP       (AT91_CAST(AT91_REG *)  0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
2465
#define EMAC_RSR        (AT91_CAST(AT91_REG *)  0x00000020) // (EMAC_RSR) Receive Status Register
2466
#define EMAC_ISR        (AT91_CAST(AT91_REG *)  0x00000024) // (EMAC_ISR) Interrupt Status Register
2467
#define EMAC_IER        (AT91_CAST(AT91_REG *)  0x00000028) // (EMAC_IER) Interrupt Enable Register
2468
#define EMAC_IDR        (AT91_CAST(AT91_REG *)  0x0000002C) // (EMAC_IDR) Interrupt Disable Register
2469
#define EMAC_IMR        (AT91_CAST(AT91_REG *)  0x00000030) // (EMAC_IMR) Interrupt Mask Register
2470
#define EMAC_MAN        (AT91_CAST(AT91_REG *)  0x00000034) // (EMAC_MAN) PHY Maintenance Register
2471
#define EMAC_PTR        (AT91_CAST(AT91_REG *)  0x00000038) // (EMAC_PTR) Pause Time Register
2472
#define EMAC_PFR        (AT91_CAST(AT91_REG *)  0x0000003C) // (EMAC_PFR) Pause Frames received Register
2473
#define EMAC_FTO        (AT91_CAST(AT91_REG *)  0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
2474
#define EMAC_SCF        (AT91_CAST(AT91_REG *)  0x00000044) // (EMAC_SCF) Single Collision Frame Register
2475
#define EMAC_MCF        (AT91_CAST(AT91_REG *)  0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
2476
#define EMAC_FRO        (AT91_CAST(AT91_REG *)  0x0000004C) // (EMAC_FRO) Frames Received OK Register
2477
#define EMAC_FCSE       (AT91_CAST(AT91_REG *)  0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
2478
#define EMAC_ALE        (AT91_CAST(AT91_REG *)  0x00000054) // (EMAC_ALE) Alignment Error Register
2479
#define EMAC_DTF        (AT91_CAST(AT91_REG *)  0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
2480
#define EMAC_LCOL       (AT91_CAST(AT91_REG *)  0x0000005C) // (EMAC_LCOL) Late Collision Register
2481
#define EMAC_ECOL       (AT91_CAST(AT91_REG *)  0x00000060) // (EMAC_ECOL) Excessive Collision Register
2482
#define EMAC_TUND       (AT91_CAST(AT91_REG *)  0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
2483
#define EMAC_CSE        (AT91_CAST(AT91_REG *)  0x00000068) // (EMAC_CSE) Carrier Sense Error Register
2484
#define EMAC_RRE        (AT91_CAST(AT91_REG *)  0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
2485
#define EMAC_ROV        (AT91_CAST(AT91_REG *)  0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
2486
#define EMAC_RSE        (AT91_CAST(AT91_REG *)  0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
2487
#define EMAC_ELE        (AT91_CAST(AT91_REG *)  0x00000078) // (EMAC_ELE) Excessive Length Errors Register
2488
#define EMAC_RJA        (AT91_CAST(AT91_REG *)  0x0000007C) // (EMAC_RJA) Receive Jabbers Register
2489
#define EMAC_USF        (AT91_CAST(AT91_REG *)  0x00000080) // (EMAC_USF) Undersize Frames Register
2490
#define EMAC_STE        (AT91_CAST(AT91_REG *)  0x00000084) // (EMAC_STE) SQE Test Error Register
2491
#define EMAC_RLE        (AT91_CAST(AT91_REG *)  0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
2492
#define EMAC_TPF        (AT91_CAST(AT91_REG *)  0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
2493
#define EMAC_HRB        (AT91_CAST(AT91_REG *)  0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
2494
#define EMAC_HRT        (AT91_CAST(AT91_REG *)  0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
2495
#define EMAC_SA1L       (AT91_CAST(AT91_REG *)  0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
2496
#define EMAC_SA1H       (AT91_CAST(AT91_REG *)  0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
2497
#define EMAC_SA2L       (AT91_CAST(AT91_REG *)  0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
2498
#define EMAC_SA2H       (AT91_CAST(AT91_REG *)  0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
2499
#define EMAC_SA3L       (AT91_CAST(AT91_REG *)  0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
2500
#define EMAC_SA3H       (AT91_CAST(AT91_REG *)  0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
2501
#define EMAC_SA4L       (AT91_CAST(AT91_REG *)  0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
2502
#define EMAC_SA4H       (AT91_CAST(AT91_REG *)  0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
2503
#define EMAC_TID        (AT91_CAST(AT91_REG *)  0x000000B8) // (EMAC_TID) Type ID Checking Register
2504
#define EMAC_TPQ        (AT91_CAST(AT91_REG *)  0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
2505
#define EMAC_USRIO      (AT91_CAST(AT91_REG *)  0x000000C0) // (EMAC_USRIO) USER Input/Output Register
2506
#define EMAC_WOL        (AT91_CAST(AT91_REG *)  0x000000C4) // (EMAC_WOL) Wake On LAN Register
2507
#define EMAC_REV        (AT91_CAST(AT91_REG *)  0x000000FC) // (EMAC_REV) Revision Register
2508
 
2509
#endif
2510
// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
2511
#define AT91C_EMAC_LB         (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
2512
#define AT91C_EMAC_LLB        (0x1 <<  1) // (EMAC) Loopback local. 
2513
#define AT91C_EMAC_RE         (0x1 <<  2) // (EMAC) Receive enable. 
2514
#define AT91C_EMAC_TE         (0x1 <<  3) // (EMAC) Transmit enable. 
2515
#define AT91C_EMAC_MPE        (0x1 <<  4) // (EMAC) Management port enable. 
2516
#define AT91C_EMAC_CLRSTAT    (0x1 <<  5) // (EMAC) Clear statistics registers. 
2517
#define AT91C_EMAC_INCSTAT    (0x1 <<  6) // (EMAC) Increment statistics registers. 
2518
#define AT91C_EMAC_WESTAT     (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
2519
#define AT91C_EMAC_BP         (0x1 <<  8) // (EMAC) Back pressure. 
2520
#define AT91C_EMAC_TSTART     (0x1 <<  9) // (EMAC) Start Transmission. 
2521
#define AT91C_EMAC_THALT      (0x1 << 10) // (EMAC) Transmission Halt. 
2522
#define AT91C_EMAC_TPFR       (0x1 << 11) // (EMAC) Transmit pause frame 
2523
#define AT91C_EMAC_TZQ        (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
2524
// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
2525
#define AT91C_EMAC_SPD        (0x1 <<  0) // (EMAC) Speed. 
2526
#define AT91C_EMAC_FD         (0x1 <<  1) // (EMAC) Full duplex. 
2527
#define AT91C_EMAC_JFRAME     (0x1 <<  3) // (EMAC) Jumbo Frames. 
2528
#define AT91C_EMAC_CAF        (0x1 <<  4) // (EMAC) Copy all frames. 
2529
#define AT91C_EMAC_NBC        (0x1 <<  5) // (EMAC) No broadcast. 
2530
#define AT91C_EMAC_MTI        (0x1 <<  6) // (EMAC) Multicast hash event enable
2531
#define AT91C_EMAC_UNI        (0x1 <<  7) // (EMAC) Unicast hash enable. 
2532
#define AT91C_EMAC_BIG        (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
2533
#define AT91C_EMAC_EAE        (0x1 <<  9) // (EMAC) External address match enable. 
2534
#define AT91C_EMAC_CLK        (0x3 << 10) // (EMAC) 
2535
#define         AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
2536
#define         AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
2537
#define         AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
2538
#define         AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
2539
#define AT91C_EMAC_RTY        (0x1 << 12) // (EMAC) 
2540
#define AT91C_EMAC_PAE        (0x1 << 13) // (EMAC) 
2541
#define AT91C_EMAC_RBOF       (0x3 << 14) // (EMAC) 
2542
#define         AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
2543
#define         AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
2544
#define         AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
2545
#define         AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
2546
#define AT91C_EMAC_RLCE       (0x1 << 16) // (EMAC) Receive Length field Checking Enable
2547
#define AT91C_EMAC_DRFCS      (0x1 << 17) // (EMAC) Discard Receive FCS
2548
#define AT91C_EMAC_EFRHD      (0x1 << 18) // (EMAC) 
2549
#define AT91C_EMAC_IRXFCS     (0x1 << 19) // (EMAC) Ignore RX FCS
2550
// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
2551
#define AT91C_EMAC_LINKR      (0x1 <<  0) // (EMAC) 
2552
#define AT91C_EMAC_MDIO       (0x1 <<  1) // (EMAC) 
2553
#define AT91C_EMAC_IDLE       (0x1 <<  2) // (EMAC) 
2554
// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
2555
#define AT91C_EMAC_UBR        (0x1 <<  0) // (EMAC) 
2556
#define AT91C_EMAC_COL        (0x1 <<  1) // (EMAC) 
2557
#define AT91C_EMAC_RLES       (0x1 <<  2) // (EMAC) 
2558
#define AT91C_EMAC_TGO        (0x1 <<  3) // (EMAC) Transmit Go
2559
#define AT91C_EMAC_BEX        (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
2560
#define AT91C_EMAC_COMP       (0x1 <<  5) // (EMAC) 
2561
#define AT91C_EMAC_UND        (0x1 <<  6) // (EMAC) 
2562
// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
2563
#define AT91C_EMAC_BNA        (0x1 <<  0) // (EMAC) 
2564
#define AT91C_EMAC_REC        (0x1 <<  1) // (EMAC) 
2565
#define AT91C_EMAC_OVR        (0x1 <<  2) // (EMAC) 
2566
// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
2567
#define AT91C_EMAC_MFD        (0x1 <<  0) // (EMAC) 
2568
#define AT91C_EMAC_RCOMP      (0x1 <<  1) // (EMAC) 
2569
#define AT91C_EMAC_RXUBR      (0x1 <<  2) // (EMAC) 
2570
#define AT91C_EMAC_TXUBR      (0x1 <<  3) // (EMAC) 
2571
#define AT91C_EMAC_TUNDR      (0x1 <<  4) // (EMAC) 
2572
#define AT91C_EMAC_RLEX       (0x1 <<  5) // (EMAC) 
2573
#define AT91C_EMAC_TXERR      (0x1 <<  6) // (EMAC) 
2574
#define AT91C_EMAC_TCOMP      (0x1 <<  7) // (EMAC) 
2575
#define AT91C_EMAC_LINK       (0x1 <<  9) // (EMAC) 
2576
#define AT91C_EMAC_ROVR       (0x1 << 10) // (EMAC) 
2577
#define AT91C_EMAC_HRESP      (0x1 << 11) // (EMAC) 
2578
#define AT91C_EMAC_PFRE       (0x1 << 12) // (EMAC) 
2579
#define AT91C_EMAC_PTZ        (0x1 << 13) // (EMAC) 
2580
// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
2581
// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
2582
// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
2583
// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
2584
#define AT91C_EMAC_DATA       (0xFFFF <<  0) // (EMAC) 
2585
#define AT91C_EMAC_CODE       (0x3 << 16) // (EMAC) 
2586
#define AT91C_EMAC_REGA       (0x1F << 18) // (EMAC) 
2587
#define AT91C_EMAC_PHYA       (0x1F << 23) // (EMAC) 
2588
#define AT91C_EMAC_RW         (0x3 << 28) // (EMAC) 
2589
#define AT91C_EMAC_SOF        (0x3 << 30) // (EMAC) 
2590
// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
2591
#define AT91C_EMAC_RMII       (0x1 <<  0) // (EMAC) Reduce MII
2592
#define AT91C_EMAC_CLKEN      (0x1 <<  1) // (EMAC) Clock Enable
2593
// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
2594
#define AT91C_EMAC_IP         (0xFFFF <<  0) // (EMAC) ARP request IP address
2595
#define AT91C_EMAC_MAG        (0x1 << 16) // (EMAC) Magic packet event enable
2596
#define AT91C_EMAC_ARP        (0x1 << 17) // (EMAC) ARP request event enable
2597
#define AT91C_EMAC_SA1        (0x1 << 18) // (EMAC) Specific address register 1 event enable
2598
// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
2599
#define AT91C_EMAC_REVREF     (0xFFFF <<  0) // (EMAC) 
2600
#define AT91C_EMAC_PARTREF    (0xFFFF << 16) // (EMAC) 
2601
 
2602
// *****************************************************************************
2603
//              SOFTWARE API DEFINITION  FOR USB Device Interface
2604
// *****************************************************************************
2605
#ifndef __ASSEMBLY__
2606
typedef struct _AT91S_UDP {
2607
        AT91_REG         UDP_NUM;       // Frame Number Register
2608
        AT91_REG         UDP_GLBSTATE;  // Global State Register
2609
        AT91_REG         UDP_FADDR;     // Function Address Register
2610
        AT91_REG         Reserved0[1];  // 
2611
        AT91_REG         UDP_IER;       // Interrupt Enable Register
2612
        AT91_REG         UDP_IDR;       // Interrupt Disable Register
2613
        AT91_REG         UDP_IMR;       // Interrupt Mask Register
2614
        AT91_REG         UDP_ISR;       // Interrupt Status Register
2615
        AT91_REG         UDP_ICR;       // Interrupt Clear Register
2616
        AT91_REG         Reserved1[1];  // 
2617
        AT91_REG         UDP_RSTEP;     // Reset Endpoint Register
2618
        AT91_REG         Reserved2[1];  // 
2619
        AT91_REG         UDP_CSR[6];    // Endpoint Control and Status Register
2620
        AT91_REG         Reserved3[2];  // 
2621
        AT91_REG         UDP_FDR[6];    // Endpoint FIFO Data Register
2622
        AT91_REG         Reserved4[3];  // 
2623
        AT91_REG         UDP_TXVC;      // Transceiver Control Register
2624
} AT91S_UDP, *AT91PS_UDP;
2625
#else
2626
#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *)  0x00000000) // (UDP_FRM_NUM) Frame Number Register
2627
#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *)  0x00000004) // (UDP_GLBSTATE) Global State Register
2628
#define UDP_FADDR       (AT91_CAST(AT91_REG *)  0x00000008) // (UDP_FADDR) Function Address Register
2629
#define UDP_IER         (AT91_CAST(AT91_REG *)  0x00000010) // (UDP_IER) Interrupt Enable Register
2630
#define UDP_IDR         (AT91_CAST(AT91_REG *)  0x00000014) // (UDP_IDR) Interrupt Disable Register
2631
#define UDP_IMR         (AT91_CAST(AT91_REG *)  0x00000018) // (UDP_IMR) Interrupt Mask Register
2632
#define UDP_ISR         (AT91_CAST(AT91_REG *)  0x0000001C) // (UDP_ISR) Interrupt Status Register
2633
#define UDP_ICR         (AT91_CAST(AT91_REG *)  0x00000020) // (UDP_ICR) Interrupt Clear Register
2634
#define UDP_RSTEP       (AT91_CAST(AT91_REG *)  0x00000028) // (UDP_RSTEP) Reset Endpoint Register
2635
#define UDP_CSR         (AT91_CAST(AT91_REG *)  0x00000030) // (UDP_CSR) Endpoint Control and Status Register
2636
#define UDP_FDR         (AT91_CAST(AT91_REG *)  0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
2637
#define UDP_TXVC        (AT91_CAST(AT91_REG *)  0x00000074) // (UDP_TXVC) Transceiver Control Register
2638
 
2639
#endif
2640
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
2641
#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
2642
#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
2643
#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
2644
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
2645
#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
2646
#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
2647
#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
2648
#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
2649
#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
2650
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
2651
#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
2652
#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
2653
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
2654
#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
2655
#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
2656
#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
2657
#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
2658
#define AT91C_UDP_EPINT4      (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
2659
#define AT91C_UDP_EPINT5      (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
2660
#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
2661
#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
2662
#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
2663
#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
2664
#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
2665
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
2666
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
2667
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
2668
#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
2669
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
2670
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
2671
#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
2672
#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
2673
#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
2674
#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
2675
#define AT91C_UDP_EP4         (0x1 <<  4) // (UDP) Reset Endpoint 4
2676
#define AT91C_UDP_EP5         (0x1 <<  5) // (UDP) Reset Endpoint 5
2677
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
2678
#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
2679
#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
2680
#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
2681
#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
2682
#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
2683
#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
2684
#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
2685
#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
2686
#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
2687
#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
2688
#define         AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
2689
#define         AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
2690
#define         AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
2691
#define         AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
2692
#define         AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
2693
#define         AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
2694
#define         AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
2695
#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
2696
#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
2697
#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
2698
// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
2699
#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP) 
2700
#define AT91C_UDP_PUON        (0x1 <<  9) // (UDP) Pull-up ON
2701
 
2702
// *****************************************************************************
2703
//              SOFTWARE API DEFINITION  FOR USB Host Interface
2704
// *****************************************************************************
2705
#ifndef __ASSEMBLY__
2706
typedef struct _AT91S_UHP {
2707
        AT91_REG         UHP_HcRevision;        // Revision
2708
        AT91_REG         UHP_HcControl;         // Operating modes for the Host Controller
2709
        AT91_REG         UHP_HcCommandStatus;   // Command & status Register
2710
        AT91_REG         UHP_HcInterruptStatus;         // Interrupt Status Register
2711
        AT91_REG         UHP_HcInterruptEnable;         // Interrupt Enable Register
2712
        AT91_REG         UHP_HcInterruptDisable;        // Interrupt Disable Register
2713
        AT91_REG         UHP_HcHCCA;    // Pointer to the Host Controller Communication Area
2714
        AT91_REG         UHP_HcPeriodCurrentED;         // Current Isochronous or Interrupt Endpoint Descriptor
2715
        AT91_REG         UHP_HcControlHeadED;   // First Endpoint Descriptor of the Control list
2716
        AT91_REG         UHP_HcControlCurrentED;        // Endpoint Control and Status Register
2717
        AT91_REG         UHP_HcBulkHeadED;      // First endpoint register of the Bulk list
2718
        AT91_REG         UHP_HcBulkCurrentED;   // Current endpoint of the Bulk list
2719
        AT91_REG         UHP_HcBulkDoneHead;    // Last completed transfer descriptor
2720
        AT91_REG         UHP_HcFmInterval;      // Bit time between 2 consecutive SOFs
2721
        AT91_REG         UHP_HcFmRemaining;     // Bit time remaining in the current Frame
2722
        AT91_REG         UHP_HcFmNumber;        // Frame number
2723
        AT91_REG         UHP_HcPeriodicStart;   // Periodic Start
2724
        AT91_REG         UHP_HcLSThreshold;     // LS Threshold
2725
        AT91_REG         UHP_HcRhDescriptorA;   // Root Hub characteristics A
2726
        AT91_REG         UHP_HcRhDescriptorB;   // Root Hub characteristics B
2727
        AT91_REG         UHP_HcRhStatus;        // Root Hub Status register
2728
        AT91_REG         UHP_HcRhPortStatus[2];         // Root Hub Port Status Register
2729
} AT91S_UHP, *AT91PS_UHP;
2730
#else
2731
#define HcRevision      (AT91_CAST(AT91_REG *)  0x00000000) // (HcRevision) Revision
2732
#define HcControl       (AT91_CAST(AT91_REG *)  0x00000004) // (HcControl) Operating modes for the Host Controller
2733
#define HcCommandStatus (AT91_CAST(AT91_REG *)  0x00000008) // (HcCommandStatus) Command & status Register
2734
#define HcInterruptStatus (AT91_CAST(AT91_REG *)        0x0000000C) // (HcInterruptStatus) Interrupt Status Register
2735
#define HcInterruptEnable (AT91_CAST(AT91_REG *)        0x00000010) // (HcInterruptEnable) Interrupt Enable Register
2736
#define HcInterruptDisable (AT91_CAST(AT91_REG *)       0x00000014) // (HcInterruptDisable) Interrupt Disable Register
2737
#define HcHCCA          (AT91_CAST(AT91_REG *)  0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area
2738
#define HcPeriodCurrentED (AT91_CAST(AT91_REG *)        0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor
2739
#define HcControlHeadED (AT91_CAST(AT91_REG *)  0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list
2740
#define HcControlCurrentED (AT91_CAST(AT91_REG *)       0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register
2741
#define HcBulkHeadED    (AT91_CAST(AT91_REG *)  0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list
2742
#define HcBulkCurrentED (AT91_CAST(AT91_REG *)  0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list
2743
#define HcBulkDoneHead  (AT91_CAST(AT91_REG *)  0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor
2744
#define HcFmInterval    (AT91_CAST(AT91_REG *)  0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs
2745
#define HcFmRemaining   (AT91_CAST(AT91_REG *)  0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame
2746
#define HcFmNumber      (AT91_CAST(AT91_REG *)  0x0000003C) // (HcFmNumber) Frame number
2747
#define HcPeriodicStart (AT91_CAST(AT91_REG *)  0x00000040) // (HcPeriodicStart) Periodic Start
2748
#define HcLSThreshold   (AT91_CAST(AT91_REG *)  0x00000044) // (HcLSThreshold) LS Threshold
2749
#define HcRhDescriptorA (AT91_CAST(AT91_REG *)  0x00000048) // (HcRhDescriptorA) Root Hub characteristics A
2750
#define HcRhDescriptorB (AT91_CAST(AT91_REG *)  0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B
2751
#define HcRhStatus      (AT91_CAST(AT91_REG *)  0x00000050) // (HcRhStatus) Root Hub Status register
2752
#define HcRhPortStatus  (AT91_CAST(AT91_REG *)  0x00000054) // (HcRhPortStatus) Root Hub Port Status Register
2753
 
2754
#endif
2755
 
2756
// *****************************************************************************
2757
//              SOFTWARE API DEFINITION  FOR Image Sensor Interface
2758
// *****************************************************************************
2759
#ifndef __ASSEMBLY__
2760
typedef struct _AT91S_ISI {
2761
        AT91_REG         ISI_CR1;       // Control Register 1
2762
        AT91_REG         ISI_CR2;       // Control Register 2
2763
        AT91_REG         ISI_SR;        // Status Register
2764
        AT91_REG         ISI_IER;       // Interrupt Enable Register
2765
        AT91_REG         ISI_IDR;       // Interrupt Disable Register
2766
        AT91_REG         ISI_IMR;       // Interrupt Mask Register
2767
        AT91_REG         Reserved0[2];  // 
2768
        AT91_REG         ISI_PSIZE;     // Preview Size Register
2769
        AT91_REG         ISI_PDECF;     // Preview Decimation Factor Register
2770
        AT91_REG         ISI_PFBD;      // Preview Frame Buffer Address Register
2771
        AT91_REG         ISI_CDBA;      // Codec Dma Address Register
2772
        AT91_REG         ISI_Y2RSET0;   // Color Space Conversion Register
2773
        AT91_REG         ISI_Y2RSET1;   // Color Space Conversion Register
2774
        AT91_REG         ISI_R2YSET0;   // Color Space Conversion Register
2775
        AT91_REG         ISI_R2YSET1;   // Color Space Conversion Register
2776
        AT91_REG         ISI_R2YSET2;   // Color Space Conversion Register
2777
} AT91S_ISI, *AT91PS_ISI;
2778
#else
2779
#define ISI_CR1         (AT91_CAST(AT91_REG *)  0x00000000) // (ISI_CR1) Control Register 1
2780
#define ISI_CR2         (AT91_CAST(AT91_REG *)  0x00000004) // (ISI_CR2) Control Register 2
2781
#define ISI_SR          (AT91_CAST(AT91_REG *)  0x00000008) // (ISI_SR) Status Register
2782
#define ISI_IER         (AT91_CAST(AT91_REG *)  0x0000000C) // (ISI_IER) Interrupt Enable Register
2783
#define ISI_IDR         (AT91_CAST(AT91_REG *)  0x00000010) // (ISI_IDR) Interrupt Disable Register
2784
#define ISI_IMR         (AT91_CAST(AT91_REG *)  0x00000014) // (ISI_IMR) Interrupt Mask Register
2785
#define ISI_PSIZE       (AT91_CAST(AT91_REG *)  0x00000020) // (ISI_PSIZE) Preview Size Register
2786
#define ISI_PDECF       (AT91_CAST(AT91_REG *)  0x00000024) // (ISI_PDECF) Preview Decimation Factor Register
2787
#define ISI_PFBD        (AT91_CAST(AT91_REG *)  0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register
2788
#define ISI_CDBA        (AT91_CAST(AT91_REG *)  0x0000002C) // (ISI_CDBA) Codec Dma Address Register
2789
#define ISI_Y2RSET0     (AT91_CAST(AT91_REG *)  0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register
2790
#define ISI_Y2RSET1     (AT91_CAST(AT91_REG *)  0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register
2791
#define ISI_R2YSET0     (AT91_CAST(AT91_REG *)  0x00000038) // (ISI_R2YSET0) Color Space Conversion Register
2792
#define ISI_R2YSET1     (AT91_CAST(AT91_REG *)  0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register
2793
#define ISI_R2YSET2     (AT91_CAST(AT91_REG *)  0x00000040) // (ISI_R2YSET2) Color Space Conversion Register
2794
 
2795
#endif
2796
// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 -------- 
2797
#define AT91C_ISI_RST         (0x1 <<  0) // (ISI) Image sensor interface reset
2798
#define AT91C_ISI_DISABLE     (0x1 <<  1) // (ISI) image sensor disable.
2799
#define AT91C_ISI_HSYNC_POL   (0x1 <<  2) // (ISI) Horizontal synchronisation polarity
2800
#define AT91C_ISI_PIXCLK_POL  (0x1 <<  4) // (ISI) Pixel Clock Polarity
2801
#define AT91C_ISI_EMB_SYNC    (0x1 <<  6) // (ISI) Embedded synchronisation
2802
#define AT91C_ISI_CRC_SYNC    (0x1 <<  7) // (ISI) CRC correction
2803
#define AT91C_ISI_FULL        (0x1 << 12) // (ISI) Full mode is allowed
2804
#define AT91C_ISI_THMASK      (0x3 << 13) // (ISI) DMA Burst Mask
2805
#define         AT91C_ISI_THMASK_4_8_16_BURST         (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed
2806
#define         AT91C_ISI_THMASK_8_16_BURST           (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed
2807
#define         AT91C_ISI_THMASK_16_BURST             (0x2 << 13) // (ISI) Only 16 AHB burst are allowed
2808
#define AT91C_ISI_CODEC_ON    (0x1 << 15) // (ISI) Enable the codec path
2809
#define AT91C_ISI_SLD         (0xFF << 16) // (ISI) Start of Line Delay
2810
#define AT91C_ISI_SFD         (0xFF << 24) // (ISI) Start of frame Delay
2811
// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 -------- 
2812
#define AT91C_ISI_IM_VSIZE    (0x7FF <<  0) // (ISI) Vertical size of the Image sensor [0..2047]
2813
#define AT91C_ISI_GS_MODE     (0x1 << 11) // (ISI) Grayscale Memory Mode
2814
#define AT91C_ISI_RGB_MODE    (0x3 << 12) // (ISI) RGB mode
2815
#define         AT91C_ISI_RGB_MODE_RGB_888              (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
2816
#define         AT91C_ISI_RGB_MODE_RGB_565              (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
2817
#define         AT91C_ISI_RGB_MODE_RGB_555              (0x2 << 12) // (ISI) RGB 5:5:5 16 bits
2818
#define AT91C_ISI_GRAYSCALE   (0x1 << 13) // (ISI) Grayscale Mode
2819
#define AT91C_ISI_RGB_SWAP    (0x1 << 14) // (ISI) RGB Swap
2820
#define AT91C_ISI_COL_SPACE   (0x1 << 15) // (ISI) Color space for the image data
2821
#define AT91C_ISI_IM_HSIZE    (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
2822
#define         AT91C_ISI_RGB_MODE_YCC_DEF              (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
2823
#define         AT91C_ISI_RGB_MODE_YCC_MOD1             (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
2824
#define         AT91C_ISI_RGB_MODE_YCC_MOD2             (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
2825
#define         AT91C_ISI_RGB_MODE_YCC_MOD3             (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
2826
#define AT91C_ISI_RGB_CFG     (0x3 << 30) // (ISI) RGB configuration
2827
#define         AT91C_ISI_RGB_CFG_RGB_DEF              (0x0 << 30) // (ISI) R/G(MSB)  G(LSB)/B  R/G(MSB)  G(LSB)/B
2828
#define         AT91C_ISI_RGB_CFG_RGB_MOD1             (0x1 << 30) // (ISI) B/G(MSB)  G(LSB)/R  B/G(MSB)  G(LSB)/R
2829
#define         AT91C_ISI_RGB_CFG_RGB_MOD2             (0x2 << 30) // (ISI) G(LSB)/R  B/G(MSB)  G(LSB)/R  B/G(MSB)
2830
#define         AT91C_ISI_RGB_CFG_RGB_MOD3             (0x3 << 30) // (ISI) G(LSB)/B  R/G(MSB)  G(LSB)/B  R/G(MSB)
2831
// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register -------- 
2832
#define AT91C_ISI_SOF         (0x1 <<  0) // (ISI) Start of Frame
2833
#define AT91C_ISI_DIS         (0x1 <<  1) // (ISI) Image Sensor Interface disable
2834
#define AT91C_ISI_SOFTRST     (0x1 <<  2) // (ISI) Software Reset
2835
#define AT91C_ISI_CRC_ERR     (0x1 <<  4) // (ISI) CRC synchronisation error
2836
#define AT91C_ISI_FO_C_OVF    (0x1 <<  5) // (ISI) Fifo Codec Overflow 
2837
#define AT91C_ISI_FO_P_OVF    (0x1 <<  6) // (ISI) Fifo Preview Overflow 
2838
#define AT91C_ISI_FO_P_EMP    (0x1 <<  7) // (ISI) Fifo Preview Empty
2839
#define AT91C_ISI_FO_C_EMP    (0x1 <<  8) // (ISI) Fifo Codec Empty
2840
#define AT91C_ISI_FR_OVR      (0x1 <<  9) // (ISI) Frame rate overun
2841
// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register -------- 
2842
// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register -------- 
2843
// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register -------- 
2844
// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register -------- 
2845
#define AT91C_ISI_PREV_VSIZE  (0x3FF <<  0) // (ISI) Vertical size for the preview path
2846
#define AT91C_ISI_PREV_HSIZE  (0x3FF << 16) // (ISI) Horizontal size for the preview path
2847
// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register -------- 
2848
#define AT91C_ISI_Y2R_C0      (0xFF <<  0) // (ISI) Color Space Conversion Matrix Coefficient C0
2849
#define AT91C_ISI_Y2R_C1      (0xFF <<  8) // (ISI) Color Space Conversion Matrix Coefficient C1
2850
#define AT91C_ISI_Y2R_C2      (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
2851
#define AT91C_ISI_Y2R_C3      (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
2852
// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- 
2853
#define AT91C_ISI_Y2R_C4      (0x1FF <<  0) // (ISI) Color Space Conversion Matrix Coefficient C4
2854
#define AT91C_ISI_Y2R_YOFF    (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset
2855
#define AT91C_ISI_Y2R_CROFF   (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset
2856
#define AT91C_ISI_Y2R_CBFF    (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset
2857
// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register -------- 
2858
#define AT91C_ISI_R2Y_C0      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
2859
#define AT91C_ISI_R2Y_C1      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
2860
#define AT91C_ISI_R2Y_C2      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
2861
#define AT91C_ISI_R2Y_ROFF    (0x1 <<  4) // (ISI) Color Space Conversion Red component offset
2862
// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register -------- 
2863
#define AT91C_ISI_R2Y_C3      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
2864
#define AT91C_ISI_R2Y_C4      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
2865
#define AT91C_ISI_R2Y_C5      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
2866
#define AT91C_ISI_R2Y_GOFF    (0x1 <<  4) // (ISI) Color Space Conversion Green component offset
2867
// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register -------- 
2868
#define AT91C_ISI_R2Y_C6      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
2869
#define AT91C_ISI_R2Y_C7      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
2870
#define AT91C_ISI_R2Y_C8      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
2871
#define AT91C_ISI_R2Y_BOFF    (0x1 <<  4) // (ISI) Color Space Conversion Blue component offset
2872
 
2873
// *****************************************************************************
2874
//               REGISTER ADDRESS DEFINITION FOR AT91SAM9XE512
2875
// *****************************************************************************
2876
// ========== Register definition for SYS peripheral ========== 
2877
#define AT91C_SYS_GPBR  (AT91_CAST(AT91_REG *)  0xFFFFFFFF) // (SYS) General Purpose Register
2878
// ========== Register definition for EBI peripheral ========== 
2879
#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *)  0xFFFFEA00) // (EBI) Dummy register - Do not use
2880
// ========== Register definition for HECC peripheral ========== 
2881
#define AT91C_HECC_VR   (AT91_CAST(AT91_REG *)  0xFFFFE8FC) // (HECC)  ECC Version register
2882
#define AT91C_HECC_NPR  (AT91_CAST(AT91_REG *)  0xFFFFE810) // (HECC)  ECC Parity N register
2883
#define AT91C_HECC_SR   (AT91_CAST(AT91_REG *)  0xFFFFE808) // (HECC)  ECC Status register
2884
#define AT91C_HECC_PR   (AT91_CAST(AT91_REG *)  0xFFFFE80C) // (HECC)  ECC Parity register
2885
#define AT91C_HECC_MR   (AT91_CAST(AT91_REG *)  0xFFFFE804) // (HECC)  ECC Page size register
2886
#define AT91C_HECC_CR   (AT91_CAST(AT91_REG *)  0xFFFFE800) // (HECC)  ECC reset register
2887
// ========== Register definition for SDRAMC peripheral ========== 
2888
#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *)  0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register
2889
#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *)         0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
2890
#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *)         0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register
2891
#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *)         0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register
2892
#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *)         0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register
2893
#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *)  0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register
2894
#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *)  0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register
2895
#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *)         0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register
2896
#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *)         0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register
2897
#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *)         0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register
2898
// ========== Register definition for SMC peripheral ========== 
2899
#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *)  0xFFFFEC1C) // (SMC)  Control Register for CS 1
2900
#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *)         0xFFFFEC74) // (SMC)  Pulse Register for CS 7
2901
#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *)         0xFFFFEC64) // (SMC)  Pulse Register for CS 6
2902
#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *)         0xFFFFEC40) // (SMC)  Setup Register for CS 4
2903
#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *)         0xFFFFEC34) // (SMC)  Pulse Register for CS 3
2904
#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *)         0xFFFFEC58) // (SMC)  Cycle Register for CS 5
2905
#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *)         0xFFFFEC28) // (SMC)  Cycle Register for CS 2
2906
#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *)  0xFFFFEC2C) // (SMC)  Control Register for CS 2
2907
#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *)  0xFFFFEC0C) // (SMC)  Control Register for CS 0
2908
#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *)         0xFFFFEC54) // (SMC)  Pulse Register for CS 5
2909
#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *)         0xFFFFEC14) // (SMC)  Pulse Register for CS 1
2910
#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *)         0xFFFFEC04) // (SMC)  Pulse Register for CS 0
2911
#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *)         0xFFFFEC78) // (SMC)  Cycle Register for CS 7
2912
#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *)  0xFFFFEC4C) // (SMC)  Control Register for CS 4
2913
#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *)  0xFFFFEC3C) // (SMC)  Control Register for CS 3
2914
#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *)         0xFFFFEC70) // (SMC)  Setup Register for CS 7
2915
#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *)  0xFFFFEC7C) // (SMC)  Control Register for CS 7
2916
#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *)         0xFFFFEC10) // (SMC)  Setup Register for CS 1
2917
#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *)         0xFFFFEC08) // (SMC)  Cycle Register for CS 0
2918
#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *)  0xFFFFEC5C) // (SMC)  Control Register for CS 5
2919
#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *)         0xFFFFEC18) // (SMC)  Cycle Register for CS 1
2920
#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *)  0xFFFFEC6C) // (SMC)  Control Register for CS 6
2921
#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *)         0xFFFFEC00) // (SMC)  Setup Register for CS 0
2922
#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *)         0xFFFFEC44) // (SMC)  Pulse Register for CS 4
2923
#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *)         0xFFFFEC50) // (SMC)  Setup Register for CS 5
2924
#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *)         0xFFFFEC20) // (SMC)  Setup Register for CS 2
2925
#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *)         0xFFFFEC38) // (SMC)  Cycle Register for CS 3
2926
#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *)         0xFFFFEC68) // (SMC)  Cycle Register for CS 6
2927
#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *)         0xFFFFEC60) // (SMC)  Setup Register for CS 6
2928
#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *)         0xFFFFEC48) // (SMC)  Cycle Register for CS 4
2929
#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *)         0xFFFFEC24) // (SMC)  Pulse Register for CS 2
2930
#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *)         0xFFFFEC30) // (SMC)  Setup Register for CS 3
2931
// ========== Register definition for MATRIX peripheral ========== 
2932
#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *)       0xFFFFEE00) // (MATRIX)  Master Configuration Register 0 (ram96k)     
2933
#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *)       0xFFFFEE1C) // (MATRIX)  Master Configuration Register 7 (teak_prog)     
2934
#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *)       0xFFFFEE44) // (MATRIX)  Slave Configuration Register 1 (rom)    
2935
#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *)       0xFFFFEE10) // (MATRIX)  Master Configuration Register 4 (bridge)    
2936
#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *)     0xFFFFEFFC) // (MATRIX)  Version Register
2937
#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *)       0xFFFFEE08) // (MATRIX)  Master Configuration Register 2 (hperiphs) 
2938
#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *)       0xFFFFEEA4) // (MATRIX)  PRBS4 : ebi
2939
#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *)       0xFFFFEE84) // (MATRIX)  PRBS0 (ram0) 
2940
#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *)       0xFFFFEE4C) // (MATRIX)  Slave Configuration Register 3 (ebi)
2941
#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *)       0xFFFFEE18) // (MATRIX)  Master Configuration Register 6 (ram16k)  
2942
#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *)         0xFFFFEF1C) // (MATRIX)  Slave 3 (ebi) Special Function Register
2943
#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *)       0xFFFFEE40) // (MATRIX)  Slave Configuration Register 0 (ram96k)     
2944
#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *)       0xFFFFEE9C) // (MATRIX)  PRBS3 : usb_dev_hs
2945
#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *)       0xFFFFEE98) // (MATRIX)  PRAS3 : usb_dev_hs
2946
#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *)       0xFFFFEE80) // (MATRIX)  PRAS0 (ram0) 
2947
#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *)       0xFFFFEE0C) // (MATRIX)  Master Configuration Register 3 (ebi)
2948
#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *)       0xFFFFEE88) // (MATRIX)  PRAS1 (ram1) 
2949
#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *)       0xFFFFEE90) // (MATRIX)  PRAS2 (ram2) 
2950
#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *)       0xFFFFEE48) // (MATRIX)  Slave Configuration Register 2 (hperiphs) 
2951
#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *)       0xFFFFEE14) // (MATRIX)  Master Configuration Register 5 (mailbox)    
2952
#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *)       0xFFFFEE04) // (MATRIX)  Master Configuration Register 1 (rom)    
2953
#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *)       0xFFFFEEA0) // (MATRIX)  PRAS4 : ebi
2954
#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *)        0xFFFFEF00) // (MATRIX)  Master Remp Control Register 
2955
#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *)       0xFFFFEE94) // (MATRIX)  PRBS2 (ram2) 
2956
#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *)       0xFFFFEE50) // (MATRIX)  Slave Configuration Register 4 (bridge)    
2957
#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *)     0xFFFFEF2C) // (MATRIX)  Slave 7 (teak_prog) Special Function Register
2958
#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *)       0xFFFFEE8C) // (MATRIX)  PRBS1 (ram1) 
2959
// ========== Register definition for CCFG peripheral ========== 
2960
#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *)         0xFFFFEFFC) // (CCFG)  Version Register
2961
#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *)        0xFFFFEF1C) // (CCFG)  EBI Chip Select Assignement Register
2962
// ========== Register definition for PDC_DBGU peripheral ========== 
2963
#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *)  0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
2964
#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *)  0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
2965
#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *)  0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
2966
#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *)  0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
2967
#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *)  0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
2968
#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *)  0xFFFFF304) // (PDC_DBGU) Receive Counter Register
2969
#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *)  0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
2970
#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *)  0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
2971
#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *)  0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
2972
#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *)  0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
2973
// ========== Register definition for DBGU peripheral ========== 
2974
#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *)  0xFFFFF244) // (DBGU) Chip ID Extension Register
2975
#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *)  0xFFFFF220) // (DBGU) Baud Rate Generator Register
2976
#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *)  0xFFFFF20C) // (DBGU) Interrupt Disable Register
2977
#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *)  0xFFFFF214) // (DBGU) Channel Status Register
2978
#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *)  0xFFFFF240) // (DBGU) Chip ID Register
2979
#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *)  0xFFFFF204) // (DBGU) Mode Register
2980
#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *)  0xFFFFF210) // (DBGU) Interrupt Mask Register
2981
#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *)  0xFFFFF200) // (DBGU) Control Register
2982
#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *)  0xFFFFF248) // (DBGU) Force NTRST Register
2983
#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *)  0xFFFFF21C) // (DBGU) Transmitter Holding Register
2984
#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *)  0xFFFFF218) // (DBGU) Receiver Holding Register
2985
#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *)  0xFFFFF208) // (DBGU) Interrupt Enable Register
2986
// ========== Register definition for AIC peripheral ========== 
2987
#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *)  0xFFFFF100) // (AIC) IRQ Vector Register
2988
#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *)  0xFFFFF000) // (AIC) Source Mode Register
2989
#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *)  0xFFFFF104) // (AIC) FIQ Vector Register
2990
#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *)  0xFFFFF138) // (AIC) Debug Control Register (Protect)
2991
#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *)  0xFFFFF130) // (AIC) End of Interrupt Command Register
2992
#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *)  0xFFFFF080) // (AIC) Source Vector Register
2993
#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *)  0xFFFFF148) // (AIC) Fast Forcing Status Register
2994
#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *)  0xFFFFF128) // (AIC) Interrupt Clear Command Register
2995
#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *)  0xFFFFF108) // (AIC) Interrupt Status Register
2996
#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *)  0xFFFFF110) // (AIC) Interrupt Mask Register
2997
#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *)  0xFFFFF10C) // (AIC) Interrupt Pending Register
2998
#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *)  0xFFFFF140) // (AIC) Fast Forcing Enable Register
2999
#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *)  0xFFFFF120) // (AIC) Interrupt Enable Command Register
3000
#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *)  0xFFFFF12C) // (AIC) Interrupt Set Command Register
3001
#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *)  0xFFFFF144) // (AIC) Fast Forcing Disable Register
3002
#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *)  0xFFFFF114) // (AIC) Core Interrupt Status Register
3003
#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *)  0xFFFFF124) // (AIC) Interrupt Disable Command Register
3004
#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *)  0xFFFFF134) // (AIC) Spurious Vector Register
3005
// ========== Register definition for PIOA peripheral ========== 
3006
#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *)  0xFFFFF414) // (PIOA) Output Disable Registerr
3007
#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *)  0xFFFFF430) // (PIOA) Set Output Data Register
3008
#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *)  0xFFFFF44C) // (PIOA) Interrupt Status Register
3009
#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *)  0xFFFFF478) // (PIOA) AB Select Status Register
3010
#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *)  0xFFFFF440) // (PIOA) Interrupt Enable Register
3011
#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *)         0xFFFFF460) // (PIOA) Pull-up Disable Register
3012
#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *)  0xFFFFF448) // (PIOA) Interrupt Mask Register
3013
#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *)  0xFFFFF400) // (PIOA) PIO Enable Register
3014
#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *)  0xFFFFF424) // (PIOA) Input Filter Disable Register
3015
#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *)  0xFFFFF4A4) // (PIOA) Output Write Disable Register
3016
#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *)  0xFFFFF458) // (PIOA) Multi-driver Status Register
3017
#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *)  0xFFFFF444) // (PIOA) Interrupt Disable Register
3018
#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *)  0xFFFFF438) // (PIOA) Output Data Status Register
3019
#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *)         0xFFFFF468) // (PIOA) Pull-up Status Register
3020
#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *)  0xFFFFF4A8) // (PIOA) Output Write Status Register
3021
#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *)  0xFFFFF474) // (PIOA) Select B Register
3022
#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *)  0xFFFFF4A0) // (PIOA) Output Write Enable Register
3023
#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *)  0xFFFFF420) // (PIOA) Input Filter Enable Register
3024
#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *)  0xFFFFF43C) // (PIOA) Pin Data Status Register
3025
#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *)         0xFFFFF464) // (PIOA) Pull-up Enable Register
3026
#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *)  0xFFFFF418) // (PIOA) Output Status Register
3027
#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *)  0xFFFFF470) // (PIOA) Select A Register
3028
#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *)  0xFFFFF454) // (PIOA) Multi-driver Disable Register
3029
#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *)  0xFFFFF434) // (PIOA) Clear Output Data Register
3030
#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *)  0xFFFFF450) // (PIOA) Multi-driver Enable Register
3031
#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *)  0xFFFFF404) // (PIOA) PIO Disable Register
3032
#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *)  0xFFFFF428) // (PIOA) Input Filter Status Register
3033
#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *)  0xFFFFF410) // (PIOA) Output Enable Register
3034
#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *)  0xFFFFF408) // (PIOA) PIO Status Register
3035
// ========== Register definition for PIOB peripheral ========== 
3036
#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *)  0xFFFFF6A4) // (PIOB) Output Write Disable Register
3037
#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *)  0xFFFFF650) // (PIOB) Multi-driver Enable Register
3038
#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *)         0xFFFFF668) // (PIOB) Pull-up Status Register
3039
#define AT91C_PIOB_IMR  (AT91_CAST(AT91_REG *)  0xFFFFF648) // (PIOB) Interrupt Mask Register
3040
#define AT91C_PIOB_ASR  (AT91_CAST(AT91_REG *)  0xFFFFF670) // (PIOB) Select A Register
3041
#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *)         0xFFFFF660) // (PIOB) Pull-up Disable Register
3042
#define AT91C_PIOB_PSR  (AT91_CAST(AT91_REG *)  0xFFFFF608) // (PIOB) PIO Status Register
3043
#define AT91C_PIOB_IER  (AT91_CAST(AT91_REG *)  0xFFFFF640) // (PIOB) Interrupt Enable Register
3044
#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *)  0xFFFFF634) // (PIOB) Clear Output Data Register
3045
#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *)  0xFFFFF6A0) // (PIOB) Output Write Enable Register
3046
#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *)  0xFFFFF678) // (PIOB) AB Select Status Register
3047
#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *)  0xFFFFF624) // (PIOB) Input Filter Disable Register
3048
#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *)  0xFFFFF63C) // (PIOB) Pin Data Status Register
3049
#define AT91C_PIOB_IDR  (AT91_CAST(AT91_REG *)  0xFFFFF644) // (PIOB) Interrupt Disable Register
3050
#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *)  0xFFFFF6A8) // (PIOB) Output Write Status Register
3051
#define AT91C_PIOB_PDR  (AT91_CAST(AT91_REG *)  0xFFFFF604) // (PIOB) PIO Disable Register
3052
#define AT91C_PIOB_ODR  (AT91_CAST(AT91_REG *)  0xFFFFF614) // (PIOB) Output Disable Registerr
3053
#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *)  0xFFFFF628) // (PIOB) Input Filter Status Register
3054
#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *)         0xFFFFF664) // (PIOB) Pull-up Enable Register
3055
#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *)  0xFFFFF630) // (PIOB) Set Output Data Register
3056
#define AT91C_PIOB_ISR  (AT91_CAST(AT91_REG *)  0xFFFFF64C) // (PIOB) Interrupt Status Register
3057
#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *)  0xFFFFF638) // (PIOB) Output Data Status Register
3058
#define AT91C_PIOB_OSR  (AT91_CAST(AT91_REG *)  0xFFFFF618) // (PIOB) Output Status Register
3059
#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *)  0xFFFFF658) // (PIOB) Multi-driver Status Register
3060
#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *)  0xFFFFF620) // (PIOB) Input Filter Enable Register
3061
#define AT91C_PIOB_BSR  (AT91_CAST(AT91_REG *)  0xFFFFF674) // (PIOB) Select B Register
3062
#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *)  0xFFFFF654) // (PIOB) Multi-driver Disable Register
3063
#define AT91C_PIOB_OER  (AT91_CAST(AT91_REG *)  0xFFFFF610) // (PIOB) Output Enable Register
3064
#define AT91C_PIOB_PER  (AT91_CAST(AT91_REG *)  0xFFFFF600) // (PIOB) PIO Enable Register
3065
// ========== Register definition for PIOC peripheral ========== 
3066
#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *)  0xFFFFF8A4) // (PIOC) Output Write Disable Register
3067
#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *)  0xFFFFF830) // (PIOC) Set Output Data Register
3068
#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *)         0xFFFFF864) // (PIOC) Pull-up Enable Register
3069
#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *)  0xFFFFF834) // (PIOC) Clear Output Data Register
3070
#define AT91C_PIOC_PSR  (AT91_CAST(AT91_REG *)  0xFFFFF808) // (PIOC) PIO Status Register
3071
#define AT91C_PIOC_PDR  (AT91_CAST(AT91_REG *)  0xFFFFF804) // (PIOC) PIO Disable Register
3072
#define AT91C_PIOC_ODR  (AT91_CAST(AT91_REG *)  0xFFFFF814) // (PIOC) Output Disable Registerr
3073
#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *)         0xFFFFF868) // (PIOC) Pull-up Status Register
3074
#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *)  0xFFFFF878) // (PIOC) AB Select Status Register
3075
#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *)  0xFFFFF828) // (PIOC) Input Filter Status Register
3076
#define AT91C_PIOC_OER  (AT91_CAST(AT91_REG *)  0xFFFFF810) // (PIOC) Output Enable Register
3077
#define AT91C_PIOC_IMR  (AT91_CAST(AT91_REG *)  0xFFFFF848) // (PIOC) Interrupt Mask Register
3078
#define AT91C_PIOC_ASR  (AT91_CAST(AT91_REG *)  0xFFFFF870) // (PIOC) Select A Register
3079
#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *)  0xFFFFF854) // (PIOC) Multi-driver Disable Register
3080
#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *)  0xFFFFF8A8) // (PIOC) Output Write Status Register
3081
#define AT91C_PIOC_PER  (AT91_CAST(AT91_REG *)  0xFFFFF800) // (PIOC) PIO Enable Register
3082
#define AT91C_PIOC_IDR  (AT91_CAST(AT91_REG *)  0xFFFFF844) // (PIOC) Interrupt Disable Register
3083
#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *)  0xFFFFF850) // (PIOC) Multi-driver Enable Register
3084
#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *)  0xFFFFF83C) // (PIOC) Pin Data Status Register
3085
#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *)  0xFFFFF858) // (PIOC) Multi-driver Status Register
3086
#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *)  0xFFFFF8A0) // (PIOC) Output Write Enable Register
3087
#define AT91C_PIOC_BSR  (AT91_CAST(AT91_REG *)  0xFFFFF874) // (PIOC) Select B Register
3088
#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *)         0xFFFFF860) // (PIOC) Pull-up Disable Register
3089
#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *)  0xFFFFF824) // (PIOC) Input Filter Disable Register
3090
#define AT91C_PIOC_IER  (AT91_CAST(AT91_REG *)  0xFFFFF840) // (PIOC) Interrupt Enable Register
3091
#define AT91C_PIOC_OSR  (AT91_CAST(AT91_REG *)  0xFFFFF818) // (PIOC) Output Status Register
3092
#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *)  0xFFFFF838) // (PIOC) Output Data Status Register
3093
#define AT91C_PIOC_ISR  (AT91_CAST(AT91_REG *)  0xFFFFF84C) // (PIOC) Interrupt Status Register
3094
#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *)  0xFFFFF820) // (PIOC) Input Filter Enable Register
3095
// ========== Register definition for EFC peripheral ========== 
3096
#define AT91C_EFC_FVR   (AT91_CAST(AT91_REG *)  0xFFFFFA10) // (EFC) EFC Flash Version Register
3097
#define AT91C_EFC_FCR   (AT91_CAST(AT91_REG *)  0xFFFFFA04) // (EFC) EFC Flash Command Register
3098
#define AT91C_EFC_FMR   (AT91_CAST(AT91_REG *)  0xFFFFFA00) // (EFC) EFC Flash Mode Register
3099
#define AT91C_EFC_FRR   (AT91_CAST(AT91_REG *)  0xFFFFFA0C) // (EFC) EFC Flash Result Register
3100
#define AT91C_EFC_FSR   (AT91_CAST(AT91_REG *)  0xFFFFFA08) // (EFC) EFC Flash Status Register
3101
// ========== Register definition for CKGR peripheral ========== 
3102
#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *)  0xFFFFFC20) // (CKGR) Main Oscillator Register
3103
#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *)         0xFFFFFC2C) // (CKGR) PLL B Register
3104
#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *)  0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
3105
#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *)         0xFFFFFC28) // (CKGR) PLL A Register
3106
// ========== Register definition for PMC peripheral ========== 
3107
#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *)  0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
3108
#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *)  0xFFFFFC40) // (PMC) Programmable Clock Register
3109
#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *)  0xFFFFFC30) // (PMC) Master Clock Register
3110
#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *)  0xFFFFFC28) // (PMC) PLL A Register
3111
#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *)  0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
3112
#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *)  0xFFFFFC08) // (PMC) System Clock Status Register
3113
#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *)  0xFFFFFC24) // (PMC) Main Clock  Frequency Register
3114
#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *)  0xFFFFFC6C) // (PMC) Interrupt Mask Register
3115
#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *)  0xFFFFFC60) // (PMC) Interrupt Enable Register
3116
#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *)  0xFFFFFC20) // (PMC) Main Oscillator Register
3117
#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *)  0xFFFFFC64) // (PMC) Interrupt Disable Register
3118
#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *)  0xFFFFFC2C) // (PMC) PLL B Register
3119
#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *)  0xFFFFFC04) // (PMC) System Clock Disable Register
3120
#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *)  0xFFFFFC18) // (PMC) Peripheral Clock Status Register
3121
#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *)  0xFFFFFC00) // (PMC) System Clock Enable Register
3122
#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *)  0xFFFFFC68) // (PMC) Status Register
3123
// ========== Register definition for RSTC peripheral ========== 
3124
#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *)  0xFFFFFD00) // (RSTC) Reset Control Register
3125
#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *)  0xFFFFFD08) // (RSTC) Reset Mode Register
3126
#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *)  0xFFFFFD04) // (RSTC) Reset Status Register
3127
// ========== Register definition for SHDWC peripheral ========== 
3128
#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *)         0xFFFFFD18) // (SHDWC) Shut Down Status Register
3129
#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *)         0xFFFFFD14) // (SHDWC) Shut Down Mode Register
3130
#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *)         0xFFFFFD10) // (SHDWC) Shut Down Control Register
3131
// ========== Register definition for RTTC peripheral ========== 
3132
#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *)  0xFFFFFD2C) // (RTTC) Real-time Status Register
3133
#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *)  0xFFFFFD20) // (RTTC) Real-time Mode Register
3134
#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *)  0xFFFFFD28) // (RTTC) Real-time Value Register
3135
#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *)  0xFFFFFD24) // (RTTC) Real-time Alarm Register
3136
// ========== Register definition for PITC peripheral ========== 
3137
#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *)  0xFFFFFD38) // (PITC) Period Interval Value Register
3138
#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *)  0xFFFFFD34) // (PITC) Period Interval Status Register
3139
#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *)  0xFFFFFD3C) // (PITC) Period Interval Image Register
3140
#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *)  0xFFFFFD30) // (PITC) Period Interval Mode Register
3141
// ========== Register definition for WDTC peripheral ========== 
3142
#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *)  0xFFFFFD40) // (WDTC) Watchdog Control Register
3143
#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *)  0xFFFFFD48) // (WDTC) Watchdog Status Register
3144
#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *)  0xFFFFFD44) // (WDTC) Watchdog Mode Register
3145
// ========== Register definition for TC0 peripheral ========== 
3146
#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *)  0xFFFA0020) // (TC0) Status Register
3147
#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *)  0xFFFA001C) // (TC0) Register C
3148
#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *)  0xFFFA0018) // (TC0) Register B
3149
#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *)  0xFFFA0000) // (TC0) Channel Control Register
3150
#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *)  0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
3151
#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *)  0xFFFA0024) // (TC0) Interrupt Enable Register
3152
#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *)  0xFFFA0014) // (TC0) Register A
3153
#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *)  0xFFFA0028) // (TC0) Interrupt Disable Register
3154
#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *)  0xFFFA0010) // (TC0) Counter Value
3155
#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *)  0xFFFA002C) // (TC0) Interrupt Mask Register
3156
// ========== Register definition for TC1 peripheral ========== 
3157
#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *)  0xFFFA0058) // (TC1) Register B
3158
#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *)  0xFFFA0040) // (TC1) Channel Control Register
3159
#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *)  0xFFFA0064) // (TC1) Interrupt Enable Register
3160
#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *)  0xFFFA0068) // (TC1) Interrupt Disable Register
3161
#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *)  0xFFFA0060) // (TC1) Status Register
3162
#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *)  0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
3163
#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *)  0xFFFA0054) // (TC1) Register A
3164
#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *)  0xFFFA005C) // (TC1) Register C
3165
#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *)  0xFFFA006C) // (TC1) Interrupt Mask Register
3166
#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *)  0xFFFA0050) // (TC1) Counter Value
3167
// ========== Register definition for TC2 peripheral ========== 
3168
#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *)  0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
3169
#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *)  0xFFFA0080) // (TC2) Channel Control Register
3170
#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *)  0xFFFA0090) // (TC2) Counter Value
3171
#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *)  0xFFFA0094) // (TC2) Register A
3172
#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *)  0xFFFA0098) // (TC2) Register B
3173
#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *)  0xFFFA00A8) // (TC2) Interrupt Disable Register
3174
#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *)  0xFFFA00AC) // (TC2) Interrupt Mask Register
3175
#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *)  0xFFFA009C) // (TC2) Register C
3176
#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *)  0xFFFA00A4) // (TC2) Interrupt Enable Register
3177
#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *)  0xFFFA00A0) // (TC2) Status Register
3178
// ========== Register definition for TC3 peripheral ========== 
3179
#define AT91C_TC3_IER   (AT91_CAST(AT91_REG *)  0xFFFDC024) // (TC3) Interrupt Enable Register
3180
#define AT91C_TC3_RB    (AT91_CAST(AT91_REG *)  0xFFFDC018) // (TC3) Register B
3181
#define AT91C_TC3_CMR   (AT91_CAST(AT91_REG *)  0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
3182
#define AT91C_TC3_RC    (AT91_CAST(AT91_REG *)  0xFFFDC01C) // (TC3) Register C
3183
#define AT91C_TC3_CCR   (AT91_CAST(AT91_REG *)  0xFFFDC000) // (TC3) Channel Control Register
3184
#define AT91C_TC3_SR    (AT91_CAST(AT91_REG *)  0xFFFDC020) // (TC3) Status Register
3185
#define AT91C_TC3_CV    (AT91_CAST(AT91_REG *)  0xFFFDC010) // (TC3) Counter Value
3186
#define AT91C_TC3_RA    (AT91_CAST(AT91_REG *)  0xFFFDC014) // (TC3) Register A
3187
#define AT91C_TC3_IDR   (AT91_CAST(AT91_REG *)  0xFFFDC028) // (TC3) Interrupt Disable Register
3188
#define AT91C_TC3_IMR   (AT91_CAST(AT91_REG *)  0xFFFDC02C) // (TC3) Interrupt Mask Register
3189
// ========== Register definition for TC4 peripheral ========== 
3190
#define AT91C_TC4_CMR   (AT91_CAST(AT91_REG *)  0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
3191
#define AT91C_TC4_RC    (AT91_CAST(AT91_REG *)  0xFFFDC05C) // (TC4) Register C
3192
#define AT91C_TC4_SR    (AT91_CAST(AT91_REG *)  0xFFFDC060) // (TC4) Status Register
3193
#define AT91C_TC4_RB    (AT91_CAST(AT91_REG *)  0xFFFDC058) // (TC4) Register B
3194
#define AT91C_TC4_IER   (AT91_CAST(AT91_REG *)  0xFFFDC064) // (TC4) Interrupt Enable Register
3195
#define AT91C_TC4_CV    (AT91_CAST(AT91_REG *)  0xFFFDC050) // (TC4) Counter Value
3196
#define AT91C_TC4_RA    (AT91_CAST(AT91_REG *)  0xFFFDC054) // (TC4) Register A
3197
#define AT91C_TC4_IDR   (AT91_CAST(AT91_REG *)  0xFFFDC068) // (TC4) Interrupt Disable Register
3198
#define AT91C_TC4_IMR   (AT91_CAST(AT91_REG *)  0xFFFDC06C) // (TC4) Interrupt Mask Register
3199
#define AT91C_TC4_CCR   (AT91_CAST(AT91_REG *)  0xFFFDC040) // (TC4) Channel Control Register
3200
// ========== Register definition for TC5 peripheral ========== 
3201
#define AT91C_TC5_RB    (AT91_CAST(AT91_REG *)  0xFFFDC098) // (TC5) Register B
3202
#define AT91C_TC5_RA    (AT91_CAST(AT91_REG *)  0xFFFDC094) // (TC5) Register A
3203
#define AT91C_TC5_CV    (AT91_CAST(AT91_REG *)  0xFFFDC090) // (TC5) Counter Value
3204
#define AT91C_TC5_CCR   (AT91_CAST(AT91_REG *)  0xFFFDC080) // (TC5) Channel Control Register
3205
#define AT91C_TC5_SR    (AT91_CAST(AT91_REG *)  0xFFFDC0A0) // (TC5) Status Register
3206
#define AT91C_TC5_IER   (AT91_CAST(AT91_REG *)  0xFFFDC0A4) // (TC5) Interrupt Enable Register
3207
#define AT91C_TC5_IDR   (AT91_CAST(AT91_REG *)  0xFFFDC0A8) // (TC5) Interrupt Disable Register
3208
#define AT91C_TC5_RC    (AT91_CAST(AT91_REG *)  0xFFFDC09C) // (TC5) Register C
3209
#define AT91C_TC5_IMR   (AT91_CAST(AT91_REG *)  0xFFFDC0AC) // (TC5) Interrupt Mask Register
3210
#define AT91C_TC5_CMR   (AT91_CAST(AT91_REG *)  0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
3211
// ========== Register definition for TCB0 peripheral ========== 
3212
#define AT91C_TCB0_BMR  (AT91_CAST(AT91_REG *)  0xFFFA00C4) // (TCB0) TC Block Mode Register
3213
#define AT91C_TCB0_BCR  (AT91_CAST(AT91_REG *)  0xFFFA00C0) // (TCB0) TC Block Control Register
3214
// ========== Register definition for TCB1 peripheral ========== 
3215
#define AT91C_TCB1_BCR  (AT91_CAST(AT91_REG *)  0xFFFDC0C0) // (TCB1) TC Block Control Register
3216
#define AT91C_TCB1_BMR  (AT91_CAST(AT91_REG *)  0xFFFDC0C4) // (TCB1) TC Block Mode Register
3217
// ========== Register definition for PDC_MCI peripheral ========== 
3218
#define AT91C_MCI_RNCR  (AT91_CAST(AT91_REG *)  0xFFFA8114) // (PDC_MCI) Receive Next Counter Register
3219
#define AT91C_MCI_TCR   (AT91_CAST(AT91_REG *)  0xFFFA810C) // (PDC_MCI) Transmit Counter Register
3220
#define AT91C_MCI_RCR   (AT91_CAST(AT91_REG *)  0xFFFA8104) // (PDC_MCI) Receive Counter Register
3221
#define AT91C_MCI_TNPR  (AT91_CAST(AT91_REG *)  0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register
3222
#define AT91C_MCI_RNPR  (AT91_CAST(AT91_REG *)  0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register
3223
#define AT91C_MCI_RPR   (AT91_CAST(AT91_REG *)  0xFFFA8100) // (PDC_MCI) Receive Pointer Register
3224
#define AT91C_MCI_TNCR  (AT91_CAST(AT91_REG *)  0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register
3225
#define AT91C_MCI_TPR   (AT91_CAST(AT91_REG *)  0xFFFA8108) // (PDC_MCI) Transmit Pointer Register
3226
#define AT91C_MCI_PTSR  (AT91_CAST(AT91_REG *)  0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register
3227
#define AT91C_MCI_PTCR  (AT91_CAST(AT91_REG *)  0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register
3228
// ========== Register definition for MCI peripheral ========== 
3229
#define AT91C_MCI_RDR   (AT91_CAST(AT91_REG *)  0xFFFA8030) // (MCI) MCI Receive Data Register
3230
#define AT91C_MCI_CMDR  (AT91_CAST(AT91_REG *)  0xFFFA8014) // (MCI) MCI Command Register
3231
#define AT91C_MCI_VR    (AT91_CAST(AT91_REG *)  0xFFFA80FC) // (MCI) MCI Version Register
3232
#define AT91C_MCI_IDR   (AT91_CAST(AT91_REG *)  0xFFFA8048) // (MCI) MCI Interrupt Disable Register
3233
#define AT91C_MCI_DTOR  (AT91_CAST(AT91_REG *)  0xFFFA8008) // (MCI) MCI Data Timeout Register
3234
#define AT91C_MCI_TDR   (AT91_CAST(AT91_REG *)  0xFFFA8034) // (MCI) MCI Transmit Data Register
3235
#define AT91C_MCI_IER   (AT91_CAST(AT91_REG *)  0xFFFA8044) // (MCI) MCI Interrupt Enable Register
3236
#define AT91C_MCI_BLKR  (AT91_CAST(AT91_REG *)  0xFFFA8018) // (MCI) MCI Block Register
3237
#define AT91C_MCI_MR    (AT91_CAST(AT91_REG *)  0xFFFA8004) // (MCI) MCI Mode Register
3238
#define AT91C_MCI_IMR   (AT91_CAST(AT91_REG *)  0xFFFA804C) // (MCI) MCI Interrupt Mask Register
3239
#define AT91C_MCI_CR    (AT91_CAST(AT91_REG *)  0xFFFA8000) // (MCI) MCI Control Register
3240
#define AT91C_MCI_ARGR  (AT91_CAST(AT91_REG *)  0xFFFA8010) // (MCI) MCI Argument Register
3241
#define AT91C_MCI_SDCR  (AT91_CAST(AT91_REG *)  0xFFFA800C) // (MCI) MCI SD Card Register
3242
#define AT91C_MCI_SR    (AT91_CAST(AT91_REG *)  0xFFFA8040) // (MCI) MCI Status Register
3243
#define AT91C_MCI_RSPR  (AT91_CAST(AT91_REG *)  0xFFFA8020) // (MCI) MCI Response Register
3244
// ========== Register definition for PDC_TWI0 peripheral ========== 
3245
#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *)  0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register
3246
#define AT91C_TWI0_RPR  (AT91_CAST(AT91_REG *)  0xFFFAC100) // (PDC_TWI0) Receive Pointer Register
3247
#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *)  0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register
3248
#define AT91C_TWI0_RCR  (AT91_CAST(AT91_REG *)  0xFFFAC104) // (PDC_TWI0) Receive Counter Register
3249
#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *)  0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register
3250
#define AT91C_TWI0_TPR  (AT91_CAST(AT91_REG *)  0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register
3251
#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *)  0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register
3252
#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *)  0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register
3253
#define AT91C_TWI0_TCR  (AT91_CAST(AT91_REG *)  0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register
3254
#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *)  0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register
3255
// ========== Register definition for TWI0 peripheral ========== 
3256
#define AT91C_TWI0_THR  (AT91_CAST(AT91_REG *)  0xFFFAC034) // (TWI0) Transmit Holding Register
3257
#define AT91C_TWI0_IDR  (AT91_CAST(AT91_REG *)  0xFFFAC028) // (TWI0) Interrupt Disable Register
3258
#define AT91C_TWI0_SMR  (AT91_CAST(AT91_REG *)  0xFFFAC008) // (TWI0) Slave Mode Register
3259
#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *)  0xFFFAC010) // (TWI0) Clock Waveform Generator Register
3260
#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *)  0xFFFAC00C) // (TWI0) Internal Address Register
3261
#define AT91C_TWI0_RHR  (AT91_CAST(AT91_REG *)  0xFFFAC030) // (TWI0) Receive Holding Register
3262
#define AT91C_TWI0_IER  (AT91_CAST(AT91_REG *)  0xFFFAC024) // (TWI0) Interrupt Enable Register
3263
#define AT91C_TWI0_MMR  (AT91_CAST(AT91_REG *)  0xFFFAC004) // (TWI0) Master Mode Register
3264
#define AT91C_TWI0_SR   (AT91_CAST(AT91_REG *)  0xFFFAC020) // (TWI0) Status Register
3265
#define AT91C_TWI0_IMR  (AT91_CAST(AT91_REG *)  0xFFFAC02C) // (TWI0) Interrupt Mask Register
3266
#define AT91C_TWI0_CR   (AT91_CAST(AT91_REG *)  0xFFFAC000) // (TWI0) Control Register
3267
// ========== Register definition for PDC_TWI1 peripheral ========== 
3268
#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *)  0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register
3269
#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *)  0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register
3270
#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *)  0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register
3271
#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *)  0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register
3272
#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *)  0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register
3273
#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *)  0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register
3274
#define AT91C_TWI1_RPR  (AT91_CAST(AT91_REG *)  0xFFFD8100) // (PDC_TWI1) Receive Pointer Register
3275
#define AT91C_TWI1_TCR  (AT91_CAST(AT91_REG *)  0xFFFD810C) // (PDC_TWI1) Transmit Counter Register
3276
#define AT91C_TWI1_TPR  (AT91_CAST(AT91_REG *)  0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register
3277
#define AT91C_TWI1_RCR  (AT91_CAST(AT91_REG *)  0xFFFD8104) // (PDC_TWI1) Receive Counter Register
3278
// ========== Register definition for TWI1 peripheral ========== 
3279
#define AT91C_TWI1_RHR  (AT91_CAST(AT91_REG *)  0xFFFD8030) // (TWI1) Receive Holding Register
3280
#define AT91C_TWI1_IER  (AT91_CAST(AT91_REG *)  0xFFFD8024) // (TWI1) Interrupt Enable Register
3281
#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *)  0xFFFD8010) // (TWI1) Clock Waveform Generator Register
3282
#define AT91C_TWI1_MMR  (AT91_CAST(AT91_REG *)  0xFFFD8004) // (TWI1) Master Mode Register
3283
#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *)  0xFFFD800C) // (TWI1) Internal Address Register
3284
#define AT91C_TWI1_THR  (AT91_CAST(AT91_REG *)  0xFFFD8034) // (TWI1) Transmit Holding Register
3285
#define AT91C_TWI1_IMR  (AT91_CAST(AT91_REG *)  0xFFFD802C) // (TWI1) Interrupt Mask Register
3286
#define AT91C_TWI1_SR   (AT91_CAST(AT91_REG *)  0xFFFD8020) // (TWI1) Status Register
3287
#define AT91C_TWI1_IDR  (AT91_CAST(AT91_REG *)  0xFFFD8028) // (TWI1) Interrupt Disable Register
3288
#define AT91C_TWI1_CR   (AT91_CAST(AT91_REG *)  0xFFFD8000) // (TWI1) Control Register
3289
#define AT91C_TWI1_SMR  (AT91_CAST(AT91_REG *)  0xFFFD8008) // (TWI1) Slave Mode Register
3290
// ========== Register definition for PDC_US0 peripheral ========== 
3291
#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *)  0xFFFB010C) // (PDC_US0) Transmit Counter Register
3292
#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *)  0xFFFB0120) // (PDC_US0) PDC Transfer Control Register
3293
#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *)  0xFFFB0114) // (PDC_US0) Receive Next Counter Register
3294
#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *)  0xFFFB0124) // (PDC_US0) PDC Transfer Status Register
3295
#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *)  0xFFFB011C) // (PDC_US0) Transmit Next Counter Register
3296
#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *)  0xFFFB0110) // (PDC_US0) Receive Next Pointer Register
3297
#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *)  0xFFFB0104) // (PDC_US0) Receive Counter Register
3298
#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *)  0xFFFB0108) // (PDC_US0) Transmit Pointer Register
3299
#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *)  0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register
3300
#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *)  0xFFFB0100) // (PDC_US0) Receive Pointer Register
3301
// ========== Register definition for US0 peripheral ========== 
3302
#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *)  0xFFFB0018) // (US0) Receiver Holding Register
3303
#define AT91C_US0_NER   (AT91_CAST(AT91_REG *)  0xFFFB0044) // (US0) Nb Errors Register
3304
#define AT91C_US0_IER   (AT91_CAST(AT91_REG *)  0xFFFB0008) // (US0) Interrupt Enable Register
3305
#define AT91C_US0_CR    (AT91_CAST(AT91_REG *)  0xFFFB0000) // (US0) Control Register
3306
#define AT91C_US0_THR   (AT91_CAST(AT91_REG *)  0xFFFB001C) // (US0) Transmitter Holding Register
3307
#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *)  0xFFFB0014) // (US0) Channel Status Register
3308
#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *)  0xFFFB0020) // (US0) Baud Rate Generator Register
3309
#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *)  0xFFFB0024) // (US0) Receiver Time-out Register
3310
#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *)  0xFFFB0028) // (US0) Transmitter Time-guard Register
3311
#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *)  0xFFFB000C) // (US0) Interrupt Disable Register
3312
#define AT91C_US0_MR    (AT91_CAST(AT91_REG *)  0xFFFB0004) // (US0) Mode Register
3313
#define AT91C_US0_IF    (AT91_CAST(AT91_REG *)  0xFFFB004C) // (US0) IRDA_FILTER Register
3314
#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *)  0xFFFB0040) // (US0) FI_DI_Ratio Register
3315
#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *)  0xFFFB0010) // (US0) Interrupt Mask Register
3316
// ========== Register definition for PDC_US1 peripheral ========== 
3317
#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *)  0xFFFB4120) // (PDC_US1) PDC Transfer Control Register
3318
#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *)  0xFFFB4104) // (PDC_US1) Receive Counter Register
3319
#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *)  0xFFFB4100) // (PDC_US1) Receive Pointer Register
3320
#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *)  0xFFFB4124) // (PDC_US1) PDC Transfer Status Register
3321
#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *)  0xFFFB4108) // (PDC_US1) Transmit Pointer Register
3322
#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *)  0xFFFB410C) // (PDC_US1) Transmit Counter Register
3323
#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *)  0xFFFB4110) // (PDC_US1) Receive Next Pointer Register
3324
#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *)  0xFFFB411C) // (PDC_US1) Transmit Next Counter Register
3325
#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *)  0xFFFB4114) // (PDC_US1) Receive Next Counter Register
3326
#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *)  0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register
3327
// ========== Register definition for US1 peripheral ========== 
3328
#define AT91C_US1_THR   (AT91_CAST(AT91_REG *)  0xFFFB401C) // (US1) Transmitter Holding Register
3329
#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *)  0xFFFB4028) // (US1) Transmitter Time-guard Register
3330
#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *)  0xFFFB4020) // (US1) Baud Rate Generator Register
3331
#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *)  0xFFFB400C) // (US1) Interrupt Disable Register
3332
#define AT91C_US1_MR    (AT91_CAST(AT91_REG *)  0xFFFB4004) // (US1) Mode Register
3333
#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *)  0xFFFB4024) // (US1) Receiver Time-out Register
3334
#define AT91C_US1_CR    (AT91_CAST(AT91_REG *)  0xFFFB4000) // (US1) Control Register
3335
#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *)  0xFFFB4010) // (US1) Interrupt Mask Register
3336
#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *)  0xFFFB4040) // (US1) FI_DI_Ratio Register
3337
#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *)  0xFFFB4018) // (US1) Receiver Holding Register
3338
#define AT91C_US1_IER   (AT91_CAST(AT91_REG *)  0xFFFB4008) // (US1) Interrupt Enable Register
3339
#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *)  0xFFFB4014) // (US1) Channel Status Register
3340
#define AT91C_US1_IF    (AT91_CAST(AT91_REG *)  0xFFFB404C) // (US1) IRDA_FILTER Register
3341
#define AT91C_US1_NER   (AT91_CAST(AT91_REG *)  0xFFFB4044) // (US1) Nb Errors Register
3342
// ========== Register definition for PDC_US2 peripheral ========== 
3343
#define AT91C_US2_TNCR  (AT91_CAST(AT91_REG *)  0xFFFB811C) // (PDC_US2) Transmit Next Counter Register
3344
#define AT91C_US2_RNCR  (AT91_CAST(AT91_REG *)  0xFFFB8114) // (PDC_US2) Receive Next Counter Register
3345
#define AT91C_US2_TNPR  (AT91_CAST(AT91_REG *)  0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register
3346
#define AT91C_US2_PTCR  (AT91_CAST(AT91_REG *)  0xFFFB8120) // (PDC_US2) PDC Transfer Control Register
3347
#define AT91C_US2_TCR   (AT91_CAST(AT91_REG *)  0xFFFB810C) // (PDC_US2) Transmit Counter Register
3348
#define AT91C_US2_RPR   (AT91_CAST(AT91_REG *)  0xFFFB8100) // (PDC_US2) Receive Pointer Register
3349
#define AT91C_US2_TPR   (AT91_CAST(AT91_REG *)  0xFFFB8108) // (PDC_US2) Transmit Pointer Register
3350
#define AT91C_US2_RCR   (AT91_CAST(AT91_REG *)  0xFFFB8104) // (PDC_US2) Receive Counter Register
3351
#define AT91C_US2_PTSR  (AT91_CAST(AT91_REG *)  0xFFFB8124) // (PDC_US2) PDC Transfer Status Register
3352
#define AT91C_US2_RNPR  (AT91_CAST(AT91_REG *)  0xFFFB8110) // (PDC_US2) Receive Next Pointer Register
3353
// ========== Register definition for US2 peripheral ========== 
3354
#define AT91C_US2_RTOR  (AT91_CAST(AT91_REG *)  0xFFFB8024) // (US2) Receiver Time-out Register
3355
#define AT91C_US2_CSR   (AT91_CAST(AT91_REG *)  0xFFFB8014) // (US2) Channel Status Register
3356
#define AT91C_US2_CR    (AT91_CAST(AT91_REG *)  0xFFFB8000) // (US2) Control Register
3357
#define AT91C_US2_BRGR  (AT91_CAST(AT91_REG *)  0xFFFB8020) // (US2) Baud Rate Generator Register
3358
#define AT91C_US2_NER   (AT91_CAST(AT91_REG *)  0xFFFB8044) // (US2) Nb Errors Register
3359
#define AT91C_US2_FIDI  (AT91_CAST(AT91_REG *)  0xFFFB8040) // (US2) FI_DI_Ratio Register
3360
#define AT91C_US2_TTGR  (AT91_CAST(AT91_REG *)  0xFFFB8028) // (US2) Transmitter Time-guard Register
3361
#define AT91C_US2_RHR   (AT91_CAST(AT91_REG *)  0xFFFB8018) // (US2) Receiver Holding Register
3362
#define AT91C_US2_IDR   (AT91_CAST(AT91_REG *)  0xFFFB800C) // (US2) Interrupt Disable Register
3363
#define AT91C_US2_THR   (AT91_CAST(AT91_REG *)  0xFFFB801C) // (US2) Transmitter Holding Register
3364
#define AT91C_US2_MR    (AT91_CAST(AT91_REG *)  0xFFFB8004) // (US2) Mode Register
3365
#define AT91C_US2_IMR   (AT91_CAST(AT91_REG *)  0xFFFB8010) // (US2) Interrupt Mask Register
3366
#define AT91C_US2_IF    (AT91_CAST(AT91_REG *)  0xFFFB804C) // (US2) IRDA_FILTER Register
3367
#define AT91C_US2_IER   (AT91_CAST(AT91_REG *)  0xFFFB8008) // (US2) Interrupt Enable Register
3368
// ========== Register definition for PDC_US3 peripheral ========== 
3369
#define AT91C_US3_RNPR  (AT91_CAST(AT91_REG *)  0xFFFD0110) // (PDC_US3) Receive Next Pointer Register
3370
#define AT91C_US3_RNCR  (AT91_CAST(AT91_REG *)  0xFFFD0114) // (PDC_US3) Receive Next Counter Register
3371
#define AT91C_US3_PTSR  (AT91_CAST(AT91_REG *)  0xFFFD0124) // (PDC_US3) PDC Transfer Status Register
3372
#define AT91C_US3_PTCR  (AT91_CAST(AT91_REG *)  0xFFFD0120) // (PDC_US3) PDC Transfer Control Register
3373
#define AT91C_US3_TCR   (AT91_CAST(AT91_REG *)  0xFFFD010C) // (PDC_US3) Transmit Counter Register
3374
#define AT91C_US3_TNPR  (AT91_CAST(AT91_REG *)  0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register
3375
#define AT91C_US3_RCR   (AT91_CAST(AT91_REG *)  0xFFFD0104) // (PDC_US3) Receive Counter Register
3376
#define AT91C_US3_TPR   (AT91_CAST(AT91_REG *)  0xFFFD0108) // (PDC_US3) Transmit Pointer Register
3377
#define AT91C_US3_TNCR  (AT91_CAST(AT91_REG *)  0xFFFD011C) // (PDC_US3) Transmit Next Counter Register
3378
#define AT91C_US3_RPR   (AT91_CAST(AT91_REG *)  0xFFFD0100) // (PDC_US3) Receive Pointer Register
3379
// ========== Register definition for US3 peripheral ========== 
3380
#define AT91C_US3_NER   (AT91_CAST(AT91_REG *)  0xFFFD0044) // (US3) Nb Errors Register
3381
#define AT91C_US3_RTOR  (AT91_CAST(AT91_REG *)  0xFFFD0024) // (US3) Receiver Time-out Register
3382
#define AT91C_US3_IDR   (AT91_CAST(AT91_REG *)  0xFFFD000C) // (US3) Interrupt Disable Register
3383
#define AT91C_US3_MR    (AT91_CAST(AT91_REG *)  0xFFFD0004) // (US3) Mode Register
3384
#define AT91C_US3_FIDI  (AT91_CAST(AT91_REG *)  0xFFFD0040) // (US3) FI_DI_Ratio Register
3385
#define AT91C_US3_BRGR  (AT91_CAST(AT91_REG *)  0xFFFD0020) // (US3) Baud Rate Generator Register
3386
#define AT91C_US3_THR   (AT91_CAST(AT91_REG *)  0xFFFD001C) // (US3) Transmitter Holding Register
3387
#define AT91C_US3_CR    (AT91_CAST(AT91_REG *)  0xFFFD0000) // (US3) Control Register
3388
#define AT91C_US3_IF    (AT91_CAST(AT91_REG *)  0xFFFD004C) // (US3) IRDA_FILTER Register
3389
#define AT91C_US3_IER   (AT91_CAST(AT91_REG *)  0xFFFD0008) // (US3) Interrupt Enable Register
3390
#define AT91C_US3_TTGR  (AT91_CAST(AT91_REG *)  0xFFFD0028) // (US3) Transmitter Time-guard Register
3391
#define AT91C_US3_RHR   (AT91_CAST(AT91_REG *)  0xFFFD0018) // (US3) Receiver Holding Register
3392
#define AT91C_US3_IMR   (AT91_CAST(AT91_REG *)  0xFFFD0010) // (US3) Interrupt Mask Register
3393
#define AT91C_US3_CSR   (AT91_CAST(AT91_REG *)  0xFFFD0014) // (US3) Channel Status Register
3394
// ========== Register definition for PDC_US4 peripheral ========== 
3395
#define AT91C_US4_TNCR  (AT91_CAST(AT91_REG *)  0xFFFD411C) // (PDC_US4) Transmit Next Counter Register
3396
#define AT91C_US4_RPR   (AT91_CAST(AT91_REG *)  0xFFFD4100) // (PDC_US4) Receive Pointer Register
3397
#define AT91C_US4_RNCR  (AT91_CAST(AT91_REG *)  0xFFFD4114) // (PDC_US4) Receive Next Counter Register
3398
#define AT91C_US4_TPR   (AT91_CAST(AT91_REG *)  0xFFFD4108) // (PDC_US4) Transmit Pointer Register
3399
#define AT91C_US4_PTCR  (AT91_CAST(AT91_REG *)  0xFFFD4120) // (PDC_US4) PDC Transfer Control Register
3400
#define AT91C_US4_TCR   (AT91_CAST(AT91_REG *)  0xFFFD410C) // (PDC_US4) Transmit Counter Register
3401
#define AT91C_US4_RCR   (AT91_CAST(AT91_REG *)  0xFFFD4104) // (PDC_US4) Receive Counter Register
3402
#define AT91C_US4_RNPR  (AT91_CAST(AT91_REG *)  0xFFFD4110) // (PDC_US4) Receive Next Pointer Register
3403
#define AT91C_US4_TNPR  (AT91_CAST(AT91_REG *)  0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register
3404
#define AT91C_US4_PTSR  (AT91_CAST(AT91_REG *)  0xFFFD4124) // (PDC_US4) PDC Transfer Status Register
3405
// ========== Register definition for US4 peripheral ========== 
3406
#define AT91C_US4_BRGR  (AT91_CAST(AT91_REG *)  0xFFFD4020) // (US4) Baud Rate Generator Register
3407
#define AT91C_US4_THR   (AT91_CAST(AT91_REG *)  0xFFFD401C) // (US4) Transmitter Holding Register
3408
#define AT91C_US4_RTOR  (AT91_CAST(AT91_REG *)  0xFFFD4024) // (US4) Receiver Time-out Register
3409
#define AT91C_US4_IMR   (AT91_CAST(AT91_REG *)  0xFFFD4010) // (US4) Interrupt Mask Register
3410
#define AT91C_US4_NER   (AT91_CAST(AT91_REG *)  0xFFFD4044) // (US4) Nb Errors Register
3411
#define AT91C_US4_TTGR  (AT91_CAST(AT91_REG *)  0xFFFD4028) // (US4) Transmitter Time-guard Register
3412
#define AT91C_US4_FIDI  (AT91_CAST(AT91_REG *)  0xFFFD4040) // (US4) FI_DI_Ratio Register
3413
#define AT91C_US4_MR    (AT91_CAST(AT91_REG *)  0xFFFD4004) // (US4) Mode Register
3414
#define AT91C_US4_IER   (AT91_CAST(AT91_REG *)  0xFFFD4008) // (US4) Interrupt Enable Register
3415
#define AT91C_US4_RHR   (AT91_CAST(AT91_REG *)  0xFFFD4018) // (US4) Receiver Holding Register
3416
#define AT91C_US4_CR    (AT91_CAST(AT91_REG *)  0xFFFD4000) // (US4) Control Register
3417
#define AT91C_US4_IF    (AT91_CAST(AT91_REG *)  0xFFFD404C) // (US4) IRDA_FILTER Register
3418
#define AT91C_US4_IDR   (AT91_CAST(AT91_REG *)  0xFFFD400C) // (US4) Interrupt Disable Register
3419
#define AT91C_US4_CSR   (AT91_CAST(AT91_REG *)  0xFFFD4014) // (US4) Channel Status Register
3420
// ========== Register definition for PDC_SSC0 peripheral ========== 
3421
#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *)  0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register
3422
#define AT91C_SSC0_TCR  (AT91_CAST(AT91_REG *)  0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register
3423
#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *)  0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register
3424
#define AT91C_SSC0_RPR  (AT91_CAST(AT91_REG *)  0xFFFBC100) // (PDC_SSC0) Receive Pointer Register
3425
#define AT91C_SSC0_TPR  (AT91_CAST(AT91_REG *)  0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register
3426
#define AT91C_SSC0_RCR  (AT91_CAST(AT91_REG *)  0xFFFBC104) // (PDC_SSC0) Receive Counter Register
3427
#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *)  0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register
3428
#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *)  0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register
3429
#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *)  0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register
3430
#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *)  0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register
3431
// ========== Register definition for SSC0 peripheral ========== 
3432
#define AT91C_SSC0_IMR  (AT91_CAST(AT91_REG *)  0xFFFBC04C) // (SSC0) Interrupt Mask Register
3433
#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *)  0xFFFBC014) // (SSC0) Receive Frame Mode Register
3434
#define AT91C_SSC0_CR   (AT91_CAST(AT91_REG *)  0xFFFBC000) // (SSC0) Control Register
3435
#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *)  0xFFFBC01C) // (SSC0) Transmit Frame Mode Register
3436
#define AT91C_SSC0_CMR  (AT91_CAST(AT91_REG *)  0xFFFBC004) // (SSC0) Clock Mode Register
3437
#define AT91C_SSC0_IER  (AT91_CAST(AT91_REG *)  0xFFFBC044) // (SSC0) Interrupt Enable Register
3438
#define AT91C_SSC0_RHR  (AT91_CAST(AT91_REG *)  0xFFFBC020) // (SSC0) Receive Holding Register
3439
#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *)  0xFFFBC010) // (SSC0) Receive Clock ModeRegister
3440
#define AT91C_SSC0_SR   (AT91_CAST(AT91_REG *)  0xFFFBC040) // (SSC0) Status Register
3441
#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *)  0xFFFBC030) // (SSC0) Receive Sync Holding Register
3442
#define AT91C_SSC0_THR  (AT91_CAST(AT91_REG *)  0xFFFBC024) // (SSC0) Transmit Holding Register
3443
#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *)  0xFFFBC018) // (SSC0) Transmit Clock Mode Register
3444
#define AT91C_SSC0_IDR  (AT91_CAST(AT91_REG *)  0xFFFBC048) // (SSC0) Interrupt Disable Register
3445
#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *)  0xFFFBC034) // (SSC0) Transmit Sync Holding Register
3446
// ========== Register definition for PDC_SPI0 peripheral ========== 
3447
#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *)  0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register
3448
#define AT91C_SPI0_TCR  (AT91_CAST(AT91_REG *)  0xFFFC810C) // (PDC_SPI0) Transmit Counter Register
3449
#define AT91C_SPI0_RPR  (AT91_CAST(AT91_REG *)  0xFFFC8100) // (PDC_SPI0) Receive Pointer Register
3450
#define AT91C_SPI0_TPR  (AT91_CAST(AT91_REG *)  0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register
3451
#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *)  0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register
3452
#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *)  0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register
3453
#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *)  0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register
3454
#define AT91C_SPI0_RCR  (AT91_CAST(AT91_REG *)  0xFFFC8104) // (PDC_SPI0) Receive Counter Register
3455
#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *)  0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register
3456
#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *)  0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register
3457
// ========== Register definition for SPI0 peripheral ========== 
3458
#define AT91C_SPI0_IDR  (AT91_CAST(AT91_REG *)  0xFFFC8018) // (SPI0) Interrupt Disable Register
3459
#define AT91C_SPI0_TDR  (AT91_CAST(AT91_REG *)  0xFFFC800C) // (SPI0) Transmit Data Register
3460
#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *)  0xFFFC8010) // (SPI0) Status Register
3461
#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *)  0xFFFC8000) // (SPI0) Control Register
3462
#define AT91C_SPI0_CSR  (AT91_CAST(AT91_REG *)  0xFFFC8030) // (SPI0) Chip Select Register
3463
#define AT91C_SPI0_RDR  (AT91_CAST(AT91_REG *)  0xFFFC8008) // (SPI0) Receive Data Register
3464
#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *)  0xFFFC8004) // (SPI0) Mode Register
3465
#define AT91C_SPI0_IER  (AT91_CAST(AT91_REG *)  0xFFFC8014) // (SPI0) Interrupt Enable Register
3466
#define AT91C_SPI0_IMR  (AT91_CAST(AT91_REG *)  0xFFFC801C) // (SPI0) Interrupt Mask Register
3467
// ========== Register definition for PDC_SPI1 peripheral ========== 
3468
#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *)  0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register
3469
#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *)  0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register
3470
#define AT91C_SPI1_RCR  (AT91_CAST(AT91_REG *)  0xFFFCC104) // (PDC_SPI1) Receive Counter Register
3471
#define AT91C_SPI1_TPR  (AT91_CAST(AT91_REG *)  0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register
3472
#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *)  0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register
3473
#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *)  0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register
3474
#define AT91C_SPI1_RPR  (AT91_CAST(AT91_REG *)  0xFFFCC100) // (PDC_SPI1) Receive Pointer Register
3475
#define AT91C_SPI1_TCR  (AT91_CAST(AT91_REG *)  0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register
3476
#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *)  0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register
3477
#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *)  0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register
3478
// ========== Register definition for SPI1 peripheral ========== 
3479
#define AT91C_SPI1_IER  (AT91_CAST(AT91_REG *)  0xFFFCC014) // (SPI1) Interrupt Enable Register
3480
#define AT91C_SPI1_RDR  (AT91_CAST(AT91_REG *)  0xFFFCC008) // (SPI1) Receive Data Register
3481
#define AT91C_SPI1_SR   (AT91_CAST(AT91_REG *)  0xFFFCC010) // (SPI1) Status Register
3482
#define AT91C_SPI1_IMR  (AT91_CAST(AT91_REG *)  0xFFFCC01C) // (SPI1) Interrupt Mask Register
3483
#define AT91C_SPI1_TDR  (AT91_CAST(AT91_REG *)  0xFFFCC00C) // (SPI1) Transmit Data Register
3484
#define AT91C_SPI1_IDR  (AT91_CAST(AT91_REG *)  0xFFFCC018) // (SPI1) Interrupt Disable Register
3485
#define AT91C_SPI1_CSR  (AT91_CAST(AT91_REG *)  0xFFFCC030) // (SPI1) Chip Select Register
3486
#define AT91C_SPI1_CR   (AT91_CAST(AT91_REG *)  0xFFFCC000) // (SPI1) Control Register
3487
#define AT91C_SPI1_MR   (AT91_CAST(AT91_REG *)  0xFFFCC004) // (SPI1) Mode Register
3488
// ========== Register definition for PDC_ADC peripheral ========== 
3489
#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *)  0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register
3490
#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *)  0xFFFE0108) // (PDC_ADC) Transmit Pointer Register
3491
#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *)  0xFFFE010C) // (PDC_ADC) Transmit Counter Register
3492
#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *)  0xFFFE0104) // (PDC_ADC) Receive Counter Register
3493
#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *)  0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register
3494
#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *)  0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register
3495
#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *)  0xFFFE0100) // (PDC_ADC) Receive Pointer Register
3496
#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *)  0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register
3497
#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *)  0xFFFE0114) // (PDC_ADC) Receive Next Counter Register
3498
#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *)  0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register
3499
// ========== Register definition for ADC peripheral ========== 
3500
#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *)  0xFFFE0014) // (ADC) ADC Channel Disable Register
3501
#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *)  0xFFFE003C) // (ADC) ADC Channel Data Register 3
3502
#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *)  0xFFFE0000) // (ADC) ADC Control Register
3503
#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *)  0xFFFE002C) // (ADC) ADC Interrupt Mask Register
3504
#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *)  0xFFFE0038) // (ADC) ADC Channel Data Register 2
3505
#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *)  0xFFFE001C) // (ADC) ADC Status Register
3506
#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *)  0xFFFE0024) // (ADC) ADC Interrupt Enable Register
3507
#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *)  0xFFFE004C) // (ADC) ADC Channel Data Register 7
3508
#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *)  0xFFFE0030) // (ADC) ADC Channel Data Register 0
3509
#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *)  0xFFFE0044) // (ADC) ADC Channel Data Register 5
3510
#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *)  0xFFFE0040) // (ADC) ADC Channel Data Register 4
3511
#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *)  0xFFFE0010) // (ADC) ADC Channel Enable Register
3512
#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *)  0xFFFE0018) // (ADC) ADC Channel Status Register
3513
#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *)  0xFFFE0004) // (ADC) ADC Mode Register
3514
#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *)  0xFFFE0048) // (ADC) ADC Channel Data Register 6
3515
#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *)  0xFFFE0020) // (ADC) ADC Last Converted Data Register
3516
#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *)  0xFFFE0034) // (ADC) ADC Channel Data Register 1
3517
#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *)  0xFFFE0028) // (ADC) ADC Interrupt Disable Register
3518
// ========== Register definition for EMACB peripheral ========== 
3519
#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *)        0xFFFC40C0) // (EMACB) USER Input/Output Register
3520
#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *)  0xFFFC4074) // (EMACB) Receive Symbol Errors Register
3521
#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *)  0xFFFC4044) // (EMACB) Single Collision Frame Register
3522
#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *)  0xFFFC4084) // (EMACB) SQE Test Error Register
3523
#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *)         0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes
3524
#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *)  0xFFFC4070) // (EMACB) Receive Overrun Errors Register
3525
#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *)         0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer
3526
#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *)  0xFFFC4030) // (EMACB) Interrupt Mask Register
3527
#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *)  0xFFFC4028) // (EMACB) Interrupt Enable Register
3528
#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *)  0xFFFC40FC) // (EMACB) Revision Register
3529
#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *)         0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes
3530
#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *)  0xFFFC4078) // (EMACB) Excessive Length Errors Register
3531
#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *)  0xFFFC4094) // (EMACB) Hash Address Top[63:32]
3532
#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *)         0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes
3533
#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *)  0xFFFC406C) // (EMACB) Receive Ressource Error Register
3534
#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *)  0xFFFC404C) // (EMACB) Frames Received OK Register
3535
#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *)  0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register
3536
#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *)  0xFFFC4024) // (EMACB) Interrupt Status Register
3537
#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *)  0xFFFC4014) // (EMACB) Transmit Status Register
3538
#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *)  0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register
3539
#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *)  0xFFFC4080) // (EMACB) Undersize Frames Register
3540
#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *)  0xFFFC40C4) // (EMACB) Wake On LAN Register
3541
#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *)  0xFFFC408C) // (EMACB) Transmitted Pause Frames Register
3542
#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *)  0xFFFC4038) // (EMACB) Pause Time Register
3543
#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *)         0xFFFC4064) // (EMACB) Transmit Underrun Error Register
3544
#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *)  0xFFFC4034) // (EMACB) PHY Maintenance Register
3545
#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *)  0xFFFC407C) // (EMACB) Receive Jabbers Register
3546
#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *)         0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes
3547
#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *)  0xFFFC4068) // (EMACB) Carrier Sense Error Register
3548
#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *)  0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]
3549
#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *)  0xFFFC4054) // (EMACB) Alignment Error Register
3550
#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *)         0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes
3551
#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *)  0xFFFC4000) // (EMACB) Network Control Register
3552
#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *)  0xFFFC4040) // (EMACB) Frames Transmitted OK Register
3553
#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *)         0xFFFC4060) // (EMACB) Excessive Collision Register
3554
#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *)  0xFFFC4058) // (EMACB) Deferred Transmission Frame Register
3555
#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *)         0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes
3556
#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *)         0xFFFC4050) // (EMACB) Frame Check Sequence Error Register
3557
#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *)  0xFFFC40B8) // (EMACB) Type ID Checking Register
3558
#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *)  0xFFFC403C) // (EMACB) Pause Frames received Register
3559
#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *)  0xFFFC402C) // (EMACB) Interrupt Disable Register
3560
#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *)         0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes
3561
#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *)  0xFFFC4008) // (EMACB) Network Status Register
3562
#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *)  0xFFFC4048) // (EMACB) Multiple Collision Frame Register
3563
#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *)         0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer
3564
#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *)  0xFFFC4020) // (EMACB) Receive Status Register
3565
#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *)         0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes
3566
#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *)        0xFFFC4004) // (EMACB) Network Configuration Register
3567
#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *)         0xFFFC405C) // (EMACB) Late Collision Register
3568
// ========== Register definition for UDP peripheral ========== 
3569
#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *)       0xFFFA4004) // (UDP) Global State Register
3570
#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *)  0xFFFA4050) // (UDP) Endpoint FIFO Data Register
3571
#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *)  0xFFFA4028) // (UDP) Reset Endpoint Register
3572
#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *)  0xFFFA4008) // (UDP) Function Address Register
3573
#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *)  0xFFFA4000) // (UDP) Frame Number Register
3574
#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *)  0xFFFA4014) // (UDP) Interrupt Disable Register
3575
#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *)  0xFFFA4018) // (UDP) Interrupt Mask Register
3576
#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *)  0xFFFA4030) // (UDP) Endpoint Control and Status Register
3577
#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *)  0xFFFA4010) // (UDP) Interrupt Enable Register
3578
#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *)  0xFFFA4020) // (UDP) Interrupt Clear Register
3579
#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *)  0xFFFA4074) // (UDP) Transceiver Control Register
3580
#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *)  0xFFFA401C) // (UDP) Interrupt Status Register
3581
// ========== Register definition for UHP peripheral ========== 
3582
#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *)      0x0050000C) // (UHP) Interrupt Status Register
3583
#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *)        0x00500008) // (UHP) Command & status Register
3584
#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *)     0x00500050) // (UHP) Root Hub Status register
3585
#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *)     0x00500014) // (UHP) Interrupt Disable Register
3586
#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *)        0x00500040) // (UHP) Periodic Start
3587
#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *)     0x00500024) // (UHP) Endpoint Control and Status Register
3588
#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *)      0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
3589
#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *)   0x00500028) // (UHP) First endpoint register of the Bulk list
3590
#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *)     0x00500000) // (UHP) Revision
3591
#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *)        0x0050002C) // (UHP) Current endpoint of the Bulk list
3592
#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *)        0x0050004C) // (UHP) Root Hub characteristics B
3593
#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *)        0x00500020) // (UHP) First Endpoint Descriptor of the Control list
3594
#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *)  0x00500038) // (UHP) Bit time remaining in the current Frame
3595
#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *)         0x00500018) // (UHP) Pointer to the Host Controller Communication Area
3596
#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *)  0x00500044) // (UHP) LS Threshold
3597
#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *)         0x00500054) // (UHP) Root Hub Port Status Register
3598
#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *)      0x00500010) // (UHP) Interrupt Enable Register
3599
#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *)     0x0050003C) // (UHP) Frame number
3600
#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *)   0x00500034) // (UHP) Bit time between 2 consecutive SOFs
3601
#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *)      0x00500004) // (UHP) Operating modes for the Host Controller
3602
#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *)         0x00500030) // (UHP) Last completed transfer descriptor
3603
#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *)        0x00500048) // (UHP) Root Hub characteristics A
3604
// ========== Register definition for HECC peripheral ========== 
3605
// ========== Register definition for HISI peripheral ========== 
3606
#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *)         0xFFFC0020) // (HISI) Preview Size Register
3607
#define AT91C_HISI_CR1  (AT91_CAST(AT91_REG *)  0xFFFC0000) // (HISI) Control Register 1
3608
#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *)       0xFFFC003C) // (HISI) Color Space Conversion Register
3609
#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *)  0xFFFC002C) // (HISI) Codec Dma Address Register
3610
#define AT91C_HISI_IDR  (AT91_CAST(AT91_REG *)  0xFFFC0010) // (HISI) Interrupt Disable Register
3611
#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *)       0xFFFC0040) // (HISI) Color Space Conversion Register
3612
#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *)       0xFFFC0034) // (HISI) Color Space Conversion Register
3613
#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *)  0xFFFC0028) // (HISI) Preview Frame Buffer Address Register
3614
#define AT91C_HISI_CR2  (AT91_CAST(AT91_REG *)  0xFFFC0004) // (HISI) Control Register 2
3615
#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *)       0xFFFC0030) // (HISI) Color Space Conversion Register
3616
#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *)         0xFFFC0024) // (HISI) Preview Decimation Factor Register
3617
#define AT91C_HISI_IMR  (AT91_CAST(AT91_REG *)  0xFFFC0014) // (HISI) Interrupt Mask Register
3618
#define AT91C_HISI_IER  (AT91_CAST(AT91_REG *)  0xFFFC000C) // (HISI) Interrupt Enable Register
3619
#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *)       0xFFFC0038) // (HISI) Color Space Conversion Register
3620
#define AT91C_HISI_SR   (AT91_CAST(AT91_REG *)  0xFFFC0008) // (HISI) Status Register
3621
 
3622
// *****************************************************************************
3623
//               PIO DEFINITIONS FOR AT91SAM9XE512
3624
// *****************************************************************************
3625
#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
3626
#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) //  SPI 0 Master In Slave
3627
#define AT91C_PA0_MCDB0    (AT91C_PIO_PA0) //  Multimedia Card B Data 0
3628
#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
3629
#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) //  SPI 0 Master Out Slave
3630
#define AT91C_PA1_MCCDB    (AT91C_PIO_PA1) //  Multimedia Card B Command
3631
#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
3632
#define AT91C_PA10_MCDA2    (AT91C_PIO_PA10) //  Multimedia Card A Data 2
3633
#define AT91C_PA10_ETX2_0   (AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 2
3634
#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
3635
#define AT91C_PA11_MCDA3    (AT91C_PIO_PA11) //  Multimedia Card A Data 3
3636
#define AT91C_PA11_ETX3_0   (AT91C_PIO_PA11) //  Ethernet MAC Transmit Data 3
3637
#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
3638
#define AT91C_PA12_ETX0     (AT91C_PIO_PA12) //  Ethernet MAC Transmit Data 0
3639
#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
3640
#define AT91C_PA13_ETX1     (AT91C_PIO_PA13) //  Ethernet MAC Transmit Data 1
3641
#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
3642
#define AT91C_PA14_ERX0     (AT91C_PIO_PA14) //  Ethernet MAC Receive Data 0
3643
#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
3644
#define AT91C_PA15_ERX1     (AT91C_PIO_PA15) //  Ethernet MAC Receive Data 1
3645
#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
3646
#define AT91C_PA16_ETXEN    (AT91C_PIO_PA16) //  Ethernet MAC Transmit Enable
3647
#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
3648
#define AT91C_PA17_ERXDV    (AT91C_PIO_PA17) //  Ethernet MAC Receive Data Valid
3649
#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
3650
#define AT91C_PA18_ERXER    (AT91C_PIO_PA18) //  Ethernet MAC Receive Error
3651
#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
3652
#define AT91C_PA19_ETXCK    (AT91C_PIO_PA19) //  Ethernet MAC Transmit Clock/Reference Clock
3653
#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
3654
#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) //  SPI 0 Serial Clock
3655
#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
3656
#define AT91C_PA20_EMDC     (AT91C_PIO_PA20) //  Ethernet MAC Management Data Clock
3657
#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
3658
#define AT91C_PA21_EMDIO    (AT91C_PIO_PA21) //  Ethernet MAC Management Data Input/Output
3659
#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
3660
#define AT91C_PA22_ADTRG    (AT91C_PIO_PA22) //  ADC Trigger
3661
#define AT91C_PA22_ETXER    (AT91C_PIO_PA22) //  Ethernet MAC Transmikt Coding Error
3662
#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
3663
#define AT91C_PA23_TWD0     (AT91C_PIO_PA23) //  TWI Two-wire Serial Data 0
3664
#define AT91C_PA23_ETX2_1   (AT91C_PIO_PA23) //  Ethernet MAC Transmit Data 2
3665
#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
3666
#define AT91C_PA24_TWCK0    (AT91C_PIO_PA24) //  TWI Two-wire Serial Clock 0
3667
#define AT91C_PA24_ETX3_1   (AT91C_PIO_PA24) //  Ethernet MAC Transmit Data 3
3668
#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
3669
#define AT91C_PA25_TCLK0    (AT91C_PIO_PA25) //  Timer Counter 0 external clock input
3670
#define AT91C_PA25_ERX2     (AT91C_PIO_PA25) //  Ethernet MAC Receive Data 2
3671
#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
3672
#define AT91C_PA26_TIOA0    (AT91C_PIO_PA26) //  Timer Counter 0 Multipurpose Timer I/O Pin A
3673
#define AT91C_PA26_ERX3     (AT91C_PIO_PA26) //  Ethernet MAC Receive Data 3
3674
#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
3675
#define AT91C_PA27_TIOA1    (AT91C_PIO_PA27) //  Timer Counter 1 Multipurpose Timer I/O Pin A
3676
#define AT91C_PA27_ERXCK    (AT91C_PIO_PA27) //  Ethernet MAC Receive Clock
3677
#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
3678
#define AT91C_PA28_TIOA2    (AT91C_PIO_PA28) //  Timer Counter 2 Multipurpose Timer I/O Pin A
3679
#define AT91C_PA28_ECRS     (AT91C_PIO_PA28) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
3680
#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
3681
#define AT91C_PA29_SCK1     (AT91C_PIO_PA29) //  USART 1 Serial Clock
3682
#define AT91C_PA29_ECOL     (AT91C_PIO_PA29) //  Ethernet MAC Collision Detected
3683
#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
3684
#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) //  SPI 0 Peripheral Chip Select 0
3685
#define AT91C_PA3_MCDB3    (AT91C_PIO_PA3) //  Multimedia Card B Data 3
3686
#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
3687
#define AT91C_PA30_SCK2     (AT91C_PIO_PA30) //  USART 2 Serial Clock
3688
#define AT91C_PA30_RXD4     (AT91C_PIO_PA30) //  USART 4 Receive Data
3689
#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31
3690
#define AT91C_PA31_SCK0     (AT91C_PIO_PA31) //  USART 0 Serial Clock
3691
#define AT91C_PA31_TXD4     (AT91C_PIO_PA31) //  USART 4 Transmit Data
3692
#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
3693
#define AT91C_PA4_RTS2     (AT91C_PIO_PA4) //  USART 2 Ready To Send
3694
#define AT91C_PA4_MCDB2    (AT91C_PIO_PA4) //  Multimedia Card B Data 2
3695
#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
3696
#define AT91C_PA5_CTS2     (AT91C_PIO_PA5) //  USART 2 Clear To Send
3697
#define AT91C_PA5_MCDB1    (AT91C_PIO_PA5) //  Multimedia Card B Data 1
3698
#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
3699
#define AT91C_PA6_MCDA0    (AT91C_PIO_PA6) //  Multimedia Card A Data 0
3700
#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
3701
#define AT91C_PA7_MCCDA    (AT91C_PIO_PA7) //  Multimedia Card A Command
3702
#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
3703
#define AT91C_PA8_MCCK     (AT91C_PIO_PA8) //  Multimedia Card Clock
3704
#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
3705
#define AT91C_PA9_MCDA1    (AT91C_PIO_PA9) //  Multimedia Card A Data 1
3706
#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0
3707
#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) //  SPI 1 Master In Slave
3708
#define AT91C_PB0_TIOA3    (AT91C_PIO_PB0) //  Timer Counter 3 Multipurpose Timer I/O Pin A
3709
#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1
3710
#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) //  SPI 1 Master Out Slave
3711
#define AT91C_PB1_TIOB3    (AT91C_PIO_PB1) //  Timer Counter 3 Multipurpose Timer I/O Pin B
3712
#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10
3713
#define AT91C_PB10_TXD3     (AT91C_PIO_PB10) //  USART 3 Transmit Data
3714
#define AT91C_PB10_ISI_D8   (AT91C_PIO_PB10) //  Image Sensor Data 8
3715
#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11
3716
#define AT91C_PB11_RXD3     (AT91C_PIO_PB11) //  USART 3 Receive Data
3717
#define AT91C_PB11_ISI_D9   (AT91C_PIO_PB11) //  Image Sensor Data 9
3718
#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12
3719
#define AT91C_PB12_TWD1     (AT91C_PIO_PB12) //  TWI Two-wire Serial Data 1
3720
#define AT91C_PB12_ISI_D10  (AT91C_PIO_PB12) //  Image Sensor Data 10
3721
#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13
3722
#define AT91C_PB13_TWCK1    (AT91C_PIO_PB13) //  TWI Two-wire Serial Clock 1
3723
#define AT91C_PB13_ISI_D11  (AT91C_PIO_PB13) //  Image Sensor Data 11
3724
#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14
3725
#define AT91C_PB14_DRXD     (AT91C_PIO_PB14) //  DBGU Debug Receive Data
3726
#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15
3727
#define AT91C_PB15_DTXD     (AT91C_PIO_PB15) //  DBGU Debug Transmit Data
3728
#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16
3729
#define AT91C_PB16_TK0      (AT91C_PIO_PB16) //  SSC0 Transmit Clock
3730
#define AT91C_PB16_TCLK3    (AT91C_PIO_PB16) //  Timer Counter 3 external clock input
3731
#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17
3732
#define AT91C_PB17_TF0      (AT91C_PIO_PB17) //  SSC0 Transmit Frame Sync
3733
#define AT91C_PB17_TCLK4    (AT91C_PIO_PB17) //  Timer Counter 4 external clock input
3734
#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18
3735
#define AT91C_PB18_TD0      (AT91C_PIO_PB18) //  SSC0 Transmit data
3736
#define AT91C_PB18_TIOB4    (AT91C_PIO_PB18) //  Timer Counter 4 Multipurpose Timer I/O Pin B
3737
#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19
3738
#define AT91C_PB19_RD0      (AT91C_PIO_PB19) //  SSC0 Receive Data
3739
#define AT91C_PB19_TIOB5    (AT91C_PIO_PB19) //  Timer Counter 5 Multipurpose Timer I/O Pin B
3740
#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2
3741
#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) //  SPI 1 Serial Clock
3742
#define AT91C_PB2_TIOA4    (AT91C_PIO_PB2) //  Timer Counter 4 Multipurpose Timer I/O Pin A
3743
#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20
3744
#define AT91C_PB20_RK0      (AT91C_PIO_PB20) //  SSC0 Receive Clock
3745
#define AT91C_PB20_ISI_D0   (AT91C_PIO_PB20) //  Image Sensor Data 0
3746
#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21
3747
#define AT91C_PB21_RF0      (AT91C_PIO_PB21) //  SSC0 Receive Frame Sync
3748
#define AT91C_PB21_ISI_D1   (AT91C_PIO_PB21) //  Image Sensor Data 1
3749
#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22
3750
#define AT91C_PB22_DSR0     (AT91C_PIO_PB22) //  USART 0 Data Set ready
3751
#define AT91C_PB22_ISI_D2   (AT91C_PIO_PB22) //  Image Sensor Data 2
3752
#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23
3753
#define AT91C_PB23_DCD0     (AT91C_PIO_PB23) //  USART 0 Data Carrier Detect
3754
#define AT91C_PB23_ISI_D3   (AT91C_PIO_PB23) //  Image Sensor Data 3
3755
#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24
3756
#define AT91C_PB24_DTR0     (AT91C_PIO_PB24) //  USART 0 Data Terminal ready
3757
#define AT91C_PB24_ISI_D4   (AT91C_PIO_PB24) //  Image Sensor Data 4
3758
#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25
3759
#define AT91C_PB25_RI0      (AT91C_PIO_PB25) //  USART 0 Ring Indicator
3760
#define AT91C_PB25_ISI_D5   (AT91C_PIO_PB25) //  Image Sensor Data 5
3761
#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26
3762
#define AT91C_PB26_RTS0     (AT91C_PIO_PB26) //  USART 0 Ready To Send
3763
#define AT91C_PB26_ISI_D6   (AT91C_PIO_PB26) //  Image Sensor Data 6
3764
#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27
3765
#define AT91C_PB27_CTS0     (AT91C_PIO_PB27) //  USART 0 Clear To Send
3766
#define AT91C_PB27_ISI_D7   (AT91C_PIO_PB27) //  Image Sensor Data 7
3767
#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28
3768
#define AT91C_PB28_RTS1     (AT91C_PIO_PB28) //  USART 1 Ready To Send
3769
#define AT91C_PB28_ISI_PCK  (AT91C_PIO_PB28) //  Image Sensor Data Clock
3770
#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29
3771
#define AT91C_PB29_CTS1     (AT91C_PIO_PB29) //  USART 1 Clear To Send
3772
#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) //  Image Sensor Vertical Synchro
3773
#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3
3774
#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) //  SPI 1 Peripheral Chip Select 0
3775
#define AT91C_PB3_TIOA5    (AT91C_PIO_PB3) //  Timer Counter 5 Multipurpose Timer I/O Pin A
3776
#define AT91C_PIO_PB30       (1 << 30) // Pin Controlled by PB30
3777
#define AT91C_PB30_PCK0_0   (AT91C_PIO_PB30) //  PMC Programmable Clock Output 0
3778
#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) //  Image Sensor Horizontal Synchro
3779
#define AT91C_PIO_PB31       (1 << 31) // Pin Controlled by PB31
3780
#define AT91C_PB31_PCK1_0   (AT91C_PIO_PB31) //  PMC Programmable Clock Output 1
3781
#define AT91C_PB31_ISI_MCK  (AT91C_PIO_PB31) //  Image Sensor Reference Clock
3782
#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4
3783
#define AT91C_PB4_TXD0     (AT91C_PIO_PB4) //  USART 0 Transmit Data
3784
#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5
3785
#define AT91C_PB5_RXD0     (AT91C_PIO_PB5) //  USART 0 Receive Data
3786
#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6
3787
#define AT91C_PB6_TXD1     (AT91C_PIO_PB6) //  USART 1 Transmit Data
3788
#define AT91C_PB6_TCLK1    (AT91C_PIO_PB6) //  Timer Counter 1 external clock input
3789
#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7
3790
#define AT91C_PB7_RXD1     (AT91C_PIO_PB7) //  USART 1 Receive Data
3791
#define AT91C_PB7_TCLK2    (AT91C_PIO_PB7) //  Timer Counter 2 external clock input
3792
#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8
3793
#define AT91C_PB8_TXD2     (AT91C_PIO_PB8) //  USART 2 Transmit Data
3794
#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9
3795
#define AT91C_PB9_RXD2     (AT91C_PIO_PB9) //  USART 2 Receive Data
3796
#define AT91C_PIO_PC0        (1 <<  0) // Pin Controlled by PC0
3797
#define AT91C_PC0_AD0      (AT91C_PIO_PC0) //  ADC Analog Input 0
3798
#define AT91C_PC0_SCK3     (AT91C_PIO_PC0) //  USART 3 Serial Clock
3799
#define AT91C_PIO_PC1        (1 <<  1) // Pin Controlled by PC1
3800
#define AT91C_PC1_AD1      (AT91C_PIO_PC1) //  ADC Analog Input 1
3801
#define AT91C_PC1_PCK0     (AT91C_PIO_PC1) //  PMC Programmable Clock Output 0
3802
#define AT91C_PIO_PC10       (1 << 10) // Pin Controlled by PC10
3803
#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) //  Address Bus[25]
3804
#define AT91C_PC10_CTS3     (AT91C_PIO_PC10) //  USART 3 Clear To Send
3805
#define AT91C_PIO_PC11       (1 << 11) // Pin Controlled by PC11
3806
#define AT91C_PC11_NCS2     (AT91C_PIO_PC11) //  Chip Select Line 2
3807
#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) //  SPI 0 Peripheral Chip Select 1
3808
#define AT91C_PIO_PC12       (1 << 12) // Pin Controlled by PC12
3809
#define AT91C_PC12_IRQ0     (AT91C_PIO_PC12) //  External Interrupt 0
3810
#define AT91C_PC12_NCS7     (AT91C_PIO_PC12) //  Chip Select Line 7
3811
#define AT91C_PIO_PC13       (1 << 13) // Pin Controlled by PC13
3812
#define AT91C_PC13_FIQ      (AT91C_PIO_PC13) //  AIC Fast Interrupt Input
3813
#define AT91C_PC13_NCS6     (AT91C_PIO_PC13) //  Chip Select Line 6
3814
#define AT91C_PIO_PC14       (1 << 14) // Pin Controlled by PC14
3815
#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) //  Chip Select Line 3
3816
#define AT91C_PC14_IRQ2     (AT91C_PIO_PC14) //  External Interrupt 2
3817
#define AT91C_PIO_PC15       (1 << 15) // Pin Controlled by PC15
3818
#define AT91C_PC15_NWAIT    (AT91C_PIO_PC15) //  External Wait Signal
3819
#define AT91C_PC15_IRQ1     (AT91C_PIO_PC15) //  External Interrupt 1
3820
#define AT91C_PIO_PC16       (1 << 16) // Pin Controlled by PC16
3821
#define AT91C_PC16_D16      (AT91C_PIO_PC16) //  Data Bus[16]
3822
#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) //  SPI 0 Peripheral Chip Select 2
3823
#define AT91C_PIO_PC17       (1 << 17) // Pin Controlled by PC17
3824
#define AT91C_PC17_D17      (AT91C_PIO_PC17) //  Data Bus[17]
3825
#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) //  SPI 0 Peripheral Chip Select 3
3826
#define AT91C_PIO_PC18       (1 << 18) // Pin Controlled by PC18
3827
#define AT91C_PC18_D18      (AT91C_PIO_PC18) //  Data Bus[18]
3828
#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) //  SPI 1 Peripheral Chip Select 1
3829
#define AT91C_PIO_PC19       (1 << 19) // Pin Controlled by PC19
3830
#define AT91C_PC19_D19      (AT91C_PIO_PC19) //  Data Bus[19]
3831
#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) //  SPI 1 Peripheral Chip Select 2
3832
#define AT91C_PIO_PC2        (1 <<  2) // Pin Controlled by PC2
3833
#define AT91C_PC2_AD2      (AT91C_PIO_PC2) //  ADC Analog Input 2
3834
#define AT91C_PC2_PCK1     (AT91C_PIO_PC2) //  PMC Programmable Clock Output 1
3835
#define AT91C_PIO_PC20       (1 << 20) // Pin Controlled by PC20
3836
#define AT91C_PC20_D20      (AT91C_PIO_PC20) //  Data Bus[20]
3837
#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) //  SPI 1 Peripheral Chip Select 3
3838
#define AT91C_PIO_PC21       (1 << 21) // Pin Controlled by PC21
3839
#define AT91C_PC21_D21      (AT91C_PIO_PC21) //  Data Bus[21]
3840
#define AT91C_PC21_EF100    (AT91C_PIO_PC21) //  Ethernet MAC Force 100 Mbits/sec
3841
#define AT91C_PIO_PC22       (1 << 22) // Pin Controlled by PC22
3842
#define AT91C_PC22_D22      (AT91C_PIO_PC22) //  Data Bus[22]
3843
#define AT91C_PC22_TCLK5    (AT91C_PIO_PC22) //  Timer Counter 5 external clock input
3844
#define AT91C_PIO_PC23       (1 << 23) // Pin Controlled by PC23
3845
#define AT91C_PC23_D23      (AT91C_PIO_PC23) //  Data Bus[23]
3846
#define AT91C_PIO_PC24       (1 << 24) // Pin Controlled by PC24
3847
#define AT91C_PC24_D24      (AT91C_PIO_PC24) //  Data Bus[24]
3848
#define AT91C_PIO_PC25       (1 << 25) // Pin Controlled by PC25
3849
#define AT91C_PC25_D25      (AT91C_PIO_PC25) //  Data Bus[25]
3850
#define AT91C_PIO_PC26       (1 << 26) // Pin Controlled by PC26
3851
#define AT91C_PC26_D26      (AT91C_PIO_PC26) //  Data Bus[26]
3852
#define AT91C_PIO_PC27       (1 << 27) // Pin Controlled by PC27
3853
#define AT91C_PC27_D27      (AT91C_PIO_PC27) //  Data Bus[27]
3854
#define AT91C_PIO_PC28       (1 << 28) // Pin Controlled by PC28
3855
#define AT91C_PC28_D28      (AT91C_PIO_PC28) //  Data Bus[28]
3856
#define AT91C_PIO_PC29       (1 << 29) // Pin Controlled by PC29
3857
#define AT91C_PC29_D29      (AT91C_PIO_PC29) //  Data Bus[29]
3858
#define AT91C_PIO_PC3        (1 <<  3) // Pin Controlled by PC3
3859
#define AT91C_PC3_AD3      (AT91C_PIO_PC3) //  ADC Analog Input 3
3860
#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) //  SPI 1 Peripheral Chip Select 3
3861
#define AT91C_PIO_PC30       (1 << 30) // Pin Controlled by PC30
3862
#define AT91C_PC30_D30      (AT91C_PIO_PC30) //  Data Bus[30]
3863
#define AT91C_PIO_PC31       (1 << 31) // Pin Controlled by PC31
3864
#define AT91C_PC31_D31      (AT91C_PIO_PC31) //  Data Bus[31]
3865
#define AT91C_PIO_PC4        (1 <<  4) // Pin Controlled by PC4
3866
#define AT91C_PC4_A23      (AT91C_PIO_PC4) //  Address Bus[23]
3867
#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) //  SPI 1 Peripheral Chip Select 2
3868
#define AT91C_PIO_PC5        (1 <<  5) // Pin Controlled by PC5
3869
#define AT91C_PC5_A24      (AT91C_PIO_PC5) //  Address Bus[24]
3870
#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) //  SPI 1 Peripheral Chip Select 1
3871
#define AT91C_PIO_PC6        (1 <<  6) // Pin Controlled by PC6
3872
#define AT91C_PC6_TIOB2    (AT91C_PIO_PC6) //  Timer Counter 2 Multipurpose Timer I/O Pin B
3873
#define AT91C_PC6_CFCE1    (AT91C_PIO_PC6) //  Compact Flash Enable 1
3874
#define AT91C_PIO_PC7        (1 <<  7) // Pin Controlled by PC7
3875
#define AT91C_PC7_TIOB1    (AT91C_PIO_PC7) //  Timer Counter 1 Multipurpose Timer I/O Pin B
3876
#define AT91C_PC7_CFCE2    (AT91C_PIO_PC7) //  Compact Flash Enable 2
3877
#define AT91C_PIO_PC8        (1 <<  8) // Pin Controlled by PC8
3878
#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) //  Chip Select Line 4
3879
#define AT91C_PC8_RTS3     (AT91C_PIO_PC8) //  USART 3 Ready To Send
3880
#define AT91C_PIO_PC9        (1 <<  9) // Pin Controlled by PC9
3881
#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) //  Chip Select Line 5
3882
#define AT91C_PC9_TIOB0    (AT91C_PIO_PC9) //  Timer Counter 0 Multipurpose Timer I/O Pin B
3883
 
3884
// *****************************************************************************
3885
//               PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE512
3886
// *****************************************************************************
3887
#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
3888
#define AT91C_ID_SYS    ( 1) // System Controller
3889
#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
3890
#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
3891
#define AT91C_ID_PIOC   ( 4) // Parallel IO Controller C
3892
#define AT91C_ID_ADC    ( 5) // ADC
3893
#define AT91C_ID_US0    ( 6) // USART 0
3894
#define AT91C_ID_US1    ( 7) // USART 1
3895
#define AT91C_ID_US2    ( 8) // USART 2
3896
#define AT91C_ID_MCI    ( 9) // Multimedia Card Interface 0
3897
#define AT91C_ID_UDP    (10) // USB Device Port
3898
#define AT91C_ID_TWI0   (11) // Two-Wire Interface 0
3899
#define AT91C_ID_SPI0   (12) // Serial Peripheral Interface 0
3900
#define AT91C_ID_SPI1   (13) // Serial Peripheral Interface 1
3901
#define AT91C_ID_SSC0   (14) // Serial Synchronous Controller 0
3902
#define AT91C_ID_TC0    (17) // Timer Counter 0
3903
#define AT91C_ID_TC1    (18) // Timer Counter 1
3904
#define AT91C_ID_TC2    (19) // Timer Counter 2
3905
#define AT91C_ID_UHP    (20) // USB Host Port
3906
#define AT91C_ID_EMAC   (21) // Ethernet Mac
3907
#define AT91C_ID_HISI   (22) // Image Sensor Interface
3908
#define AT91C_ID_US3    (23) // USART 3
3909
#define AT91C_ID_US4    (24) // USART 4
3910
#define AT91C_ID_TWI1   (25) // Two-Wire Interface 1
3911
#define AT91C_ID_TC3    (26) // Timer Counter 3
3912
#define AT91C_ID_TC4    (27) // Timer Counter 4
3913
#define AT91C_ID_TC5    (28) // Timer Counter 5
3914
#define AT91C_ID_IRQ0   (29) // Advanced Interrupt Controller (IRQ0)
3915
#define AT91C_ID_IRQ1   (30) // Advanced Interrupt Controller (IRQ1)
3916
#define AT91C_ID_IRQ2   (31) // Advanced Interrupt Controller (IRQ2)
3917
#define AT91C_ALL_INT   (0xFFFE7FFF) // ALL VALID INTERRUPTS
3918
 
3919
// *****************************************************************************
3920
//               BASE ADDRESS DEFINITIONS FOR AT91SAM9XE512
3921
// *****************************************************************************
3922
#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS)     0xFFFFFD00) // (SYS) Base Address
3923
#define AT91C_BASE_EBI       (AT91_CAST(AT91PS_EBI)     0xFFFFEA00) // (EBI) Base Address
3924
#define AT91C_BASE_HECC      (AT91_CAST(AT91PS_ECC)     0xFFFFE800) // (HECC) Base Address
3925
#define AT91C_BASE_SDRAMC    (AT91_CAST(AT91PS_SDRAMC)  0xFFFFEA00) // (SDRAMC) Base Address
3926
#define AT91C_BASE_SMC       (AT91_CAST(AT91PS_SMC)     0xFFFFEC00) // (SMC) Base Address
3927
#define AT91C_BASE_MATRIX    (AT91_CAST(AT91PS_MATRIX)  0xFFFFEE00) // (MATRIX) Base Address
3928
#define AT91C_BASE_CCFG      (AT91_CAST(AT91PS_CCFG)    0xFFFFEF10) // (CCFG) Base Address
3929
#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC)     0xFFFFF300) // (PDC_DBGU) Base Address
3930
#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU)    0xFFFFF200) // (DBGU) Base Address
3931
#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC)     0xFFFFF000) // (AIC) Base Address
3932
#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO)     0xFFFFF400) // (PIOA) Base Address
3933
#define AT91C_BASE_PIOB      (AT91_CAST(AT91PS_PIO)     0xFFFFF600) // (PIOB) Base Address
3934
#define AT91C_BASE_PIOC      (AT91_CAST(AT91PS_PIO)     0xFFFFF800) // (PIOC) Base Address
3935
#define AT91C_BASE_EFC       (AT91_CAST(AT91PS_EFC)     0xFFFFFA00) // (EFC) Base Address
3936
#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR)    0xFFFFFC20) // (CKGR) Base Address
3937
#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC)     0xFFFFFC00) // (PMC) Base Address
3938
#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC)    0xFFFFFD00) // (RSTC) Base Address
3939
#define AT91C_BASE_SHDWC     (AT91_CAST(AT91PS_SHDWC)   0xFFFFFD10) // (SHDWC) Base Address
3940
#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC)    0xFFFFFD20) // (RTTC) Base Address
3941
#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC)    0xFFFFFD30) // (PITC) Base Address
3942
#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC)    0xFFFFFD40) // (WDTC) Base Address
3943
#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC)      0xFFFA0000) // (TC0) Base Address
3944
#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC)      0xFFFA0040) // (TC1) Base Address
3945
#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC)      0xFFFA0080) // (TC2) Base Address
3946
#define AT91C_BASE_TC3       (AT91_CAST(AT91PS_TC)      0xFFFDC000) // (TC3) Base Address
3947
#define AT91C_BASE_TC4       (AT91_CAST(AT91PS_TC)      0xFFFDC040) // (TC4) Base Address
3948
#define AT91C_BASE_TC5       (AT91_CAST(AT91PS_TC)      0xFFFDC080) // (TC5) Base Address
3949
#define AT91C_BASE_TCB0      (AT91_CAST(AT91PS_TCB)     0xFFFA0000) // (TCB0) Base Address
3950
#define AT91C_BASE_TCB1      (AT91_CAST(AT91PS_TCB)     0xFFFDC000) // (TCB1) Base Address
3951
#define AT91C_BASE_PDC_MCI   (AT91_CAST(AT91PS_PDC)     0xFFFA8100) // (PDC_MCI) Base Address
3952
#define AT91C_BASE_MCI       (AT91_CAST(AT91PS_MCI)     0xFFFA8000) // (MCI) Base Address
3953
#define AT91C_BASE_PDC_TWI0  (AT91_CAST(AT91PS_PDC)     0xFFFAC100) // (PDC_TWI0) Base Address
3954
#define AT91C_BASE_TWI0      (AT91_CAST(AT91PS_TWI)     0xFFFAC000) // (TWI0) Base Address
3955
#define AT91C_BASE_PDC_TWI1  (AT91_CAST(AT91PS_PDC)     0xFFFD8100) // (PDC_TWI1) Base Address
3956
#define AT91C_BASE_TWI1      (AT91_CAST(AT91PS_TWI)     0xFFFD8000) // (TWI1) Base Address
3957
#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC)     0xFFFB0100) // (PDC_US0) Base Address
3958
#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART)   0xFFFB0000) // (US0) Base Address
3959
#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC)     0xFFFB4100) // (PDC_US1) Base Address
3960
#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART)   0xFFFB4000) // (US1) Base Address
3961
#define AT91C_BASE_PDC_US2   (AT91_CAST(AT91PS_PDC)     0xFFFB8100) // (PDC_US2) Base Address
3962
#define AT91C_BASE_US2       (AT91_CAST(AT91PS_USART)   0xFFFB8000) // (US2) Base Address
3963
#define AT91C_BASE_PDC_US3   (AT91_CAST(AT91PS_PDC)     0xFFFD0100) // (PDC_US3) Base Address
3964
#define AT91C_BASE_US3       (AT91_CAST(AT91PS_USART)   0xFFFD0000) // (US3) Base Address
3965
#define AT91C_BASE_PDC_US4   (AT91_CAST(AT91PS_PDC)     0xFFFD4100) // (PDC_US4) Base Address
3966
#define AT91C_BASE_US4       (AT91_CAST(AT91PS_USART)   0xFFFD4000) // (US4) Base Address
3967
#define AT91C_BASE_PDC_SSC0  (AT91_CAST(AT91PS_PDC)     0xFFFBC100) // (PDC_SSC0) Base Address
3968
#define AT91C_BASE_SSC0      (AT91_CAST(AT91PS_SSC)     0xFFFBC000) // (SSC0) Base Address
3969
#define AT91C_BASE_PDC_SPI0  (AT91_CAST(AT91PS_PDC)     0xFFFC8100) // (PDC_SPI0) Base Address
3970
#define AT91C_BASE_SPI0      (AT91_CAST(AT91PS_SPI)     0xFFFC8000) // (SPI0) Base Address
3971
#define AT91C_BASE_PDC_SPI1  (AT91_CAST(AT91PS_PDC)     0xFFFCC100) // (PDC_SPI1) Base Address
3972
#define AT91C_BASE_SPI1      (AT91_CAST(AT91PS_SPI)     0xFFFCC000) // (SPI1) Base Address
3973
#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC)     0xFFFE0100) // (PDC_ADC) Base Address
3974
#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC)     0xFFFE0000) // (ADC) Base Address
3975
#define AT91C_BASE_EMACB     (AT91_CAST(AT91PS_EMAC)    0xFFFC4000) // (EMACB) Base Address
3976
#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP)     0xFFFA4000) // (UDP) Base Address
3977
#define AT91C_BASE_UHP       (AT91_CAST(AT91PS_UHP)     0x00500000) // (UHP) Base Address
3978
#define AT91C_BASE_HISI      (AT91_CAST(AT91PS_ISI)     0xFFFC0000) // (HISI) Base Address
3979
 
3980
// *****************************************************************************
3981
//               MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE512
3982
// *****************************************************************************
3983
// IROM
3984
#define AT91C_IROM       (0x00100000) // Internal ROM base address
3985
#define AT91C_IROM_SIZE  (0x00008000) // Internal ROM size in byte (32 Kbytes)
3986
// ISRAM
3987
#define AT91C_ISRAM      (0x00300000) // Maximum IRAM Area : 32Kbyte base address
3988
#define AT91C_ISRAM_SIZE         (0x00008000) // Maximum IRAM Area : 32Kbyte size in byte (32 Kbytes)
3989
// ISRAM_MIN
3990
#define AT91C_ISRAM_MIN  (0x00300000) // Minimun IRAM Area : 32Kbyte base address
3991
#define AT91C_ISRAM_MIN_SIZE     (0x00008000) // Minimun IRAM Area : 32Kbyte size in byte (32 Kbytes)
3992
// IFLASH
3993
#define AT91C_IFLASH     (0x00200000) // Maximum IFLASH Area : 512Kbyte base address
3994
#define AT91C_IFLASH_SIZE        (0x00080000) // Maximum IFLASH Area : 512Kbyte size in byte (512 Kbytes)
3995
#define AT91C_IFLASH_PAGE_SIZE   (512) // Maximum IFLASH Area : 512Kbyte Page Size: 512 bytes
3996
#define AT91C_IFLASH_LOCK_REGION_SIZE    (16384) // Maximum IFLASH Area : 512Kbyte Lock Region Size: 16 Kbytes
3997
#define AT91C_IFLASH_NB_OF_PAGES         (1024) // Maximum IFLASH Area : 512Kbyte Number of Pages: 1024 bytes
3998
#define AT91C_IFLASH_NB_OF_LOCK_BITS     (32) // Maximum IFLASH Area : 512Kbyte Number of Lock Bits: 32 bytes
3999
// EBI_CS0
4000
#define AT91C_EBI_CS0    (0x10000000) // EBI Chip Select 0 base address
4001
#define AT91C_EBI_CS0_SIZE       (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
4002
// EBI_CS1
4003
#define AT91C_EBI_CS1    (0x20000000) // EBI Chip Select 1 base address
4004
#define AT91C_EBI_CS1_SIZE       (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
4005
// EBI_SDRAM
4006
#define AT91C_EBI_SDRAM  (0x20000000) // SDRAM on EBI Chip Select 1 base address
4007
#define AT91C_EBI_SDRAM_SIZE     (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
4008
// EBI_SDRAM_16BIT
4009
#define AT91C_EBI_SDRAM_16BIT    (0x20000000) // SDRAM on EBI Chip Select 1 base address
4010
#define AT91C_EBI_SDRAM_16BIT_SIZE       (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
4011
// EBI_SDRAM_32BIT
4012
#define AT91C_EBI_SDRAM_32BIT    (0x20000000) // SDRAM on EBI Chip Select 1 base address
4013
#define AT91C_EBI_SDRAM_32BIT_SIZE       (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
4014
// EBI_CS2
4015
#define AT91C_EBI_CS2    (0x30000000) // EBI Chip Select 2 base address
4016
#define AT91C_EBI_CS2_SIZE       (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
4017
// EBI_CS3
4018
#define AT91C_EBI_CS3    (0x40000000) // EBI Chip Select 3 base address
4019
#define AT91C_EBI_CS3_SIZE       (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
4020
// EBI_SM
4021
#define AT91C_EBI_SM     (0x40000000) // SmartMedia on Chip Select 3 base address
4022
#define AT91C_EBI_SM_SIZE        (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)
4023
// EBI_CS4
4024
#define AT91C_EBI_CS4    (0x50000000) // EBI Chip Select 4 base address
4025
#define AT91C_EBI_CS4_SIZE       (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
4026
// EBI_CF0
4027
#define AT91C_EBI_CF0    (0x50000000) // CompactFlash 0 on Chip Select 4 base address
4028
#define AT91C_EBI_CF0_SIZE       (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)
4029
// EBI_CS5
4030
#define AT91C_EBI_CS5    (0x60000000) // EBI Chip Select 5 base address
4031
#define AT91C_EBI_CS5_SIZE       (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
4032
// EBI_CF1
4033
#define AT91C_EBI_CF1    (0x60000000) // CompactFlash 1 on Chip Select 5 base address
4034
#define AT91C_EBI_CF1_SIZE       (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)
4035
// EBI_CS6
4036
#define AT91C_EBI_CS6    (0x70000000) // EBI Chip Select 6 base address
4037
#define AT91C_EBI_CS6_SIZE       (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)
4038
// EBI_CS7
4039
#define AT91C_EBI_CS7    (0x80000000) // EBI Chip Select 7 base address
4040
#define AT91C_EBI_CS7_SIZE       (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)
4041
 
4042
#endif

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