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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [Atmel/] [at91lib/] [boards/] [at91sam9xe-ek/] [board_memories.c] - Blame information for rev 608

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Line No. Rev Author Line
1 608 jeremybenn 
/* ----------------------------------------------------------------------------
2 
 *         ATMEL Microcontroller Software Support
3 
 * ----------------------------------------------------------------------------
4 
 * Copyright (c) 2008, Atmel Corporation
5 
 *
6 
 * All rights reserved.
7 
 *
8 
 * Redistribution and use in source and binary forms, with or without
9 
 * modification, are permitted provided that the following conditions are met:
10 
 *
11 
 * - Redistributions of source code must retain the above copyright notice,
12 
 * this list of conditions and the disclaimer below.
13 
 *
14 
 * Atmel's name may not be used to endorse or promote products derived from
15 
 * this software without specific prior written permission.
16 
 *
17 
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18 
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20 
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21 
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23 
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 
 * ----------------------------------------------------------------------------
28 
 */
29 
 
30 
//------------------------------------------------------------------------------
31 
//         Headers
32 
//------------------------------------------------------------------------------
33 
 
34 
#include <board.h>
35 
#include <pio/pio.h>
36 
 
37 
//------------------------------------------------------------------------------
38 
//         Local macros
39 
//------------------------------------------------------------------------------
40 
 
41 
/// Reads a register value. Useful to add trace information to read  accesses.
42 
#define READ(peripheral, register)          (peripheral->register)
43 
/// Writes data in a register. Useful to add trace information to write accesses.
44 
#define WRITE(peripheral, register, value)  (peripheral->register = value)
45 
 
46 
//------------------------------------------------------------------------------
47 
//         Global functions
48 
//------------------------------------------------------------------------------
49 
 
50 
//------------------------------------------------------------------------------
51 
/// Changes the mapping of the chip so that the remap area mirrors the
52 
/// internal ROM or the EBI CS0 (depending on the BMS input).
53 
//------------------------------------------------------------------------------
54 
void BOARD_RemapRom(void)
55 
{
56 
    WRITE(AT91C_BASE_MATRIX, MATRIX_MRCR, 0);
57 
}
58 
 
59 
//------------------------------------------------------------------------------
60 
/// Changes the mapping of the chip so that the remap area mirrors the
61 
/// internal RAM.
62 
//------------------------------------------------------------------------------
63 
void BOARD_RemapRam(void)
64 
{
65 
    WRITE(AT91C_BASE_MATRIX,
66 
          MATRIX_MRCR,
67 
          (AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D));
68 
}
69 
 
70 
//------------------------------------------------------------------------------
71 
/// Initialize and configure the external SDRAM.
72 
//------------------------------------------------------------------------------
73 
void BOARD_ConfigureSdram(void)
74 
{
75 
        volatile unsigned int i;
76 
        static const Pin pinsSdram = PINS_SDRAM;
77 
        volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
78 
 
79 
        // Enable corresponding PIOs
80 
    PIO_Configure(&pinsSdram, 1);
81 
 
82 
        // Enable EBI chip select for the SDRAM
83 
        WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
84 
 
85 
 
86 
        // CFG Control Register
87 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
88 
                                                        | AT91C_SDRAMC_NR_13
89 
                                                        | AT91C_SDRAMC_CAS_2
90 
                                                        | AT91C_SDRAMC_NB_4_BANKS
91 
                                                        | AT91C_SDRAMC_DBW_32_BITS
92 
                                                        | AT91C_SDRAMC_TWR_2
93 
                                                        | AT91C_SDRAMC_TRC_7
94 
                                                        | AT91C_SDRAMC_TRP_2
95 
                                                        | AT91C_SDRAMC_TRCD_2
96 
                                                        | AT91C_SDRAMC_TRAS_5
97 
                                                        | AT91C_SDRAMC_TXSR_8);
98 
 
99 
        for (i = 0; i < 1000; i++);
100 
 
101 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
102 
        pSdram[0] = 0x00000000;
103 
 
104 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD);     // Set PRCHG AL
105 
        pSdram[0] = 0x00000000;                                          // Perform PRCHG
106 
 
107 
        for (i = 0; i < 10000; i++);
108 
 
109 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 1st CBR
110 
        pSdram[1] = 0x00000001;                                         // Perform CBR
111 
 
112 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 2 CBR
113 
        pSdram[2] = 0x00000002;                                         // Perform CBR
114 
 
115 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 3 CBR
116 
        pSdram[3] = 0x00000003;                                    // Perform CBR
117 
 
118 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 4 CBR
119 
        pSdram[4] = 0x00000004;                                   // Perform CBR
120 
 
121 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 5 CBR
122 
        pSdram[5] = 0x00000005;                                   // Perform CBR
123 
 
124 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 6 CBR
125 
        pSdram[6] = 0x00000006;                                 // Perform CBR
126 
 
127 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 7 CBR
128 
        pSdram[7] = 0x00000007;                                 // Perform CBR
129 
 
130 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 8 CBR
131 
        pSdram[8] = 0x00000008;                                 // Perform CBR
132 
 
133 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD);         // Set LMR operation
134 
        pSdram[9] = 0xcafedede;                                 // Perform LMR burst=1, lat=2
135 
 
136 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000);         // Set Refresh Timer
137 
 
138 
        WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD);      // Set Normal mode
139 
        pSdram[0] = 0x00000000;                                          // Perform Normal mode
140 
}
141 
 
142 
//------------------------------------------------------------------------------
143 
/// Initialize and configure the SDRAM for a 48 MHz MCK (ROM code clock settings).
144 
//------------------------------------------------------------------------------
145 
void BOARD_ConfigureSdram48MHz(void)
146 
{
147 
    volatile unsigned int i;
148 
    static const Pin pinsSdram = PINS_SDRAM;
149 
    volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
150 
 
151 
    // Enable corresponding PIOs
152 
    PIO_Configure(&pinsSdram, 1);
153 
 
154 
    // Enable EBI chip select for the SDRAM
155 
    WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
156 
 
157 
 
158 
    // CFG Control Register
159 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
160 
                                        | AT91C_SDRAMC_NR_13
161 
                                        | AT91C_SDRAMC_CAS_2
162 
                                        | AT91C_SDRAMC_NB_4_BANKS
163 
                                        | AT91C_SDRAMC_DBW_32_BITS
164 
                                        | AT91C_SDRAMC_TWR_1
165 
                                        | AT91C_SDRAMC_TRC_4
166 
                                        | AT91C_SDRAMC_TRP_1
167 
                                        | AT91C_SDRAMC_TRCD_1
168 
                                        | AT91C_SDRAMC_TRAS_2
169 
                                        | AT91C_SDRAMC_TXSR_3);
170 
 
171 
    for (i = 0; i < 1000; i++);
172 
 
173 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
174 
    pSdram[0] = 0x00000000;
175 
 
176 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
177 
    pSdram[0] = 0x00000000;                     // Perform PRCHG
178 
 
179 
    for (i = 0; i < 10000; i++);
180 
 
181 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 1st CBR
182 
    pSdram[1] = 0x00000001;                     // Perform CBR
183 
 
184 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 2 CBR
185 
    pSdram[2] = 0x00000002;                     // Perform CBR
186 
 
187 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 3 CBR
188 
    pSdram[3] = 0x00000003;                    // Perform CBR
189 
 
190 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 4 CBR
191 
    pSdram[4] = 0x00000004;                   // Perform CBR
192 
 
193 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 5 CBR
194 
    pSdram[5] = 0x00000005;                   // Perform CBR
195 
 
196 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 6 CBR
197 
    pSdram[6] = 0x00000006;                 // Perform CBR
198 
 
199 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 7 CBR
200 
    pSdram[7] = 0x00000007;                 // Perform CBR
201 
 
202 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 8 CBR
203 
    pSdram[8] = 0x00000008;                 // Perform CBR
204 
 
205 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD);     // Set LMR operation
206 
    pSdram[9] = 0xcafedede;                 // Perform LMR burst=1, lat=2
207 
 
208 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (48000000 * 7) / 1000000);      // Set Refresh Timer
209 
 
210 
    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD);  // Set Normal mode
211 
    pSdram[0] = 0x00000000;                     // Perform Normal mode
212 
}
213 
 
214 
//------------------------------------------------------------------------------
215 
/// Configures the EBI for NandFlash access. Pins must be configured after or
216 
/// before calling this function.
217 
//------------------------------------------------------------------------------
218 
void BOARD_ConfigureNandFlash(unsigned char busWidth)
219 
{
220 
    // Configure EBI
221 
    AT91C_BASE_MATRIX->MATRIX_EBI |= AT91C_MATRIX_CS3A_SM;
222 
 
223 
    // Configure SMC
224 
    AT91C_BASE_SMC->SMC_SETUP3 = 0x00000000;
225 
    AT91C_BASE_SMC->SMC_PULSE3 = 0x00030003;
226 
    AT91C_BASE_SMC->SMC_CYCLE3 = 0x00050005;
227 
    AT91C_BASE_SMC->SMC_CTRL3  = 0x00002003;
228 
 
229 
    if (busWidth == 8) {
230 
 
231 
        AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
232 
    }
233 
    else if (busWidth == 16) {
234 
 
235 
        AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
236 
    }
237 
}
238 
 
239 
//------------------------------------------------------------------------------
240 
/// Configures the EBI for NandFlash access at 48MHz. Pins must be configured
241 
/// after or before calling this function.
242 
//------------------------------------------------------------------------------
243 
void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth)
244 
{
245 
    // Configure EBI
246 
    AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM;
247 
 
248 
    // Configure SMC
249 
    AT91C_BASE_SMC->SMC_SETUP3 = 0x00010001;
250 
    AT91C_BASE_SMC->SMC_PULSE3 = 0x04030302;
251 
    AT91C_BASE_SMC->SMC_CYCLE3 = 0x00070004;
252 
    AT91C_BASE_SMC->SMC_CTRL3  = (AT91C_SMC_READMODE
253 
                                 | AT91C_SMC_WRITEMODE
254 
                                 | AT91C_SMC_NWAITM_NWAIT_DISABLE
255 
                                 | ((0x1 << 16) & AT91C_SMC_TDF));
256 
 
257 
    if (busWidth == 8) {
258 
 
259 
        AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
260 
    }
261 
    else if (busWidth == 16) {
262 
 
263 
        AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
264 
    }
265 
}
266 
 
267 
//------------------------------------------------------------------------------
268 
/// Configures the EBI for NorFlash access at 48MHz.
269 
/// \Param busWidth Bus width
270 
//------------------------------------------------------------------------------
271 
void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth)
272 
{
273 
    // Configure SMC
274 
    AT91C_BASE_SMC->SMC_SETUP0 = 0x00000001;
275 
    AT91C_BASE_SMC->SMC_PULSE0 = 0x07070703;
276 
    AT91C_BASE_SMC->SMC_CYCLE0 = 0x00070007;
277 
    AT91C_BASE_SMC->SMC_CTRL0  = (AT91C_SMC_READMODE
278 
                                  | AT91C_SMC_WRITEMODE
279 
                                  | AT91C_SMC_NWAITM_NWAIT_DISABLE
280 
                                  | ((0x1 << 16) & AT91C_SMC_TDF));
281 
 
282 
    if (busWidth == 8) {
283 
 
284 
        AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
285 
    }
286 
    else if (busWidth == 16) {
287 
 
288 
        AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
289 
    }
290 
    else if (busWidth == 32) {
291 
 
292 
        AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS;
293 
    }
294 
}
295 
 
296 
//------------------------------------------------------------------------------
297 
/// Set flash wait states in the EFC for 48MHz
298 
//------------------------------------------------------------------------------
299 
void BOARD_ConfigureFlash48MHz(void)
300 
{
301 
    // Set flash wait states
302 
    //----------------------
303 
    AT91C_BASE_EFC->EFC_FMR = 6 << 8;
304 
}

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