OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [Atmel/] [at91lib/] [peripherals/] [rstc/] [rstc.h] - Blame information for rev 608

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 608 jeremybenn
/* ----------------------------------------------------------------------------
2
 *         ATMEL Microcontroller Software Support
3
 * ----------------------------------------------------------------------------
4
 * Copyright (c) 2008, Atmel Corporation
5
 *
6
 * All rights reserved.
7
 *
8
 * Redistribution and use in source and binary forms, with or without
9
 * modification, are permitted provided that the following conditions are met:
10
 *
11
 * - Redistributions of source code must retain the above copyright notice,
12
 * this list of conditions and the disclaimer below.
13
 *
14
 * Atmel's name may not be used to endorse or promote products derived from
15
 * this software without specific prior written permission.
16
 *
17
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 * ----------------------------------------------------------------------------
28
 */
29
 
30
#ifndef _RSTC_H
31
#define _RSTC_H
32
 
33
//-----------------------------------------------------------------------------
34
//         Exported functions
35
//-----------------------------------------------------------------------------
36
 
37
extern void RSTC_ConfigureMode(AT91PS_RSTC rstc, unsigned int rmr);
38
 
39
extern void RSTC_SetUserResetEnable(AT91PS_RSTC rstc, unsigned char enable);
40
 
41
extern void RSTC_SetUserResetInterruptEnable(AT91PS_RSTC rstc,
42
                                             unsigned char enable);
43
 
44
extern void RSTC_SetExtResetLength(AT91PS_RSTC rstc, unsigned char powl);
45
 
46
extern void RSTC_ProcessorReset(AT91PS_RSTC rstc);
47
 
48
extern void RSTC_PeripheralReset(AT91PS_RSTC rstc);
49
 
50
extern void RSTC_ExtReset(AT91PS_RSTC rstc);
51
 
52
extern unsigned char RSTC_GetNrstLevel(AT91PS_RSTC rstc);
53
 
54
extern unsigned char RSTC_IsUserReseetDetected(AT91PS_RSTC rstc);
55
 
56
extern unsigned char RSTC_IsBusy(AT91PS_RSTC rstc);
57
 
58
#endif // #ifndef _RSTC_H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.