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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [LuminaryMicro/] [hw_adc.h] - Blame information for rev 610

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1 610 jeremybenn
//*****************************************************************************
2
//
3
// hw_adc.h - Macros used when accessing the ADC hardware.
4
//
5
// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
6
// 
7
// Software License Agreement
8
// 
9
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
11
// 
12
// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws.  All rights are reserved.  You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program.  Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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// 
19
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
20
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
21
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
22
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
23
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
24
// 
25
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
26
//
27
//*****************************************************************************
28
 
29
#ifndef __HW_ADC_H__
30
#define __HW_ADC_H__
31
 
32
//*****************************************************************************
33
//
34
// The following are defines for the ADC register offsets.
35
//
36
//*****************************************************************************
37
#define ADC_O_ACTSS             0x00000000  // Active sample register
38
#define ADC_O_RIS               0x00000004  // Raw interrupt status register
39
#define ADC_O_IM                0x00000008  // Interrupt mask register
40
#define ADC_O_ISC               0x0000000C  // Interrupt status/clear register
41
#define ADC_O_OSTAT             0x00000010  // Overflow status register
42
#define ADC_O_EMUX              0x00000014  // Event multiplexer select reg.
43
#define ADC_O_USTAT             0x00000018  // Underflow status register
44
#define ADC_O_SSPRI             0x00000020  // Channel priority register
45
#define ADC_O_PSSI              0x00000028  // Processor sample initiate reg.
46
#define ADC_O_SAC               0x00000030  // Sample Averaging Control reg.
47
#define ADC_O_SSMUX0            0x00000040  // Multiplexer select 0 register
48
#define ADC_O_SSCTL0            0x00000044  // Sample sequence control 0 reg.
49
#define ADC_O_SSFIFO0           0x00000048  // Result FIFO 0 register
50
#define ADC_O_SSFSTAT0          0x0000004C  // FIFO 0 status register
51
#define ADC_O_SSMUX1            0x00000060  // Multiplexer select 1 register
52
#define ADC_O_SSCTL1            0x00000064  // Sample sequence control 1 reg.
53
#define ADC_O_SSFIFO1           0x00000068  // Result FIFO 1 register
54
#define ADC_O_SSFSTAT1          0x0000006C  // FIFO 1 status register
55
#define ADC_O_SSMUX2            0x00000080  // Multiplexer select 2 register
56
#define ADC_O_SSCTL2            0x00000084  // Sample sequence control 2 reg.
57
#define ADC_O_SSFIFO2           0x00000088  // Result FIFO 2 register
58
#define ADC_O_SSFSTAT2          0x0000008C  // FIFO 2 status register
59
#define ADC_O_SSMUX3            0x000000A0  // Multiplexer select 3 register
60
#define ADC_O_SSCTL3            0x000000A4  // Sample sequence control 3 reg.
61
#define ADC_O_SSFIFO3           0x000000A8  // Result FIFO 3 register
62
#define ADC_O_SSFSTAT3          0x000000AC  // FIFO 3 status register
63
#define ADC_O_TMLB              0x00000100  // Test mode loopback register
64
 
65
//*****************************************************************************
66
//
67
// The following are defines for the bit fields in the ADC_ACTSS register.
68
//
69
//*****************************************************************************
70
#define ADC_ACTSS_ASEN3         0x00000008  // Sample sequence 3 enable
71
#define ADC_ACTSS_ASEN2         0x00000004  // Sample sequence 2 enable
72
#define ADC_ACTSS_ASEN1         0x00000002  // Sample sequence 1 enable
73
#define ADC_ACTSS_ASEN0         0x00000001  // Sample sequence 0 enable
74
 
75
//*****************************************************************************
76
//
77
// The following are defines for the bit fields in the ADC_RIS register.
78
//
79
//*****************************************************************************
80
#define ADC_RIS_INR3            0x00000008  // Sample sequence 3 interrupt
81
#define ADC_RIS_INR2            0x00000004  // Sample sequence 2 interrupt
82
#define ADC_RIS_INR1            0x00000002  // Sample sequence 1 interrupt
83
#define ADC_RIS_INR0            0x00000001  // Sample sequence 0 interrupt
84
 
85
//*****************************************************************************
86
//
87
// The following are defines for the bit fields in the ADC_IM register.
88
//
89
//*****************************************************************************
90
#define ADC_IM_MASK3            0x00000008  // Sample sequence 3 mask
91
#define ADC_IM_MASK2            0x00000004  // Sample sequence 2 mask
92
#define ADC_IM_MASK1            0x00000002  // Sample sequence 1 mask
93
#define ADC_IM_MASK0            0x00000001  // Sample sequence 0 mask
94
 
95
//*****************************************************************************
96
//
97
// The following are defines for the bit fields in the ADC_ISC register.
98
//
99
//*****************************************************************************
100
#define ADC_ISC_IN3             0x00000008  // Sample sequence 3 interrupt
101
#define ADC_ISC_IN2             0x00000004  // Sample sequence 2 interrupt
102
#define ADC_ISC_IN1             0x00000002  // Sample sequence 1 interrupt
103
#define ADC_ISC_IN0             0x00000001  // Sample sequence 0 interrupt
104
 
105
//*****************************************************************************
106
//
107
// The following are defines for the bit fields in the ADC_OSTAT register.
108
//
109
//*****************************************************************************
110
#define ADC_OSTAT_OV3           0x00000008  // Sample sequence 3 overflow
111
#define ADC_OSTAT_OV2           0x00000004  // Sample sequence 2 overflow
112
#define ADC_OSTAT_OV1           0x00000002  // Sample sequence 1 overflow
113
#define ADC_OSTAT_OV0           0x00000001  // Sample sequence 0 overflow
114
 
115
//*****************************************************************************
116
//
117
// The following are defines for the bit fields in the ADC_EMUX register.
118
//
119
//*****************************************************************************
120
#define ADC_EMUX_EM3_M          0x0000F000  // Event mux 3 mask
121
#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor event
122
#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog comparator 0 event
123
#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog comparator 1 event
124
#define ADC_EMUX_EM3_COMP2      0x00003000  // Analog comparator 2 event
125
#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External event
126
#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer event
127
#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM0 event
128
#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM1 event
129
#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2 event
130
#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always event
131
#define ADC_EMUX_EM2_M          0x00000F00  // Event mux 2 mask
132
#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor event
133
#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog comparator 0 event
134
#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog comparator 1 event
135
#define ADC_EMUX_EM2_COMP2      0x00000300  // Analog comparator 2 event
136
#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External event
137
#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer event
138
#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM0 event
139
#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM1 event
140
#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2 event
141
#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always event
142
#define ADC_EMUX_EM1_M          0x000000F0  // Event mux 1 mask
143
#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor event
144
#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog comparator 0 event
145
#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog comparator 1 event
146
#define ADC_EMUX_EM1_COMP2      0x00000030  // Analog comparator 2 event
147
#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External event
148
#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer event
149
#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM0 event
150
#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM1 event
151
#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2 event
152
#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always event
153
#define ADC_EMUX_EM0_M          0x0000000F  // Event mux 0 mask
154
#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor event
155
#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog comparator 0 event
156
#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog comparator 1 event
157
#define ADC_EMUX_EM0_COMP2      0x00000003  // Analog comparator 2 event
158
#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External event
159
#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer event
160
#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM0 event
161
#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM1 event
162
#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM2 event
163
#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always event
164
 
165
//*****************************************************************************
166
//
167
// The following are defines for the bit fields in the ADC_USTAT register.
168
//
169
//*****************************************************************************
170
#define ADC_USTAT_UV3           0x00000008  // Sample sequence 3 underflow
171
#define ADC_USTAT_UV2           0x00000004  // Sample sequence 2 underflow
172
#define ADC_USTAT_UV1           0x00000002  // Sample sequence 1 underflow
173
#define ADC_USTAT_UV0           0x00000001  // Sample sequence 0 underflow
174
 
175
//*****************************************************************************
176
//
177
// The following are defines for the bit fields in the ADC_SSPRI register.
178
//
179
//*****************************************************************************
180
#define ADC_SSPRI_SS3_M         0x00003000  // Sequencer 3 priority mask
181
#define ADC_SSPRI_SS3_1ST       0x00000000  // First priority
182
#define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority
183
#define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority
184
#define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority
185
#define ADC_SSPRI_SS2_M         0x00000300  // Sequencer 2 priority mask
186
#define ADC_SSPRI_SS2_1ST       0x00000000  // First priority
187
#define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority
188
#define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority
189
#define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority
190
#define ADC_SSPRI_SS1_M         0x00000030  // Sequencer 1 priority mask
191
#define ADC_SSPRI_SS1_1ST       0x00000000  // First priority
192
#define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority
193
#define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority
194
#define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority
195
#define ADC_SSPRI_SS0_M         0x00000003  // Sequencer 0 priority mask
196
#define ADC_SSPRI_SS0_1ST       0x00000000  // First priority
197
#define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority
198
#define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority
199
#define ADC_SSPRI_SS0_4TH       0x00000003  // Fourth priority
200
 
201
//*****************************************************************************
202
//
203
// The following are defines for the bit fields in the ADC_PSSI register.
204
//
205
//*****************************************************************************
206
#define ADC_PSSI_SS3            0x00000008  // Trigger sample sequencer 3
207
#define ADC_PSSI_SS2            0x00000004  // Trigger sample sequencer 2
208
#define ADC_PSSI_SS1            0x00000002  // Trigger sample sequencer 1
209
#define ADC_PSSI_SS0            0x00000001  // Trigger sample sequencer 0
210
 
211
//*****************************************************************************
212
//
213
// The following are defines for the bit fields in the ADC_SAC register.
214
//
215
//*****************************************************************************
216
#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control.
217
#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
218
#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
219
#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
220
#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
221
#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
222
#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
223
#define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
224
 
225
//*****************************************************************************
226
//
227
// The following are defines for the bit fields in the ADC_TMLB register.
228
//
229
//*****************************************************************************
230
#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter.
231
#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator.
232
#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator.
233
#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator.
234
#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator.
235
#define ADC_TMLB_LB             0x00000001  // Loopback control signals
236
#define ADC_TMLB_CNT_S          6           // Sample counter shift
237
#define ADC_TMLB_MUX_S          0           // Input channel number shift
238
 
239
//*****************************************************************************
240
//
241
// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
242
//
243
//*****************************************************************************
244
#define ADC_SSMUX0_MUX7_M       0x70000000  // 8th Sample Input Select.
245
#define ADC_SSMUX0_MUX6_M       0x07000000  // 7th Sample Input Select.
246
#define ADC_SSMUX0_MUX5_M       0x00700000  // 6th Sample Input Select.
247
#define ADC_SSMUX0_MUX4_M       0x00070000  // 5th Sample Input Select.
248
#define ADC_SSMUX0_MUX3_M       0x00007000  // 4th Sample Input Select.
249
#define ADC_SSMUX0_MUX2_M       0x00000700  // 3rd Sample Input Select.
250
#define ADC_SSMUX0_MUX1_M       0x00000070  // 2nd Sample Input Select.
251
#define ADC_SSMUX0_MUX0_M       0x00000007  // 1st Sample Input Select.
252
#define ADC_SSMUX0_MUX7_S       28
253
#define ADC_SSMUX0_MUX6_S       24
254
#define ADC_SSMUX0_MUX5_S       20
255
#define ADC_SSMUX0_MUX4_S       16
256
#define ADC_SSMUX0_MUX3_S       12
257
#define ADC_SSMUX0_MUX2_S       8
258
#define ADC_SSMUX0_MUX1_S       4
259
#define ADC_SSMUX0_MUX0_S       0
260
 
261
//*****************************************************************************
262
//
263
// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
264
//
265
//*****************************************************************************
266
#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select.
267
#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable.
268
#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence.
269
#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select.
270
#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select.
271
#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable.
272
#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence.
273
#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select.
274
#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select.
275
#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable.
276
#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence.
277
#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select.
278
#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select.
279
#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable.
280
#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence.
281
#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select.
282
#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select.
283
#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable.
284
#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence.
285
#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select.
286
#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
287
#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable.
288
#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence.
289
#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select.
290
#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
291
#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable.
292
#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence.
293
#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select.
294
#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select.
295
#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable.
296
#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence.
297
#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select.
298
 
299
//*****************************************************************************
300
//
301
// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
302
//
303
//*****************************************************************************
304
#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data.
305
#define ADC_SSFIFO0_DATA_S      0
306
 
307
//*****************************************************************************
308
//
309
// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
310
//
311
//*****************************************************************************
312
#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full.
313
#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty.
314
#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer.
315
#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer.
316
#define ADC_SSFSTAT0_HPTR_S     4
317
#define ADC_SSFSTAT0_TPTR_S     0
318
 
319
//*****************************************************************************
320
//
321
// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
322
//
323
//*****************************************************************************
324
#define ADC_SSMUX1_MUX3_M       0x00007000  // 4th Sample Input Select.
325
#define ADC_SSMUX1_MUX2_M       0x00000700  // 3rd Sample Input Select.
326
#define ADC_SSMUX1_MUX1_M       0x00000070  // 2nd Sample Input Select.
327
#define ADC_SSMUX1_MUX0_M       0x00000007  // 1st Sample Input Select.
328
#define ADC_SSMUX1_MUX3_S       12
329
#define ADC_SSMUX1_MUX2_S       8
330
#define ADC_SSMUX1_MUX1_S       4
331
#define ADC_SSMUX1_MUX0_S       0
332
 
333
//*****************************************************************************
334
//
335
// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
336
//
337
//*****************************************************************************
338
#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select.
339
#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable.
340
#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence.
341
#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select.
342
#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
343
#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable.
344
#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence.
345
#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select.
346
#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
347
#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable.
348
#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence.
349
#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select.
350
#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select.
351
#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable.
352
#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence.
353
#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select.
354
 
355
//*****************************************************************************
356
//
357
// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
358
//
359
//*****************************************************************************
360
#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data.
361
#define ADC_SSFIFO1_DATA_S      0
362
 
363
//*****************************************************************************
364
//
365
// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
366
//
367
//*****************************************************************************
368
#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full.
369
#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty.
370
#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer.
371
#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer.
372
#define ADC_SSFSTAT1_HPTR_S     4
373
#define ADC_SSFSTAT1_TPTR_S     0
374
 
375
//*****************************************************************************
376
//
377
// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
378
//
379
//*****************************************************************************
380
#define ADC_SSMUX2_MUX3_M       0x00007000  // 4th Sample Input Select.
381
#define ADC_SSMUX2_MUX2_M       0x00000700  // 3rd Sample Input Select.
382
#define ADC_SSMUX2_MUX1_M       0x00000070  // 2nd Sample Input Select.
383
#define ADC_SSMUX2_MUX0_M       0x00000007  // 1st Sample Input Select.
384
#define ADC_SSMUX2_MUX3_S       12
385
#define ADC_SSMUX2_MUX2_S       8
386
#define ADC_SSMUX2_MUX1_S       4
387
#define ADC_SSMUX2_MUX0_S       0
388
 
389
//*****************************************************************************
390
//
391
// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
392
//
393
//*****************************************************************************
394
#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select.
395
#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable.
396
#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence.
397
#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select.
398
#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
399
#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable.
400
#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence.
401
#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select.
402
#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
403
#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable.
404
#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence.
405
#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select.
406
#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select.
407
#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable.
408
#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence.
409
#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select.
410
 
411
//*****************************************************************************
412
//
413
// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
414
//
415
//*****************************************************************************
416
#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data.
417
#define ADC_SSFIFO2_DATA_S      0
418
 
419
//*****************************************************************************
420
//
421
// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
422
//
423
//*****************************************************************************
424
#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full.
425
#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty.
426
#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer.
427
#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer.
428
#define ADC_SSFSTAT2_HPTR_S     4
429
#define ADC_SSFSTAT2_TPTR_S     0
430
 
431
//*****************************************************************************
432
//
433
// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
434
//
435
//*****************************************************************************
436
#define ADC_SSMUX3_MUX0_M       0x00000007  // 1st Sample Input Select.
437
#define ADC_SSMUX3_MUX0_S       0
438
 
439
//*****************************************************************************
440
//
441
// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
442
//
443
//*****************************************************************************
444
#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select.
445
#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable.
446
#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence.
447
#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select.
448
 
449
//*****************************************************************************
450
//
451
// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
452
//
453
//*****************************************************************************
454
#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data.
455
#define ADC_SSFIFO3_DATA_S      0
456
 
457
//*****************************************************************************
458
//
459
// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
460
//
461
//*****************************************************************************
462
#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full.
463
#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty.
464
#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer.
465
#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer.
466
#define ADC_SSFSTAT3_HPTR_S     4
467
#define ADC_SSFSTAT3_TPTR_S     0
468
 
469
//*****************************************************************************
470
//
471
// The following definitions are deprecated.
472
//
473
//*****************************************************************************
474
#ifndef DEPRECATED
475
 
476
//*****************************************************************************
477
//
478
// The following are deprecated defines for the ADC sequence register offsets.
479
//
480
//*****************************************************************************
481
#define ADC_O_SEQ               0x00000040  // Offset to the first sequence
482
#define ADC_O_SEQ_STEP          0x00000020  // Increment to the next sequence
483
#define ADC_O_X_SSFSTAT         0x0000000C  // FIFO status register
484
#define ADC_O_X_SSFIFO          0x00000008  // Result FIFO register
485
#define ADC_O_X_SSCTL           0x00000004  // Sample sequence control register
486
#define ADC_O_X_SSMUX           0x00000000  // Multiplexer select register
487
 
488
//*****************************************************************************
489
//
490
// The following are deprecated defines for the bit fields in the ADC_EMUX
491
// register.
492
//
493
//*****************************************************************************
494
#define ADC_EMUX_EM3_MASK       0x0000F000  // Event mux 3 mask
495
#define ADC_EMUX_EM2_MASK       0x00000F00  // Event mux 2 mask
496
#define ADC_EMUX_EM1_MASK       0x000000F0  // Event mux 1 mask
497
#define ADC_EMUX_EM0_MASK       0x0000000F  // Event mux 0 mask
498
#define ADC_EMUX_EM3_SHIFT      12          // The shift for the fourth event
499
#define ADC_EMUX_EM2_SHIFT      8           // The shift for the third event
500
#define ADC_EMUX_EM1_SHIFT      4           // The shift for the second event
501
#define ADC_EMUX_EM0_SHIFT      0           // The shift for the first event
502
 
503
//*****************************************************************************
504
//
505
// The following are deprecated defines for the bit fields in the ADC_SSPRI
506
// register.
507
//
508
//*****************************************************************************
509
#define ADC_SSPRI_SS3_MASK      0x00003000  // Sequencer 3 priority mask
510
#define ADC_SSPRI_SS2_MASK      0x00000300  // Sequencer 2 priority mask
511
#define ADC_SSPRI_SS1_MASK      0x00000030  // Sequencer 1 priority mask
512
#define ADC_SSPRI_SS0_MASK      0x00000003  // Sequencer 0 priority mask
513
 
514
//*****************************************************************************
515
//
516
// The following are deprecated defines for the bit fields in the ADC_SSMUX0,
517
// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present
518
// in all registers.
519
//
520
//*****************************************************************************
521
#define ADC_SSMUX_MUX7_MASK     0x70000000  // 8th mux select mask
522
#define ADC_SSMUX_MUX6_MASK     0x07000000  // 7th mux select mask
523
#define ADC_SSMUX_MUX5_MASK     0x00700000  // 6th mux select mask
524
#define ADC_SSMUX_MUX4_MASK     0x00070000  // 5th mux select mask
525
#define ADC_SSMUX_MUX3_MASK     0x00007000  // 4th mux select mask
526
#define ADC_SSMUX_MUX2_MASK     0x00000700  // 3rd mux select mask
527
#define ADC_SSMUX_MUX1_MASK     0x00000070  // 2nd mux select mask
528
#define ADC_SSMUX_MUX0_MASK     0x00000007  // 1st mux select mask
529
#define ADC_SSMUX_MUX7_SHIFT    28
530
#define ADC_SSMUX_MUX6_SHIFT    24
531
#define ADC_SSMUX_MUX5_SHIFT    20
532
#define ADC_SSMUX_MUX4_SHIFT    16
533
#define ADC_SSMUX_MUX3_SHIFT    12
534
#define ADC_SSMUX_MUX2_SHIFT    8
535
#define ADC_SSMUX_MUX1_SHIFT    4
536
#define ADC_SSMUX_MUX0_SHIFT    0
537
 
538
//*****************************************************************************
539
//
540
// The following are deprecated defines for the bit fields in the ADC_SSCTL0,
541
// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present
542
// in all registers.
543
//
544
//*****************************************************************************
545
#define ADC_SSCTL_TS7           0x80000000  // 8th temperature sensor select
546
#define ADC_SSCTL_IE7           0x40000000  // 8th interrupt enable
547
#define ADC_SSCTL_END7          0x20000000  // 8th sequence end select
548
#define ADC_SSCTL_D7            0x10000000  // 8th differential select
549
#define ADC_SSCTL_TS6           0x08000000  // 7th temperature sensor select
550
#define ADC_SSCTL_IE6           0x04000000  // 7th interrupt enable
551
#define ADC_SSCTL_END6          0x02000000  // 7th sequence end select
552
#define ADC_SSCTL_D6            0x01000000  // 7th differential select
553
#define ADC_SSCTL_TS5           0x00800000  // 6th temperature sensor select
554
#define ADC_SSCTL_IE5           0x00400000  // 6th interrupt enable
555
#define ADC_SSCTL_END5          0x00200000  // 6th sequence end select
556
#define ADC_SSCTL_D5            0x00100000  // 6th differential select
557
#define ADC_SSCTL_TS4           0x00080000  // 5th temperature sensor select
558
#define ADC_SSCTL_IE4           0x00040000  // 5th interrupt enable
559
#define ADC_SSCTL_END4          0x00020000  // 5th sequence end select
560
#define ADC_SSCTL_D4            0x00010000  // 5th differential select
561
#define ADC_SSCTL_TS3           0x00008000  // 4th temperature sensor select
562
#define ADC_SSCTL_IE3           0x00004000  // 4th interrupt enable
563
#define ADC_SSCTL_END3          0x00002000  // 4th sequence end select
564
#define ADC_SSCTL_D3            0x00001000  // 4th differential select
565
#define ADC_SSCTL_TS2           0x00000800  // 3rd temperature sensor select
566
#define ADC_SSCTL_IE2           0x00000400  // 3rd interrupt enable
567
#define ADC_SSCTL_END2          0x00000200  // 3rd sequence end select
568
#define ADC_SSCTL_D2            0x00000100  // 3rd differential select
569
#define ADC_SSCTL_TS1           0x00000080  // 2nd temperature sensor select
570
#define ADC_SSCTL_IE1           0x00000040  // 2nd interrupt enable
571
#define ADC_SSCTL_END1          0x00000020  // 2nd sequence end select
572
#define ADC_SSCTL_D1            0x00000010  // 2nd differential select
573
#define ADC_SSCTL_TS0           0x00000008  // 1st temperature sensor select
574
#define ADC_SSCTL_IE0           0x00000004  // 1st interrupt enable
575
#define ADC_SSCTL_END0          0x00000002  // 1st sequence end select
576
#define ADC_SSCTL_D0            0x00000001  // 1st differential select
577
 
578
//*****************************************************************************
579
//
580
// The following are deprecated defines for the bit fields in the ADC_SSFIFO0,
581
// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers.
582
//
583
//*****************************************************************************
584
#define ADC_SSFIFO_DATA_MASK    0x000003FF  // Sample data
585
#define ADC_SSFIFO_DATA_SHIFT   0
586
 
587
//*****************************************************************************
588
//
589
// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0,
590
// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
591
//
592
//*****************************************************************************
593
#define ADC_SSFSTAT_FULL        0x00001000  // FIFO is full
594
#define ADC_SSFSTAT_EMPTY       0x00000100  // FIFO is empty
595
#define ADC_SSFSTAT_HPTR        0x000000F0  // FIFO head pointer
596
#define ADC_SSFSTAT_TPTR        0x0000000F  // FIFO tail pointer
597
 
598
//*****************************************************************************
599
//
600
// The following are deprecated defines for the bit fields in the loopback ADC
601
// data.
602
//
603
//*****************************************************************************
604
#define ADC_LB_CNT_MASK         0x000003C0  // Sample counter mask
605
#define ADC_LB_CONT             0x00000020  // Continuation sample
606
#define ADC_LB_DIFF             0x00000010  // Differential sample
607
#define ADC_LB_TS               0x00000008  // Temperature sensor sample
608
#define ADC_LB_MUX_MASK         0x00000007  // Input channel number mask
609
#define ADC_LB_CNT_SHIFT        6           // Sample counter shift
610
#define ADC_LB_MUX_SHIFT        0           // Input channel number shift
611
 
612
#endif
613
 
614
#endif // __HW_ADC_H__

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