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//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
// 
// Software License Agreement
// 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
// 
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws.  All rights are reserved.  You may not combine
// this software with "viral" open-source software in order to form a larger
// program.  Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
// 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
// 
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
 
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
 
//*****************************************************************************
//
// The following are defines for the offsets between the I2C master and slave
// registers.
//
//*****************************************************************************
#define I2C_O_MSA               0x00000000  // I2C Master Slave Address
#define I2C_O_SOAR              0x00000000  // I2C Slave Own Address
#define I2C_O_SCSR              0x00000004  // I2C Slave Control/Status
#define I2C_O_MCS               0x00000004  // I2C Master Control/Status
#define I2C_O_SDR               0x00000008  // I2C Slave Data
#define I2C_O_MDR               0x00000008  // I2C Master Data
#define I2C_O_MTPR              0x0000000C  // I2C Master Timer Period
#define I2C_O_SIMR              0x0000000C  // I2C Slave Interrupt Mask
#define I2C_O_SRIS              0x00000010  // I2C Slave Raw Interrupt Status
#define I2C_O_MIMR              0x00000010  // I2C Master Interrupt Mask
#define I2C_O_MRIS              0x00000014  // I2C Master Raw Interrupt Status
#define I2C_O_SMIS              0x00000014  // I2C Slave Masked Interrupt
                                            // Status
#define I2C_O_SICR              0x00000018  // I2C Slave Interrupt Clear
#define I2C_O_MMIS              0x00000018  // I2C Master Masked Interrupt
                                            // Status
#define I2C_O_MICR              0x0000001C  // I2C Master Interrupt Clear
#define I2C_O_MCR               0x00000020  // I2C Master Configuration
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MSA register.
//
//*****************************************************************************
#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address.
#define I2C_MSA_RS              0x00000001  // Receive not Send
#define I2C_MSA_SA_S            1
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR register.
//
//*****************************************************************************
#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address.
#define I2C_SOAR_OAR_S          0
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SCSR register.
//
//*****************************************************************************
#define I2C_SCSR_FBR            0x00000004  // First Byte Received.
#define I2C_SCSR_TREQ           0x00000002  // Transmit Request.
#define I2C_SCSR_DA             0x00000001  // Device Active.
#define I2C_SCSR_RREQ           0x00000001  // Receive Request.
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//*****************************************************************************
#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy.
#define I2C_MCS_IDLE            0x00000020  // I2C Idle.
#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost.
#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable.
#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data.
#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address.
#define I2C_MCS_STOP            0x00000004  // Generate STOP.
#define I2C_MCS_START           0x00000002  // Generate START.
#define I2C_MCS_ERROR           0x00000002  // Error.
#define I2C_MCS_RUN             0x00000001  // I2C Master Enable.
#define I2C_MCS_BUSY            0x00000001  // I2C Busy.
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SDR register.
//
//*****************************************************************************
#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer.
#define I2C_SDR_DATA_S          0
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MDR register.
//
//*****************************************************************************
#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred.
#define I2C_MDR_DATA_S          0
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MTPR register.
//
//*****************************************************************************
#define I2C_MTPR_TPR_M          0x000000FF  // SCL Clock Period.
#define I2C_MTPR_TPR_S          0
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SIMR register.
//
//*****************************************************************************
#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask.
#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask.
#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask.
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SRIS register.
//
//*****************************************************************************
#define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
                                            // Status.
#define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
                                            // Status.
#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status.
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//*****************************************************************************
#define I2C_MIMR_IM             0x00000001  // Interrupt Mask.
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//*****************************************************************************
#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status.
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SMIS register.
//
//*****************************************************************************
#define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
                                            // Status.
#define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
                                            // Status.
#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status.
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SICR register.
//
//*****************************************************************************
#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear.
#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear.
#define I2C_SICR_DATAIC         0x00000001  // Data Clear Interrupt.
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//*****************************************************************************
#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status.
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//*****************************************************************************
#define I2C_MICR_IC             0x00000001  // Interrupt Clear.
 
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
//
//*****************************************************************************
#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable.
#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable.
#define I2C_MCR_LPBK            0x00000001  // I2C Loopback.
 
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
 
//*****************************************************************************
//
// The following are deprecated defines for the offsets between the I2C master
// and slave registers.
//
//*****************************************************************************
#define I2C_O_SLAVE             0x00000800  // Offset from master to slave
 
//*****************************************************************************
//
// The following are deprecated defines for the I2C master register offsets.
//
//*****************************************************************************
#define I2C_MASTER_O_SA         0x00000000  // Slave address register
#define I2C_MASTER_O_CS         0x00000004  // Control and Status register
#define I2C_MASTER_O_DR         0x00000008  // Data register
#define I2C_MASTER_O_TPR        0x0000000C  // Timer period register
#define I2C_MASTER_O_IMR        0x00000010  // Interrupt mask register
#define I2C_MASTER_O_RIS        0x00000014  // Raw interrupt status register
#define I2C_MASTER_O_MIS        0x00000018  // Masked interrupt status reg
#define I2C_MASTER_O_MICR       0x0000001C  // Interrupt clear register
#define I2C_MASTER_O_CR         0x00000020  // Configuration register
 
//*****************************************************************************
//
// The following are deprecated defines for the I2C slave register offsets.
//
//*****************************************************************************
#define I2C_SLAVE_O_SICR        0x00000018  // Interrupt clear register
#define I2C_SLAVE_O_MIS         0x00000014  // Masked interrupt status reg
#define I2C_SLAVE_O_RIS         0x00000010  // Raw interrupt status register
#define I2C_SLAVE_O_IM          0x0000000C  // Interrupt mask register
#define I2C_SLAVE_O_DR          0x00000008  // Data register
#define I2C_SLAVE_O_CSR         0x00000004  // Control/Status register
#define I2C_SLAVE_O_OAR         0x00000000  // Own address register
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C master
// slave address register.
//
//*****************************************************************************
#define I2C_MASTER_SA_SA_MASK   0x000000FE  // Slave address
#define I2C_MASTER_SA_RS        0x00000001  // Receive/send
#define I2C_MASTER_SA_SA_SHIFT  1
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Control and Status register.
//
//*****************************************************************************
#define I2C_MASTER_CS_BUS_BUSY  0x00000040  // Bus busy
#define I2C_MASTER_CS_IDLE      0x00000020  // Idle
#define I2C_MASTER_CS_ERR_MASK  0x0000001C
#define I2C_MASTER_CS_BUSY      0x00000001  // Controller is TX/RX data
#define I2C_MASTER_CS_ERROR     0x00000002  // Error occurred
#define I2C_MASTER_CS_ADDR_ACK  0x00000004  // Address byte not acknowledged
#define I2C_MASTER_CS_DATA_ACK  0x00000008  // Data byte not acknowledged
#define I2C_MASTER_CS_ARB_LOST  0x00000010  // Lost arbitration
#define I2C_MASTER_CS_ACK       0x00000008  // Acknowlegde
#define I2C_MASTER_CS_STOP      0x00000004  // Stop
#define I2C_MASTER_CS_START     0x00000002  // Start
#define I2C_MASTER_CS_RUN       0x00000001  // Run
 
//*****************************************************************************
//
// The following are deprecated defines for the values used in determining the
// contents of the I2C Master Timer Period register.
//
//*****************************************************************************
#define I2C_SCL_FAST            400000      // SCL fast frequency
#define I2C_SCL_STANDARD        100000      // SCL standard frequency
#define I2C_MASTER_TPR_SCL_LP   0x00000006  // SCL low period
#define I2C_MASTER_TPR_SCL_HP   0x00000004  // SCL high period
#define I2C_MASTER_TPR_SCL      (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Interrupt Mask register.
//
//*****************************************************************************
#define I2C_MASTER_IMR_IM       0x00000001  // Master interrupt mask
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Raw Interrupt Status register.
//
//*****************************************************************************
#define I2C_MASTER_RIS_RIS      0x00000001  // Master raw interrupt status
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Masked Interrupt Status register.
//
//*****************************************************************************
#define I2C_MASTER_MIS_MIS      0x00000001  // Master masked interrupt status
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Interrupt Clear register.
//
//*****************************************************************************
#define I2C_MASTER_MICR_IC      0x00000001  // Master interrupt clear
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Configuration register.
//
//*****************************************************************************
#define I2C_MASTER_CR_SFE       0x00000020  // Slave function enable
#define I2C_MASTER_CR_MFE       0x00000010  // Master function enable
#define I2C_MASTER_CR_LPBK      0x00000001  // Loopback enable
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave Own
// Address register.
//
//*****************************************************************************
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F  // Slave address
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Control/Status register.
//
//*****************************************************************************
#define I2C_SLAVE_CSR_FBR       0x00000004  // First byte received from master
#define I2C_SLAVE_CSR_TREQ      0x00000002  // Transmit request received
#define I2C_SLAVE_CSR_DA        0x00000001  // Enable the device
#define I2C_SLAVE_CSR_RREQ      0x00000001  // Receive data from I2C master
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Interrupt Mask register.
//
//*****************************************************************************
#define I2C_SLAVE_IMR_IM        0x00000001  // Slave interrupt mask
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave Raw
// Interrupt Status register.
//
//*****************************************************************************
#define I2C_SLAVE_RIS_RIS       0x00000001  // Slave raw interrupt status
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Masked Interrupt Status register.
//
//*****************************************************************************
#define I2C_SLAVE_MIS_MIS       0x00000001  // Slave masked interrupt status
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Interrupt Clear register.
//
//*****************************************************************************
#define I2C_SLAVE_SICR_IC       0x00000001  // Slave interrupt clear
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SIMR
// register.
//
//*****************************************************************************
#define I2C_SIMR_IM             0x00000001  // Interrupt Mask.
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SRIS
// register.
//
//*****************************************************************************
#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status.
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SMIS
// register.
//
//*****************************************************************************
#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status.
 
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SICR
// register.
//
//*****************************************************************************
#define I2C_SICR_IC             0x00000001  // Clear Interrupt.
 
#endif
 
#endif // __HW_I2C_H__

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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [LuminaryMicro/] [hw_i2c.h] - Blame information for rev 867

Line No.	Rev	Author	Line
1	610	jeremybenn	`//*****************************************************************************`
2			`//`
3			`// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.`
4			`//`
5			`// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.`
6			`//`
7			`// Software License Agreement`
8			`//`
9			`// Luminary Micro, Inc. (LMI) is supplying this software for use solely and`
10			`// exclusively on LMI's microcontroller products.`
11			`//`
12			`// The software is owned by LMI and/or its suppliers, and is protected under`
13			`// applicable copyright laws. All rights are reserved. You may not combine`
14			`// this software with "viral" open-source software in order to form a larger`
15			`// program. Any use in violation of the foregoing restrictions may subject`
16			`// the user to criminal sanctions under applicable laws, as well as to civil`
17			`// liability for the breach of the terms and conditions of this license.`
18			`//`
19			`// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED`
20			`// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF`
21			`// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.`
22			`// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR`
23			`// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.`
24			`//`
25			`// This is part of revision 2523 of the Stellaris Peripheral Driver Library.`
26			`//`
27			`//*****************************************************************************`
28
29			`#ifndef __HW_I2C_H__`
30			`#define __HW_I2C_H__`
31
32			`//*****************************************************************************`
33			`//`
34			`// The following are defines for the offsets between the I2C master and slave`
35			`// registers.`
36			`//`
37			`//*****************************************************************************`
38			`#define I2C_O_MSA 0x00000000 // I2C Master Slave Address`
39			`#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address`
40			`#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status`
41			`#define I2C_O_MCS 0x00000004 // I2C Master Control/Status`
42			`#define I2C_O_SDR 0x00000008 // I2C Slave Data`
43			`#define I2C_O_MDR 0x00000008 // I2C Master Data`
44			`#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period`
45			`#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask`
46			`#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status`
47			`#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask`
48			`#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status`
49			`#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt`
50			`// Status`
51			`#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear`
52			`#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt`
53			`// Status`
54			`#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear`
55			`#define I2C_O_MCR 0x00000020 // I2C Master Configuration`
56
57			`//*****************************************************************************`
58			`//`
59			`// The following are defines for the bit fields in the I2C_O_MSA register.`
60			`//`
61			`//*****************************************************************************`
62			`#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address.`
63			`#define I2C_MSA_RS 0x00000001 // Receive not Send`
64			`#define I2C_MSA_SA_S 1`
65
66			`//*****************************************************************************`
67			`//`
68			`// The following are defines for the bit fields in the I2C_O_SOAR register.`
69			`//`
70			`//*****************************************************************************`
71			`#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address.`
72			`#define I2C_SOAR_OAR_S 0`
73
74			`//*****************************************************************************`
75			`//`
76			`// The following are defines for the bit fields in the I2C_O_SCSR register.`
77			`//`
78			`//*****************************************************************************`
79			`#define I2C_SCSR_FBR 0x00000004 // First Byte Received.`
80			`#define I2C_SCSR_TREQ 0x00000002 // Transmit Request.`
81			`#define I2C_SCSR_DA 0x00000001 // Device Active.`
82			`#define I2C_SCSR_RREQ 0x00000001 // Receive Request.`
83
84			`//*****************************************************************************`
85			`//`
86			`// The following are defines for the bit fields in the I2C_O_MCS register.`
87			`//`
88			`//*****************************************************************************`
89			`#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy.`
90			`#define I2C_MCS_IDLE 0x00000020 // I2C Idle.`
91			`#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost.`
92			`#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable.`
93			`#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data.`
94			`#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address.`
95			`#define I2C_MCS_STOP 0x00000004 // Generate STOP.`
96			`#define I2C_MCS_START 0x00000002 // Generate START.`
97			`#define I2C_MCS_ERROR 0x00000002 // Error.`
98			`#define I2C_MCS_RUN 0x00000001 // I2C Master Enable.`
99			`#define I2C_MCS_BUSY 0x00000001 // I2C Busy.`
100
101			`//*****************************************************************************`
102			`//`
103			`// The following are defines for the bit fields in the I2C_O_SDR register.`
104			`//`
105			`//*****************************************************************************`
106			`#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer.`
107			`#define I2C_SDR_DATA_S 0`
108
109			`//*****************************************************************************`
110			`//`
111			`// The following are defines for the bit fields in the I2C_O_MDR register.`
112			`//`
113			`//*****************************************************************************`
114			`#define I2C_MDR_DATA_M 0x000000FF // Data Transferred.`
115			`#define I2C_MDR_DATA_S 0`
116
117			`//*****************************************************************************`
118			`//`
119			`// The following are defines for the bit fields in the I2C_O_MTPR register.`
120			`//`
121			`//*****************************************************************************`
122			`#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period.`
123			`#define I2C_MTPR_TPR_S 0`
124
125			`//*****************************************************************************`
126			`//`
127			`// The following are defines for the bit fields in the I2C_O_SIMR register.`
128			`//`
129			`//*****************************************************************************`
130			`#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask.`
131			`#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask.`
132			`#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask.`
133
134			`//*****************************************************************************`
135			`//`
136			`// The following are defines for the bit fields in the I2C_O_SRIS register.`
137			`//`
138			`//*****************************************************************************`
139			`#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt`
140			`// Status.`
141			`#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt`
142			`// Status.`
143			`#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status.`
144
145			`//*****************************************************************************`
146			`//`
147			`// The following are defines for the bit fields in the I2C_O_MIMR register.`
148			`//`
149			`//*****************************************************************************`
150			`#define I2C_MIMR_IM 0x00000001 // Interrupt Mask.`
151
152			`//*****************************************************************************`
153			`//`
154			`// The following are defines for the bit fields in the I2C_O_MRIS register.`
155			`//`
156			`//*****************************************************************************`
157			`#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status.`
158
159			`//*****************************************************************************`
160			`//`
161			`// The following are defines for the bit fields in the I2C_O_SMIS register.`
162			`//`
163			`//*****************************************************************************`
164			`#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt`
165			`// Status.`
166			`#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt`
167			`// Status.`
168			`#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status.`
169
170			`//*****************************************************************************`
171			`//`
172			`// The following are defines for the bit fields in the I2C_O_SICR register.`
173			`//`
174			`//*****************************************************************************`
175			`#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear.`
176			`#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear.`
177			`#define I2C_SICR_DATAIC 0x00000001 // Data Clear Interrupt.`
178
179			`//*****************************************************************************`
180			`//`
181			`// The following are defines for the bit fields in the I2C_O_MMIS register.`
182			`//`
183			`//*****************************************************************************`
184			`#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status.`
185
186			`//*****************************************************************************`
187			`//`
188			`// The following are defines for the bit fields in the I2C_O_MICR register.`
189			`//`
190			`//*****************************************************************************`
191			`#define I2C_MICR_IC 0x00000001 // Interrupt Clear.`
192
193			`//*****************************************************************************`
194			`//`
195			`// The following are defines for the bit fields in the I2C_O_MCR register.`
196			`//`
197			`//*****************************************************************************`
198			`#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable.`
199			`#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable.`
200			`#define I2C_MCR_LPBK 0x00000001 // I2C Loopback.`
201
202			`//*****************************************************************************`
203			`//`
204			`// The following definitions are deprecated.`
205			`//`
206			`//*****************************************************************************`
207			`#ifndef DEPRECATED`
208
209			`//*****************************************************************************`
210			`//`
211			`// The following are deprecated defines for the offsets between the I2C master`
212			`// and slave registers.`
213			`//`
214			`//*****************************************************************************`
215			`#define I2C_O_SLAVE 0x00000800 // Offset from master to slave`
216
217			`//*****************************************************************************`
218			`//`
219			`// The following are deprecated defines for the I2C master register offsets.`
220			`//`
221			`//*****************************************************************************`
222			`#define I2C_MASTER_O_SA 0x00000000 // Slave address register`
223			`#define I2C_MASTER_O_CS 0x00000004 // Control and Status register`
224			`#define I2C_MASTER_O_DR 0x00000008 // Data register`
225			`#define I2C_MASTER_O_TPR 0x0000000C // Timer period register`
226			`#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register`
227			`#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register`
228			`#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg`
229			`#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register`
230			`#define I2C_MASTER_O_CR 0x00000020 // Configuration register`
231
232			`//*****************************************************************************`
233			`//`
234			`// The following are deprecated defines for the I2C slave register offsets.`
235			`//`
236			`//*****************************************************************************`
237			`#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register`
238			`#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg`
239			`#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register`
240			`#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register`
241			`#define I2C_SLAVE_O_DR 0x00000008 // Data register`
242			`#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register`
243			`#define I2C_SLAVE_O_OAR 0x00000000 // Own address register`
244
245			`//*****************************************************************************`
246			`//`
247			`// The following are deprecated defines for the bit fields in the I2C master`
248			`// slave address register.`
249			`//`
250			`//*****************************************************************************`
251			`#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address`
252			`#define I2C_MASTER_SA_RS 0x00000001 // Receive/send`
253			`#define I2C_MASTER_SA_SA_SHIFT 1`
254
255			`//*****************************************************************************`
256			`//`
257			`// The following are deprecated defines for the bit fields in the I2C Master`
258			`// Control and Status register.`
259			`//`
260			`//*****************************************************************************`
261			`#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy`
262			`#define I2C_MASTER_CS_IDLE 0x00000020 // Idle`
263			`#define I2C_MASTER_CS_ERR_MASK 0x0000001C`
264			`#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data`
265			`#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred`
266			`#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged`
267			`#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged`
268			`#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration`
269			`#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde`
270			`#define I2C_MASTER_CS_STOP 0x00000004 // Stop`
271			`#define I2C_MASTER_CS_START 0x00000002 // Start`
272			`#define I2C_MASTER_CS_RUN 0x00000001 // Run`
273
274			`//*****************************************************************************`
275			`//`
276			`// The following are deprecated defines for the values used in determining the`
277			`// contents of the I2C Master Timer Period register.`
278			`//`
279			`//*****************************************************************************`
280			`#define I2C_SCL_FAST 400000 // SCL fast frequency`
281			`#define I2C_SCL_STANDARD 100000 // SCL standard frequency`
282			`#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period`
283			`#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period`
284			`#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)`
285
286			`//*****************************************************************************`
287			`//`
288			`// The following are deprecated defines for the bit fields in the I2C Master`
289			`// Interrupt Mask register.`
290			`//`
291			`//*****************************************************************************`
292			`#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask`
293
294			`//*****************************************************************************`
295			`//`
296			`// The following are deprecated defines for the bit fields in the I2C Master`
297			`// Raw Interrupt Status register.`
298			`//`
299			`//*****************************************************************************`
300			`#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status`
301
302			`//*****************************************************************************`
303			`//`
304			`// The following are deprecated defines for the bit fields in the I2C Master`
305			`// Masked Interrupt Status register.`
306			`//`
307			`//*****************************************************************************`
308			`#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status`
309
310			`//*****************************************************************************`
311			`//`
312			`// The following are deprecated defines for the bit fields in the I2C Master`
313			`// Interrupt Clear register.`
314			`//`
315			`//*****************************************************************************`
316			`#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear`
317
318			`//*****************************************************************************`
319			`//`
320			`// The following are deprecated defines for the bit fields in the I2C Master`
321			`// Configuration register.`
322			`//`
323			`//*****************************************************************************`
324			`#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable`
325			`#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable`
326			`#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable`
327
328			`//*****************************************************************************`
329			`//`
330			`// The following are deprecated defines for the bit fields in the I2C Slave Own`
331			`// Address register.`
332			`//`
333			`//*****************************************************************************`
334			`#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address`
335
336			`//*****************************************************************************`
337			`//`
338			`// The following are deprecated defines for the bit fields in the I2C Slave`
339			`// Control/Status register.`
340			`//`
341			`//*****************************************************************************`
342			`#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master`
343			`#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received`
344			`#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device`
345			`#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master`
346
347			`//*****************************************************************************`
348			`//`
349			`// The following are deprecated defines for the bit fields in the I2C Slave`
350			`// Interrupt Mask register.`
351			`//`
352			`//*****************************************************************************`
353			`#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask`
354
355			`//*****************************************************************************`
356			`//`
357			`// The following are deprecated defines for the bit fields in the I2C Slave Raw`
358			`// Interrupt Status register.`
359			`//`
360			`//*****************************************************************************`
361			`#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status`
362
363			`//*****************************************************************************`
364			`//`
365			`// The following are deprecated defines for the bit fields in the I2C Slave`
366			`// Masked Interrupt Status register.`
367			`//`
368			`//*****************************************************************************`
369			`#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status`
370
371			`//*****************************************************************************`
372			`//`
373			`// The following are deprecated defines for the bit fields in the I2C Slave`
374			`// Interrupt Clear register.`
375			`//`
376			`//*****************************************************************************`
377			`#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear`
378
379			`//*****************************************************************************`
380			`//`
381			`// The following are deprecated defines for the bit fields in the I2C_O_SIMR`
382			`// register.`
383			`//`
384			`//*****************************************************************************`
385			`#define I2C_SIMR_IM 0x00000001 // Interrupt Mask.`
386
387			`//*****************************************************************************`
388			`//`
389			`// The following are deprecated defines for the bit fields in the I2C_O_SRIS`
390			`// register.`
391			`//`
392			`//*****************************************************************************`
393			`#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status.`
394
395			`//*****************************************************************************`
396			`//`
397			`// The following are deprecated defines for the bit fields in the I2C_O_SMIS`
398			`// register.`
399			`//`
400			`//*****************************************************************************`
401			`#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status.`
402
403			`//*****************************************************************************`
404			`//`
405			`// The following are deprecated defines for the bit fields in the I2C_O_SICR`
406			`// register.`
407			`//`
408			`//*****************************************************************************`
409			`#define I2C_SICR_IC 0x00000001 // Clear Interrupt.`
410
411			`#endif`
412
413			`#endif // __HW_I2C_H__`