OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [LuminaryMicro/] [hw_ints.h] - Blame information for rev 610

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 610 jeremybenn
//*****************************************************************************
2
//
3
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
4
//
5
// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
6
// 
7
// Software License Agreement
8
// 
9
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10
// exclusively on LMI's microcontroller products.
11
// 
12
// The software is owned by LMI and/or its suppliers, and is protected under
13
// applicable copyright laws.  All rights are reserved.  You may not combine
14
// this software with "viral" open-source software in order to form a larger
15
// program.  Any use in violation of the foregoing restrictions may subject
16
// the user to criminal sanctions under applicable laws, as well as to civil
17
// liability for the breach of the terms and conditions of this license.
18
// 
19
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
20
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
21
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
22
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
23
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
24
// 
25
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
26
//
27
//*****************************************************************************
28
 
29
#ifndef __HW_INTS_H__
30
#define __HW_INTS_H__
31
 
32
//*****************************************************************************
33
//
34
// The following are defines for the fault assignments.
35
//
36
//*****************************************************************************
37
#define FAULT_NMI               2           // NMI fault
38
#define FAULT_HARD              3           // Hard fault
39
#define FAULT_MPU               4           // MPU fault
40
#define FAULT_BUS               5           // Bus fault
41
#define FAULT_USAGE             6           // Usage fault
42
#define FAULT_SVCALL            11          // SVCall
43
#define FAULT_DEBUG             12          // Debug monitor
44
#define FAULT_PENDSV            14          // PendSV
45
#define FAULT_SYSTICK           15          // System Tick
46
 
47
//*****************************************************************************
48
//
49
// The following are defines for the interrupt assignments.
50
//
51
//*****************************************************************************
52
#define INT_GPIOA               16          // GPIO Port A
53
#define INT_GPIOB               17          // GPIO Port B
54
#define INT_GPIOC               18          // GPIO Port C
55
#define INT_GPIOD               19          // GPIO Port D
56
#define INT_GPIOE               20          // GPIO Port E
57
#define INT_UART0               21          // UART0 Rx and Tx
58
#define INT_UART1               22          // UART1 Rx and Tx
59
#define INT_SSI0                23          // SSI0 Rx and Tx
60
#define INT_I2C0                24          // I2C0 Master and Slave
61
#define INT_PWM_FAULT           25          // PWM Fault
62
#define INT_PWM0                26          // PWM Generator 0
63
#define INT_PWM1                27          // PWM Generator 1
64
#define INT_PWM2                28          // PWM Generator 2
65
#define INT_QEI0                29          // Quadrature Encoder 0
66
#define INT_ADC0                30          // ADC Sequence 0
67
#define INT_ADC1                31          // ADC Sequence 1
68
#define INT_ADC2                32          // ADC Sequence 2
69
#define INT_ADC3                33          // ADC Sequence 3
70
#define INT_WATCHDOG            34          // Watchdog timer
71
#define INT_TIMER0A             35          // Timer 0 subtimer A
72
#define INT_TIMER0B             36          // Timer 0 subtimer B
73
#define INT_TIMER1A             37          // Timer 1 subtimer A
74
#define INT_TIMER1B             38          // Timer 1 subtimer B
75
#define INT_TIMER2A             39          // Timer 2 subtimer A
76
#define INT_TIMER2B             40          // Timer 2 subtimer B
77
#define INT_COMP0               41          // Analog Comparator 0
78
#define INT_COMP1               42          // Analog Comparator 1
79
#define INT_COMP2               43          // Analog Comparator 2
80
#define INT_SYSCTL              44          // System Control (PLL, OSC, BO)
81
#define INT_FLASH               45          // FLASH Control
82
#define INT_GPIOF               46          // GPIO Port F
83
#define INT_GPIOG               47          // GPIO Port G
84
#define INT_GPIOH               48          // GPIO Port H
85
#define INT_UART2               49          // UART2 Rx and Tx
86
#define INT_SSI1                50          // SSI1 Rx and Tx
87
#define INT_TIMER3A             51          // Timer 3 subtimer A
88
#define INT_TIMER3B             52          // Timer 3 subtimer B
89
#define INT_I2C1                53          // I2C1 Master and Slave
90
#define INT_QEI1                54          // Quadrature Encoder 1
91
#define INT_CAN0                55          // CAN0
92
#define INT_CAN1                56          // CAN1
93
#define INT_CAN2                57          // CAN2
94
#define INT_ETH                 58          // Ethernet
95
#define INT_HIBERNATE           59          // Hibernation module
96
#define INT_USB0                60          // USB 0 Controller
97
#define INT_PWM3                61          // PWM Generator 3
98
#define INT_UDMA                62          // uDMA controller
99
#define INT_UDMAERR             63          // uDMA Error
100
 
101
//*****************************************************************************
102
//
103
// The following are defines for the total number of interrupts.
104
//
105
//*****************************************************************************
106
#define NUM_INTERRUPTS          64
107
 
108
//*****************************************************************************
109
//
110
// The following are defines for the total number of priority levels.
111
//
112
//*****************************************************************************
113
#define NUM_PRIORITY            8
114
#define NUM_PRIORITY_BITS       3
115
 
116
//*****************************************************************************
117
//
118
// The following definitions are deprecated.
119
//
120
//*****************************************************************************
121
#ifndef DEPRECATED
122
 
123
//*****************************************************************************
124
//
125
// The following are deprecated defines for the interrupt assignments.
126
//
127
//*****************************************************************************
128
#define INT_SSI                 23          // SSI Rx and Tx
129
#define INT_I2C                 24          // I2C Master and Slave
130
#define INT_QEI                 29          // Quadrature Encoder
131
 
132
#endif
133
 
134
#endif // __HW_INTS_H__

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.