OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [LuminaryMicro/] [hw_udma.h] - Blame information for rev 610

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 610 jeremybenn
//*****************************************************************************
2
//
3
// hw_udma.h - Macros for use in accessing the UDMA registers.
4
//
5
// Copyright (c) 2007-2008 Luminary Micro, Inc.  All rights reserved.
6
// 
7
// Software License Agreement
8
// 
9
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10
// exclusively on LMI's microcontroller products.
11
// 
12
// The software is owned by LMI and/or its suppliers, and is protected under
13
// applicable copyright laws.  All rights are reserved.  You may not combine
14
// this software with "viral" open-source software in order to form a larger
15
// program.  Any use in violation of the foregoing restrictions may subject
16
// the user to criminal sanctions under applicable laws, as well as to civil
17
// liability for the breach of the terms and conditions of this license.
18
// 
19
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
20
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
21
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
22
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
23
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
24
// 
25
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
26
//
27
//*****************************************************************************
28
 
29
#ifndef __HW_UDMA_H__
30
#define __HW_UDMA_H__
31
 
32
//*****************************************************************************
33
//
34
// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
35
//
36
//*****************************************************************************
37
#define UDMA_STAT               0x400FF000  // DMA Status
38
#define UDMA_CFG                0x400FF004  // DMA Configuration
39
#define UDMA_CTLBASE            0x400FF008  // DMA Channel Control Base Pointer
40
#define UDMA_ALTBASE            0x400FF00C  // DMA Alternate Channel Control
41
                                            // Base Pointer
42
#define UDMA_WAITSTAT           0x400FF010  // DMA Channel Wait on Request
43
                                            // Status
44
#define UDMA_SWREQ              0x400FF014  // DMA Channel Software Request
45
#define UDMA_USEBURSTSET        0x400FF018  // DMA Channel Useburst Set
46
#define UDMA_USEBURSTCLR        0x400FF01C  // DMA Channel Useburst Clear
47
#define UDMA_REQMASKSET         0x400FF020  // DMA Channel Request Mask Set
48
#define UDMA_REQMASKCLR         0x400FF024  // DMA Channel Request Mask Clear
49
#define UDMA_ENASET             0x400FF028  // DMA Channel Enable Set
50
#define UDMA_ENACLR             0x400FF02C  // DMA Channel Enable Clear
51
#define UDMA_ALTSET             0x400FF030  // DMA Channel Primary Alternate
52
                                            // Set
53
#define UDMA_ALTCLR             0x400FF034  // DMA Channel Primary Alternate
54
                                            // Clear
55
#define UDMA_PRIOSET            0x400FF038  // DMA Channel Priority Set
56
#define UDMA_PRIOCLR            0x400FF03C  // DMA Channel Priority Clear
57
#define UDMA_ERRCLR             0x400FF04C  // DMA Bus Error Clear
58
 
59
//*****************************************************************************
60
//
61
// Micro Direct Memory Access (uDMA) offsets.
62
//
63
//*****************************************************************************
64
#define UDMA_O_SRCENDP          0x00000000  // DMA Channel Source Address End
65
                                            // Pointer
66
#define UDMA_O_DSTENDP          0x00000004  // DMA Channel Destination Address
67
                                            // End Pointer
68
#define UDMA_O_CHCTL            0x00000008  // DMA Channel Control Word
69
 
70
//*****************************************************************************
71
//
72
// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
73
//
74
//*****************************************************************************
75
#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer.
76
#define UDMA_SRCENDP_ADDR_S     0
77
 
78
//*****************************************************************************
79
//
80
// The following are defines for the bit fields in the UDMA_STAT register.
81
//
82
//*****************************************************************************
83
#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available DMA Channels Minus 1.
84
#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine State.
85
#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
86
#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
87
#define UDMA_STAT_STATE_RD_SRCENDP \
88
                                0x00000020  // Reading source end pointer
89
#define UDMA_STAT_STATE_RD_DSTENDP \
90
                                0x00000030  // Reading destination end pointer
91
#define UDMA_STAT_STATE_RD_SRCDAT \
92
                                0x00000040  // Reading source data
93
#define UDMA_STAT_STATE_WR_DSTDAT \
94
                                0x00000050  // Writing destination data
95
#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for DMA request to clear
96
#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
97
#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
98
#define UDMA_STAT_STATE_DONE    0x00000090  // Done
99
#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
100
#define UDMA_STAT_MASTEN        0x00000001  // Master Enable.
101
#define UDMA_STAT_DMACHANS_S    16
102
 
103
//*****************************************************************************
104
//
105
// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
106
//
107
//*****************************************************************************
108
#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer.
109
#define UDMA_DSTENDP_ADDR_S     0
110
 
111
//*****************************************************************************
112
//
113
// The following are defines for the bit fields in the UDMA_CFG register.
114
//
115
//*****************************************************************************
116
#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable.
117
 
118
//*****************************************************************************
119
//
120
// The following are defines for the bit fields in the UDMA_CTLBASE register.
121
//
122
//*****************************************************************************
123
#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address.
124
#define UDMA_CTLBASE_ADDR_S     10
125
 
126
//*****************************************************************************
127
//
128
// The following are defines for the bit fields in the UDMA_O_CHCTL register.
129
//
130
//*****************************************************************************
131
#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment.
132
#define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
133
#define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
134
#define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
135
#define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
136
#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size.
137
#define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
138
#define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
139
#define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
140
#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment.
141
#define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
142
#define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
143
#define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
144
#define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
145
#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size.
146
#define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
147
#define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
148
#define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
149
#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size.
150
#define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
151
#define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
152
#define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
153
#define UDMA_CHCTL_ARBSIZE_8    0x0000C000  // 8 Transfers
154
#define UDMA_CHCTL_ARBSIZE_16   0x00010000  // 16 Transfers
155
#define UDMA_CHCTL_ARBSIZE_32   0x00014000  // 32 Transfers
156
#define UDMA_CHCTL_ARBSIZE_64   0x00018000  // 64 Transfers
157
#define UDMA_CHCTL_ARBSIZE_128  0x0001C000  // 128 Transfers
158
#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
159
#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
160
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
161
#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1).
162
#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst.
163
#define UDMA_CHCTL_XFERMODE_M   0x00000007  // DMA Transfer Mode.
164
#define UDMA_CHCTL_XFERMODE_STOP \
165
                                0x00000000  // Stop
166
#define UDMA_CHCTL_XFERMODE_BASIC \
167
                                0x00000001  // Basic
168
#define UDMA_CHCTL_XFERMODE_AUTO \
169
                                0x00000002  // Auto-Request
170
#define UDMA_CHCTL_XFERMODE_PINGPONG \
171
                                0x00000003  // Ping-Pong
172
#define UDMA_CHCTL_XFERMODE_MEM_SG \
173
                                0x00000004  // Memory Scatter-Gather
174
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
175
                                0x00000005  // Alternate Memory Scatter-Gather
176
#define UDMA_CHCTL_XFERMODE_PER_SG \
177
                                0x00000006  // Peripheral Scatter-Gather
178
#define UDMA_CHCTL_XFERMODE_PER_SGA \
179
                                0x00000007  // Alternate Peripheral
180
                                            // Scatter-Gather
181
#define UDMA_CHCTL_XFERSIZE_S   4
182
 
183
//*****************************************************************************
184
//
185
// The following are defines for the bit fields in the UDMA_ALTBASE register.
186
//
187
//*****************************************************************************
188
#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
189
                                            // Pointer.
190
#define UDMA_ALTBASE_ADDR_S     0
191
 
192
//*****************************************************************************
193
//
194
// The following are defines for the bit fields in the UDMA_WAITSTAT register.
195
//
196
//*****************************************************************************
197
#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status.
198
#define UDMA_WAITSTAT_WAITREQ_S 0
199
 
200
//*****************************************************************************
201
//
202
// The following are defines for the bit fields in the UDMA_SWREQ register.
203
//
204
//*****************************************************************************
205
#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request.
206
#define UDMA_SWREQ_S            0
207
 
208
//*****************************************************************************
209
//
210
// The following are defines for the bit fields in the UDMA_USEBURSTSET
211
// register.
212
//
213
//*****************************************************************************
214
#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set.
215
#define UDMA_USEBURSTSET_SET__0 0x00000000  // No Effect
216
#define UDMA_USEBURSTSET_SET__1 0x00000001  // Burst Only
217
 
218
//*****************************************************************************
219
//
220
// The following are defines for the bit fields in the UDMA_USEBURSTCLR
221
// register.
222
//
223
//*****************************************************************************
224
#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear.
225
#define UDMA_USEBURSTCLR_CLR__0 0x00000000  // No Effect
226
#define UDMA_USEBURSTCLR_CLR__1 0x00000001  // Single and Burst
227
 
228
//*****************************************************************************
229
//
230
// The following are defines for the bit fields in the UDMA_REQMASKSET
231
// register.
232
//
233
//*****************************************************************************
234
#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set.
235
#define UDMA_REQMASKSET_SET__0  0x00000000  // No Effect
236
#define UDMA_REQMASKSET_SET__1  0x00000001  // Masked
237
 
238
//*****************************************************************************
239
//
240
// The following are defines for the bit fields in the UDMA_REQMASKCLR
241
// register.
242
//
243
//*****************************************************************************
244
#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear.
245
#define UDMA_REQMASKCLR_CLR__0  0x00000000  // No Effect
246
#define UDMA_REQMASKCLR_CLR__1  0x00000001  // Clear Mask
247
 
248
//*****************************************************************************
249
//
250
// The following are defines for the bit fields in the UDMA_ENASET register.
251
//
252
//*****************************************************************************
253
#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set.
254
#define UDMA_ENASET_SET__0      0x00000000  // Disabled
255
#define UDMA_ENASET_SET__1      0x00000001  // Enabled
256
#define UDMA_ENASET_CHENSET_M   0xFFFFFFFF  // Channel [n] Enable Set.
257
#define UDMA_ENASET_CHENSET__0  0x00000000  // No Effect
258
#define UDMA_ENASET_CHENSET__1  0x00000001  // Enable
259
 
260
//*****************************************************************************
261
//
262
// The following are defines for the bit fields in the UDMA_ENACLR register.
263
//
264
//*****************************************************************************
265
#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable.
266
#define UDMA_ENACLR_CLR__0      0x00000000  // No Effect
267
#define UDMA_ENACLR_CLR__1      0x00000001  // Disable
268
 
269
//*****************************************************************************
270
//
271
// The following are defines for the bit fields in the UDMA_ALTSET register.
272
//
273
//*****************************************************************************
274
#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set.
275
#define UDMA_ALTSET_SET__0      0x00000000  // No Effect
276
#define UDMA_ALTSET_SET__1      0x00000001  // Alternate
277
 
278
//*****************************************************************************
279
//
280
// The following are defines for the bit fields in the UDMA_ALTCLR register.
281
//
282
//*****************************************************************************
283
#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear.
284
#define UDMA_ALTCLR_CLR__0      0x00000000  // No Effect
285
#define UDMA_ALTCLR_CLR__1      0x00000001  // Primary
286
 
287
//*****************************************************************************
288
//
289
// The following are defines for the bit fields in the UDMA_PRIOSET register.
290
//
291
//*****************************************************************************
292
#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set.
293
#define UDMA_PRIOSET_SET__0     0x00000000  // No Effect
294
#define UDMA_PRIOSET_SET__1     0x00000001  // High Priority
295
 
296
//*****************************************************************************
297
//
298
// The following are defines for the bit fields in the UDMA_PRIOCLR register.
299
//
300
//*****************************************************************************
301
#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear.
302
#define UDMA_PRIOCLR_CLR__0     0x00000000  // No Effect
303
#define UDMA_PRIOCLR_CLR__1     0x00000001  // Default Priority
304
 
305
//*****************************************************************************
306
//
307
// The following are defines for the bit fields in the UDMA_ERRCLR register.
308
//
309
//*****************************************************************************
310
#define UDMA_ERRCLR_ERRCLR      0x00000001  // DMA Bus Error Status.
311
 
312
#endif // __HW_UDMA_H__

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.