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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [LuminaryMicro/] [sysctl.h] - Blame information for rev 610

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1 610 jeremybenn 
//*****************************************************************************
2 
//
3 
// sysctl.h - Prototypes for the system control driver.
4 
//
5 
// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
6 
//
7 
// Software License Agreement
8 
//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
11 
//
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// The software is owned by LMI and/or its suppliers, and is protected under
13 
// applicable copyright laws.  All rights are reserved.  You may not combine
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// this software with "viral" open-source software in order to form a larger
15 
// program.  Any use in violation of the foregoing restrictions may subject
16 
// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
21 
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
22 
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
23 
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
24 
//
25 
// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
26 
//
27 
//*****************************************************************************
28 
 
29 
#ifndef __SYSCTL_H__
30 
#define __SYSCTL_H__
31 
 
32 
//*****************************************************************************
33 
//
34 
// If building with a C++ compiler, make all of the definitions in this header
35 
// have a C binding.
36 
//
37 
//*****************************************************************************
38 
#ifdef __cplusplus
39 
extern "C"
40 
{
41 
#endif
42 
 
43 
//*****************************************************************************
44 
//
45 
// The following are values that can be passed to the
46 
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
47 
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
48 
// ulPeripheral parameter.  The peripherals in the fourth group (upper nibble
49 
// is 3) can only be used with the SysCtlPeripheralPresent() API.
50 
//
51 
//*****************************************************************************
52 
#define SYSCTL_PERIPH_WDOG      0x00000008  // Watchdog
53 
#define SYSCTL_PERIPH_HIBERNATE 0x00000040  // Hibernation module
54 
#define SYSCTL_PERIPH_ADC       0x00100001  // ADC
55 
#define SYSCTL_PERIPH_PWM       0x00100010  // PWM
56 
#define SYSCTL_PERIPH_CAN0      0x00100100  // CAN 0
57 
#define SYSCTL_PERIPH_CAN1      0x00100200  // CAN 1
58 
#define SYSCTL_PERIPH_CAN2      0x00100400  // CAN 2
59 
#define SYSCTL_PERIPH_UART0     0x10000001  // UART 0
60 
#define SYSCTL_PERIPH_UART1     0x10000002  // UART 1
61 
#define SYSCTL_PERIPH_UART2     0x10000004  // UART 2
62 
#ifndef DEPRECATED
63 
#define SYSCTL_PERIPH_SSI       0x10000010  // SSI
64 
#endif
65 
#define SYSCTL_PERIPH_SSI0      0x10000010  // SSI 0
66 
#define SYSCTL_PERIPH_SSI1      0x10000020  // SSI 1
67 
#ifndef DEPRECATED
68 
#define SYSCTL_PERIPH_QEI       0x10000100  // QEI
69 
#endif
70 
#define SYSCTL_PERIPH_QEI0      0x10000100  // QEI 0
71 
#define SYSCTL_PERIPH_QEI1      0x10000200  // QEI 1
72 
#ifndef DEPRECATED
73 
#define SYSCTL_PERIPH_I2C       0x10001000  // I2C
74 
#endif
75 
#define SYSCTL_PERIPH_I2C0      0x10001000  // I2C 0
76 
#define SYSCTL_PERIPH_I2C1      0x10004000  // I2C 1
77 
#define SYSCTL_PERIPH_TIMER0    0x10100001  // Timer 0
78 
#define SYSCTL_PERIPH_TIMER1    0x10100002  // Timer 1
79 
#define SYSCTL_PERIPH_TIMER2    0x10100004  // Timer 2
80 
#define SYSCTL_PERIPH_TIMER3    0x10100008  // Timer 3
81 
#define SYSCTL_PERIPH_COMP0     0x10100100  // Analog comparator 0
82 
#define SYSCTL_PERIPH_COMP1     0x10100200  // Analog comparator 1
83 
#define SYSCTL_PERIPH_COMP2     0x10100400  // Analog comparator 2
84 
#define SYSCTL_PERIPH_GPIOA     0x20000001  // GPIO A
85 
#define SYSCTL_PERIPH_GPIOB     0x20000002  // GPIO B
86 
#define SYSCTL_PERIPH_GPIOC     0x20000004  // GPIO C
87 
#define SYSCTL_PERIPH_GPIOD     0x20000008  // GPIO D
88 
#define SYSCTL_PERIPH_GPIOE     0x20000010  // GPIO E
89 
#define SYSCTL_PERIPH_GPIOF     0x20000020  // GPIO F
90 
#define SYSCTL_PERIPH_GPIOG     0x20000040  // GPIO G
91 
#define SYSCTL_PERIPH_GPIOH     0x20000080  // GPIO H
92 
#define SYSCTL_PERIPH_UDMA      0x20002000  // uDMA
93 
#define SYSCTL_PERIPH_USB0      0x20100001  // USB0
94 
#define SYSCTL_PERIPH_ETH       0x20105000  // ETH
95 
#define SYSCTL_PERIPH_IEEE1588  0x20100100  // IEEE1588
96 
#define SYSCTL_PERIPH_PLL       0x30000010  // PLL
97 
#define SYSCTL_PERIPH_TEMP      0x30000020  // Temperature sensor
98 
#define SYSCTL_PERIPH_MPU       0x30000080  // Cortex M3 MPU
99 
 
100 
//*****************************************************************************
101 
//
102 
// The following are values that can be passed to the SysCtlPinPresent() API
103 
// as the ulPin parameter.
104 
//
105 
//*****************************************************************************
106 
#define SYSCTL_PIN_PWM0         0x00000001  // PWM0 pin
107 
#define SYSCTL_PIN_PWM1         0x00000002  // PWM1 pin
108 
#define SYSCTL_PIN_PWM2         0x00000004  // PWM2 pin
109 
#define SYSCTL_PIN_PWM3         0x00000008  // PWM3 pin
110 
#define SYSCTL_PIN_PWM4         0x00000010  // PWM4 pin
111 
#define SYSCTL_PIN_PWM5         0x00000020  // PWM5 pin
112 
#define SYSCTL_PIN_PWM6         0x00000040  // PWM6 pin
113 
#define SYSCTL_PIN_PWM7         0x00000080  // PWM7 pin
114 
#define SYSCTL_PIN_C0MINUS      0x00000040  // C0- pin
115 
#define SYSCTL_PIN_C0PLUS       0x00000080  // C0+ pin
116 
#define SYSCTL_PIN_C0O          0x00000100  // C0o pin
117 
#define SYSCTL_PIN_C1MINUS      0x00000200  // C1- pin
118 
#define SYSCTL_PIN_C1PLUS       0x00000400  // C1+ pin
119 
#define SYSCTL_PIN_C1O          0x00000800  // C1o pin
120 
#define SYSCTL_PIN_C2MINUS      0x00001000  // C2- pin
121 
#define SYSCTL_PIN_C2PLUS       0x00002000  // C2+ pin
122 
#define SYSCTL_PIN_C2O          0x00004000  // C2o pin
123 
#define SYSCTL_PIN_MC_FAULT0    0x00008000  // MC0 Fault pin
124 
#define SYSCTL_PIN_ADC0         0x00010000  // ADC0 pin
125 
#define SYSCTL_PIN_ADC1         0x00020000  // ADC1 pin
126 
#define SYSCTL_PIN_ADC2         0x00040000  // ADC2 pin
127 
#define SYSCTL_PIN_ADC3         0x00080000  // ADC3 pin
128 
#define SYSCTL_PIN_ADC4         0x00100000  // ADC4 pin
129 
#define SYSCTL_PIN_ADC5         0x00200000  // ADC5 pin
130 
#define SYSCTL_PIN_ADC6         0x00400000  // ADC6 pin
131 
#define SYSCTL_PIN_ADC7         0x00800000  // ADC7 pin
132 
#define SYSCTL_PIN_CCP0         0x01000000  // CCP0 pin
133 
#define SYSCTL_PIN_CCP1         0x02000000  // CCP1 pin
134 
#define SYSCTL_PIN_CCP2         0x04000000  // CCP2 pin
135 
#define SYSCTL_PIN_CCP3         0x08000000  // CCP3 pin
136 
#define SYSCTL_PIN_CCP4         0x10000000  // CCP4 pin
137 
#define SYSCTL_PIN_CCP5         0x20000000  // CCP5 pin
138 
#define SYSCTL_PIN_32KHZ        0x80000000  // 32kHz pin
139 
 
140 
//*****************************************************************************
141 
//
142 
// The following are values that can be passed to the SysCtlLDOSet() API as
143 
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
144 
//
145 
//*****************************************************************************
146 
#define SYSCTL_LDO_2_25V        0x00000005  // LDO output of 2.25V
147 
#define SYSCTL_LDO_2_30V        0x00000004  // LDO output of 2.30V
148 
#define SYSCTL_LDO_2_35V        0x00000003  // LDO output of 2.35V
149 
#define SYSCTL_LDO_2_40V        0x00000002  // LDO output of 2.40V
150 
#define SYSCTL_LDO_2_45V        0x00000001  // LDO output of 2.45V
151 
#define SYSCTL_LDO_2_50V        0x00000000  // LDO output of 2.50V
152 
#define SYSCTL_LDO_2_55V        0x0000001f  // LDO output of 2.55V
153 
#define SYSCTL_LDO_2_60V        0x0000001e  // LDO output of 2.60V
154 
#define SYSCTL_LDO_2_65V        0x0000001d  // LDO output of 2.65V
155 
#define SYSCTL_LDO_2_70V        0x0000001c  // LDO output of 2.70V
156 
#define SYSCTL_LDO_2_75V        0x0000001b  // LDO output of 2.75V
157 
 
158 
//*****************************************************************************
159 
//
160 
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
161 
//
162 
//*****************************************************************************
163 
#define SYSCTL_LDOCFG_ARST      0x00000001  // Allow LDO failure to reset
164 
#define SYSCTL_LDOCFG_NORST     0x00000000  // Do not reset on LDO failure
165 
 
166 
//*****************************************************************************
167 
//
168 
// The following are values that can be passed to the SysCtlIntEnable(),
169 
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
170 
// by the SysCtlIntStatus() API.
171 
//
172 
//*****************************************************************************
173 
#define SYSCTL_INT_PLL_LOCK     0x00000040  // PLL lock interrupt
174 
#define SYSCTL_INT_CUR_LIMIT    0x00000020  // Current limit interrupt
175 
#define SYSCTL_INT_IOSC_FAIL    0x00000010  // Internal oscillator failure int
176 
#define SYSCTL_INT_MOSC_FAIL    0x00000008  // Main oscillator failure int
177 
#define SYSCTL_INT_POR          0x00000004  // Power on reset interrupt
178 
#define SYSCTL_INT_BOR          0x00000002  // Brown out interrupt
179 
#define SYSCTL_INT_PLL_FAIL     0x00000001  // PLL failure interrupt
180 
 
181 
//*****************************************************************************
182 
//
183 
// The following are values that can be passed to the SysCtlResetCauseClear()
184 
// API or returned by the SysCtlResetCauseGet() API.
185 
//
186 
//*****************************************************************************
187 
#define SYSCTL_CAUSE_LDO        0x00000020  // LDO power not OK reset
188 
#define SYSCTL_CAUSE_SW         0x00000010  // Software reset
189 
#define SYSCTL_CAUSE_WDOG       0x00000008  // Watchdog reset
190 
#define SYSCTL_CAUSE_BOR        0x00000004  // Brown-out reset
191 
#define SYSCTL_CAUSE_POR        0x00000002  // Power on reset
192 
#define SYSCTL_CAUSE_EXT        0x00000001  // External reset
193 
 
194 
//*****************************************************************************
195 
//
196 
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
197 
// API as the ulConfig parameter.
198 
//
199 
//*****************************************************************************
200 
#define SYSCTL_BOR_RESET        0x00000002  // Reset instead of interrupting
201 
#define SYSCTL_BOR_RESAMPLE     0x00000001  // Resample BOR before asserting
202 
 
203 
//*****************************************************************************
204 
//
205 
// The following are values that can be passed to the SysCtlPWMClockSet() API
206 
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
207 
// API.
208 
//
209 
//*****************************************************************************
210 
#define SYSCTL_PWMDIV_1         0x00000000  // PWM clock is processor clock /1
211 
#define SYSCTL_PWMDIV_2         0x00100000  // PWM clock is processor clock /2
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#define SYSCTL_PWMDIV_4         0x00120000  // PWM clock is processor clock /4
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#define SYSCTL_PWMDIV_8         0x00140000  // PWM clock is processor clock /8
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#define SYSCTL_PWMDIV_16        0x00160000  // PWM clock is processor clock /16
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#define SYSCTL_PWMDIV_32        0x00180000  // PWM clock is processor clock /32
216 
#define SYSCTL_PWMDIV_64        0x001A0000  // PWM clock is processor clock /64
217 
 
218 
//*****************************************************************************
219 
//
220 
// The following are values that can be passed to the SysCtlADCSpeedSet() API
221 
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
222 
// API.
223 
//
224 
//*****************************************************************************
225 
#define SYSCTL_ADCSPEED_1MSPS   0x00000300  // 1,000,000 samples per second
226 
#define SYSCTL_ADCSPEED_500KSPS 0x00000200  // 500,000 samples per second
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#define SYSCTL_ADCSPEED_250KSPS 0x00000100  // 250,000 samples per second
228 
#define SYSCTL_ADCSPEED_125KSPS 0x00000000  // 125,000 samples per second
229 
 
230 
//*****************************************************************************
231 
//
232 
// The following are values that can be passed to the SysCtlClockSet() API as
233 
// the ulConfig parameter.
234 
//
235 
//*****************************************************************************
236 
#define SYSCTL_SYSDIV_1         0x07800000  // Processor clock is osc/pll /1
237 
#define SYSCTL_SYSDIV_2         0x00C00000  // Processor clock is osc/pll /2
238 
#define SYSCTL_SYSDIV_3         0x01400000  // Processor clock is osc/pll /3
239 
#define SYSCTL_SYSDIV_4         0x01C00000  // Processor clock is osc/pll /4
240 
#define SYSCTL_SYSDIV_5         0x02400000  // Processor clock is osc/pll /5
241 
#define SYSCTL_SYSDIV_6         0x02C00000  // Processor clock is osc/pll /6
242 
#define SYSCTL_SYSDIV_7         0x03400000  // Processor clock is osc/pll /7
243 
#define SYSCTL_SYSDIV_8         0x03C00000  // Processor clock is osc/pll /8
244 
#define SYSCTL_SYSDIV_9         0x04400000  // Processor clock is osc/pll /9
245 
#define SYSCTL_SYSDIV_10        0x04C00000  // Processor clock is osc/pll /10
246 
#define SYSCTL_SYSDIV_11        0x05400000  // Processor clock is osc/pll /11
247 
#define SYSCTL_SYSDIV_12        0x05C00000  // Processor clock is osc/pll /12
248 
#define SYSCTL_SYSDIV_13        0x06400000  // Processor clock is osc/pll /13
249 
#define SYSCTL_SYSDIV_14        0x06C00000  // Processor clock is osc/pll /14
250 
#define SYSCTL_SYSDIV_15        0x07400000  // Processor clock is osc/pll /15
251 
#define SYSCTL_SYSDIV_16        0x07C00000  // Processor clock is osc/pll /16
252 
#define SYSCTL_SYSDIV_17        0x88400000  // Processor clock is osc/pll /17
253 
#define SYSCTL_SYSDIV_18        0x88C00000  // Processor clock is osc/pll /18
254 
#define SYSCTL_SYSDIV_19        0x89400000  // Processor clock is osc/pll /19
255 
#define SYSCTL_SYSDIV_20        0x89C00000  // Processor clock is osc/pll /20
256 
#define SYSCTL_SYSDIV_21        0x8A400000  // Processor clock is osc/pll /21
257 
#define SYSCTL_SYSDIV_22        0x8AC00000  // Processor clock is osc/pll /22
258 
#define SYSCTL_SYSDIV_23        0x8B400000  // Processor clock is osc/pll /23
259 
#define SYSCTL_SYSDIV_24        0x8BC00000  // Processor clock is osc/pll /24
260 
#define SYSCTL_SYSDIV_25        0x8C400000  // Processor clock is osc/pll /25
261 
#define SYSCTL_SYSDIV_26        0x8CC00000  // Processor clock is osc/pll /26
262 
#define SYSCTL_SYSDIV_27        0x8D400000  // Processor clock is osc/pll /27
263 
#define SYSCTL_SYSDIV_28        0x8DC00000  // Processor clock is osc/pll /28
264 
#define SYSCTL_SYSDIV_29        0x8E400000  // Processor clock is osc/pll /29
265 
#define SYSCTL_SYSDIV_30        0x8EC00000  // Processor clock is osc/pll /30
266 
#define SYSCTL_SYSDIV_31        0x8F400000  // Processor clock is osc/pll /31
267 
#define SYSCTL_SYSDIV_32        0x8FC00000  // Processor clock is osc/pll /32
268 
#define SYSCTL_SYSDIV_33        0x90400000  // Processor clock is osc/pll /33
269 
#define SYSCTL_SYSDIV_34        0x90C00000  // Processor clock is osc/pll /34
270 
#define SYSCTL_SYSDIV_35        0x91400000  // Processor clock is osc/pll /35
271 
#define SYSCTL_SYSDIV_36        0x91C00000  // Processor clock is osc/pll /36
272 
#define SYSCTL_SYSDIV_37        0x92400000  // Processor clock is osc/pll /37
273 
#define SYSCTL_SYSDIV_38        0x92C00000  // Processor clock is osc/pll /38
274 
#define SYSCTL_SYSDIV_39        0x93400000  // Processor clock is osc/pll /39
275 
#define SYSCTL_SYSDIV_40        0x93C00000  // Processor clock is osc/pll /40
276 
#define SYSCTL_SYSDIV_41        0x94400000  // Processor clock is osc/pll /41
277 
#define SYSCTL_SYSDIV_42        0x94C00000  // Processor clock is osc/pll /42
278 
#define SYSCTL_SYSDIV_43        0x95400000  // Processor clock is osc/pll /43
279 
#define SYSCTL_SYSDIV_44        0x95C00000  // Processor clock is osc/pll /44
280 
#define SYSCTL_SYSDIV_45        0x96400000  // Processor clock is osc/pll /45
281 
#define SYSCTL_SYSDIV_46        0x96C00000  // Processor clock is osc/pll /46
282 
#define SYSCTL_SYSDIV_47        0x97400000  // Processor clock is osc/pll /47
283 
#define SYSCTL_SYSDIV_48        0x97C00000  // Processor clock is osc/pll /48
284 
#define SYSCTL_SYSDIV_49        0x98400000  // Processor clock is osc/pll /49
285 
#define SYSCTL_SYSDIV_50        0x98C00000  // Processor clock is osc/pll /50
286 
#define SYSCTL_SYSDIV_51        0x99400000  // Processor clock is osc/pll /51
287 
#define SYSCTL_SYSDIV_52        0x99C00000  // Processor clock is osc/pll /52
288 
#define SYSCTL_SYSDIV_53        0x9A400000  // Processor clock is osc/pll /53
289 
#define SYSCTL_SYSDIV_54        0x9AC00000  // Processor clock is osc/pll /54
290 
#define SYSCTL_SYSDIV_55        0x9B400000  // Processor clock is osc/pll /55
291 
#define SYSCTL_SYSDIV_56        0x9BC00000  // Processor clock is osc/pll /56
292 
#define SYSCTL_SYSDIV_57        0x9C400000  // Processor clock is osc/pll /57
293 
#define SYSCTL_SYSDIV_58        0x9CC00000  // Processor clock is osc/pll /58
294 
#define SYSCTL_SYSDIV_59        0x9D400000  // Processor clock is osc/pll /59
295 
#define SYSCTL_SYSDIV_60        0x9DC00000  // Processor clock is osc/pll /60
296 
#define SYSCTL_SYSDIV_61        0x9E400000  // Processor clock is osc/pll /61
297 
#define SYSCTL_SYSDIV_62        0x9EC00000  // Processor clock is osc/pll /62
298 
#define SYSCTL_SYSDIV_63        0x9F400000  // Processor clock is osc/pll /63
299 
#define SYSCTL_SYSDIV_64        0x9FC00000  // Processor clock is osc/pll /64
300 
#define SYSCTL_USE_PLL          0x00000000  // System clock is the PLL clock
301 
#define SYSCTL_USE_OSC          0x00003800  // System clock is the osc clock
302 
#define SYSCTL_XTAL_1MHZ        0x00000000  // External crystal is 1MHz
303 
#define SYSCTL_XTAL_1_84MHZ     0x00000040  // External crystal is 1.8432MHz
304 
#define SYSCTL_XTAL_2MHZ        0x00000080  // External crystal is 2MHz
305 
#define SYSCTL_XTAL_2_45MHZ     0x000000C0  // External crystal is 2.4576MHz
306 
#define SYSCTL_XTAL_3_57MHZ     0x00000100  // External crystal is 3.579545MHz
307 
#define SYSCTL_XTAL_3_68MHZ     0x00000140  // External crystal is 3.6864MHz
308 
#define SYSCTL_XTAL_4MHZ        0x00000180  // External crystal is 4MHz
309 
#define SYSCTL_XTAL_4_09MHZ     0x000001C0  // External crystal is 4.096MHz
310 
#define SYSCTL_XTAL_4_91MHZ     0x00000200  // External crystal is 4.9152MHz
311 
#define SYSCTL_XTAL_5MHZ        0x00000240  // External crystal is 5MHz
312 
#define SYSCTL_XTAL_5_12MHZ     0x00000280  // External crystal is 5.12MHz
313 
#define SYSCTL_XTAL_6MHZ        0x000002C0  // External crystal is 6MHz
314 
#define SYSCTL_XTAL_6_14MHZ     0x00000300  // External crystal is 6.144MHz
315 
#define SYSCTL_XTAL_7_37MHZ     0x00000340  // External crystal is 7.3728MHz
316 
#define SYSCTL_XTAL_8MHZ        0x00000380  // External crystal is 8MHz
317 
#define SYSCTL_XTAL_8_19MHZ     0x000003C0  // External crystal is 8.192MHz
318 
#define SYSCTL_XTAL_10MHZ       0x00000400  // External crystal is 10 MHz
319 
#define SYSCTL_XTAL_12MHZ       0x00000440  // External crystal is 12 MHz
320 
#define SYSCTL_XTAL_12_2MHZ     0x00000480  // External crystal is 12.288 MHz
321 
#define SYSCTL_XTAL_13_5MHZ     0x000004C0  // External crystal is 13.56 MHz
322 
#define SYSCTL_XTAL_14_3MHZ     0x00000500  // External crystal is 14.31818 MHz
323 
#define SYSCTL_XTAL_16MHZ       0x00000540  // External crystal is 16 MHz
324 
#define SYSCTL_XTAL_16_3MHZ     0x00000580  // External crystal is 16.384 MHz
325 
#define SYSCTL_OSC_MAIN         0x00000000  // Oscillator source is main osc
326 
#define SYSCTL_OSC_INT          0x00000010  // Oscillator source is int. osc
327 
#define SYSCTL_OSC_INT4         0x00000020  // Oscillator source is int. osc /4
328 
#define SYSCTL_OSC_INT30        0x80000030  // Oscillator source is int. 30 KHz
329 
#define SYSCTL_OSC_EXT32        0x80000038  // Oscillator source is ext. 32 KHz
330 
#define SYSCTL_INT_OSC_DIS      0x00000002  // Disable internal oscillator
331 
#define SYSCTL_MAIN_OSC_DIS     0x00000001  // Disable main oscillator
332 
 
333 
//*****************************************************************************
334 
//
335 
// Prototypes for the APIs.
336 
//
337 
//*****************************************************************************
338 
extern unsigned long SysCtlSRAMSizeGet(void);
339 
extern unsigned long SysCtlFlashSizeGet(void);
340 
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
341 
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
342 
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
343 
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
344 
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
345 
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
346 
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
347 
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
348 
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
349 
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
350 
extern void SysCtlIntRegister(void (*pfnHandler)(void));
351 
extern void SysCtlIntUnregister(void);
352 
extern void SysCtlIntEnable(unsigned long ulInts);
353 
extern void SysCtlIntDisable(unsigned long ulInts);
354 
extern void SysCtlIntClear(unsigned long ulInts);
355 
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
356 
extern void SysCtlLDOSet(unsigned long ulVoltage);
357 
extern unsigned long SysCtlLDOGet(void);
358 
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
359 
extern void SysCtlReset(void);
360 
extern void SysCtlSleep(void);
361 
extern void SysCtlDeepSleep(void);
362 
extern unsigned long SysCtlResetCauseGet(void);
363 
extern void SysCtlResetCauseClear(unsigned long ulCauses);
364 
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
365 
                                    unsigned long ulDelay);
366 
extern void SysCtlDelay(unsigned long ulCount);
367 
extern void SysCtlClockSet(unsigned long ulConfig);
368 
extern unsigned long SysCtlClockGet(void);
369 
extern void SysCtlPWMClockSet(unsigned long ulConfig);
370 
extern unsigned long SysCtlPWMClockGet(void);
371 
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
372 
extern unsigned long SysCtlADCSpeedGet(void);
373 
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
374 
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
375 
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
376 
extern void SysCtlClkVerificationClear(void);
377 
extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
378 
extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
379 
extern void SysCtlUSBPLLEnable(void);
380 
extern void SysCtlUSBPLLDisable(void);
381 
 
382 
//*****************************************************************************
383 
//
384 
// Mark the end of the C bindings section for C++ compilers.
385 
//
386 
//*****************************************************************************
387 
#ifdef __cplusplus
388 
}
389 
#endif
390 
 
391 
#endif // __SYSCTL_H__

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