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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [ST/] [STM32F10xFWLib/] [inc/] [stm32f10x_fsmc.h] - Blame information for rev 867

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/**
  ******************************************************************************
  * @file  stm32f10x_fsmc.h
  * @author  MCD Application Team
  * @version  V3.0.0
  * @date  04/06/2009
  * @brief  This file contains all the functions prototypes for the FSMC
  *         firmware library.
  ******************************************************************************
  * @copy
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
  */
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FSMC_H
#define __STM32F10x_FSMC_H
 
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
 
/** @addtogroup StdPeriph_Driver
  * @{
  */
 
/** @addtogroup FSMC
  * @{
  */
 
/** @defgroup FSMC_Exported_Types
  * @{
  */
 
/**
  * @brief  Timing parameters For NOR/SRAM Banks
  */
 
typedef struct
{
  uint32_t FSMC_AddressSetupTime;
  uint32_t FSMC_AddressHoldTime;
  uint32_t FSMC_DataSetupTime;
  uint32_t FSMC_BusTurnAroundDuration;
  uint32_t FSMC_CLKDivision;
  uint32_t FSMC_DataLatency;
  uint32_t FSMC_AccessMode;
}FSMC_NORSRAMTimingInitTypeDef;
 
/**
  * @brief  FSMC NOR/SRAM Init structure definition
  */
 
typedef struct
{
  uint32_t FSMC_Bank;
  uint32_t FSMC_DataAddressMux;
  uint32_t FSMC_MemoryType;
  uint32_t FSMC_MemoryDataWidth;
  uint32_t FSMC_BurstAccessMode;
  uint32_t FSMC_WaitSignalPolarity;
  uint32_t FSMC_WrapMode;
  uint32_t FSMC_WaitSignalActive;
  uint32_t FSMC_WriteOperation;
  uint32_t FSMC_WaitSignal;
  uint32_t FSMC_ExtendedMode;
  uint32_t FSMC_WriteBurst;
  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;/* Timing Parameters for write and read access if the  ExtendedMode is not used*/
  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;/* Timing Parameters for write access if the  ExtendedMode is used*/
}FSMC_NORSRAMInitTypeDef;
 
/**
  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
  */
 
typedef struct
{
  uint32_t FSMC_SetupTime;
  uint32_t FSMC_WaitSetupTime;
  uint32_t FSMC_HoldSetupTime;
  uint32_t FSMC_HiZSetupTime;
}FSMC_NAND_PCCARDTimingInitTypeDef;
 
/**
  * @brief  FSMC NAND Init structure definition
  */
 
typedef struct
{
  uint32_t FSMC_Bank;
  uint32_t FSMC_Waitfeature;
  uint32_t FSMC_MemoryDataWidth;
  uint32_t FSMC_ECC;
  uint32_t FSMC_ECCPageSize;
  uint32_t FSMC_TCLRSetupTime;
  uint32_t FSMC_TARSetupTime;
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;/* FSMC Attribute Space Timing */
}FSMC_NANDInitTypeDef;
 
/**
  * @brief  FSMC PCCARD Init structure definition
  */
 
typedef struct
{
  uint32_t FSMC_Waitfeature;
  uint32_t FSMC_TCLRSetupTime;
  uint32_t FSMC_TARSetupTime;
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /* FSMC Attribute Space Timing */
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct;  /* FSMC IO Space Timing */
}FSMC_PCCARDInitTypeDef;
 
/**
  * @}
  */
 
/** @defgroup FSMC_Exported_Constants
  * @{
  */
 
/** @defgroup FSMC_Banks_definitions
  * @{
  */
 
#define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
#define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
#define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
#define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
#define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
#define FSMC_Bank3_NAND                                 ((uint32_t)0x00000100)
#define FSMC_Bank4_PCCARD                               ((uint32_t)0x00001000)
 
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM4))
 
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
                                 ((BANK) == FSMC_Bank3_NAND))
 
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
                                    ((BANK) == FSMC_Bank3_NAND) || \
                                    ((BANK) == FSMC_Bank4_PCCARD))
 
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
                               ((BANK) == FSMC_Bank3_NAND) || \
                               ((BANK) == FSMC_Bank4_PCCARD))
/**
  * @}
  */
 
/** @defgroup NOR_SRAM_Banks
  * @{
  */
 
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
  * @{
  */
 
#define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
#define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
                          ((MUX) == FSMC_DataAddressMux_Enable))
 
/**
  * @}
  */
 
/** @defgroup FSMC_Memory_Type
  * @{
  */
 
#define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
#define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
#define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
                                ((MEMORY) == FSMC_MemoryType_NOR))
 
/**
  * @}
  */
 
/** @defgroup FSMC_Data_Width
  * @{
  */
 
#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
 
/**
  * @}
  */
 
/** @defgroup FSMC_Burst_Access_Mode
  * @{
  */
 
#define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
#define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
                                  ((STATE) == FSMC_BurstAccessMode_Enable))
/**
  * @}
  */
 
/** @defgroup FSMC_Wait_Signal_Polarity
  * @{
  */
 
#define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
#define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
                                         ((POLARITY) == FSMC_WaitSignalPolarity_High))
 
/**
  * @}
  */
 
/** @defgroup FSMC_Wrap_Mode
  * @{
  */
 
#define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
#define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
                                 ((MODE) == FSMC_WrapMode_Enable))
 
/**
  * @}
  */
 
/** @defgroup FSMC_Wait_Timing
  * @{
  */
 
#define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
 
/**
  * @}
  */
 
/** @defgroup FSMC_Write_Operation
  * @{
  */
 
#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
                                            ((OPERATION) == FSMC_WriteOperation_Enable))
 
/**
  * @}
  */
 
/** @defgroup FSMC_Wait_Signal
  * @{
  */
 
#define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
#define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
/**
  * @}
  */
 
/** @defgroup FSMC_Extended_Mode
  * @{
  */
 
#define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
#define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
 
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
                                     ((MODE) == FSMC_ExtendedMode_Enable))
 
/**
  * @}
  */
 
/** @defgroup FSMC_Write_Burst
  * @{
  */
 
#define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
#define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
                                    ((BURST) == FSMC_WriteBurst_Enable))
/**
  * @}
  */
 
/** @defgroup FSMC_Address_Setup_Time
  * @{
  */
 
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_Address_Hold_Time
  * @{
  */
 
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_Data_Setup_Time
  * @{
  */
 
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
 
/**
  * @}
  */
 
/** @defgroup FSMC_Bus_Turn_around_Duration
  * @{
  */
 
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_CLK_Division
  * @{
  */
 
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_Data_Latency
  * @{
  */
 
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_Access_Mode
  * @{
  */
 
#define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
#define FSMC_AccessMode_B                               ((uint32_t)0x10000000) 
#define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
#define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
                                   ((MODE) == FSMC_AccessMode_B) || \
                                   ((MODE) == FSMC_AccessMode_C) || \
                                   ((MODE) == FSMC_AccessMode_D))
 
/**
  * @}
  */
 
/**
  * @}
  */
 
/** @defgroup NAND_and_PCCARD_Banks
  * @{
  */
 
/** @defgroup FSMC_Wait_feature
  * @{
  */
 
#define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)
#define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
                                       ((FEATURE) == FSMC_Waitfeature_Enable))
 
/**
  * @}
  */
 
/** @defgroup FSMC_Memory_Data_Width
  * @{
  */
#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
                                   ((WIDTH) == FSMC_MemoryDataWidth_16b))
 
/**
  * @}
  */
 
/** @defgroup FSMC_ECC
  * @{
  */
 
#define FSMC_ECC_Disable                                ((uint32_t)0x00000000)
#define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
                                  ((STATE) == FSMC_ECC_Enable))
 
/**
  * @}
  */
 
/** @defgroup FSMC_ECC_Page_Size
  * @{
  */
 
#define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)
#define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)
#define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)
#define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)
#define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)
#define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
 
/**
  * @}
  */
 
/** @defgroup FSMC_TCLR_Setup_Time
  * @{
  */
 
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_TAR_Setup_Time
  * @{
  */
 
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_Setup_Time
  * @{
  */
 
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_Wait_Setup_Time
  * @{
  */
 
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_Hold_Setup_Time
  * @{
  */
 
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_HiZ_Setup_Time
  * @{
  */
 
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
 
/**
  * @}
  */
 
/** @defgroup FSMC_Interrupt_sources
  * @{
  */
 
#define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)
#define FSMC_IT_Level                                   ((uint32_t)0x00000010)
#define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
                            ((IT) == FSMC_IT_Level) || \
                            ((IT) == FSMC_IT_FallingEdge))
/**
  * @}
  */
 
/** @defgroup FSMC_Flags
  * @{
  */
 
#define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)
#define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)
#define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)
#define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
                                ((FLAG) == FSMC_FLAG_Level) || \
                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
                                ((FLAG) == FSMC_FLAG_FEMPT))
 
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
 
/**
  * @}
  */
 
/**
  * @}
  */
 
/**
  * @}
  */
 
/** @defgroup FSMC_Exported_Macros
  * @{
  */
 
/**
  * @}
  */
 
/** @defgroup FSMC_Exported_Functions
  * @{
  */
 
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
void FSMC_PCCARDDeInit(void);
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_PCCARDCmd(FunctionalState NewState);
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
 
#endif /*__STM32F10x_FSMC_H */
/**
  * @}
  */
 
/**
  * @}
  */
 
/**
  * @}
  */
 
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [ST/] [STM32F10xFWLib/] [inc/] [stm32f10x_fsmc.h] - Blame information for rev 867

Line No.	Rev	Author	Line
1	608	jeremybenn	`/**`
2			`******************************************************************************`
3			`* @file stm32f10x_fsmc.h`
4			`* @author MCD Application Team`
5			`* @version V3.0.0`
6			`* @date 04/06/2009`
7			`* @brief This file contains all the functions prototypes for the FSMC`
8			`* firmware library.`
9			`******************************************************************************`
10			`* @copy`
11			`*`
12			`* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS`
13			`* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE`
14			`* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY`
15			`* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING`
16			`* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE`
17			`* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.`
18			`*`
19			`* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>`
20			`*/`
21
22			`/* Define to prevent recursive inclusion -------------------------------------*/`
23			`#ifndef __STM32F10x_FSMC_H`
24			`#define __STM32F10x_FSMC_H`
25
26			`/* Includes ------------------------------------------------------------------*/`
27			`#include "stm32f10x.h"`
28
29			`/** @addtogroup StdPeriph_Driver`
30			`* @{`
31			`*/`
32
33			`/** @addtogroup FSMC`
34			`* @{`
35			`*/`
36
37			`/** @defgroup FSMC_Exported_Types`
38			`* @{`
39			`*/`
40
41			`/**`
42			`* @brief Timing parameters For NOR/SRAM Banks`
43			`*/`
44
45			`typedef struct`
46			`{`
47			`uint32_t FSMC_AddressSetupTime;`
48			`uint32_t FSMC_AddressHoldTime;`
49			`uint32_t FSMC_DataSetupTime;`
50			`uint32_t FSMC_BusTurnAroundDuration;`
51			`uint32_t FSMC_CLKDivision;`
52			`uint32_t FSMC_DataLatency;`
53			`uint32_t FSMC_AccessMode;`
54			`}FSMC_NORSRAMTimingInitTypeDef;`
55
56			`/**`
57			`* @brief FSMC NOR/SRAM Init structure definition`
58			`*/`
59
60			`typedef struct`
61			`{`
62			`uint32_t FSMC_Bank;`
63			`uint32_t FSMC_DataAddressMux;`
64			`uint32_t FSMC_MemoryType;`
65			`uint32_t FSMC_MemoryDataWidth;`
66			`uint32_t FSMC_BurstAccessMode;`
67			`uint32_t FSMC_WaitSignalPolarity;`
68			`uint32_t FSMC_WrapMode;`
69			`uint32_t FSMC_WaitSignalActive;`
70			`uint32_t FSMC_WriteOperation;`
71			`uint32_t FSMC_WaitSignal;`
72			`uint32_t FSMC_ExtendedMode;`
73			`uint32_t FSMC_WriteBurst;`
74			`FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;/* Timing Parameters for write and read access if the ExtendedMode is not used*/`
75			`FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;/* Timing Parameters for write access if the ExtendedMode is used*/`
76			`}FSMC_NORSRAMInitTypeDef;`
77
78			`/**`
79			`* @brief Timing parameters For FSMC NAND and PCCARD Banks`
80			`*/`
81
82			`typedef struct`
83			`{`
84			`uint32_t FSMC_SetupTime;`
85			`uint32_t FSMC_WaitSetupTime;`
86			`uint32_t FSMC_HoldSetupTime;`
87			`uint32_t FSMC_HiZSetupTime;`
88			`}FSMC_NAND_PCCARDTimingInitTypeDef;`
89
90			`/**`
91			`* @brief FSMC NAND Init structure definition`
92			`*/`
93
94			`typedef struct`
95			`{`
96			`uint32_t FSMC_Bank;`
97			`uint32_t FSMC_Waitfeature;`
98			`uint32_t FSMC_MemoryDataWidth;`
99			`uint32_t FSMC_ECC;`
100			`uint32_t FSMC_ECCPageSize;`
101			`uint32_t FSMC_TCLRSetupTime;`
102			`uint32_t FSMC_TARSetupTime;`
103			`FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */`
104			`FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;/* FSMC Attribute Space Timing */`
105			`}FSMC_NANDInitTypeDef;`
106
107			`/**`
108			`* @brief FSMC PCCARD Init structure definition`
109			`*/`
110
111			`typedef struct`
112			`{`
113			`uint32_t FSMC_Waitfeature;`
114			`uint32_t FSMC_TCLRSetupTime;`
115			`uint32_t FSMC_TARSetupTime;`
116			`FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */`
117			`FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */`
118			`FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /* FSMC IO Space Timing */`
119			`}FSMC_PCCARDInitTypeDef;`
120
121			`/**`
122			`* @}`
123			`*/`
124
125			`/** @defgroup FSMC_Exported_Constants`
126			`* @{`
127			`*/`
128
129			`/** @defgroup FSMC_Banks_definitions`
130			`* @{`
131			`*/`
132
133			`#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)`
134			`#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)`
135			`#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)`
136			`#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)`
137			`#define FSMC_Bank2_NAND ((uint32_t)0x00000010)`
138			`#define FSMC_Bank3_NAND ((uint32_t)0x00000100)`
139			`#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)`
140
141			`#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) \|\| \`
142			`((BANK) == FSMC_Bank1_NORSRAM2) \|\| \`
143			`((BANK) == FSMC_Bank1_NORSRAM3) \|\| \`
144			`((BANK) == FSMC_Bank1_NORSRAM4))`
145
146			`#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) \|\| \`
147			`((BANK) == FSMC_Bank3_NAND))`
148
149			`#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) \|\| \`
150			`((BANK) == FSMC_Bank3_NAND) \|\| \`
151			`((BANK) == FSMC_Bank4_PCCARD))`
152
153			`#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) \|\| \`
154			`((BANK) == FSMC_Bank3_NAND) \|\| \`
155			`((BANK) == FSMC_Bank4_PCCARD))`
156			`/**`
157			`* @}`
158			`*/`
159
160			`/** @defgroup NOR_SRAM_Banks`
161			`* @{`
162			`*/`
163
164			`/** @defgroup FSMC_Data_Address_Bus_Multiplexing`
165			`* @{`
166			`*/`
167
168			`#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)`
169			`#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)`
170			`#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) \|\| \`
171			`((MUX) == FSMC_DataAddressMux_Enable))`
172
173			`/**`
174			`* @}`
175			`*/`
176
177			`/** @defgroup FSMC_Memory_Type`
178			`* @{`
179			`*/`
180
181			`#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)`
182			`#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)`
183			`#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)`
184			`#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) \|\| \`
185			`((MEMORY) == FSMC_MemoryType_PSRAM)\|\| \`
186			`((MEMORY) == FSMC_MemoryType_NOR))`
187
188			`/**`
189			`* @}`
190			`*/`
191
192			`/** @defgroup FSMC_Data_Width`
193			`* @{`
194			`*/`
195
196			`#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)`
197			`#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)`
198			`#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) \|\| \`
199			`((WIDTH) == FSMC_MemoryDataWidth_16b))`
200
201			`/**`
202			`* @}`
203			`*/`
204
205			`/** @defgroup FSMC_Burst_Access_Mode`
206			`* @{`
207			`*/`
208
209			`#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)`
210			`#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)`
211			`#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) \|\| \`
212			`((STATE) == FSMC_BurstAccessMode_Enable))`
213			`/**`
214			`* @}`
215			`*/`
216
217			`/** @defgroup FSMC_Wait_Signal_Polarity`
218			`* @{`
219			`*/`
220
221			`#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)`
222			`#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)`
223			`#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) \|\| \`
224			`((POLARITY) == FSMC_WaitSignalPolarity_High))`
225
226			`/**`
227			`* @}`
228			`*/`
229
230			`/** @defgroup FSMC_Wrap_Mode`
231			`* @{`
232			`*/`
233
234			`#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)`
235			`#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)`
236			`#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) \|\| \`
237			`((MODE) == FSMC_WrapMode_Enable))`
238
239			`/**`
240			`* @}`
241			`*/`
242
243			`/** @defgroup FSMC_Wait_Timing`
244			`* @{`
245			`*/`
246
247			`#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)`
248			`#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)`
249			`#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) \|\| \`
250			`((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))`
251
252			`/**`
253			`* @}`
254			`*/`
255
256			`/** @defgroup FSMC_Write_Operation`
257			`* @{`
258			`*/`
259
260			`#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)`
261			`#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)`
262			`#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) \|\| \`
263			`((OPERATION) == FSMC_WriteOperation_Enable))`
264
265			`/**`
266			`* @}`
267			`*/`
268
269			`/** @defgroup FSMC_Wait_Signal`
270			`* @{`
271			`*/`
272
273			`#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)`
274			`#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)`
275			`#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) \|\| \`
276			`((SIGNAL) == FSMC_WaitSignal_Enable))`
277			`/**`
278			`* @}`
279			`*/`
280
281			`/** @defgroup FSMC_Extended_Mode`
282			`* @{`
283			`*/`
284
285			`#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)`
286			`#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)`
287
288			`#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) \|\| \`
289			`((MODE) == FSMC_ExtendedMode_Enable))`
290
291			`/**`
292			`* @}`
293			`*/`
294
295			`/** @defgroup FSMC_Write_Burst`
296			`* @{`
297			`*/`
298
299			`#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)`
300			`#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)`
301			`#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) \|\| \`
302			`((BURST) == FSMC_WriteBurst_Enable))`
303			`/**`
304			`* @}`
305			`*/`
306
307			`/** @defgroup FSMC_Address_Setup_Time`
308			`* @{`
309			`*/`
310
311			`#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)`
312
313			`/**`
314			`* @}`
315			`*/`
316
317			`/** @defgroup FSMC_Address_Hold_Time`
318			`* @{`
319			`*/`
320
321			`#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)`
322
323			`/**`
324			`* @}`
325			`*/`
326
327			`/** @defgroup FSMC_Data_Setup_Time`
328			`* @{`
329			`*/`
330
331			`#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))`
332
333			`/**`
334			`* @}`
335			`*/`
336
337			`/** @defgroup FSMC_Bus_Turn_around_Duration`
338			`* @{`
339			`*/`
340
341			`#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)`
342
343			`/**`
344			`* @}`
345			`*/`
346
347			`/** @defgroup FSMC_CLK_Division`
348			`* @{`
349			`*/`
350
351			`#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)`
352
353			`/**`
354			`* @}`
355			`*/`
356
357			`/** @defgroup FSMC_Data_Latency`
358			`* @{`
359			`*/`
360
361			`#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)`
362
363			`/**`
364			`* @}`
365			`*/`
366
367			`/** @defgroup FSMC_Access_Mode`
368			`* @{`
369			`*/`
370
371			`#define FSMC_AccessMode_A ((uint32_t)0x00000000)`
372			`#define FSMC_AccessMode_B ((uint32_t)0x10000000)`
373			`#define FSMC_AccessMode_C ((uint32_t)0x20000000)`
374			`#define FSMC_AccessMode_D ((uint32_t)0x30000000)`
375			`#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) \|\| \`
376			`((MODE) == FSMC_AccessMode_B) \|\| \`
377			`((MODE) == FSMC_AccessMode_C) \|\| \`
378			`((MODE) == FSMC_AccessMode_D))`
379
380			`/**`
381			`* @}`
382			`*/`
383
384			`/**`
385			`* @}`
386			`*/`
387
388			`/** @defgroup NAND_and_PCCARD_Banks`
389			`* @{`
390			`*/`
391
392			`/** @defgroup FSMC_Wait_feature`
393			`* @{`
394			`*/`
395
396			`#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)`
397			`#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)`
398			`#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) \|\| \`
399			`((FEATURE) == FSMC_Waitfeature_Enable))`
400
401			`/**`
402			`* @}`
403			`*/`
404
405			`/** @defgroup FSMC_Memory_Data_Width`
406			`* @{`
407			`*/`
408			`#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)`
409			`#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)`
410			`#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) \|\| \`
411			`((WIDTH) == FSMC_MemoryDataWidth_16b))`
412
413			`/**`
414			`* @}`
415			`*/`
416
417			`/** @defgroup FSMC_ECC`
418			`* @{`
419			`*/`
420
421			`#define FSMC_ECC_Disable ((uint32_t)0x00000000)`
422			`#define FSMC_ECC_Enable ((uint32_t)0x00000040)`
423			`#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) \|\| \`
424			`((STATE) == FSMC_ECC_Enable))`
425
426			`/**`
427			`* @}`
428			`*/`
429
430			`/** @defgroup FSMC_ECC_Page_Size`
431			`* @{`
432			`*/`
433
434			`#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)`
435			`#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)`
436			`#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)`
437			`#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)`
438			`#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)`
439			`#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)`
440			`#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) \|\| \`
441			`((SIZE) == FSMC_ECCPageSize_512Bytes) \|\| \`
442			`((SIZE) == FSMC_ECCPageSize_1024Bytes) \|\| \`
443			`((SIZE) == FSMC_ECCPageSize_2048Bytes) \|\| \`
444			`((SIZE) == FSMC_ECCPageSize_4096Bytes) \|\| \`
445			`((SIZE) == FSMC_ECCPageSize_8192Bytes))`
446
447			`/**`
448			`* @}`
449			`*/`
450
451			`/** @defgroup FSMC_TCLR_Setup_Time`
452			`* @{`
453			`*/`
454
455			`#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)`
456
457			`/**`
458			`* @}`
459			`*/`
460
461			`/** @defgroup FSMC_TAR_Setup_Time`
462			`* @{`
463			`*/`
464
465			`#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)`
466
467			`/**`
468			`* @}`
469			`*/`
470
471			`/** @defgroup FSMC_Setup_Time`
472			`* @{`
473			`*/`
474
475			`#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)`
476
477			`/**`
478			`* @}`
479			`*/`
480
481			`/** @defgroup FSMC_Wait_Setup_Time`
482			`* @{`
483			`*/`
484
485			`#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)`
486
487			`/**`
488			`* @}`
489			`*/`
490
491			`/** @defgroup FSMC_Hold_Setup_Time`
492			`* @{`
493			`*/`
494
495			`#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)`
496
497			`/**`
498			`* @}`
499			`*/`
500
501			`/** @defgroup FSMC_HiZ_Setup_Time`
502			`* @{`
503			`*/`
504
505			`#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)`
506
507			`/**`
508			`* @}`
509			`*/`
510
511			`/** @defgroup FSMC_Interrupt_sources`
512			`* @{`
513			`*/`
514
515			`#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)`
516			`#define FSMC_IT_Level ((uint32_t)0x00000010)`
517			`#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)`
518			`#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))`
519			`#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) \|\| \`
520			`((IT) == FSMC_IT_Level) \|\| \`
521			`((IT) == FSMC_IT_FallingEdge))`
522			`/**`
523			`* @}`
524			`*/`
525
526			`/** @defgroup FSMC_Flags`
527			`* @{`
528			`*/`
529
530			`#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)`
531			`#define FSMC_FLAG_Level ((uint32_t)0x00000002)`
532			`#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)`
533			`#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)`
534			`#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) \|\| \`
535			`((FLAG) == FSMC_FLAG_Level) \|\| \`
536			`((FLAG) == FSMC_FLAG_FallingEdge) \|\| \`
537			`((FLAG) == FSMC_FLAG_FEMPT))`
538
539			`#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))`
540
541			`/**`
542			`* @}`
543			`*/`
544
545			`/**`
546			`* @}`
547			`*/`
548
549			`/**`
550			`* @}`
551			`*/`
552
553			`/** @defgroup FSMC_Exported_Macros`
554			`* @{`
555			`*/`
556
557			`/**`
558			`* @}`
559			`*/`
560
561			`/** @defgroup FSMC_Exported_Functions`
562			`* @{`
563			`*/`
564
565			`void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);`
566			`void FSMC_NANDDeInit(uint32_t FSMC_Bank);`
567			`void FSMC_PCCARDDeInit(void);`
568			`void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);`
569			`void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);`
570			`void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);`
571			`void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);`
572			`void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);`
573			`void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);`
574			`void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);`
575			`void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);`
576			`void FSMC_PCCARDCmd(FunctionalState NewState);`
577			`void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);`
578			`uint32_t FSMC_GetECC(uint32_t FSMC_Bank);`
579			`void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);`
580			`FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);`
581			`void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);`
582			`ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);`
583			`void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);`
584
585			`#endif /__STM32F10x_FSMC_H /`
586			`/**`
587			`* @}`
588			`*/`
589
590			`/**`
591			`* @}`
592			`*/`
593
594			`/**`
595			`* @}`
596			`*/`
597
598			`/***************** (C) COPYRIGHT 2009 STMicroelectronics *END OF FILE**/`