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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [ST/] [STM32F10xFWLib/] [inc/] [stm32f10x_map.h] - Blame information for rev 608

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1 608 jeremybenn
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2
* File Name          : stm32f10x_map.h
3
* Author             : MCD Application Team
4
* Date First Issued  : 09/29/2006
5
* Description        : This file contains all the peripheral register's definitions
6
*                      and memory mapping.
7
********************************************************************************
8
* History:
9
* 04/02/2007: V0.2
10
* 02/05/2007: V0.1
11
* 09/29/2006: V0.01
12
********************************************************************************
13
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
15
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
16
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
17
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
18
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19
*******************************************************************************/
20
 
21
/* Define to prevent recursive inclusion -------------------------------------*/
22
#ifndef __STM32F10x_MAP_H
23
#define __STM32F10x_MAP_H
24
 
25
#ifndef EXT
26
  #define EXT extern
27
#endif /* EXT */
28
 
29
/* Includes ------------------------------------------------------------------*/
30
#include "stm32f10x_conf.h"
31
#include "stm32f10x_type.h"
32
#include "cortexm3_macro.h"
33
 
34
/* Exported types ------------------------------------------------------------*/
35
/******************************************************************************/
36
/*                          IP registers structures                           */
37
/******************************************************************************/
38
 
39
/*------------------------ Analog to Digital Converter -----------------------*/
40
typedef struct
41
{
42
  vu32 SR;
43
  vu32 CR1;
44
  vu32 CR2;
45
  vu32 SMPR1;
46
  vu32 SMPR2;
47
  vu32 JOFR1;
48
  vu32 JOFR2;
49
  vu32 JOFR3;
50
  vu32 JOFR4;
51
  vu32 HTR;
52
  vu32 LTR;
53
  vu32 SQR1;
54
  vu32 SQR2;
55
  vu32 SQR3;
56
  vu32 JSQR;
57
  vu32 JDR1;
58
  vu32 JDR2;
59
  vu32 JDR3;
60
  vu32 JDR4;
61
  vu32 DR;
62
} ADC_TypeDef;
63
 
64
/*------------------------ Backup Registers ----------------------------------*/
65
typedef struct
66
{
67
  u32 RESERVED0;
68
  vu16 DR1;
69
  u16  RESERVED1;
70
  vu16 DR2;
71
  u16  RESERVED2;
72
  vu16 DR3;
73
  u16  RESERVED3;
74
  vu16 DR4;
75
  u16  RESERVED4;
76
  vu16 DR5;
77
  u16  RESERVED5;
78
  vu16 DR6;
79
  u16  RESERVED6;
80
  vu16 DR7;
81
  u16  RESERVED7;
82
  vu16 DR8;
83
  u16  RESERVED8;
84
  vu16 DR9;
85
  u16  RESERVED9;
86
  vu16 DR10;
87
  u16  RESERVED10;
88
  vu16 RTCCR;
89
  u16  RESERVED11;
90
  vu16 CR;
91
  u16  RESERVED12;
92
  vu16 CSR;
93
  u16  RESERVED13;
94
} BKP_TypeDef;
95
 
96
/*------------------------ Controller Area Network ---------------------------*/
97
typedef struct
98
{
99
  vu32 TIR;
100
  vu32 TDTR;
101
  vu32 TDLR;
102
  vu32 TDHR;
103
} CAN_TxMailBox_TypeDef;
104
 
105
typedef struct
106
{
107
  vu32 RIR;
108
  vu32 RDTR;
109
  vu32 RDLR;
110
  vu32 RDHR;
111
} CAN_FIFOMailBox_TypeDef;
112
 
113
typedef struct
114
{
115
  vu32 FR0;
116
  vu32 FR1;
117
} CAN_FilterRegister_TypeDef;
118
 
119
typedef struct
120
{
121
  vu32 MCR;
122
  vu32 MSR;
123
  vu32 TSR;
124
  vu32 RF0R;
125
  vu32 RF1R;
126
  vu32 IER;
127
  vu32 ESR;
128
  vu32 BTR;
129
  u32 RESERVED0[88];
130
  CAN_TxMailBox_TypeDef sTxMailBox[3];
131
  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
132
  u32 RESERVED1[12];
133
  vu32 FMR;
134
  vu32 FM0R;
135
  u32 RESERVED2[1];
136
  vu32 FS0R;
137
  u32 RESERVED3[1];
138
  vu32 FFA0R;
139
  u32 RESERVED4[1];
140
  vu32 FA0R;
141
  u32 RESERVED5[8];
142
  CAN_FilterRegister_TypeDef sFilterRegister[14];
143
} CAN_TypeDef;
144
 
145
/*------------------------ DMA Controller ------------------------------------*/
146
typedef struct
147
{
148
  vu32 CCR;
149
  vu32 CNDTR;
150
  vu32 CPAR;
151
  vu32 CMAR;
152
} DMA_Channel_TypeDef;
153
 
154
typedef struct
155
{
156
  vu32 ISR;
157
  vu32 IFCR;
158
} DMA_TypeDef;
159
 
160
/*------------------------ External Interrupt/Event Controller ---------------*/
161
typedef struct
162
{
163
  vu32 IMR;
164
  vu32 EMR;
165
  vu32 RTSR;
166
  vu32 FTSR;
167
  vu32 SWIER;
168
  vu32 PR;
169
} EXTI_TypeDef;
170
 
171
/*------------------------ FLASH and Option Bytes Registers ------------------*/
172
typedef struct
173
{
174
  vu32 ACR;
175
  vu32 KEYR;
176
  vu32 OPTKEYR;
177
  vu32 SR;
178
  vu32 CR;
179
  vu32 AR;
180
  vu32 RESERVED;
181
  vu32 OBR;
182
  vu32 WRPR;
183
} FLASH_TypeDef;
184
 
185
typedef struct
186
{
187
  vu16 RDP;
188
  vu16 USER;
189
  vu16 Data0;
190
  vu16 Data1;
191
  vu16 WRP0;
192
  vu16 WRP1;
193
  vu16 WRP2;
194
  vu16 WRP3;
195
} OB_TypeDef;
196
 
197
/*------------------------ General Purpose and Alternate Function IO ---------*/
198
typedef struct
199
{
200
  vu32 CRL;
201
  vu32 CRH;
202
  vu32 IDR;
203
  vu32 ODR;
204
  vu32 BSRR;
205
  vu32 BRR;
206
  vu32 LCKR;
207
} GPIO_TypeDef;
208
 
209
typedef struct
210
{
211
  vu32 EVCR;
212
  vu32 MAPR;
213
  vu32 EXTICR[4];
214
} AFIO_TypeDef;
215
 
216
/*------------------------ Inter-integrated Circuit Interface ----------------*/
217
typedef struct
218
{
219
  vu16 CR1;
220
  u16 RESERVED0;
221
  vu16 CR2;
222
  u16 RESERVED1;
223
  vu16 OAR1;
224
  u16 RESERVED2;
225
  vu16 OAR2;
226
  u16 RESERVED3;
227
  vu16 DR;
228
  u16 RESERVED4;
229
  vu16 SR1;
230
  u16 RESERVED5;
231
  vu16 SR2;
232
  u16 RESERVED6;
233
  vu16 CCR;
234
  u16 RESERVED7;
235
  vu16 TRISE;
236
  u16 RESERVED8;
237
} I2C_TypeDef;
238
 
239
/*------------------------ Independent WATCHDOG ------------------------------*/
240
typedef struct
241
{
242
  vu32 KR;
243
  vu32 PR;
244
  vu32 RLR;
245
  vu32 SR;
246
} IWDG_TypeDef;
247
 
248
/*------------------------ Nested Vectored Interrupt Controller --------------*/
249
typedef struct
250
{
251
  vu32 Enable[2];
252
  u32 RESERVED0[30];
253
  vu32 Disable[2];
254
  u32 RSERVED1[30];
255
  vu32 Set[2];
256
  u32 RESERVED2[30];
257
  vu32 Clear[2];
258
  u32 RESERVED3[30];
259
  vu32 Active[2];
260
  u32 RESERVED4[62];
261
  vu32 Priority[11];
262
} NVIC_TypeDef;
263
 
264
typedef struct
265
{
266
  vu32 CPUID;
267
  vu32 IRQControlState;
268
  vu32 ExceptionTableOffset;
269
  vu32 AIRC;
270
  vu32 SysCtrl;
271
  vu32 ConfigCtrl;
272
  vu32 SystemPriority[3];
273
  vu32 SysHandlerCtrl;
274
  vu32 ConfigFaultStatus;
275
  vu32 HardFaultStatus;
276
  vu32 DebugFaultStatus;
277
  vu32 MemoryManageFaultAddr;
278
  vu32 BusFaultAddr;
279
} SCB_TypeDef;
280
 
281
/*------------------------ Power Controller ----------------------------------*/
282
typedef struct
283
{
284
  vu32 CR;
285
  vu32 CSR;
286
} PWR_TypeDef;
287
 
288
/*------------------------ Reset and Clock Controller ------------------------*/
289
typedef struct
290
{
291
  vu32 CR;
292
  vu32 CFGR;
293
  vu32 CIR;
294
  vu32 APB2RSTR;
295
  vu32 APB1RSTR;
296
  vu32 AHBENR;
297
  vu32 APB2ENR;
298
  vu32 APB1ENR;
299
  vu32 BDCR;
300
  vu32 CSR;
301
} RCC_TypeDef;
302
 
303
/*------------------------ Real-Time Clock -----------------------------------*/
304
typedef struct
305
{
306
  vu16 CRH;
307
  u16 RESERVED0;
308
  vu16 CRL;
309
  u16 RESERVED1;
310
  vu16 PRLH;
311
  u16 RESERVED2;
312
  vu16 PRLL;
313
  u16 RESERVED3;
314
  vu16 DIVH;
315
  u16 RESERVED4;
316
  vu16 DIVL;
317
  u16 RESERVED5;
318
  vu16 CNTH;
319
  u16 RESERVED6;
320
  vu16 CNTL;
321
  u16 RESERVED7;
322
  vu16 ALRH;
323
  u16 RESERVED8;
324
  vu16 ALRL;
325
  u16 RESERVED9;
326
} RTC_TypeDef;
327
 
328
/*------------------------ Serial Peripheral Interface -----------------------*/
329
typedef struct
330
{
331
  vu16 CR1;
332
  u16 RESERVED0;
333
  vu16 CR2;
334
  u16 RESERVED1;
335
  vu16 SR;
336
  u16  RESERVED2;
337
  vu16 DR;
338
  u16  RESERVED3;
339
  vu16 CRCPR;
340
  u16 RESERVED4;
341
  vu16 RXCRCR;
342
  u16  RESERVED5;
343
  vu16 TXCRCR;
344
  u16  RESERVED6;
345
  vu16 I2SCFGR;
346
  u16  RESERVED7;
347
  vu16 I2SPR;
348
  u16 RESERVED8;
349
 
350
} SPI_TypeDef;
351
 
352
/*------------------------ SystemTick ----------------------------------------*/
353
typedef struct
354
{
355
  vu32 CTRL;
356
  vu32 LOAD;
357
  vu32 VAL;
358
  vuc32 CALIB;
359
} SysTick_TypeDef;
360
 
361
/*------------------------ Advanced Control Timer ----------------------------*/
362
typedef struct
363
{
364
  vu16 CR1;
365
  u16 RESERVED0;
366
  vu16 CR2;
367
  u16 RESERVED1;
368
  vu16 SMCR;
369
  u16 RESERVED2;
370
  vu16 DIER;
371
  u16 RESERVED3;
372
  vu16 SR;
373
  u16 RESERVED4;
374
  vu16 EGR;
375
  u16 RESERVED5;
376
  vu16 CCMR1;
377
  u16 RESERVED6;
378
  vu16 CCMR2;
379
  u16 RESERVED7;
380
  vu16 CCER;
381
  u16 RESERVED8;
382
  vu16 CNT;
383
  u16 RESERVED9;
384
  vu16 PSC;
385
  u16 RESERVED10;
386
  vu16 ARR;
387
  u16 RESERVED11;
388
  vu16 RCR;
389
  u16 RESERVED12;
390
  vu16 CCR1;
391
  u16 RESERVED13;
392
  vu16 CCR2;
393
  u16 RESERVED14;
394
  vu16 CCR3;
395
  u16 RESERVED15;
396
  vu16 CCR4;
397
  u16 RESERVED16;
398
  vu16 BDTR;
399
  u16 RESERVED17;
400
  vu16 DCR;
401
  u16 RESERVED18;
402
  vu16 DMAR;
403
  u16 RESERVED19;
404
} TIM1_TypeDef;
405
 
406
/*------------------------ General Purpose Timer -----------------------------*/
407
typedef struct
408
{
409
  vu16 CR1;
410
  u16 RESERVED0;
411
  vu16 CR2;
412
  u16 RESERVED1;
413
  vu16 SMCR;
414
  u16 RESERVED2;
415
  vu16 DIER;
416
  u16 RESERVED3;
417
  vu16 SR;
418
  u16 RESERVED4;
419
  vu16 EGR;
420
  u16 RESERVED5;
421
  vu16 CCMR1;
422
  u16 RESERVED6;
423
  vu16 CCMR2;
424
  u16 RESERVED7;
425
  vu16 CCER;
426
  u16 RESERVED8;
427
  vu16 CNT;
428
  u16 RESERVED9;
429
  vu16 PSC;
430
  u16 RESERVED10;
431
  vu16 ARR;
432
  u16 RESERVED11[3];
433
  vu16 CCR1;
434
  u16 RESERVED12;
435
  vu16 CCR2;
436
  u16 RESERVED13;
437
  vu16 CCR3;
438
  u16 RESERVED14;
439
  vu16 CCR4;
440
  u16 RESERVED15[3];
441
  vu16 DCR;
442
  u16 RESERVED16;
443
  vu16 DMAR;
444
  u16 RESERVED17;
445
} TIM_TypeDef;
446
 
447
/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
448
typedef struct
449
{
450
  vu16 SR;
451
  u16 RESERVED0;
452
  vu16 DR;
453
  u16 RESERVED1;
454
  vu16 BRR;
455
  u16 RESERVED2;
456
  vu16 CR1;
457
  u16 RESERVED3;
458
  vu16 CR2;
459
  u16 RESERVED4;
460
  vu16 CR3;
461
  u16 RESERVED5;
462
  vu16 GTPR;
463
  u16 RESERVED6;
464
} USART_TypeDef;
465
 
466
/*------------------------ Window WATCHDOG -----------------------------------*/
467
typedef struct
468
{
469
  vu32 CR;
470
  vu32 CFR;
471
  vu32 SR;
472
} WWDG_TypeDef;
473
 
474
/******************************************************************************/
475
/*                       Peripheral memory map                                */
476
/******************************************************************************/
477
/* Peripheral and SRAM base address in the alias region */
478
#define PERIPH_BB_BASE        ((u32)0x42000000)
479
#define SRAM_BB_BASE          ((u32)0x22000000)
480
 
481
/* Peripheral and SRAM base address in the bit-band region */
482
#define SRAM_BASE             ((u32)0x20000000)
483
#define PERIPH_BASE           ((u32)0x40000000)
484
 
485
/* Flash refisters base address */
486
#define FLASH_BASE            ((u32)0x40022000)
487
/* Flash Option Bytes base address */
488
#define OB_BASE               ((u32)0x1FFFF800)
489
 
490
/* Peripheral memory map */
491
#define APB1PERIPH_BASE       PERIPH_BASE
492
#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
493
#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
494
 
495
#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
496
#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
497
#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
498
#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
499
#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
500
#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
501
#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
502
#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
503
#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
504
#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
505
#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
506
#define CAN_BASE              (APB1PERIPH_BASE + 0x6400)
507
#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
508
#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
509
 
510
#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
511
#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
512
#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
513
#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
514
#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
515
#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
516
#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
517
#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
518
#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
519
#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
520
#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
521
#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
522
 
523
#define DMA_BASE              (AHBPERIPH_BASE + 0x0000)
524
#define DMA_Channel1_BASE     (AHBPERIPH_BASE + 0x0008)
525
#define DMA_Channel2_BASE     (AHBPERIPH_BASE + 0x001C)
526
#define DMA_Channel3_BASE     (AHBPERIPH_BASE + 0x0030)
527
#define DMA_Channel4_BASE     (AHBPERIPH_BASE + 0x0044)
528
#define DMA_Channel5_BASE     (AHBPERIPH_BASE + 0x0058)
529
#define DMA_Channel6_BASE     (AHBPERIPH_BASE + 0x006C)
530
#define DMA_Channel7_BASE     (AHBPERIPH_BASE + 0x0080)
531
#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
532
 
533
/* System Control Space memory map */
534
#define SCS_BASE              ((u32)0xE000E000)
535
 
536
#define SysTick_BASE          (SCS_BASE + 0x0010)
537
#define NVIC_BASE             (SCS_BASE + 0x0100)
538
#define SCB_BASE              (SCS_BASE + 0x0D00)
539
 
540
 
541
/******************************************************************************/
542
/*                            IPs' declaration                                */
543
/******************************************************************************/
544
 
545
/*------------------- Non Debug Mode -----------------------------------------*/
546
#ifndef DEBUG
547
#ifdef _TIM2
548
  #define TIM2                  ((TIM_TypeDef *) TIM2_BASE)
549
#endif /*_TIM2 */
550
 
551
#ifdef _TIM3
552
  #define TIM3                  ((TIM_TypeDef *) TIM3_BASE)
553
#endif /*_TIM3 */
554
 
555
#ifdef _TIM4
556
  #define TIM4                  ((TIM_TypeDef *) TIM4_BASE)
557
#endif /*_TIM4 */
558
 
559
#ifdef _RTC
560
  #define RTC                   ((RTC_TypeDef *) RTC_BASE)
561
#endif /*_RTC */
562
 
563
#ifdef _WWDG
564
  #define WWDG                  ((WWDG_TypeDef *) WWDG_BASE)
565
#endif /*_WWDG */
566
 
567
#ifdef _IWDG
568
  #define IWDG                  ((IWDG_TypeDef *) IWDG_BASE)
569
#endif /*_IWDG */
570
 
571
#ifdef _SPI2
572
  #define SPI2                  ((SPI_TypeDef *) SPI2_BASE)
573
#endif /*_SPI2 */
574
 
575
#ifdef _USART2
576
  #define USART2                ((USART_TypeDef *) USART2_BASE)
577
#endif /*_USART2 */
578
 
579
#ifdef _USART3
580
  #define USART3                ((USART_TypeDef *) USART3_BASE)
581
#endif /*_USART3 */
582
 
583
#ifdef _I2C1
584
  #define I2C1                  ((I2C_TypeDef *) I2C1_BASE)
585
#endif /*_I2C1 */
586
 
587
#ifdef _I2C2
588
  #define I2C2                  ((I2C_TypeDef *) I2C2_BASE)
589
#endif /*_I2C2 */
590
 
591
#ifdef _CAN
592
  #define CAN                   ((CAN_TypeDef *) CAN_BASE)
593
#endif /*_CAN */
594
 
595
#ifdef _BKP
596
  #define BKP                   ((BKP_TypeDef *) BKP_BASE)
597
#endif /*_BKP */
598
 
599
#ifdef _PWR
600
  #define PWR                   ((PWR_TypeDef *) PWR_BASE)
601
#endif /*_PWR */
602
 
603
#ifdef _AFIO
604
  #define AFIO                  ((AFIO_TypeDef *) AFIO_BASE)
605
#endif /*_AFIO */
606
 
607
#ifdef _EXTI
608
  #define EXTI                  ((EXTI_TypeDef *) EXTI_BASE)
609
#endif /*_EXTI */
610
 
611
#ifdef _GPIOA
612
  #define GPIOA                 ((GPIO_TypeDef *) GPIOA_BASE)
613
#endif /*_GPIOA */
614
 
615
#ifdef _GPIOB
616
  #define GPIOB                 ((GPIO_TypeDef *) GPIOB_BASE)
617
#endif /*_GPIOB */
618
 
619
#ifdef _GPIOC
620
  #define GPIOC                 ((GPIO_TypeDef *) GPIOC_BASE)
621
#endif /*_GPIOC */
622
 
623
#ifdef _GPIOD
624
  #define GPIOD                 ((GPIO_TypeDef *) GPIOD_BASE)
625
#endif /*_GPIOD */
626
 
627
#ifdef _GPIOE
628
  #define GPIOE                 ((GPIO_TypeDef *) GPIOE_BASE)
629
#endif /*_GPIOE */
630
 
631
#ifdef _ADC1
632
  #define ADC1                  ((ADC_TypeDef *) ADC1_BASE)
633
#endif /*_ADC1 */
634
 
635
#ifdef _ADC2
636
  #define ADC2                  ((ADC_TypeDef *) ADC2_BASE)
637
#endif /*_ADC2 */
638
 
639
#ifdef _TIM1
640
  #define TIM1                  ((TIM1_TypeDef *) TIM1_BASE)
641
#endif /*_TIM1 */
642
 
643
#ifdef _SPI1
644
  #define SPI1                  ((SPI_TypeDef *) SPI1_BASE)
645
#endif /*_SPI1 */
646
 
647
#ifdef _USART1
648
  #define USART1                ((USART_TypeDef *) USART1_BASE)
649
#endif /*_USART1 */
650
 
651
#ifdef _DMA
652
  #define DMA                   ((DMA_TypeDef *) DMA_BASE)
653
#endif /*_DMA */
654
 
655
#ifdef _DMA_Channel1
656
  #define DMA_Channel1          ((DMA_Channel_TypeDef *) DMA_Channel1_BASE)
657
#endif /*_DMA_Channel1 */
658
 
659
#ifdef _DMA_Channel2
660
  #define DMA_Channel2          ((DMA_Channel_TypeDef *) DMA_Channel2_BASE)
661
#endif /*_DMA_Channel2 */
662
 
663
#ifdef _DMA_Channel3
664
  #define DMA_Channel3          ((DMA_Channel_TypeDef *) DMA_Channel3_BASE)
665
#endif /*_DMA_Channel3 */
666
 
667
#ifdef _DMA_Channel4
668
  #define DMA_Channel4          ((DMA_Channel_TypeDef *) DMA_Channel4_BASE)
669
#endif /*_DMA_Channel4 */
670
 
671
#ifdef _DMA_Channel5
672
  #define DMA_Channel5          ((DMA_Channel_TypeDef *) DMA_Channel5_BASE)
673
#endif /*_DMA_Channel5 */
674
 
675
#ifdef _DMA_Channel6
676
  #define DMA_Channel6          ((DMA_Channel_TypeDef *) DMA_Channel6_BASE)
677
#endif /*_DMA_Channel6 */
678
 
679
#ifdef _DMA_Channel7
680
  #define DMA_Channel7          ((DMA_Channel_TypeDef *) DMA_Channel7_BASE)
681
#endif /*_DMA_Channel7 */
682
 
683
#ifdef _FLASH
684
  #define FLASH                 ((FLASH_TypeDef *) FLASH_BASE)
685
  #define OB                    ((OB_TypeDef *) OB_BASE)
686
#endif /*_FLASH */
687
 
688
#ifdef _RCC
689
  #define RCC                   ((RCC_TypeDef *) RCC_BASE)
690
#endif /*_RCC */
691
 
692
#ifdef _SysTick
693
  #define SysTick               ((SysTick_TypeDef *) SysTick_BASE)
694
#endif /*_SysTick */
695
 
696
#ifdef _NVIC
697
  #define NVIC                  ((NVIC_TypeDef *) NVIC_BASE)
698
#endif /*_NVIC */
699
 
700
#ifdef _SCB
701
  #define SCB                   ((SCB_TypeDef *) SCB_BASE)
702
#endif /*_SCB */
703
/*----------------------  Debug Mode -----------------------------------------*/
704
#else   /* DEBUG */
705
#ifdef _TIM2
706
  EXT TIM_TypeDef             *TIM2;
707
#endif /*_TIM2 */
708
 
709
#ifdef _TIM3
710
  EXT TIM_TypeDef             *TIM3;
711
#endif /*_TIM3 */
712
 
713
#ifdef _TIM4
714
  EXT TIM_TypeDef             *TIM4;
715
#endif /*_TIM4 */
716
 
717
#ifdef _RTC
718
  EXT RTC_TypeDef             *RTC;
719
#endif /*_RTC */
720
 
721
#ifdef _WWDG
722
  EXT WWDG_TypeDef            *WWDG;
723
#endif /*_WWDG */
724
 
725
#ifdef _IWDG
726
  EXT IWDG_TypeDef            *IWDG;
727
#endif /*_IWDG */
728
 
729
#ifdef _SPI2
730
  EXT SPI_TypeDef             *SPI2;
731
#endif /*_SPI2 */
732
 
733
#ifdef _USART2
734
  EXT USART_TypeDef           *USART2;
735
#endif /*_USART2 */
736
 
737
#ifdef _USART3
738
  EXT USART_TypeDef           *USART3;
739
#endif /*_USART3 */
740
 
741
#ifdef _I2C1
742
  EXT I2C_TypeDef             *I2C1;
743
#endif /*_I2C1 */
744
 
745
#ifdef _I2C2
746
  EXT I2C_TypeDef             *I2C2;
747
#endif /*_I2C2 */
748
 
749
#ifdef _CAN
750
  EXT CAN_TypeDef             *CAN;
751
#endif /*_CAN */
752
 
753
#ifdef _BKP
754
  EXT BKP_TypeDef             *BKP;
755
#endif /*_BKP */
756
 
757
#ifdef _PWR
758
  EXT PWR_TypeDef             *PWR;
759
#endif /*_PWR */
760
 
761
#ifdef _AFIO
762
  EXT AFIO_TypeDef            *AFIO;
763
#endif /*_AFIO */
764
 
765
#ifdef _EXTI
766
  EXT EXTI_TypeDef            *EXTI;
767
#endif /*_EXTI */
768
 
769
#ifdef _GPIOA
770
  EXT GPIO_TypeDef            *GPIOA;
771
#endif /*_GPIOA */
772
 
773
#ifdef _GPIOB
774
  EXT GPIO_TypeDef            *GPIOB;
775
#endif /*_GPIOB */
776
 
777
#ifdef _GPIOC
778
  EXT GPIO_TypeDef            *GPIOC;
779
#endif /*_GPIOC */
780
 
781
#ifdef _GPIOD
782
  EXT GPIO_TypeDef            *GPIOD;
783
#endif /*_GPIOD */
784
 
785
#ifdef _GPIOE
786
  EXT GPIO_TypeDef            *GPIOE;
787
#endif /*_GPIOE */
788
 
789
#ifdef _ADC1
790
  EXT ADC_TypeDef             *ADC1;
791
#endif /*_ADC1 */
792
 
793
#ifdef _ADC2
794
  EXT ADC_TypeDef             *ADC2;
795
#endif /*_ADC2 */
796
 
797
#ifdef _TIM1
798
  EXT TIM1_TypeDef            *TIM1;
799
#endif /*_TIM1 */
800
 
801
#ifdef _SPI1
802
  EXT SPI_TypeDef             *SPI1;
803
#endif /*_SPI1 */
804
 
805
#ifdef _USART1
806
  EXT USART_TypeDef           *USART1;
807
#endif /*_USART1 */
808
 
809
#ifdef _DMA
810
  EXT DMA_TypeDef             *DMA;
811
#endif /*_DMA */
812
 
813
#ifdef _DMA_Channel1
814
  EXT DMA_Channel_TypeDef     *DMA_Channel1;
815
#endif /*_DMA_Channel1 */
816
 
817
#ifdef _DMA_Channel2
818
  EXT DMA_Channel_TypeDef     *DMA_Channel2;
819
#endif /*_DMA_Channel2 */
820
 
821
#ifdef _DMA_Channel3
822
  EXT DMA_Channel_TypeDef     *DMA_Channel3;
823
#endif /*_DMA_Channel3 */
824
 
825
#ifdef _DMA_Channel4
826
  EXT DMA_Channel_TypeDef     *DMA_Channel4;
827
#endif /*_DMA_Channel4 */
828
 
829
#ifdef _DMA_Channel5
830
  EXT DMA_Channel_TypeDef     *DMA_Channel5;
831
#endif /*_DMA_Channel5 */
832
 
833
#ifdef _DMA_Channel6
834
  EXT DMA_Channel_TypeDef     *DMA_Channel6;
835
#endif /*_DMA_Channel6 */
836
 
837
#ifdef _DMA_Channel7
838
  EXT DMA_Channel_TypeDef     *DMA_Channel7;
839
#endif /*_DMA_Channel7 */
840
 
841
#ifdef _FLASH
842
  EXT FLASH_TypeDef            *FLASH;
843
  EXT OB_TypeDef               *OB;
844
#endif /*_FLASH */
845
 
846
#ifdef _RCC
847
  EXT RCC_TypeDef             *RCC;
848
#endif /*_RCC */
849
 
850
#ifdef _SysTick
851
  EXT SysTick_TypeDef         *SysTick;
852
#endif /*_SysTick */
853
 
854
#ifdef _NVIC
855
  EXT NVIC_TypeDef            *NVIC;
856
#endif /*_NVIC */
857
 
858
#ifdef _SCB
859
  EXT SCB_TypeDef             *SCB;
860
#endif /*_SCB */
861
 
862
#endif  /* DEBUG */
863
 
864
/* Exported constants --------------------------------------------------------*/
865
/* Exported macro ------------------------------------------------------------*/
866
/* Exported functions ------------------------------------------------------- */
867
 
868
#endif /* __STM32F10x_MAP_H */
869
 
870
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/

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