OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [ST/] [STM32F10xFWLib/] [inc/] [stm32f10x_tim1.h] - Blame information for rev 608

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 608 jeremybenn
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
2
* File Name          : stm32f10x_tim1.h
3
* Author             : MCD Application Team
4
* Date First Issued  : 09/29/2006
5
* Description        : This file contains all the functions prototypes for the
6
*                      TIM1 firmware library.
7
********************************************************************************
8
* History:
9
* 04/02/2007: V0.2
10
* mm/dd/yyyy: V0.1
11
* 09/29/2006: V0.01
12
********************************************************************************
13
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
15
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
16
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
17
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
18
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19
*******************************************************************************/
20
 
21
/* Define to prevent recursive inclusion -------------------------------------*/
22
#ifndef __STM32F10x_TIM1_H
23
#define __STM32F10x_TIM1_H
24
 
25
/* Includes ------------------------------------------------------------------*/
26
#include "stm32f10x_map.h"
27
 
28
/* Exported types ------------------------------------------------------------*/
29
 
30
/* TIM1 Time Base Init structure definition */
31
typedef struct
32
{
33
  u16 TIM1_Prescaler;
34
  u16 TIM1_CounterMode;
35
  u16 TIM1_Period;
36
  u16 TIM1_ClockDivision;
37
  u8 TIM1_RepetitionCounter;
38
} TIM1_TimeBaseInitTypeDef;
39
 
40
/* TIM1 Output Compare Init structure definition */
41
typedef struct
42
{
43
  u16 TIM1_OCMode;
44
  u16 TIM1_OutputState;
45
  u16 TIM1_OutputNState;
46
  u16 TIM1_Pulse;
47
  u16 TIM1_OCPolarity;
48
  u16 TIM1_OCNPolarity;
49
  u16 TIM1_OCIdleState;
50
  u16 TIM1_OCNIdleState;
51
} TIM1_OCInitTypeDef;
52
 
53
/* TIM1 Input Capture Init structure definition */
54
typedef struct
55
{
56
  u16 TIM1_Channel;
57
  u16 TIM1_ICPolarity;
58
  u16 TIM1_ICSelection;
59
  u16 TIM1_ICPrescaler;
60
  u8 TIM1_ICFilter;
61
} TIM1_ICInitTypeDef;
62
 
63
/* BDTR structure definition */
64
typedef struct
65
{
66
  u16 TIM1_OSSRState;
67
  u16 TIM1_OSSIState;
68
  u16 TIM1_LOCKLevel;
69
  u16 TIM1_DeadTime;
70
  u16 TIM1_Break;
71
  u16 TIM1_BreakPolarity;
72
  u16 TIM1_AutomaticOutput;
73
} TIM1_BDTRInitTypeDef;
74
 
75
/* Exported constants --------------------------------------------------------*/
76
/* TIM1 Output Compare and PWM modes ----------------------------------------*/
77
#define TIM1_OCMode_Timing                 ((u16)0x0000)
78
#define TIM1_OCMode_Active                 ((u16)0x0010)
79
#define TIM1_OCMode_Inactive               ((u16)0x0020)
80
#define TIM1_OCMode_Toggle                 ((u16)0x0030)
81
#define TIM1_OCMode_PWM1                   ((u16)0x0060)
82
#define TIM1_OCMode_PWM2                   ((u16)0x0070)
83
 
84
#define IS_TIM1_OC_MODE(MODE) ((MODE == TIM1_OCMode_Timing) || \
85
                               (MODE == TIM1_OCMode_Active) || \
86
                               (MODE == TIM1_OCMode_Inactive) || \
87
                               (MODE == TIM1_OCMode_Toggle)|| \
88
                               (MODE == TIM1_OCMode_PWM1) || \
89
                               (MODE == TIM1_OCMode_PWM2))
90
 
91
#define IS_TIM1_OCM(MODE)((MODE == TIM1_OCMode_Timing) || \
92
                          (MODE == TIM1_OCMode_Active) || \
93
                          (MODE == TIM1_OCMode_Inactive) || \
94
                          (MODE == TIM1_OCMode_Toggle)|| \
95
                          (MODE == TIM1_OCMode_PWM1) || \
96
                          (MODE == TIM1_OCMode_PWM2) || \
97
                          (MODE == TIM1_ForcedAction_Active) || \
98
                          (MODE == TIM1_ForcedAction_InActive))
99
/* TIM1 One Pulse Mode ------------------------------------------------------*/
100
#define TIM1_OPMode_Single                 ((u16)0x0001)
101
#define TIM1_OPMode_Repetitive             ((u16)0x0000)
102
 
103
#define IS_TIM1_OPM_MODE(MODE) ((MODE == TIM1_OPMode_Single) || \
104
                                (MODE == TIM1_OPMode_Repetitive))
105
 
106
/* TIM1 Channel -------------------------------------------------------------*/
107
#define TIM1_Channel_1                     ((u16)0x0000)
108
#define TIM1_Channel_2                     ((u16)0x0001)
109
#define TIM1_Channel_3                     ((u16)0x0002)
110
#define TIM1_Channel_4                     ((u16)0x0003)
111
 
112
#define IS_TIM1_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
113
                                  (CHANNEL == TIM1_Channel_2) || \
114
                                  (CHANNEL == TIM1_Channel_3) || \
115
                                  (CHANNEL == TIM1_Channel_4))
116
 
117
#define IS_TIM1_PWMI_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
118
                                       (CHANNEL == TIM1_Channel_2))
119
 
120
#define IS_TIM1_COMPLEMENTARY_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
121
                                                (CHANNEL == TIM1_Channel_2) || \
122
                                                (CHANNEL == TIM1_Channel_3))
123
/* TIM1 Clock Division CKD --------------------------------------------------*/
124
#define TIM1_CKD_DIV1                      ((u16)0x0000)
125
#define TIM1_CKD_DIV2                      ((u16)0x0100)
126
#define TIM1_CKD_DIV4                      ((u16)0x0200)
127
 
128
#define IS_TIM1_CKD_DIV(DIV) ((DIV == TIM1_CKD_DIV1) || \
129
                              (DIV == TIM1_CKD_DIV2) || \
130
                              (DIV == TIM1_CKD_DIV4))
131
 
132
/* TIM1 Counter Mode --------------------------------------------------------*/
133
#define TIM1_CounterMode_Up                ((u16)0x0000)
134
#define TIM1_CounterMode_Down              ((u16)0x0010)
135
#define TIM1_CounterMode_CenterAligned1    ((u16)0x0020)
136
#define TIM1_CounterMode_CenterAligned2    ((u16)0x0040)
137
#define TIM1_CounterMode_CenterAligned3    ((u16)0x0060)
138
 
139
#define IS_TIM1_COUNTER_MODE(MODE) ((MODE == TIM1_CounterMode_Up) ||  \
140
                                    (MODE == TIM1_CounterMode_Down) || \
141
                                    (MODE == TIM1_CounterMode_CenterAligned1) || \
142
                                    (MODE == TIM1_CounterMode_CenterAligned2) || \
143
                                    (MODE == TIM1_CounterMode_CenterAligned3))
144
 
145
/* TIM1 Output Compare Polarity ---------------------------------------------*/
146
#define TIM1_OCPolarity_High               ((u16)0x0000)
147
#define TIM1_OCPolarity_Low                ((u16)0x0001)
148
 
149
#define IS_TIM1_OC_POLARITY(POLARITY) ((POLARITY == TIM1_OCPolarity_High) || \
150
                                       (POLARITY == TIM1_OCPolarity_Low))
151
 
152
/* TIM1 Output Compare N Polarity -------------------------------------------*/
153
#define TIM1_OCNPolarity_High              ((u16)0x0000)
154
#define TIM1_OCNPolarity_Low               ((u16)0x0001)
155
 
156
#define IS_TIM1_OCN_POLARITY(POLARITY) ((POLARITY == TIM1_OCNPolarity_High) || \
157
                                        (POLARITY == TIM1_OCNPolarity_Low))
158
 
159
/* TIM1 Output Compare states -----------------------------------------------*/
160
#define TIM1_OutputState_Disable           ((u16)0x0000)
161
#define TIM1_OutputState_Enable            ((u16)0x0001)
162
 
163
#define IS_TIM1_OUTPUT_STATE(STATE) ((STATE == TIM1_OutputState_Disable) || \
164
                                     (STATE == TIM1_OutputState_Enable))
165
 
166
/* TIM1 Output Compare N States ---------------------------------------------*/
167
#define TIM1_OutputNState_Disable          ((u16)0x0000)
168
#define TIM1_OutputNState_Enable           ((u16)0x0001)
169
 
170
#define IS_TIM1_OUTPUTN_STATE(STATE) ((STATE == TIM1_OutputNState_Disable) || \
171
                                      (STATE == TIM1_OutputNState_Enable))
172
 
173
/* Break Input enable/disable -----------------------------------------------*/
174
#define TIM1_Break_Enable                  ((u16)0x1000)
175
#define TIM1_Break_Disable                 ((u16)0x0000)
176
 
177
#define IS_TIM1_BREAK_STATE(STATE) ((STATE == TIM1_Break_Enable) || \
178
                                    (STATE == TIM1_Break_Disable))
179
 
180
/* Break Polarity -----------------------------------------------------------*/
181
#define TIM1_BreakPolarity_Low             ((u16)0x0000)
182
#define TIM1_BreakPolarity_High            ((u16)0x2000)
183
 
184
#define IS_TIM1_BREAK_POLARITY(POLARITY) ((POLARITY == TIM1_BreakPolarity_Low) || \
185
                                          (POLARITY == TIM1_BreakPolarity_High))
186
 
187
/* TIM1 AOE Bit Set/Reset ---------------------------------------------------*/
188
#define TIM1_AutomaticOutput_Enable        ((u16)0x4000)
189
#define TIM1_AutomaticOutput_Disable       ((u16)0x0000)
190
 
191
#define IS_TIM1_AUTOMATIC_OUTPUT_STATE(STATE) ((STATE == TIM1_AutomaticOutput_Enable) || \
192
                                               (STATE == TIM1_AutomaticOutput_Disable))
193
/* Lock levels --------------------------------------------------------------*/
194
#define TIM1_LOCKLevel_OFF                 ((u16)0x0000)
195
#define TIM1_LOCKLevel_1                   ((u16)0x0100)
196
#define TIM1_LOCKLevel_2                   ((u16)0x0200)
197
#define TIM1_LOCKLevel_3                   ((u16)0x0300)
198
 
199
#define IS_TIM1_LOCK_LEVEL(LEVEL) ((LEVEL == TIM1_LOCKLevel_OFF) || \
200
                                   (LEVEL == TIM1_LOCKLevel_1) || \
201
                                   (LEVEL == TIM1_LOCKLevel_2) || \
202
                                   (LEVEL == TIM1_LOCKLevel_3))
203
 
204
/* OSSI: Off-State Selection for Idle mode states ---------------------------*/
205
#define TIM1_OSSIState_Enable              ((u16)0x0400)
206
#define TIM1_OSSIState_Disable             ((u16)0x0000)
207
 
208
#define IS_TIM1_OSSI_STATE(STATE) ((STATE == TIM1_OSSIState_Enable) || \
209
                                   (STATE == TIM1_OSSIState_Disable))
210
 
211
/* OSSR: Off-State Selection for Run mode states ----------------------------*/
212
#define TIM1_OSSRState_Enable              ((u16)0x0800)
213
#define TIM1_OSSRState_Disable             ((u16)0x0000)
214
 
215
#define IS_TIM1_OSSR_STATE(STATE) ((STATE == TIM1_OSSRState_Enable) || \
216
                                   (STATE == TIM1_OSSRState_Disable))
217
 
218
/* TIM1 Output Compare Idle State -------------------------------------------*/
219
#define TIM1_OCIdleState_Set               ((u16)0x0001)
220
#define TIM1_OCIdleState_Reset             ((u16)0x0000)
221
 
222
#define IS_TIM1_OCIDLE_STATE(STATE) ((STATE == TIM1_OCIdleState_Set) || \
223
                                     (STATE == TIM1_OCIdleState_Reset))
224
 
225
/* TIM1 Output Compare N Idle State -----------------------------------------*/
226
#define TIM1_OCNIdleState_Set              ((u16)0x0001)
227
#define TIM1_OCNIdleState_Reset            ((u16)0x0000)
228
 
229
#define IS_TIM1_OCNIDLE_STATE(STATE) ((STATE == TIM1_OCNIdleState_Set) || \
230
                                      (STATE == TIM1_OCNIdleState_Reset))
231
 
232
/* TIM1 Input Capture Polarity ----------------------------------------------*/
233
#define  TIM1_ICPolarity_Rising            ((u16)0x0000)
234
#define  TIM1_ICPolarity_Falling           ((u16)0x0001)
235
 
236
#define IS_TIM1_IC_POLARITY(POLARITY) ((POLARITY == TIM1_ICPolarity_Rising) || \
237
                                       (POLARITY == TIM1_ICPolarity_Falling))
238
 
239
/* TIM1 Input Capture Selection ---------------------------------------------*/
240
#define TIM1_ICSelection_DirectTI          ((u16)0x0001)
241
#define TIM1_ICSelection_IndirectTI        ((u16)0x0002)
242
#define TIM1_ICSelection_TRGI              ((u16)0x0003)
243
 
244
#define IS_TIM1_IC_SELECTION(SELECTION) ((SELECTION == TIM1_ICSelection_DirectTI) || \
245
                                         (SELECTION == TIM1_ICSelection_IndirectTI) || \
246
                                         (SELECTION == TIM1_ICSelection_TRGI))
247
 
248
/* TIM1 Input Capture Prescaler ---------------------------------------------*/
249
#define TIM1_ICPSC_DIV1                    ((u16)0x0000)
250
#define TIM1_ICPSC_DIV2                    ((u16)0x0004)
251
#define TIM1_ICPSC_DIV4                    ((u16)0x0008)
252
#define TIM1_ICPSC_DIV8                    ((u16)0x000C)
253
 
254
#define IS_TIM1_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ICPSC_DIV1) || \
255
                                         (PRESCALER == TIM1_ICPSC_DIV2) || \
256
                                         (PRESCALER == TIM1_ICPSC_DIV4) || \
257
                                         (PRESCALER == TIM1_ICPSC_DIV8))
258
 
259
/* TIM1 Input Capture Filer Value ---------------------------------------------*/
260
#define IS_TIM1_IC_FILTER(ICFILTER) (ICFILTER <= 0xF)                                              
261
 
262
/* TIM1 interrupt sources ---------------------------------------------------*/
263
#define TIM1_IT_Update                     ((u16)0x0001)
264
#define TIM1_IT_CC1                        ((u16)0x0002)
265
#define TIM1_IT_CC2                        ((u16)0x0004)
266
#define TIM1_IT_CC3                        ((u16)0x0008)
267
#define TIM1_IT_CC4                        ((u16)0x0010)
268
#define TIM1_IT_COM                        ((u16)0x0020)
269
#define TIM1_IT_Trigger                    ((u16)0x0040)
270
#define TIM1_IT_Break                      ((u16)0x0080)
271
 
272
#define IS_TIM1_IT(IT) (((IT & (u16)0xFF00) == 0x0000) && (IT != 0x0000))
273
 
274
#define IS_TIM1_GET_IT(IT) ((IT == TIM1_IT_Update) || \
275
                            (IT == TIM1_IT_CC1) || \
276
                            (IT == TIM1_IT_CC2) || \
277
                            (IT == TIM1_IT_CC3) || \
278
                            (IT == TIM1_IT_CC4) || \
279
                            (IT == TIM1_IT_COM) || \
280
                            (IT == TIM1_IT_Trigger) || \
281
                            (IT == TIM1_IT_Break))
282
 
283
/* TIM1 DMA Base address ----------------------------------------------------*/
284
#define TIM1_DMABase_CR1                   ((u16)0x0000)
285
#define TIM1_DMABase_CR2                   ((u16)0x0001)
286
#define TIM1_DMABase_SMCR                  ((u16)0x0002)
287
#define TIM1_DMABase_DIER                  ((u16)0x0003)
288
#define TIM1_DMABase_SR                    ((u16)0x0004)
289
#define TIM1_DMABase_EGR                   ((u16)0x0005)
290
#define TIM1_DMABase_CCMR1                 ((u16)0x0006)
291
#define TIM1_DMABase_CCMR2                 ((u16)0x0007)
292
#define TIM1_DMABase_CCER                  ((u16)0x0008)
293
#define TIM1_DMABase_CNT                   ((u16)0x0009)
294
#define TIM1_DMABase_PSC                   ((u16)0x000A)
295
#define TIM1_DMABase_ARR                   ((u16)0x000B)
296
#define TIM1_DMABase_RCR                   ((u16)0x000C)
297
#define TIM1_DMABase_CCR1                  ((u16)0x000D)
298
#define TIM1_DMABase_CCR2                  ((u16)0x000E)
299
#define TIM1_DMABase_CCR3                  ((u16)0x000F)
300
#define TIM1_DMABase_CCR4                  ((u16)0x0010)
301
#define TIM1_DMABase_BDTR                  ((u16)0x0011)
302
#define TIM1_DMABase_DCR                   ((u16)0x0012)
303
 
304
#define IS_TIM1_DMA_BASE(BASE) ((BASE == TIM1_DMABase_CR1) || \
305
                                (BASE == TIM1_DMABase_CR2) || \
306
                                (BASE == TIM1_DMABase_SMCR) || \
307
                                (BASE == TIM1_DMABase_DIER) || \
308
                                (BASE == TIM1_DMABase_SR) || \
309
                                (BASE == TIM1_DMABase_EGR) || \
310
                                (BASE == TIM1_DMABase_CCMR1) || \
311
                                (BASE == TIM1_DMABase_CCMR2) || \
312
                                (BASE == TIM1_DMABase_CCER) || \
313
                                (BASE == TIM1_DMABase_CNT) || \
314
                                (BASE == TIM1_DMABase_PSC) || \
315
                                (BASE == TIM1_DMABase_ARR) || \
316
                                (BASE == TIM1_DMABase_RCR) || \
317
                                (BASE == TIM1_DMABase_CCR1) || \
318
                                (BASE == TIM1_DMABase_CCR2) || \
319
                                (BASE == TIM1_DMABase_CCR3) || \
320
                                (BASE == TIM1_DMABase_CCR4) || \
321
                                (BASE == TIM1_DMABase_BDTR) || \
322
                                (BASE == TIM1_DMABase_DCR))
323
 
324
/* TIM1 DMA Burst Length ----------------------------------------------------*/
325
#define TIM1_DMABurstLength_1Byte          ((u16)0x0000)
326
#define TIM1_DMABurstLength_2Bytes         ((u16)0x0100)
327
#define TIM1_DMABurstLength_3Bytes         ((u16)0x0200)
328
#define TIM1_DMABurstLength_4Bytes         ((u16)0x0300)
329
#define TIM1_DMABurstLength_5Bytes         ((u16)0x0400)
330
#define TIM1_DMABurstLength_6Bytes         ((u16)0x0500)
331
#define TIM1_DMABurstLength_7Bytes         ((u16)0x0600)
332
#define TIM1_DMABurstLength_8Bytes         ((u16)0x0700)
333
#define TIM1_DMABurstLength_9Bytes         ((u16)0x0800)
334
#define TIM1_DMABurstLength_10Bytes        ((u16)0x0900)
335
#define TIM1_DMABurstLength_11Bytes        ((u16)0x0A00)
336
#define TIM1_DMABurstLength_12Bytes        ((u16)0x0B00)
337
#define TIM1_DMABurstLength_13Bytes        ((u16)0x0C00)
338
#define TIM1_DMABurstLength_14Bytes        ((u16)0x0D00)
339
#define TIM1_DMABurstLength_15Bytes        ((u16)0x0E00)
340
#define TIM1_DMABurstLength_16Bytes        ((u16)0x0F00)
341
#define TIM1_DMABurstLength_17Bytes        ((u16)0x1000)
342
#define TIM1_DMABurstLength_18Bytes        ((u16)0x1100)
343
 
344
#define IS_TIM1_DMA_LENGTH(LENGTH) ((LENGTH == TIM1_DMABurstLength_1Byte) || \
345
                                    (LENGTH == TIM1_DMABurstLength_2Bytes) || \
346
                                    (LENGTH == TIM1_DMABurstLength_3Bytes) || \
347
                                    (LENGTH == TIM1_DMABurstLength_4Bytes) || \
348
                                    (LENGTH == TIM1_DMABurstLength_5Bytes) || \
349
                                    (LENGTH == TIM1_DMABurstLength_6Bytes) || \
350
                                    (LENGTH == TIM1_DMABurstLength_7Bytes) || \
351
                                    (LENGTH == TIM1_DMABurstLength_8Bytes) || \
352
                                    (LENGTH == TIM1_DMABurstLength_9Bytes) || \
353
                                    (LENGTH == TIM1_DMABurstLength_10Bytes) || \
354
                                    (LENGTH == TIM1_DMABurstLength_11Bytes) || \
355
                                    (LENGTH == TIM1_DMABurstLength_12Bytes) || \
356
                                    (LENGTH == TIM1_DMABurstLength_13Bytes) || \
357
                                    (LENGTH == TIM1_DMABurstLength_14Bytes) || \
358
                                    (LENGTH == TIM1_DMABurstLength_15Bytes) || \
359
                                    (LENGTH == TIM1_DMABurstLength_16Bytes) || \
360
                                    (LENGTH == TIM1_DMABurstLength_17Bytes) || \
361
                                    (LENGTH == TIM1_DMABurstLength_18Bytes))
362
 
363
/* TIM1 DMA sources ---------------------------------------------------------*/
364
#define TIM1_DMA_Update                    ((u16)0x0100)
365
#define TIM1_DMA_CC1                       ((u16)0x0200)
366
#define TIM1_DMA_CC2                       ((u16)0x0400)
367
#define TIM1_DMA_CC3                       ((u16)0x0800)
368
#define TIM1_DMA_CC4                       ((u16)0x1000)
369
#define TIM1_DMA_COM                       ((u16)0x2000)
370
#define TIM1_DMA_Trigger                   ((u16)0x4000)
371
 
372
#define IS_TIM1_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0x80FF) == 0x0000) && (SOURCE != 0x0000))
373
 
374
/* TIM1 External Trigger Prescaler ------------------------------------------*/
375
#define TIM1_ExtTRGPSC_OFF                 ((u16)0x0000)
376
#define TIM1_ExtTRGPSC_DIV2                ((u16)0x1000)
377
#define TIM1_ExtTRGPSC_DIV4                ((u16)0x2000)
378
#define TIM1_ExtTRGPSC_DIV8                ((u16)0x3000)
379
 
380
#define IS_TIM1_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ExtTRGPSC_OFF) || \
381
                                          (PRESCALER == TIM1_ExtTRGPSC_DIV2) || \
382
                                          (PRESCALER == TIM1_ExtTRGPSC_DIV4) || \
383
                                          (PRESCALER == TIM1_ExtTRGPSC_DIV8))
384
 
385
/* TIM1 Internal Trigger Selection ------------------------------------------*/
386
#define TIM1_TS_ITR0                       ((u16)0x0000)
387
#define TIM1_TS_ITR1                       ((u16)0x0010)
388
#define TIM1_TS_ITR2                       ((u16)0x0020)
389
#define TIM1_TS_ITR3                       ((u16)0x0030)
390
#define TIM1_TS_TI1F_ED                    ((u16)0x0040)
391
#define TIM1_TS_TI1FP1                     ((u16)0x0050)
392
#define TIM1_TS_TI2FP2                     ((u16)0x0060)
393
#define TIM1_TS_ETRF                       ((u16)0x0070)
394
 
395
#define IS_TIM1_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \
396
                                              (SELECTION == TIM1_TS_ITR1) || \
397
                                              (SELECTION == TIM1_TS_ITR2) || \
398
                                              (SELECTION == TIM1_TS_ITR3) || \
399
                                              (SELECTION == TIM1_TS_TI1F_ED) || \
400
                                              (SELECTION == TIM1_TS_TI1FP1) || \
401
                                              (SELECTION == TIM1_TS_TI2FP2) || \
402
                                              (SELECTION == TIM1_TS_ETRF))
403
 
404
#define IS_TIM1_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \
405
                                                       (SELECTION == TIM1_TS_ITR1) || \
406
                                                       (SELECTION == TIM1_TS_ITR2) || \
407
                                                       (SELECTION == TIM1_TS_ITR3))
408
 
409
#define IS_TIM1_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_TI1F_ED) || \
410
                                                  (SELECTION == TIM1_TS_TI1FP1) || \
411
                                                  (SELECTION == TIM1_TS_TI2FP2))
412
 
413
/* TIM1 External Trigger Polarity -------------------------------------------*/
414
#define TIM1_ExtTRGPolarity_Inverted       ((u16)0x8000)
415
#define TIM1_ExtTRGPolarity_NonInverted    ((u16)0x0000)
416
 
417
#define IS_TIM1_EXT_POLARITY(POLARITY) ((POLARITY == TIM1_ExtTRGPolarity_Inverted) || \
418
                                        (POLARITY == TIM1_ExtTRGPolarity_NonInverted))
419
 
420
/* TIM1 Prescaler Reload Mode -----------------------------------------------*/
421
#define TIM1_PSCReloadMode_Update          ((u16)0x0000)
422
#define TIM1_PSCReloadMode_Immediate       ((u16)0x0001)
423
 
424
#define IS_TIM1_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM1_PSCReloadMode_Update) || \
425
                                          (RELOAD == TIM1_PSCReloadMode_Immediate))
426
 
427
/* TIM1 Forced Action -------------------------------------------------------*/
428
#define TIM1_ForcedAction_Active           ((u16)0x0050)
429
#define TIM1_ForcedAction_InActive         ((u16)0x0040)
430
 
431
#define IS_TIM1_FORCED_ACTION(ACTION) ((ACTION == TIM1_ForcedAction_Active) || \
432
                                       (ACTION == TIM1_ForcedAction_InActive))
433
 
434
/* TIM1 Encoder Mode --------------------------------------------------------*/
435
#define TIM1_EncoderMode_TI1               ((u16)0x0001)
436
#define TIM1_EncoderMode_TI2               ((u16)0x0002)
437
#define TIM1_EncoderMode_TI12              ((u16)0x0003)
438
 
439
#define IS_TIM1_ENCODER_MODE(MODE) ((MODE == TIM1_EncoderMode_TI1) || \
440
                                    (MODE == TIM1_EncoderMode_TI2) || \
441
                                    (MODE == TIM1_EncoderMode_TI12))
442
 
443
/* TIM1 Event Source --------------------------------------------------------*/
444
#define TIM1_EventSource_Update            ((u16)0x0001)
445
#define TIM1_EventSource_CC1               ((u16)0x0002)
446
#define TIM1_EventSource_CC2               ((u16)0x0004)
447
#define TIM1_EventSource_CC3               ((u16)0x0008)
448
#define TIM1_EventSource_CC4               ((u16)0x0010)
449
#define TIM1_EventSource_COM               ((u16)0x0020)
450
#define TIM1_EventSource_Trigger           ((u16)0x0040)
451
#define TIM1_EventSource_Break             ((u16)0x0080)
452
 
453
#define IS_TIM1_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFF00) == 0x0000) && (SOURCE != 0x0000))
454
 
455
 
456
/* TIM1 Update Source -------------------------------------------------------*/
457
#define TIM1_UpdateSource_Global           ((u16)0x0000)
458
#define TIM1_UpdateSource_Regular          ((u16)0x0001)
459
 
460
#define IS_TIM1_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM1_UpdateSource_Global) || \
461
                                       (SOURCE == TIM1_UpdateSource_Regular))
462
 
463
/* TIM1 Ouput Compare Preload State ------------------------------------------*/
464
#define TIM1_OCPreload_Enable              ((u16)0x0001)
465
#define TIM1_OCPreload_Disable             ((u16)0x0000)
466
 
467
#define IS_TIM1_OCPRELOAD_STATE(STATE) ((STATE == TIM1_OCPreload_Enable) || \
468
                                        (STATE == TIM1_OCPreload_Disable))
469
 
470
/* TIM1 Ouput Compare Fast State ---------------------------------------------*/
471
#define TIM1_OCFast_Enable                 ((u16)0x0001)
472
#define TIM1_OCFast_Disable                ((u16)0x0000)
473
 
474
#define IS_TIM1_OCFAST_STATE(STATE) ((STATE == TIM1_OCFast_Enable) || \
475
                                     (STATE == TIM1_OCFast_Disable))
476
 
477
/* TIM1 Trigger Output Source -----------------------------------------------*/
478
#define TIM1_TRGOSource_Reset              ((u16)0x0000)
479
#define TIM1_TRGOSource_Enable             ((u16)0x0010)
480
#define TIM1_TRGOSource_Update             ((u16)0x0020)
481
#define TIM1_TRGOSource_OC1                ((u16)0x0030)
482
#define TIM1_TRGOSource_OC1Ref             ((u16)0x0040)
483
#define TIM1_TRGOSource_OC2Ref             ((u16)0x0050)
484
#define TIM1_TRGOSource_OC3Ref             ((u16)0x0060)
485
#define TIM1_TRGOSource_OC4Ref             ((u16)0x0070)
486
 
487
#define IS_TIM1_TRGO_SOURCE(SOURCE) ((SOURCE == TIM1_TRGOSource_Reset) || \
488
                                     (SOURCE == TIM1_TRGOSource_Enable) || \
489
                                     (SOURCE == TIM1_TRGOSource_Update) || \
490
                                     (SOURCE == TIM1_TRGOSource_OC1) || \
491
                                     (SOURCE == TIM1_TRGOSource_OC1Ref) || \
492
                                     (SOURCE == TIM1_TRGOSource_OC2Ref) || \
493
                                     (SOURCE == TIM1_TRGOSource_OC3Ref) || \
494
                                     (SOURCE == TIM1_TRGOSource_OC4Ref))
495
 
496
/* TIM1 Slave Mode ----------------------------------------------------------*/
497
#define TIM1_SlaveMode_Reset               ((u16)0x0004)
498
#define TIM1_SlaveMode_Gated               ((u16)0x0005)
499
#define TIM1_SlaveMode_Trigger             ((u16)0x0006)
500
#define TIM1_SlaveMode_External1           ((u16)0x0007)
501
 
502
#define IS_TIM1_SLAVE_MODE(MODE) ((MODE == TIM1_SlaveMode_Reset) || \
503
                                  (MODE == TIM1_SlaveMode_Gated) || \
504
                                  (MODE == TIM1_SlaveMode_Trigger) || \
505
                                  (MODE == TIM1_SlaveMode_External1))
506
 
507
/* TIM1 TIx External Clock Source -------------------------------------------*/
508
#define TIM1_TIxExternalCLK1Source_TI1     ((u16)0x0050)
509
#define TIM1_TIxExternalCLK1Source_TI2     ((u16)0x0060)
510
#define TIM1_TIxExternalCLK1Source_TI1ED   ((u16)0x0040)
511
 
512
#define IS_TIM1_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM1_TIxExternalCLK1Source_TI1) || \
513
                                       (SOURCE == TIM1_TIxExternalCLK1Source_TI2) || \
514
                                       (SOURCE == TIM1_TIxExternalCLK1Source_TI1ED))
515
 
516
/* TIM1 Master Slave Mode ---------------------------------------------------*/
517
#define TIM1_MasterSlaveMode_Enable        ((u16)0x0001)
518
#define TIM1_MasterSlaveMode_Disable       ((u16)0x0000)
519
 
520
#define IS_TIM1_MSM_STATE(STATE) ((STATE == TIM1_MasterSlaveMode_Enable) || \
521
                                  (STATE == TIM1_MasterSlaveMode_Disable))
522
 
523
/* TIM1 Flags ---------------------------------------------------------------*/
524
#define TIM1_FLAG_Update                   ((u16)0x0001)
525
#define TIM1_FLAG_CC1                      ((u16)0x0002)
526
#define TIM1_FLAG_CC2                      ((u16)0x0004)
527
#define TIM1_FLAG_CC3                      ((u16)0x0008)
528
#define TIM1_FLAG_CC4                      ((u16)0x0010)
529
#define TIM1_FLAG_COM                      ((u16)0x0020)
530
#define TIM1_FLAG_Trigger                  ((u16)0x0040)
531
#define TIM1_FLAG_Break                    ((u16)0x0080)
532
#define TIM1_FLAG_CC1OF                    ((u16)0x0200)
533
#define TIM1_FLAG_CC2OF                    ((u16)0x0400)
534
#define TIM1_FLAG_CC3OF                    ((u16)0x0800)
535
#define TIM1_FLAG_CC4OF                    ((u16)0x1000)
536
 
537
#define IS_TIM1_GET_FLAG(FLAG) ((FLAG == TIM1_FLAG_Update) || \
538
                                (FLAG == TIM1_FLAG_CC1) || \
539
                                (FLAG == TIM1_FLAG_CC2) || \
540
                                (FLAG == TIM1_FLAG_CC3) || \
541
                                (FLAG == TIM1_FLAG_CC4) || \
542
                                (FLAG == TIM1_FLAG_COM) || \
543
                                (FLAG == TIM1_FLAG_Trigger) || \
544
                                (FLAG == TIM1_FLAG_Break) || \
545
                                (FLAG == TIM1_FLAG_CC1OF) || \
546
                                (FLAG == TIM1_FLAG_CC2OF) || \
547
                                (FLAG == TIM1_FLAG_CC3OF) || \
548
                                (FLAG == TIM1_FLAG_CC4OF))
549
 
550
#define IS_TIM1_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE100) == 0x0000) && (FLAG != 0x0000))
551
 
552
 
553
/* Exported macro ------------------------------------------------------------*/
554
/* Exported functions --------------------------------------------------------*/
555
 
556
void TIM1_DeInit(void);
557
void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);
558
void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
559
void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
560
void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
561
void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
562
void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct);
563
void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
564
void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
565
void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);
566
void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
567
void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
568
void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct);
569
void TIM1_Cmd(FunctionalState NewState);
570
void TIM1_CtrlPWMOutputs(FunctionalState Newstate);
571
void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState);
572
void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength);
573
void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate);
574
void TIM1_InternalClockConfig(void);
575
void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
576
                             u16 ExtTRGFilter);
577
void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
578
                             u16 ExtTRGFilter);
579
void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource);
580
void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource, u16 TIM1_ICPolarity,
581
                                u8 ICFilter);
582
void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource);
583
void TIM1_UpdateDisableConfig(FunctionalState Newstate);
584
void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource);
585
void TIM1_SelectHallSensor(FunctionalState Newstate);
586
void TIM1_SelectOnePulseMode(u16 TIM1_OPMode);
587
void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource);
588
void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode);
589
void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode);
590
void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity,
591
                                u16 TIM1_IC2Polarity);
592
void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode);
593
void TIM1_CounterModeConfig(u16 TIM1_CounterMode);
594
void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction);
595
void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction);
596
void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction);
597
void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction);
598
void TIM1_ARRPreloadConfig(FunctionalState Newstate);
599
void TIM1_SelectCOM(FunctionalState Newstate);
600
void TIM1_SelectCCDMA(FunctionalState Newstate);
601
void TIM1_CCPreloadControl(FunctionalState Newstate);
602
void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload);
603
void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload);
604
void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload);
605
void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload);
606
void TIM1_OC1FastConfig(u16 TIM1_OCFast);
607
void TIM1_OC2FastConfig(u16 TIM1_OCFast);
608
void TIM1_OC3FastConfig(u16 TIM1_OCFast);
609
void TIM1_OC4FastConfig(u16 TIM1_OCFast);
610
void TIM1_GenerateEvent(u16 TIM1_EventSource);
611
void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity);
612
void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity);
613
void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity);
614
void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity);
615
void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity);
616
void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity);
617
void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity);
618
void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate);
619
void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate);
620
void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode);
621
void TIM1_SetAutoreload(u16 Autoreload);
622
void TIM1_SetCompare1(u16 Compare1);
623
void TIM1_SetCompare2(u16 Compare2);
624
void TIM1_SetCompare3(u16 Compare3);
625
void TIM1_SetCompare4(u16 Compare4);
626
void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler);
627
void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler);
628
void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler);
629
void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler);
630
void TIM1_SetClockDivision(u16 TIM1_CKD);
631
u16 TIM1_GetCapture1(void);
632
u16 TIM1_GetCapture2(void);
633
u16 TIM1_GetCapture3(void);
634
u16 TIM1_GetCapture4(void);
635
u16 TIM1_GetCounter(void);
636
u16 TIM1_GetPrescaler(void);
637
FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG);
638
void TIM1_ClearFlag(u16 TIM1_Flag);
639
ITStatus TIM1_GetITStatus(u16 TIM1_IT);
640
void TIM1_ClearITPendingBit(u16 TIM1_IT);
641
 
642
#endif /*__STM32F10x_TIM1_H */
643
 
644
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.