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jeremybenn |
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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* File Name : stm32fxxx_eth.h
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* Author : MCD Application Team
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* Version : V0.0.1
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* Date : 12/17/2008
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* Desciption : This file contains all the functions prototypes for the
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* ETHERNET firmware library.
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********************************************************************************
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32FXXX_ETH_H
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#define __STM32FXXX_ETH_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32fxxx_eth_map.h"
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/* Exported types ------------------------------------------------------------*/
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/* ETHERNET MAC Init structure definition */
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typedef struct {
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/* MAC ----------------------------------*/
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u32 ETH_AutoNegotiation; /* Selects or not the AutoNegotiation with the external PHY */
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u32 ETH_Watchdog; /* Enable/disable Watchdog timer */
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u32 ETH_Jabber; /* Enable/disable Jabber timer */
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u32 ETH_JumboFrame; /* Enable/disable Jumbo frame */
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u32 ETH_InterFrameGap; /* Selects minimum IFG between frames during transmission */
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u32 ETH_CarrierSense; /* Enable/disable Carrier Sense */
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u32 ETH_Speed; /* Indicates the Ethernet speed: 10/100 Mbps */
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u32 ETH_ReceiveOwn; /* Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */
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u32 ETH_LoopbackMode; /* Enable/disable internal MAC MII Loopback mode */
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u32 ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */
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u32 ETH_ChecksumOffload; /* Enable/disable the calculation of complement sum of all received Ethernet frame payloads */
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u32 ETH_RetryTransmission; /* Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */
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u32 ETH_AutomaticPadCRCStrip; /* Enable/disable Automatic MAC Pad/CRC Stripping */
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u32 ETH_BackOffLimit; /* Selects the BackOff limit value */
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u32 ETH_DeferralCheck; /* Enable/disable deferral check function (Half-Duplex mode) */
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u32 ETH_ReceiveAll; /* Enable/disable all frames reception by the MAC (No fitering)*/
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u32 ETH_SourceAddrFilter; /* Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */
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u32 ETH_PassControlFrames; /* Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */
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u32 ETH_BroadcastFramesReception; /* Enable/disable reception of Broadcast Frames */
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u32 ETH_DestinationAddrFilter; /* Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */
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u32 ETH_PromiscuousMode; /* Enable/disable Promiscuous Mode */
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u32 ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */
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u32 ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */
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u32 ETH_HashTableHigh; /* This field contains the higher 32 bits of Hash table. */
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u32 ETH_HashTableLow; /* This field contains the lower 32 bits of Hash table. */
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u32 ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the transmit control frame */
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u32 ETH_ZeroQuantaPause; /* Enable/disable the automatic generation of Zero-Quanta Pause Control frames */
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u32 ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */
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u32 ETH_UnicastPauseFrameDetect; /* Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */
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u32 ETH_ReceiveFlowControl; /* Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */
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u32 ETH_TransmitFlowControl; /* Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */
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u32 ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */
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u32 ETH_VLANTagIdentifier; /* VLAN tag identifier for receive frames */
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/* DMA --------------------------*/
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u32 ETH_DropTCPIPChecksumErrorFrame; /* Enable/disable Dropping of TCP/IP Checksum Error Frames */
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u32 ETH_ReceiveStoreForward; /* Enable/disable Receive store and forward */
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u32 ETH_FlushReceivedFrame; /* Enable/disable flushing of received frames */
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u32 ETH_TransmitStoreForward; /* Enable/disable Transmit store and forward */
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u32 ETH_TransmitThresholdControl; /* Selects the Transmit Threshold Control */
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u32 ETH_ForwardErrorFrames; /* Enable/disable forward to DMA of all frames except runt error frames */
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u32 ETH_ForwardUndersizedGoodFrames; /* Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */
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u32 ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO */
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u32 ETH_SecondFrameOperate; /* Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */
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u32 ETH_AddressAlignedBeats; /* Enable/disable Address Aligned Beats */
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u32 ETH_FixedBurst; /* Enable/disable the AHB Master interface fixed burst transfers */
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u32 ETH_RxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Rx DMA transaction */
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u32 ETH_TxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Tx DMA transaction */
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u32 ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */
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u32 ETH_DMAArbitration; /* Selects DMA Tx/Rx arbitration */
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}ETH_InitTypeDef;
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/*----------------------------------------------------------------------------*/
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/* DMA descriptors types */
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/*----------------------------------------------------------------------------*/
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/* ETHERNET DMA Desciptors data structure definition */
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typedef struct {
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volatile u32 Status; /* Status */
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volatile u32 ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */
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volatile u32 Buffer1Addr; /* Buffer1 address pointer */
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volatile u32 Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */
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} ETH_DMADESCTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/* ETHERNET Frames defines */
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/*----------------------------------------------------------------------------*/
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/* ENET Buffers setting */
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#define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
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#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
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#define ETH_CRC 4 /* Ethernet CRC */
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#define ETH_EXTRA 2 /* Extra bytes in some cases */
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#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */
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#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */
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#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */
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#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */
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/*--------------------------------------------------------*/
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/* Ethernet DMA descriptors registers bits definition */
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/*--------------------------------------------------------*/
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/* DMA Tx Desciptor ---------------------------------------------------------*/
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/*-----------------------------------------------------------------------------------------------
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TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | |
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-----------------------------------------------------------------------------------------------
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TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
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-----------------------------------------------------------------------------------------------
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TDES2 | Buffer1 Address [31:0] |
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-----------------------------------------------------------------------------------------------
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TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
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----------------------------------------------------------------------------------------------*/
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/* Bit definition of TDES0 register: DMA Tx descriptor status register */
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#define ETH_DMATxDesc_OWN (0x80000000UL) /* OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMATxDesc_IC ((u32)0x40000000) /* Interrupt on Completion */
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#define ETH_DMATxDesc_LS ((u32)0x20000000) /* Last Segment */
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#define ETH_DMATxDesc_FS ((u32)0x10000000) /* First Segment */
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#define ETH_DMATxDesc_DC ((u32)0x08000000) /* Disable CRC */
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#define ETH_DMATxDesc_DP ((u32)0x04000000) /* Disable Padding */
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#define ETH_DMATxDesc_TTSE ((u32)0x02000000) /* Transmit Time Stamp Enable */
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#define ETH_DMATxDesc_CIC ((u32)0x00C00000) /* Checksum Insertion Control: 4 cases */
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#define ETH_DMATxDesc_CIC_ByPass ((u32)0x00000000) /* Do Nothing: Checksum Engine is bypassed */
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#define ETH_DMATxDesc_CIC_IPV4Header ((u32)0x00400000) /* IPV4 header Checksum Insertion */
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#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((u32)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */
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#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((u32)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */
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#define ETH_DMATxDesc_TER ((u32)0x00200000) /* Transmit End of Ring */
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#define ETH_DMATxDesc_TCH ((u32)0x00100000) /* Second Address Chained */
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#define ETH_DMATxDesc_TTSS ((u32)0x00020000) /* Tx Time Stamp Status */
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#define ETH_DMATxDesc_IHE ((u32)0x00010000) /* IP Header Error */
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#define ETH_DMATxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
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#define ETH_DMATxDesc_JT ((u32)0x00004000) /* Jabber Timeout */
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#define ETH_DMATxDesc_FF ((u32)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */
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#define ETH_DMATxDesc_PCE ((u32)0x00001000) /* Payload Checksum Error */
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#define ETH_DMATxDesc_LCA ((u32)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */
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#define ETH_DMATxDesc_NC ((u32)0x00000400) /* No Carrier: no carrier signal from the tranceiver */
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#define ETH_DMATxDesc_LCO ((u32)0x00000200) /* Late Collision: transmission aborted due to collision */
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#define ETH_DMATxDesc_EC ((u32)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */
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#define ETH_DMATxDesc_VF ((u32)0x00000080) /* VLAN Frame */
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#define ETH_DMATxDesc_CC ((u32)0x00000078) /* Collision Count */
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#define ETH_DMATxDesc_ED ((u32)0x00000004) /* Excessive Deferral */
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#define ETH_DMATxDesc_UF ((u32)0x00000002) /* Underflow Error: late data arrival from the memory */
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#define ETH_DMATxDesc_DB ((u32)0x00000001) /* Deferred Bit */
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/* Bit definition of TDES1 register */
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#define ETH_DMATxDesc_TBS2 ((u32)0x1FFF0000) /* Transmit Buffer2 Size */
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#define ETH_DMATxDesc_TBS1 ((u32)0x00001FFF) /* Transmit Buffer1 Size */
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/* Bit definition of TDES2 register */
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#define ETH_DMATxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */
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/* Bit definition of TDES3 register */
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#define ETH_DMATxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */
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/* DMA Rx descriptor ---------------------------------------------------------*/
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/*---------------------------------------------------------------------------------------------------------------------
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RDES0 | OWN(31) | Status [30:0] |
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---------------------------------------------------------------------------------------------------------------------
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RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
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---------------------------------------------------------------------------------------------------------------------
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RDES2 | Buffer1 Address [31:0] |
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---------------------------------------------------------------------------------------------------------------------
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RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
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--------------------------------------------------------------------------------------------------------------------*/
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/* Bit definition of RDES0 register: DMA Rx descriptor status register */
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#define ETH_DMARxDesc_OWN ((u32)0x80000000) /* OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMARxDesc_AFM ((u32)0x40000000) /* DA Filter Fail for the rx frame */
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#define ETH_DMARxDesc_FL ((u32)0x3FFF0000) /* Receive descriptor frame length */
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#define ETH_DMARxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
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#define ETH_DMARxDesc_DE ((u32)0x00004000) /* Desciptor error: no more descriptors for receive frame */
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#define ETH_DMARxDesc_SAF ((u32)0x00002000) /* SA Filter Fail for the received frame */
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#define ETH_DMARxDesc_LE ((u32)0x00001000) /* Frame size not matching with length field */
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#define ETH_DMARxDesc_OE ((u32)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */
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#define ETH_DMARxDesc_VLAN ((u32)0x00000400) /* VLAN Tag: received frame is a VLAN frame */
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#define ETH_DMARxDesc_FS ((u32)0x00000200) /* First descriptor of the frame */
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#define ETH_DMARxDesc_LS ((u32)0x00000100) /* Last descriptor of the frame */
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#define ETH_DMARxDesc_IPV4HCE ((u32)0x00000080) /* IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error */
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#define ETH_DMARxDesc_RxLongFrame ((u32)0x00000080) /* (Giant Frame)Rx - frame is longer than 1518/1522 */
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#define ETH_DMARxDesc_LC ((u32)0x00000040) /* Late collision occurred during reception */
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#define ETH_DMARxDesc_FT ((u32)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */
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#define ETH_DMARxDesc_RWT ((u32)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */
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#define ETH_DMARxDesc_RE ((u32)0x00000008) /* Receive error: error reported by MII interface */
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#define ETH_DMARxDesc_DBE ((u32)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */
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#define ETH_DMARxDesc_CE ((u32)0x00000002) /* CRC error */
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#define ETH_DMARxDesc_MAMPCE ((u32)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
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/* Bit definition of RDES1 register */
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#define ETH_DMARxDesc_DIC ((u32)0x80000000) /* Disable Interrupt on Completion */
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#define ETH_DMARxDesc_RBS2 ((u32)0x1FFF0000) /* Receive Buffer2 Size */
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#define ETH_DMARxDesc_RER ((u32)0x00008000) /* Receive End of Ring */
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#define ETH_DMARxDesc_RCH ((u32)0x00004000) /* Second Address Chained */
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#define ETH_DMARxDesc_RBS1 ((u32)0x00001FFF) /* Receive Buffer1 Size */
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/* Bit definition of RDES2 register */
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#define ETH_DMARxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */
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/* Bit definition of RDES3 register */
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#define ETH_DMARxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */
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/*----------------------------------------------------------------------------*/
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/* Desciption of common PHY registers */
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/*----------------------------------------------------------------------------*/
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/* PHY Read/write Timeouts */
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#define PHY_READ_TO ((u32)0x0004FFFF)
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#define PHY_WRITE_TO ((u32)0x0004FFFF)
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/* PHY Reset Delay */
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#define PHY_ResetDelay ((u32)0x000FFFFF)
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/* PHY Config Delay */
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#define PHY_ConfigDelay ((u32)0x00FFFFFF)
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/* PHY Register address */
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#define PHY_BCR 0 /* Tranceiver Basic Control Register */
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#define PHY_BSR 1 /* Tranceiver Basic Status Register */
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/* PHY basic Control register */
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#define PHY_Reset ((u16)0x8000) /* PHY Reset */
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#define PHY_Loopback ((u16)0x4000) /* Select loop-back mode */
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#define PHY_FULLDUPLEX_100M ((u16)0x2100) /* Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M ((u16)0x2000) /* Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M ((u16)0x0100) /* Set the full-duplex mode at 10 Mb/s */
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#define PHY_HALFDUPLEX_10M ((u16)0x0000) /* Set the half-duplex mode at 10 Mb/s */
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#define PHY_AutoNegotiation ((u16)0x1000) /* Enable auto-negotiation function */
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#define PHY_Restart_AutoNegotiation ((u16)0x0200) /* Restart auto-negotiation function */
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#define PHY_Powerdown ((u16)0x0800) /* Select the power down mode */
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#define PHY_Isolate ((u16)0x0400) /* Isolate PHY from MII */
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/* PHY basic status register */
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|
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#define PHY_AutoNego_Complete ((u16)0x0020) /* Auto-Negotioation process completed */
|
| 238 |
|
|
#define PHY_Linked_Status ((u16)0x0004) /* Valid link established */
|
| 239 |
|
|
#define PHY_Jabber_detection ((u16)0x0002) /* Jabber condition detected */
|
| 240 |
|
|
|
| 241 |
|
|
/* The PHY status register value change from a PHY to another so the user have to update
|
| 242 |
|
|
this value depending on the used external PHY */
|
| 243 |
|
|
/* For LAN8700 */
|
| 244 |
|
|
//#define PHY_SR 31 /* Tranceiver Status Register */
|
| 245 |
|
|
/* For DP83848 */
|
| 246 |
|
|
#define PHY_SR 16 /* Tranceiver Status Register */
|
| 247 |
|
|
|
| 248 |
|
|
/* PHY status register */
|
| 249 |
|
|
/* The Speed and Duplex mask values change from a PHY to another so the user have to update
|
| 250 |
|
|
this value depending on the used external PHY */
|
| 251 |
|
|
/* For LAN8700 */
|
| 252 |
|
|
//#define PHY_Speed_Status ((u16)0x0004) /* Configured information of Speed: 10Mbps */
|
| 253 |
|
|
//#define PHY_Duplex_Status ((u16)0x0010) /* Configured information of Duplex: Full-duplex */
|
| 254 |
|
|
/* For DP83848 */
|
| 255 |
|
|
#define PHY_Speed_Status ((u16)0x0002) /* Configured information of Speed: 10Mbps */
|
| 256 |
|
|
#define PHY_Duplex_Status ((u16)0x0004) /* Configured information of Duplex: Full-duplex */
|
| 257 |
|
|
|
| 258 |
|
|
#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
|
| 259 |
|
|
#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
|
| 260 |
|
|
((REG) == PHY_BSR) || \
|
| 261 |
|
|
((REG) == PHY_SR))
|
| 262 |
|
|
|
| 263 |
|
|
/*----------------------------------------------------------------------------*/
|
| 264 |
|
|
/* MAC defines */
|
| 265 |
|
|
/*----------------------------------------------------------------------------*/
|
| 266 |
|
|
/* ETHERNET AutoNegotiation --------------------------------------------------*/
|
| 267 |
|
|
#define ETH_AutoNegotiation_Enable ((u32)0x00000001)
|
| 268 |
|
|
#define ETH_AutoNegotiation_Disable ((u32)0x00000000)
|
| 269 |
|
|
|
| 270 |
|
|
#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
|
| 271 |
|
|
((CMD) == ETH_AutoNegotiation_Disable))
|
| 272 |
|
|
|
| 273 |
|
|
/* ETHERNET watchdog ---------------------------------------------------------*/
|
| 274 |
|
|
#define ETH_Watchdog_Enable ((u32)0x00000000)
|
| 275 |
|
|
#define ETH_Watchdog_Disable ((u32)0x00800000)
|
| 276 |
|
|
|
| 277 |
|
|
#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
|
| 278 |
|
|
((CMD) == ETH_Watchdog_Disable))
|
| 279 |
|
|
|
| 280 |
|
|
/* ETHERNET Jabber -----------------------------------------------------------*/
|
| 281 |
|
|
#define ETH_Jabber_Enable ((u32)0x00000000)
|
| 282 |
|
|
#define ETH_Jabber_Disable ((u32)0x00400000)
|
| 283 |
|
|
|
| 284 |
|
|
#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
|
| 285 |
|
|
((CMD) == ETH_Jabber_Disable))
|
| 286 |
|
|
|
| 287 |
|
|
/* ETHERNET Jumbo Frame ------------------------------------------------------*/
|
| 288 |
|
|
#define ETH_JumboFrame_Enable ((u32)0x00100000)
|
| 289 |
|
|
#define ETH_JumboFrame_Disable ((u32)0x00000000)
|
| 290 |
|
|
|
| 291 |
|
|
#define IS_ETH_JUMBO_FRAME(CMD) (((CMD) == ETH_JumboFrame_Enable) || \
|
| 292 |
|
|
((CMD) == ETH_JumboFrame_Disable))
|
| 293 |
|
|
|
| 294 |
|
|
/* ETHERNET Inter Frame Gap --------------------------------------------------*/
|
| 295 |
|
|
#define ETH_InterFrameGap_96Bit ((u32)0x00000000) /* minimum IFG between frames during transmission is 96Bit */
|
| 296 |
|
|
#define ETH_InterFrameGap_88Bit ((u32)0x00020000) /* minimum IFG between frames during transmission is 88Bit */
|
| 297 |
|
|
#define ETH_InterFrameGap_80Bit ((u32)0x00040000) /* minimum IFG between frames during transmission is 80Bit */
|
| 298 |
|
|
#define ETH_InterFrameGap_72Bit ((u32)0x00060000) /* minimum IFG between frames during transmission is 72Bit */
|
| 299 |
|
|
#define ETH_InterFrameGap_64Bit ((u32)0x00080000) /* minimum IFG between frames during transmission is 64Bit */
|
| 300 |
|
|
#define ETH_InterFrameGap_56Bit ((u32)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */
|
| 301 |
|
|
#define ETH_InterFrameGap_48Bit ((u32)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */
|
| 302 |
|
|
#define ETH_InterFrameGap_40Bit ((u32)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */
|
| 303 |
|
|
|
| 304 |
|
|
#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
|
| 305 |
|
|
((GAP) == ETH_InterFrameGap_88Bit) || \
|
| 306 |
|
|
((GAP) == ETH_InterFrameGap_80Bit) || \
|
| 307 |
|
|
((GAP) == ETH_InterFrameGap_72Bit) || \
|
| 308 |
|
|
((GAP) == ETH_InterFrameGap_64Bit) || \
|
| 309 |
|
|
((GAP) == ETH_InterFrameGap_56Bit) || \
|
| 310 |
|
|
((GAP) == ETH_InterFrameGap_48Bit) || \
|
| 311 |
|
|
((GAP) == ETH_InterFrameGap_40Bit))
|
| 312 |
|
|
|
| 313 |
|
|
/* ETHERNET Carrier Sense ----------------------------------------------------*/
|
| 314 |
|
|
#define ETH_CarrierSense_Enable ((u32)0x00000000)
|
| 315 |
|
|
#define ETH_CarrierSense_Disable ((u32)0x00010000)
|
| 316 |
|
|
|
| 317 |
|
|
#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
|
| 318 |
|
|
((CMD) == ETH_CarrierSense_Disable))
|
| 319 |
|
|
|
| 320 |
|
|
/* ETHERNET Speed ------------------------------------------------------------*/
|
| 321 |
|
|
#define ETH_Speed_10M ((u32)0x00000000)
|
| 322 |
|
|
#define ETH_Speed_100M ((u32)0x00004000)
|
| 323 |
|
|
|
| 324 |
|
|
#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
|
| 325 |
|
|
((SPEED) == ETH_Speed_100M))
|
| 326 |
|
|
|
| 327 |
|
|
/* ETHERNET Receive Own ------------------------------------------------------*/
|
| 328 |
|
|
#define ETH_ReceiveOwn_Enable ((u32)0x00000000)
|
| 329 |
|
|
#define ETH_ReceiveOwn_Disable ((u32)0x00002000)
|
| 330 |
|
|
|
| 331 |
|
|
#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
|
| 332 |
|
|
((CMD) == ETH_ReceiveOwn_Disable))
|
| 333 |
|
|
|
| 334 |
|
|
/* ETHERNET Loop back Mode ---------------------------------------------------*/
|
| 335 |
|
|
#define ETH_LoopbackMode_Enable ((u32)0x00001000)
|
| 336 |
|
|
#define ETH_LoopbackMode_Disable ((u32)0x00000000)
|
| 337 |
|
|
|
| 338 |
|
|
#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
|
| 339 |
|
|
((CMD) == ETH_LoopbackMode_Disable))
|
| 340 |
|
|
|
| 341 |
|
|
/* ETHERNET Duplex mode ------------------------------------------------------*/
|
| 342 |
|
|
#define ETH_Mode_FullDuplex ((u32)0x00000800)
|
| 343 |
|
|
#define ETH_Mode_HalfDuplex ((u32)0x00000000)
|
| 344 |
|
|
|
| 345 |
|
|
#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
|
| 346 |
|
|
((MODE) == ETH_Mode_HalfDuplex))
|
| 347 |
|
|
|
| 348 |
|
|
/* ETHERNET Checksum Offload -------------------------------------------------*/
|
| 349 |
|
|
#define ETH_ChecksumOffload_Enable ((u32)0x00000400)
|
| 350 |
|
|
#define ETH_ChecksumOffload_Disable ((u32)0x00000000)
|
| 351 |
|
|
|
| 352 |
|
|
#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
|
| 353 |
|
|
((CMD) == ETH_ChecksumOffload_Disable))
|
| 354 |
|
|
|
| 355 |
|
|
/* ETHERNET Retry Transmission -----------------------------------------------*/
|
| 356 |
|
|
#define ETH_RetryTransmission_Enable ((u32)0x00000000)
|
| 357 |
|
|
#define ETH_RetryTransmission_Disable ((u32)0x00000200)
|
| 358 |
|
|
|
| 359 |
|
|
#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
|
| 360 |
|
|
((CMD) == ETH_RetryTransmission_Disable))
|
| 361 |
|
|
|
| 362 |
|
|
/* ETHERNET Automatic Pad/CRC Strip ------------------------------------------*/
|
| 363 |
|
|
#define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080)
|
| 364 |
|
|
#define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000)
|
| 365 |
|
|
|
| 366 |
|
|
#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
|
| 367 |
|
|
((CMD) == ETH_AutomaticPadCRCStrip_Disable))
|
| 368 |
|
|
|
| 369 |
|
|
/* ETHERNET Back-Off limit ---------------------------------------------------*/
|
| 370 |
|
|
#define ETH_BackOffLimit_10 ((u32)0x00000000)
|
| 371 |
|
|
#define ETH_BackOffLimit_8 ((u32)0x00000020)
|
| 372 |
|
|
#define ETH_BackOffLimit_4 ((u32)0x00000040)
|
| 373 |
|
|
#define ETH_BackOffLimit_1 ((u32)0x00000060)
|
| 374 |
|
|
|
| 375 |
|
|
#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
|
| 376 |
|
|
((LIMIT) == ETH_BackOffLimit_8) || \
|
| 377 |
|
|
((LIMIT) == ETH_BackOffLimit_4) || \
|
| 378 |
|
|
((LIMIT) == ETH_BackOffLimit_1))
|
| 379 |
|
|
|
| 380 |
|
|
/* ETHERNET Deferral Check ---------------------------------------------------*/
|
| 381 |
|
|
#define ETH_DeferralCheck_Enable ((u32)0x00000010)
|
| 382 |
|
|
#define ETH_DeferralCheck_Disable ((u32)0x00000000)
|
| 383 |
|
|
|
| 384 |
|
|
#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
|
| 385 |
|
|
((CMD) == ETH_DeferralCheck_Disable))
|
| 386 |
|
|
|
| 387 |
|
|
/* ETHERNET Receive All ------------------------------------------------------*/
|
| 388 |
|
|
#define ETH_ReceiveAll_Enable ((u32)0x80000000)
|
| 389 |
|
|
#define ETH_ReceiveAll_Disable ((u32)0x00000000)
|
| 390 |
|
|
|
| 391 |
|
|
#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
|
| 392 |
|
|
((CMD) == ETH_ReceiveAll_Disable))
|
| 393 |
|
|
|
| 394 |
|
|
/* ETHERNET Source Addr Filter ------------------------------------------------*/
|
| 395 |
|
|
#define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200)
|
| 396 |
|
|
#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300)
|
| 397 |
|
|
#define ETH_SourceAddrFilter_Disable ((u32)0x00000000)
|
| 398 |
|
|
|
| 399 |
|
|
#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
|
| 400 |
|
|
((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
|
| 401 |
|
|
((CMD) == ETH_SourceAddrFilter_Disable))
|
| 402 |
|
|
|
| 403 |
|
|
/* ETHERNET Pass Control Frames ----------------------------------------------*/
|
| 404 |
|
|
#define ETH_PassControlFrames_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */
|
| 405 |
|
|
#define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
|
| 406 |
|
|
#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
|
| 407 |
|
|
|
| 408 |
|
|
#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
|
| 409 |
|
|
((PASS) == ETH_PassControlFrames_ForwardAll) || \
|
| 410 |
|
|
((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
|
| 411 |
|
|
|
| 412 |
|
|
/* ETHERNET Broadcast Frames Reception ---------------------------------------*/
|
| 413 |
|
|
#define ETH_BroadcastFramesReception_Enable ((u32)0x00000000)
|
| 414 |
|
|
#define ETH_BroadcastFramesReception_Disable ((u32)0x00000020)
|
| 415 |
|
|
|
| 416 |
|
|
#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
|
| 417 |
|
|
((CMD) == ETH_BroadcastFramesReception_Disable))
|
| 418 |
|
|
|
| 419 |
|
|
/* ETHERNET Destination Addr Filter ------------------------------------------*/
|
| 420 |
|
|
#define ETH_DestinationAddrFilter_Normal ((u32)0x00000000)
|
| 421 |
|
|
#define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008)
|
| 422 |
|
|
|
| 423 |
|
|
#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
|
| 424 |
|
|
((FILTER) == ETH_DestinationAddrFilter_Inverse))
|
| 425 |
|
|
|
| 426 |
|
|
/* ETHERNET Promiscuous Mode -------------------------------------------------*/
|
| 427 |
|
|
#define ETH_PromiscuousMode_Enable ((u32)0x00000001)
|
| 428 |
|
|
#define ETH_PromiscuousMode_Disable ((u32)0x00000000)
|
| 429 |
|
|
|
| 430 |
|
|
#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
|
| 431 |
|
|
((CMD) == ETH_PromiscuousMode_Disable))
|
| 432 |
|
|
|
| 433 |
|
|
/* ETHERNET multicast frames filter --------------------------------------------*/
|
| 434 |
|
|
#define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404)
|
| 435 |
|
|
#define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004)
|
| 436 |
|
|
#define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000)
|
| 437 |
|
|
#define ETH_MulticastFramesFilter_None ((u32)0x00000010)
|
| 438 |
|
|
|
| 439 |
|
|
#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
|
| 440 |
|
|
((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
|
| 441 |
|
|
((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
|
| 442 |
|
|
((FILTER) == ETH_MulticastFramesFilter_None))
|
| 443 |
|
|
|
| 444 |
|
|
/* ETHERNET unicast frames filter --------------------------------------------*/
|
| 445 |
|
|
#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402)
|
| 446 |
|
|
#define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002)
|
| 447 |
|
|
#define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000)
|
| 448 |
|
|
|
| 449 |
|
|
#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
|
| 450 |
|
|
((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
|
| 451 |
|
|
((FILTER) == ETH_UnicastFramesFilter_Perfect))
|
| 452 |
|
|
|
| 453 |
|
|
/* ETHERNET Pause Time ------------------------------------------------*/
|
| 454 |
|
|
#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
|
| 455 |
|
|
|
| 456 |
|
|
/* ETHERNET Zero Quanta Pause ------------------------------------------------*/
|
| 457 |
|
|
#define ETH_ZeroQuantaPause_Enable ((u32)0x00000000)
|
| 458 |
|
|
#define ETH_ZeroQuantaPause_Disable ((u32)0x00000080)
|
| 459 |
|
|
|
| 460 |
|
|
#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \
|
| 461 |
|
|
((CMD) == ETH_ZeroQuantaPause_Disable))
|
| 462 |
|
|
|
| 463 |
|
|
/* ETHERNET Pause Low Threshold ----------------------------------------------*/
|
| 464 |
|
|
#define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */
|
| 465 |
|
|
#define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */
|
| 466 |
|
|
#define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */
|
| 467 |
|
|
#define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */
|
| 468 |
|
|
|
| 469 |
|
|
#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
|
| 470 |
|
|
((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
|
| 471 |
|
|
((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
|
| 472 |
|
|
((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
|
| 473 |
|
|
|
| 474 |
|
|
/* ETHERNET Unicast Pause Frame Detect ---------------------------------------*/
|
| 475 |
|
|
#define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008)
|
| 476 |
|
|
#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000)
|
| 477 |
|
|
|
| 478 |
|
|
#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
|
| 479 |
|
|
((CMD) == ETH_UnicastPauseFrameDetect_Disable))
|
| 480 |
|
|
|
| 481 |
|
|
/* ETHERNET Receive Flow Control ---------------------------------------------*/
|
| 482 |
|
|
#define ETH_ReceiveFlowControl_Enable ((u32)0x00000004)
|
| 483 |
|
|
#define ETH_ReceiveFlowControl_Disable ((u32)0x00000000)
|
| 484 |
|
|
|
| 485 |
|
|
#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
|
| 486 |
|
|
((CMD) == ETH_ReceiveFlowControl_Disable))
|
| 487 |
|
|
|
| 488 |
|
|
/* ETHERNET Transmit Flow Control --------------------------------------------*/
|
| 489 |
|
|
#define ETH_TransmitFlowControl_Enable ((u32)0x00000002)
|
| 490 |
|
|
#define ETH_TransmitFlowControl_Disable ((u32)0x00000000)
|
| 491 |
|
|
|
| 492 |
|
|
#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
|
| 493 |
|
|
((CMD) == ETH_TransmitFlowControl_Disable))
|
| 494 |
|
|
|
| 495 |
|
|
/* ETHERNET VLAN Tag Comparison ----------------------------------------------*/
|
| 496 |
|
|
#define ETH_VLANTagComparison_12Bit ((u32)0x00010000)
|
| 497 |
|
|
#define ETH_VLANTagComparison_16Bit ((u32)0x00000000)
|
| 498 |
|
|
|
| 499 |
|
|
#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
|
| 500 |
|
|
((COMPARISON) == ETH_VLANTagComparison_16Bit))
|
| 501 |
|
|
|
| 502 |
|
|
#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
|
| 503 |
|
|
|
| 504 |
|
|
/* ETHERNET MAC Flags ---------------------------------------------------*/
|
| 505 |
|
|
#define ETH_MAC_FLAG_TST ((u32)0x00000200) /* Time stamp trigger flag (on MAC) */
|
| 506 |
|
|
#define ETH_MAC_FLAG_MMCT ((u32)0x00000040) /* MMC transmit flag */
|
| 507 |
|
|
#define ETH_MAC_FLAG_MMCR ((u32)0x00000020) /* MMC receive flag */
|
| 508 |
|
|
#define ETH_MAC_FLAG_MMC ((u32)0x00000010) /* MMC flag (on MAC) */
|
| 509 |
|
|
#define ETH_MAC_FLAG_PMT ((u32)0x00000008) /* PMT flag (on MAC) */
|
| 510 |
|
|
|
| 511 |
|
|
#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
|
| 512 |
|
|
((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
|
| 513 |
|
|
((FLAG) == ETH_MAC_FLAG_PMT))
|
| 514 |
|
|
|
| 515 |
|
|
/* ETHERNET MAC Interrupts ---------------------------------------------------*/
|
| 516 |
|
|
#define ETH_MAC_IT_TST ((u32)0x00000200) /* Time stamp trigger interrupt (on MAC) */
|
| 517 |
|
|
#define ETH_MAC_IT_MMCT ((u32)0x00000040) /* MMC transmit interrupt */
|
| 518 |
|
|
#define ETH_MAC_IT_MMCR ((u32)0x00000020) /* MMC receive interrupt */
|
| 519 |
|
|
#define ETH_MAC_IT_MMC ((u32)0x00000010) /* MMC interrupt (on MAC) */
|
| 520 |
|
|
#define ETH_MAC_IT_PMT ((u32)0x00000008) /* PMT interrupt (on MAC) */
|
| 521 |
|
|
|
| 522 |
|
|
#define IS_ETH_MAC_IT(IT) ((((IT) & (u32)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
|
| 523 |
|
|
#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
|
| 524 |
|
|
((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
|
| 525 |
|
|
((IT) == ETH_MAC_IT_PMT))
|
| 526 |
|
|
|
| 527 |
|
|
/* ETHERNET MAC addresses ----------------------------------------------------*/
|
| 528 |
|
|
#define ETH_MAC_Address0 ((u32)0x00000000)
|
| 529 |
|
|
#define ETH_MAC_Address1 ((u32)0x00000008)
|
| 530 |
|
|
#define ETH_MAC_Address2 ((u32)0x00000010)
|
| 531 |
|
|
#define ETH_MAC_Address3 ((u32)0x00000018)
|
| 532 |
|
|
|
| 533 |
|
|
#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
|
| 534 |
|
|
((ADDRESS) == ETH_MAC_Address1) || \
|
| 535 |
|
|
((ADDRESS) == ETH_MAC_Address2) || \
|
| 536 |
|
|
((ADDRESS) == ETH_MAC_Address3))
|
| 537 |
|
|
|
| 538 |
|
|
#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
|
| 539 |
|
|
((ADDRESS) == ETH_MAC_Address2) || \
|
| 540 |
|
|
((ADDRESS) == ETH_MAC_Address3))
|
| 541 |
|
|
|
| 542 |
|
|
/* ETHERNET MAC addresses filter: SA/DA filed of received frames ------------*/
|
| 543 |
|
|
#define ETH_MAC_AddressFilter_SA ((u32)0x00000000)
|
| 544 |
|
|
#define ETH_MAC_AddressFilter_DA ((u32)0x00000008)
|
| 545 |
|
|
|
| 546 |
|
|
#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
|
| 547 |
|
|
((FILTER) == ETH_MAC_AddressFilter_DA))
|
| 548 |
|
|
|
| 549 |
|
|
/* ETHERNET MAC addresses filter: Mask bytes ---------------------------------*/
|
| 550 |
|
|
#define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
| 551 |
|
|
#define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
| 552 |
|
|
#define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
| 553 |
|
|
#define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
| 554 |
|
|
#define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
| 555 |
|
|
#define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */
|
| 556 |
|
|
|
| 557 |
|
|
#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
|
| 558 |
|
|
((MASK) == ETH_MAC_AddressMask_Byte5) || \
|
| 559 |
|
|
((MASK) == ETH_MAC_AddressMask_Byte4) || \
|
| 560 |
|
|
((MASK) == ETH_MAC_AddressMask_Byte3) || \
|
| 561 |
|
|
((MASK) == ETH_MAC_AddressMask_Byte2) || \
|
| 562 |
|
|
((MASK) == ETH_MAC_AddressMask_Byte1))
|
| 563 |
|
|
|
| 564 |
|
|
/*----------------------------------------------------------------------------*/
|
| 565 |
|
|
/* Ethernet DMA Desciptors defines */
|
| 566 |
|
|
/*----------------------------------------------------------------------------*/
|
| 567 |
|
|
/* ETHERNET DMA Tx descriptor flags --------------------------------------------------------*/
|
| 568 |
|
|
#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
|
| 569 |
|
|
((FLAG) == ETH_DMATxDesc_IC) || \
|
| 570 |
|
|
((FLAG) == ETH_DMATxDesc_LS) || \
|
| 571 |
|
|
((FLAG) == ETH_DMATxDesc_FS) || \
|
| 572 |
|
|
((FLAG) == ETH_DMATxDesc_DC) || \
|
| 573 |
|
|
((FLAG) == ETH_DMATxDesc_DP) || \
|
| 574 |
|
|
((FLAG) == ETH_DMATxDesc_TTSE) || \
|
| 575 |
|
|
((FLAG) == ETH_DMATxDesc_TER) || \
|
| 576 |
|
|
((FLAG) == ETH_DMATxDesc_TCH) || \
|
| 577 |
|
|
((FLAG) == ETH_DMATxDesc_TTSS) || \
|
| 578 |
|
|
((FLAG) == ETH_DMATxDesc_IHE) || \
|
| 579 |
|
|
((FLAG) == ETH_DMATxDesc_ES) || \
|
| 580 |
|
|
((FLAG) == ETH_DMATxDesc_JT) || \
|
| 581 |
|
|
((FLAG) == ETH_DMATxDesc_FF) || \
|
| 582 |
|
|
((FLAG) == ETH_DMATxDesc_PCE) || \
|
| 583 |
|
|
((FLAG) == ETH_DMATxDesc_LCA) || \
|
| 584 |
|
|
((FLAG) == ETH_DMATxDesc_NC) || \
|
| 585 |
|
|
((FLAG) == ETH_DMATxDesc_LCO) || \
|
| 586 |
|
|
((FLAG) == ETH_DMATxDesc_EC) || \
|
| 587 |
|
|
((FLAG) == ETH_DMATxDesc_VF) || \
|
| 588 |
|
|
((FLAG) == ETH_DMATxDesc_CC) || \
|
| 589 |
|
|
((FLAG) == ETH_DMATxDesc_ED) || \
|
| 590 |
|
|
((FLAG) == ETH_DMATxDesc_UF) || \
|
| 591 |
|
|
((FLAG) == ETH_DMATxDesc_DB))
|
| 592 |
|
|
|
| 593 |
|
|
/* ETHERNET DMA Tx descriptor segment ----------------------------------------*/
|
| 594 |
|
|
#define ETH_DMATxDesc_LastSegment ((u32)0x40000000) /* Last Segment */
|
| 595 |
|
|
#define ETH_DMATxDesc_FirstSegment ((u32)0x20000000) /* First Segment */
|
| 596 |
|
|
|
| 597 |
|
|
#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
|
| 598 |
|
|
((SEGMENT) == ETH_DMATxDesc_FirstSegment))
|
| 599 |
|
|
|
| 600 |
|
|
/* ETHERNET DMA Tx descriptor Checksum Insertion Control --------------------*/
|
| 601 |
|
|
#define ETH_DMATxDesc_ChecksumByPass ((u32)0x00000000) /* Checksum engine bypass */
|
| 602 |
|
|
#define ETH_DMATxDesc_ChecksumIPV4Header ((u32)0x00400000) /* IPv4 header checksum insertion */
|
| 603 |
|
|
#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((u32)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
|
| 604 |
|
|
#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((u32)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */
|
| 605 |
|
|
|
| 606 |
|
|
#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
|
| 607 |
|
|
((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
|
| 608 |
|
|
((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
|
| 609 |
|
|
((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
|
| 610 |
|
|
|
| 611 |
|
|
/* ETHERNET DMA Tx Desciptor buffer size */
|
| 612 |
|
|
#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
|
| 613 |
|
|
|
| 614 |
|
|
/* ETHERNET DMA Rx descriptor flags --------------------------------------------------------*/
|
| 615 |
|
|
#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
|
| 616 |
|
|
((FLAG) == ETH_DMARxDesc_AFM) || \
|
| 617 |
|
|
((FLAG) == ETH_DMARxDesc_ES) || \
|
| 618 |
|
|
((FLAG) == ETH_DMARxDesc_DE) || \
|
| 619 |
|
|
((FLAG) == ETH_DMARxDesc_SAF) || \
|
| 620 |
|
|
((FLAG) == ETH_DMARxDesc_LE) || \
|
| 621 |
|
|
((FLAG) == ETH_DMARxDesc_OE) || \
|
| 622 |
|
|
((FLAG) == ETH_DMARxDesc_VLAN) || \
|
| 623 |
|
|
((FLAG) == ETH_DMARxDesc_FS) || \
|
| 624 |
|
|
((FLAG) == ETH_DMARxDesc_LS) || \
|
| 625 |
|
|
((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
|
| 626 |
|
|
((FLAG) == ETH_DMARxDesc_RxLongFrame) || \
|
| 627 |
|
|
((FLAG) == ETH_DMARxDesc_LC) || \
|
| 628 |
|
|
((FLAG) == ETH_DMARxDesc_FT) || \
|
| 629 |
|
|
((FLAG) == ETH_DMARxDesc_RWT) || \
|
| 630 |
|
|
((FLAG) == ETH_DMARxDesc_RE) || \
|
| 631 |
|
|
((FLAG) == ETH_DMARxDesc_DBE) || \
|
| 632 |
|
|
((FLAG) == ETH_DMARxDesc_CE) || \
|
| 633 |
|
|
((FLAG) == ETH_DMARxDesc_MAMPCE))
|
| 634 |
|
|
|
| 635 |
|
|
/* ETHERNET DMA Rx descriptor buffers ---------------------------------------*/
|
| 636 |
|
|
#define ETH_DMARxDesc_Buffer1 ((u32)0x00000000) /* DMA Rx Desc Buffer1 */
|
| 637 |
|
|
#define ETH_DMARxDesc_Buffer2 ((u32)0x00000001) /* DMA Rx Desc Buffer2 */
|
| 638 |
|
|
|
| 639 |
|
|
#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
|
| 640 |
|
|
((BUFFER) == ETH_DMARxDesc_Buffer2))
|
| 641 |
|
|
|
| 642 |
|
|
/*----------------------------------------------------------------------------*/
|
| 643 |
|
|
/* Ethernet DMA defines */
|
| 644 |
|
|
/*----------------------------------------------------------------------------*/
|
| 645 |
|
|
/* ETHERNET Drop TCP/IP Checksum Error Frame ---------------------------------*/
|
| 646 |
|
|
#define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000)
|
| 647 |
|
|
#define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000)
|
| 648 |
|
|
|
| 649 |
|
|
#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
|
| 650 |
|
|
((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
|
| 651 |
|
|
|
| 652 |
|
|
/* ETHERNET Receive Store Forward --------------------------------------------*/
|
| 653 |
|
|
#define ETH_ReceiveStoreForward_Enable ((u32)0x02000000)
|
| 654 |
|
|
#define ETH_ReceiveStoreForward_Disable ((u32)0x00000000)
|
| 655 |
|
|
|
| 656 |
|
|
#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
|
| 657 |
|
|
((CMD) == ETH_ReceiveStoreForward_Disable))
|
| 658 |
|
|
|
| 659 |
|
|
/* ETHERNET Flush Received Frame ---------------------------------------------*/
|
| 660 |
|
|
#define ETH_FlushReceivedFrame_Enable ((u32)0x00000000)
|
| 661 |
|
|
#define ETH_FlushReceivedFrame_Disable ((u32)0x01000000)
|
| 662 |
|
|
|
| 663 |
|
|
#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
|
| 664 |
|
|
((CMD) == ETH_FlushReceivedFrame_Disable))
|
| 665 |
|
|
|
| 666 |
|
|
/* ETHERNET Transmit Store Forward -------------------------------------------*/
|
| 667 |
|
|
#define ETH_TransmitStoreForward_Enable ((u32)0x00200000)
|
| 668 |
|
|
#define ETH_TransmitStoreForward_Disable ((u32)0x00000000)
|
| 669 |
|
|
|
| 670 |
|
|
#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
|
| 671 |
|
|
((CMD) == ETH_TransmitStoreForward_Disable))
|
| 672 |
|
|
|
| 673 |
|
|
/* ETHERNET Transmit Threshold Control ---------------------------------------*/
|
| 674 |
|
|
#define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
|
| 675 |
|
|
#define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
|
| 676 |
|
|
#define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
|
| 677 |
|
|
#define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
|
| 678 |
|
|
#define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
|
| 679 |
|
|
#define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
|
| 680 |
|
|
#define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
|
| 681 |
|
|
#define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
|
| 682 |
|
|
|
| 683 |
|
|
#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
|
| 684 |
|
|
((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
|
| 685 |
|
|
((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
|
| 686 |
|
|
((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
|
| 687 |
|
|
((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
|
| 688 |
|
|
((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
|
| 689 |
|
|
((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
|
| 690 |
|
|
((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
|
| 691 |
|
|
|
| 692 |
|
|
/* ETHERNET Forward Error Frames ---------------------------------------------*/
|
| 693 |
|
|
#define ETH_ForwardErrorFrames_Enable ((u32)0x00000080)
|
| 694 |
|
|
#define ETH_ForwardErrorFrames_Disable ((u32)0x00000000)
|
| 695 |
|
|
|
| 696 |
|
|
#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
|
| 697 |
|
|
((CMD) == ETH_ForwardErrorFrames_Disable))
|
| 698 |
|
|
|
| 699 |
|
|
/* ETHERNET Forward Undersized Good Frames -----------------------------------*/
|
| 700 |
|
|
#define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040)
|
| 701 |
|
|
#define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000)
|
| 702 |
|
|
|
| 703 |
|
|
#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
|
| 704 |
|
|
((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
|
| 705 |
|
|
|
| 706 |
|
|
/* ETHERNET Receive Threshold Control ----------------------------------------*/
|
| 707 |
|
|
#define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
|
| 708 |
|
|
#define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
|
| 709 |
|
|
#define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
|
| 710 |
|
|
#define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
|
| 711 |
|
|
|
| 712 |
|
|
#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
|
| 713 |
|
|
((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
|
| 714 |
|
|
((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
|
| 715 |
|
|
((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
|
| 716 |
|
|
|
| 717 |
|
|
/* ETHERNET Second Frame Operate ---------------------------------------------*/
|
| 718 |
|
|
#define ETH_SecondFrameOperate_Enable ((u32)0x00000004)
|
| 719 |
|
|
#define ETH_SecondFrameOperate_Disable ((u32)0x00000000)
|
| 720 |
|
|
|
| 721 |
|
|
#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
|
| 722 |
|
|
((CMD) == ETH_SecondFrameOperate_Disable))
|
| 723 |
|
|
|
| 724 |
|
|
/* ETHERNET Address Aligned Beats --------------------------------------------*/
|
| 725 |
|
|
#define ETH_AddressAlignedBeats_Enable ((u32)0x02000000)
|
| 726 |
|
|
#define ETH_AddressAlignedBeats_Disable ((u32)0x00000000)
|
| 727 |
|
|
|
| 728 |
|
|
#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
|
| 729 |
|
|
((CMD) == ETH_AddressAlignedBeats_Disable))
|
| 730 |
|
|
|
| 731 |
|
|
/* ETHERNET Fixed Burst ------------------------------------------------------*/
|
| 732 |
|
|
#define ETH_FixedBurst_Enable ((u32)0x00010000)
|
| 733 |
|
|
#define ETH_FixedBurst_Disable ((u32)0x00000000)
|
| 734 |
|
|
|
| 735 |
|
|
#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
|
| 736 |
|
|
((CMD) == ETH_FixedBurst_Disable))
|
| 737 |
|
|
|
| 738 |
|
|
/* ETHERNET Rx DMA Burst Length ----------------------------------------------*/
|
| 739 |
|
|
#define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
|
| 740 |
|
|
#define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
|
| 741 |
|
|
#define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
| 742 |
|
|
#define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
| 743 |
|
|
#define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
| 744 |
|
|
#define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
| 745 |
|
|
|
| 746 |
|
|
#define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
| 747 |
|
|
#define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
| 748 |
|
|
#define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
| 749 |
|
|
#define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
| 750 |
|
|
#define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
|
| 751 |
|
|
#define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
|
| 752 |
|
|
|
| 753 |
|
|
#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
|
| 754 |
|
|
((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
|
| 755 |
|
|
((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
|
| 756 |
|
|
((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
|
| 757 |
|
|
((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
|
| 758 |
|
|
((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
|
| 759 |
|
|
((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
|
| 760 |
|
|
((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
|
| 761 |
|
|
((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
|
| 762 |
|
|
((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
|
| 763 |
|
|
((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
|
| 764 |
|
|
((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
|
| 765 |
|
|
|
| 766 |
|
|
/* ETHERNET Tx DMA Burst Length ----------------------------------------------*/
|
| 767 |
|
|
#define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
|
| 768 |
|
|
#define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
|
| 769 |
|
|
#define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
| 770 |
|
|
#define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
| 771 |
|
|
#define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
| 772 |
|
|
#define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
| 773 |
|
|
|
| 774 |
|
|
#define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
| 775 |
|
|
#define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
| 776 |
|
|
#define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
| 777 |
|
|
#define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
| 778 |
|
|
#define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
|
| 779 |
|
|
#define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
|
| 780 |
|
|
|
| 781 |
|
|
#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
|
| 782 |
|
|
((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
|
| 783 |
|
|
((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
|
| 784 |
|
|
((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
|
| 785 |
|
|
((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
|
| 786 |
|
|
((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
|
| 787 |
|
|
((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
|
| 788 |
|
|
((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
|
| 789 |
|
|
((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
|
| 790 |
|
|
((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
|
| 791 |
|
|
((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
|
| 792 |
|
|
((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
|
| 793 |
|
|
|
| 794 |
|
|
/* ETHERNET DMA Desciptor SkipLength */
|
| 795 |
|
|
#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
|
| 796 |
|
|
|
| 797 |
|
|
/* ETHERNET DMA Arbitration --------------------------------------------------*/
|
| 798 |
|
|
#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000)
|
| 799 |
|
|
#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000)
|
| 800 |
|
|
#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000)
|
| 801 |
|
|
#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000)
|
| 802 |
|
|
#define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002)
|
| 803 |
|
|
|
| 804 |
|
|
#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
|
| 805 |
|
|
((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
|
| 806 |
|
|
((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
|
| 807 |
|
|
((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
|
| 808 |
|
|
((RATIO) == ETH_DMAArbitration_RxPriorTx))
|
| 809 |
|
|
|
| 810 |
|
|
/* ETHERNET DMA Flags ---------------------------------------------------*/
|
| 811 |
|
|
#define ETH_DMA_FLAG_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */
|
| 812 |
|
|
#define ETH_DMA_FLAG_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */
|
| 813 |
|
|
#define ETH_DMA_FLAG_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */
|
| 814 |
|
|
|
| 815 |
|
|
#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
|
| 816 |
|
|
#define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
|
| 817 |
|
|
#define ETH_DMA_FLAG_AccessError ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
|
| 818 |
|
|
#define ETH_DMA_FLAG_NIS ((u32)0x00010000) /* Normal interrupt summary flag */
|
| 819 |
|
|
#define ETH_DMA_FLAG_AIS ((u32)0x00008000) /* Abnormal interrupt summary flag */
|
| 820 |
|
|
#define ETH_DMA_FLAG_ER ((u32)0x00004000) /* Early receive flag */
|
| 821 |
|
|
#define ETH_DMA_FLAG_FBE ((u32)0x00002000) /* Fatal bus error flag */
|
| 822 |
|
|
#define ETH_DMA_FLAG_ET ((u32)0x00000400) /* Early transmit flag */
|
| 823 |
|
|
#define ETH_DMA_FLAG_RWT ((u32)0x00000200) /* Receive watchdog timeout flag */
|
| 824 |
|
|
#define ETH_DMA_FLAG_RPS ((u32)0x00000100) /* Receive process stopped flag */
|
| 825 |
|
|
#define ETH_DMA_FLAG_RBU ((u32)0x00000080) /* Receive buffer unavailable flag */
|
| 826 |
|
|
#define ETH_DMA_FLAG_R ((u32)0x00000040) /* Receive flag */
|
| 827 |
|
|
#define ETH_DMA_FLAG_TU ((u32)0x00000020) /* Underflow flag */
|
| 828 |
|
|
#define ETH_DMA_FLAG_RO ((u32)0x00000010) /* Overflow flag */
|
| 829 |
|
|
#define ETH_DMA_FLAG_TJT ((u32)0x00000008) /* Transmit jabber timeout flag */
|
| 830 |
|
|
#define ETH_DMA_FLAG_TBU ((u32)0x00000004) /* Transmit buffer unavailable flag */
|
| 831 |
|
|
#define ETH_DMA_FLAG_TPS ((u32)0x00000002) /* Transmit process stopped flag */
|
| 832 |
|
|
#define ETH_DMA_FLAG_T ((u32)0x00000001) /* Transmit flag */
|
| 833 |
|
|
|
| 834 |
|
|
#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (u32)0xFFFE1800) == 0x00) && ((FLAG) != 0x00))
|
| 835 |
|
|
#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
|
| 836 |
|
|
((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
|
| 837 |
|
|
((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
|
| 838 |
|
|
((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
|
| 839 |
|
|
((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
|
| 840 |
|
|
((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
|
| 841 |
|
|
((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
|
| 842 |
|
|
((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
|
| 843 |
|
|
((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
|
| 844 |
|
|
((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
|
| 845 |
|
|
((FLAG) == ETH_DMA_FLAG_T))
|
| 846 |
|
|
|
| 847 |
|
|
/* ETHERNET DMA Interrupts ---------------------------------------------------*/
|
| 848 |
|
|
#define ETH_DMA_IT_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */
|
| 849 |
|
|
#define ETH_DMA_IT_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */
|
| 850 |
|
|
#define ETH_DMA_IT_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */
|
| 851 |
|
|
|
| 852 |
|
|
#define ETH_DMA_IT_NIS ((u32)0x00010000) /* Normal interrupt summary */
|
| 853 |
|
|
#define ETH_DMA_IT_AIS ((u32)0x00008000) /* Abnormal interrupt summary */
|
| 854 |
|
|
#define ETH_DMA_IT_ER ((u32)0x00004000) /* Early receive interrupt */
|
| 855 |
|
|
#define ETH_DMA_IT_FBE ((u32)0x00002000) /* Fatal bus error interrupt */
|
| 856 |
|
|
#define ETH_DMA_IT_ET ((u32)0x00000400) /* Early transmit interrupt */
|
| 857 |
|
|
#define ETH_DMA_IT_RWT ((u32)0x00000200) /* Receive watchdog timeout interrupt */
|
| 858 |
|
|
#define ETH_DMA_IT_RPS ((u32)0x00000100) /* Receive process stopped interrupt */
|
| 859 |
|
|
#define ETH_DMA_IT_RBU ((u32)0x00000080) /* Receive buffer unavailable interrupt */
|
| 860 |
|
|
#define ETH_DMA_IT_R ((u32)0x00000040) /* Receive interrupt */
|
| 861 |
|
|
#define ETH_DMA_IT_TU ((u32)0x00000020) /* Underflow interrupt */
|
| 862 |
|
|
#define ETH_DMA_IT_RO ((u32)0x00000010) /* Overflow interrupt */
|
| 863 |
|
|
#define ETH_DMA_IT_TJT ((u32)0x00000008) /* Transmit jabber timeout interrupt */
|
| 864 |
|
|
#define ETH_DMA_IT_TBU ((u32)0x00000004) /* Transmit buffer unavailable interrupt */
|
| 865 |
|
|
#define ETH_DMA_IT_TPS ((u32)0x00000002) /* Transmit process stopped interrupt */
|
| 866 |
|
|
#define ETH_DMA_IT_T ((u32)0x00000001) /* Transmit interrupt */
|
| 867 |
|
|
|
| 868 |
|
|
#define IS_ETH_DMA_IT(IT) ((((IT) & (u32)0xFFFE1800) == 0x00) && ((IT) != 0x00))
|
| 869 |
|
|
#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
|
| 870 |
|
|
((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
|
| 871 |
|
|
((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
|
| 872 |
|
|
((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
|
| 873 |
|
|
((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
|
| 874 |
|
|
((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
|
| 875 |
|
|
((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
|
| 876 |
|
|
((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
|
| 877 |
|
|
((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
|
| 878 |
|
|
|
| 879 |
|
|
/* ETHERNET DMA transmit process state --------------------------------------------------------*/
|
| 880 |
|
|
#define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
|
| 881 |
|
|
#define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */
|
| 882 |
|
|
#define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) /* Running - waiting for status */
|
| 883 |
|
|
#define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) /* Running - reading the data from host memory */
|
| 884 |
|
|
#define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) /* Suspended - Tx Desciptor unavailabe */
|
| 885 |
|
|
#define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */
|
| 886 |
|
|
|
| 887 |
|
|
/* ETHERNET DMA receive process state --------------------------------------------------------*/
|
| 888 |
|
|
#define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
|
| 889 |
|
|
#define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */
|
| 890 |
|
|
#define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) /* Running - waiting for packet */
|
| 891 |
|
|
#define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) /* Suspended - Rx Desciptor unavailable */
|
| 892 |
|
|
#define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) /* Running - closing descriptor */
|
| 893 |
|
|
#define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */
|
| 894 |
|
|
|
| 895 |
|
|
/* ETHERNET DMA overflow --------------------------------------------------------*/
|
| 896 |
|
|
#define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */
|
| 897 |
|
|
#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) /* Overflow bit for missed frame counter */
|
| 898 |
|
|
|
| 899 |
|
|
#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
|
| 900 |
|
|
((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
|
| 901 |
|
|
|
| 902 |
|
|
/*----------------------------------------------------------------------------*/
|
| 903 |
|
|
/* Ethernet PMT defines */
|
| 904 |
|
|
/*----------------------------------------------------------------------------*/
|
| 905 |
|
|
/* ETHERNET PMT Flags --------------------------------------------------------*/
|
| 906 |
|
|
#define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */
|
| 907 |
|
|
#define ETH_PMT_FLAG_WUFR ((u32)0x00000040) /* Wake-Up Frame Received */
|
| 908 |
|
|
#define ETH_PMT_FLAG_MPR ((u32)0x00000020) /* Magic Packet Received */
|
| 909 |
|
|
|
| 910 |
|
|
#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
|
| 911 |
|
|
((FLAG) == ETH_PMT_FLAG_MPR))
|
| 912 |
|
|
|
| 913 |
|
|
/*----------------------------------------------------------------------------*/
|
| 914 |
|
|
/* Ethernet MMC defines */
|
| 915 |
|
|
/*----------------------------------------------------------------------------*/
|
| 916 |
|
|
/* ETHERNET MMC Tx Interrupts */
|
| 917 |
|
|
#define ETH_MMC_IT_TGF ((u32)0x00200000) /* When Tx good frame counter reaches half the maximum value */
|
| 918 |
|
|
#define ETH_MMC_IT_TGFMSC ((u32)0x00008000) /* When Tx good multi col counter reaches half the maximum value */
|
| 919 |
|
|
#define ETH_MMC_IT_TGFSC ((u32)0x00004000) /* When Tx good single col counter reaches half the maximum value */
|
| 920 |
|
|
|
| 921 |
|
|
/* ETHERNET MMC Rx Interrupts */
|
| 922 |
|
|
#define ETH_MMC_IT_RGUF ((u32)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */
|
| 923 |
|
|
#define ETH_MMC_IT_RFAE ((u32)0x10000040) /* When Rx alignment error counter reaches half the maximum value */
|
| 924 |
|
|
#define ETH_MMC_IT_RFCE ((u32)0x10000020) /* When Rx crc error counter reaches half the maximum value */
|
| 925 |
|
|
|
| 926 |
|
|
#define IS_ETH_MMC_IT(IT) (((((IT) & (u32)0xFFDF3FFF) == 0x00) || (((IT) & (u32)0xEFFDFF9F) == 0x00)) && \
|
| 927 |
|
|
((IT) != 0x00))
|
| 928 |
|
|
#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
|
| 929 |
|
|
((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
|
| 930 |
|
|
((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
|
| 931 |
|
|
|
| 932 |
|
|
/* ETHERNET MMC Registers */
|
| 933 |
|
|
#define ETH_MMCCR ((u32)0x00000100) /* MMC CR register */
|
| 934 |
|
|
#define ETH_MMCRIR ((u32)0x00000104) /* MMC RIR register */
|
| 935 |
|
|
#define ETH_MMCTIR ((u32)0x00000108) /* MMC TIR register */
|
| 936 |
|
|
#define ETH_MMCRIMR ((u32)0x0000010C) /* MMC RIMR register */
|
| 937 |
|
|
#define ETH_MMCTIMR ((u32)0x00000110) /* MMC TIMR register */
|
| 938 |
|
|
#define ETH_MMCTGFSCCR ((u32)0x0000014C) /* MMC TGFSCCR register */
|
| 939 |
|
|
#define ETH_MMCTGFMSCCR ((u32)0x00000150) /* MMC TGFMSCCR register */
|
| 940 |
|
|
#define ETH_MMCTGFCR ((u32)0x00000168) /* MMC TGFCR register */
|
| 941 |
|
|
#define ETH_MMCRFCECR ((u32)0x00000194) /* MMC RFCECR register */
|
| 942 |
|
|
#define ETH_MMCRFAECR ((u32)0x00000198) /* MMC RFAECR register */
|
| 943 |
|
|
#define ETH_MMCRGUFCR ((u32)0x000001C4) /* MMC RGUFCR register */
|
| 944 |
|
|
|
| 945 |
|
|
/* ETHERNET MMC registers */
|
| 946 |
|
|
#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
|
| 947 |
|
|
((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
|
| 948 |
|
|
((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
|
| 949 |
|
|
((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
|
| 950 |
|
|
((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
|
| 951 |
|
|
((REG) == ETH_MMCRGUFCR))
|
| 952 |
|
|
|
| 953 |
|
|
/*----------------------------------------------------------------------------*/
|
| 954 |
|
|
/* Ethernet PTP defines */
|
| 955 |
|
|
/*----------------------------------------------------------------------------*/
|
| 956 |
|
|
/* ETHERNET PTP time update method -------------------------------------------*/
|
| 957 |
|
|
#define ETH_PTP_FineUpdate ((u32)0x00000001) /* Fine Update method */
|
| 958 |
|
|
#define ETH_PTP_CoarseUpdate ((u32)0x00000000) /* Coarse Update method */
|
| 959 |
|
|
|
| 960 |
|
|
#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
|
| 961 |
|
|
((UPDATE) == ETH_PTP_CoarseUpdate))
|
| 962 |
|
|
|
| 963 |
|
|
/* ETHERNET PTP Flags --------------------------------------------------------*/
|
| 964 |
|
|
#define ETH_PTP_FLAG_TSARU ((u32)0x00000020) /* Addend Register Update */
|
| 965 |
|
|
#define ETH_PTP_FLAG_TSITE ((u32)0x00000010) /* Time Stamp Interrupt Trigger */
|
| 966 |
|
|
#define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) /* Time Stamp Update */
|
| 967 |
|
|
#define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) /* Time Stamp Initialize */
|
| 968 |
|
|
|
| 969 |
|
|
#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
|
| 970 |
|
|
((FLAG) == ETH_PTP_FLAG_TSITE) || \
|
| 971 |
|
|
((FLAG) == ETH_PTP_FLAG_TSSTU) || \
|
| 972 |
|
|
((FLAG) == ETH_PTP_FLAG_TSSTI))
|
| 973 |
|
|
|
| 974 |
|
|
/* ETHERNET PTP subsecond increment */
|
| 975 |
|
|
#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
|
| 976 |
|
|
|
| 977 |
|
|
/* ETHERNET PTP time sign ----------------------------------------------------*/
|
| 978 |
|
|
#define ETH_PTP_PositiveTime ((u32)0x00000000) /* Positive time value */
|
| 979 |
|
|
#define ETH_PTP_NegativeTime ((u32)0x80000000) /* Negative time value */
|
| 980 |
|
|
|
| 981 |
|
|
#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
|
| 982 |
|
|
((SIGN) == ETH_PTP_NegativeTime))
|
| 983 |
|
|
|
| 984 |
|
|
/* ETHERNET PTP time stamp low update */
|
| 985 |
|
|
#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
|
| 986 |
|
|
|
| 987 |
|
|
/* ETHERNET PTP registers */
|
| 988 |
|
|
#define ETH_PTPTSCR ((u32)0x00000700) /* PTP TSCR register */
|
| 989 |
|
|
#define ETH_PTPSSIR ((u32)0x00000704) /* PTP SSIR register */
|
| 990 |
|
|
#define ETH_PTPTSHR ((u32)0x00000708) /* PTP TSHR register */
|
| 991 |
|
|
#define ETH_PTPTSLR ((u32)0x0000070C) /* PTP TSLR register */
|
| 992 |
|
|
#define ETH_PTPTSHUR ((u32)0x00000710) /* PTP TSHUR register */
|
| 993 |
|
|
#define ETH_PTPTSLUR ((u32)0x00000714) /* PTP TSLUR register */
|
| 994 |
|
|
#define ETH_PTPTSAR ((u32)0x00000718) /* PTP TSAR register */
|
| 995 |
|
|
#define ETH_PTPTTHR ((u32)0x0000071C) /* PTP TTHR register */
|
| 996 |
|
|
#define ETH_PTPTTLR ((u32)0x00000720) /* PTP TTLR register */
|
| 997 |
|
|
|
| 998 |
|
|
#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
|
| 999 |
|
|
((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
|
| 1000 |
|
|
((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
|
| 1001 |
|
|
((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
|
| 1002 |
|
|
((REG) == ETH_PTPTTLR))
|
| 1003 |
|
|
|
| 1004 |
|
|
/* Exported macro ------------------------------------------------------------*/
|
| 1005 |
|
|
/* Exported functions ------------------------------------------------------- */
|
| 1006 |
|
|
void ETH_DeInit(void);
|
| 1007 |
|
|
u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress);
|
| 1008 |
|
|
void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
|
| 1009 |
|
|
void ETH_SoftwareReset(void);
|
| 1010 |
|
|
FlagStatus ETH_GetSoftwareResetStatus(void);
|
| 1011 |
|
|
void ETH_Start(void);
|
| 1012 |
|
|
u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength);
|
| 1013 |
|
|
u32 ETH_HandleRxPkt(u32 addr);
|
| 1014 |
|
|
|
| 1015 |
|
|
|
| 1016 |
|
|
u32 ETH_GetRxPktSize(void);
|
| 1017 |
|
|
void ETH_DropRxPkt(void);
|
| 1018 |
|
|
|
| 1019 |
|
|
/*--------------------------------- PHY ------------------------------------*/
|
| 1020 |
|
|
u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);
|
| 1021 |
|
|
u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);
|
| 1022 |
|
|
u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);
|
| 1023 |
|
|
/*--------------------------------- MAC ------------------------------------*/
|
| 1024 |
|
|
void ETH_MACTransmissionCmd(FunctionalState NewState);
|
| 1025 |
|
|
void ETH_MACReceptionCmd(FunctionalState NewState);
|
| 1026 |
|
|
FlagStatus ETH_GetFlowControlBusyStatus(void);
|
| 1027 |
|
|
void ETH_InitiatePauseControlFrame(void);
|
| 1028 |
|
|
void ETH_BackPressureActivationCmd(FunctionalState NewState);
|
| 1029 |
|
|
FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG);
|
| 1030 |
|
|
ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT);
|
| 1031 |
|
|
void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState);
|
| 1032 |
|
|
void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr);
|
| 1033 |
|
|
void ETH_GetMACAddress(u32 MacAddr, u8 *Addr);
|
| 1034 |
|
|
void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState);
|
| 1035 |
|
|
void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter);
|
| 1036 |
|
|
void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte);
|
| 1037 |
|
|
/*----------------------- DMA Tx/Rx descriptors ----------------------------*/
|
| 1038 |
|
|
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, u32 TxBuffCount);
|
| 1039 |
|
|
void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount);
|
| 1040 |
|
|
FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag);
|
| 1041 |
|
|
u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
|
| 1042 |
|
|
void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
|
| 1043 |
|
|
void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1044 |
|
|
void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment);
|
| 1045 |
|
|
void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum);
|
| 1046 |
|
|
void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1047 |
|
|
void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1048 |
|
|
void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1049 |
|
|
void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1050 |
|
|
void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1051 |
|
|
void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2);
|
| 1052 |
|
|
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount);
|
| 1053 |
|
|
void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount);
|
| 1054 |
|
|
FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag);
|
| 1055 |
|
|
void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
|
| 1056 |
|
|
u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
|
| 1057 |
|
|
void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
|
| 1058 |
|
|
void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
|
| 1059 |
|
|
void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
|
| 1060 |
|
|
u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer);
|
| 1061 |
|
|
/*--------------------------------- DMA ------------------------------------*/
|
| 1062 |
|
|
FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG);
|
| 1063 |
|
|
void ETH_DMAClearFlag(u32 ETH_DMA_FLAG);
|
| 1064 |
|
|
ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT);
|
| 1065 |
|
|
void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT);
|
| 1066 |
|
|
u32 ETH_GetTransmitProcessState(void);
|
| 1067 |
|
|
u32 ETH_GetReceiveProcessState(void);
|
| 1068 |
|
|
void ETH_FlushTransmitFIFO(void);
|
| 1069 |
|
|
FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
|
| 1070 |
|
|
void ETH_DMATransmissionCmd(FunctionalState NewState);
|
| 1071 |
|
|
void ETH_DMAReceptionCmd(FunctionalState NewState);
|
| 1072 |
|
|
void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState);
|
| 1073 |
|
|
FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow);
|
| 1074 |
|
|
u32 ETH_GetRxOverflowMissedFrameCounter(void);
|
| 1075 |
|
|
u32 ETH_GetBufferUnavailableMissedFrameCounter(void);
|
| 1076 |
|
|
u32 ETH_GetCurrentTxDescStartAddress(void);
|
| 1077 |
|
|
u32 ETH_GetCurrentRxDescStartAddress(void);
|
| 1078 |
|
|
u32 ETH_GetCurrentTxBufferAddress(void);
|
| 1079 |
|
|
u32 ETH_GetCurrentRxBufferAddress(void);
|
| 1080 |
|
|
void ETH_ResumeDMATransmission(void);
|
| 1081 |
|
|
void ETH_ResumeDMAReception(void);
|
| 1082 |
|
|
/*--------------------------------- PMT ------------------------------------*/
|
| 1083 |
|
|
void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
|
| 1084 |
|
|
void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer);
|
| 1085 |
|
|
void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
|
| 1086 |
|
|
FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG);
|
| 1087 |
|
|
void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
|
| 1088 |
|
|
void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
|
| 1089 |
|
|
void ETH_PowerDownCmd(FunctionalState NewState);
|
| 1090 |
|
|
/*--------------------------------- MMC ------------------------------------*/
|
| 1091 |
|
|
void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
|
| 1092 |
|
|
void ETH_MMCResetOnReadCmd(FunctionalState NewState);
|
| 1093 |
|
|
void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
|
| 1094 |
|
|
void ETH_MMCCountersReset(void);
|
| 1095 |
|
|
void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState);
|
| 1096 |
|
|
ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT);
|
| 1097 |
|
|
u32 ETH_GetMMCRegister(u32 ETH_MMCReg);
|
| 1098 |
|
|
/*--------------------------------- PTP ------------------------------------*/
|
| 1099 |
|
|
u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab);
|
| 1100 |
|
|
u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab);
|
| 1101 |
|
|
void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount);
|
| 1102 |
|
|
void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount);
|
| 1103 |
|
|
void ETH_EnablePTPTimeStampAddend(void);
|
| 1104 |
|
|
void ETH_EnablePTPTimeStampInterruptTrigger(void);
|
| 1105 |
|
|
void ETH_EnablePTPTimeStampUpdate(void);
|
| 1106 |
|
|
void ETH_InitializePTPTimeStamp(void);
|
| 1107 |
|
|
void ETH_PTPUpdateMethodConfig(u32 UpdateMethod);
|
| 1108 |
|
|
void ETH_PTPTimeStampCmd(FunctionalState NewState);
|
| 1109 |
|
|
FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG);
|
| 1110 |
|
|
void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue);
|
| 1111 |
|
|
void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue);
|
| 1112 |
|
|
void ETH_SetPTPTimeStampAddend(u32 Value);
|
| 1113 |
|
|
void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue);
|
| 1114 |
|
|
u32 ETH_GetPTPRegister(u32 ETH_PTPReg);
|
| 1115 |
|
|
|
| 1116 |
|
|
#endif /* __STM32FXXX_ETH_H */
|
| 1117 |
|
|
|
| 1118 |
|
|
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
|
