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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [ST/] [STM32F10xFWLib/] [inc/] [stm32fxxx_eth_map.h] - Blame information for rev 867

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1 608 jeremybenn 
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
2 
* File Name          : stm32fxxx_eth_map.h
3 
* Author             : MCD Application Team
4 
* Version            : VX.Y.Z
5 
* Date               : mm/dd/2008
6 
* Description        : This file contains all ETHERNET peripheral register's
7 
*                      definitions and memory mapping.
8 
********************************************************************************
9 
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
10 
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
11 
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
12 
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
13 
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
14 
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
15 
*******************************************************************************/
16 
 
17 
/* Define to prevent recursive inclusion -------------------------------------*/
18 
#ifndef __STM32FXXX_ETH_MAP_H
19 
#define __STM32FXXX_ETH_MAP_H
20 
 
21 
#ifndef EXT
22 
  #define EXT extern
23 
#endif /* EXT */
24 
 
25 
/* Includes ------------------------------------------------------------------*/
26 
 
27 
#include "stm32fxxx_eth_conf.h"
28 
#include "stm32f10x_type.h"
29 
 
30 
/* Exported types ------------------------------------------------------------*/
31 
/******************************************************************************/
32 
/*                Ethernet Peripheral registers structures                    */
33 
/******************************************************************************/
34 
 
35 
typedef struct
36 
{
37 
  vu32 MACCR;
38 
  vu32 MACFFR;
39 
  vu32 MACHTHR;
40 
  vu32 MACHTLR;
41 
  vu32 MACMIIAR;
42 
  vu32 MACMIIDR;
43 
  vu32 MACFCR;
44 
  vu32 MACVLANTR;
45 
  vu32 RESERVED0[2];
46 
  vu32 MACRWUFFR;
47 
  vu32 MACPMTCSR;
48 
  vu32 RESERVED1[2];
49 
  vu32 MACSR;
50 
  vu32 MACIMR;
51 
  vu32 MACA0HR;
52 
  vu32 MACA0LR;
53 
  vu32 MACA1HR;
54 
  vu32 MACA1LR;
55 
  vu32 MACA2HR;
56 
  vu32 MACA2LR;
57 
  vu32 MACA3HR;
58 
  vu32 MACA3LR;
59 
} ETH_MAC_TypeDef;
60 
 
61 
typedef struct
62 
{
63 
  vu32 MMCCR;
64 
  vu32 MMCRIR;
65 
  vu32 MMCTIR;
66 
  vu32 MMCRIMR;
67 
  vu32 MMCTIMR;
68 
  vu32 RESERVED0[14];
69 
  vu32 MMCTGFSCCR;
70 
  vu32 MMCTGFMSCCR;
71 
  vu32 RESERVED1[5];
72 
  vu32 MMCTGFCR;
73 
  vu32 RESERVED2[10];
74 
  vu32 MMCRFCECR;
75 
  vu32 MMCRFAER;
76 
  vu32 RESERVED3[10];
77 
  vu32 MMCRGUFCR;
78 
} ETH_MMC_TypeDef;
79 
 
80 
typedef struct
81 
{
82 
  vu32 PTPTSCR;
83 
  vu32 PTPSSIR;
84 
  vu32 PTPTSHR;
85 
  vu32 PTPTSLR;
86 
  vu32 PTPTSHUR;
87 
  vu32 PTPTSLUR;
88 
  vu32 PTPTSAR;
89 
  vu32 PTPTTHR;
90 
  vu32 PTPTTLR;
91 
} ETH_PTP_TypeDef;
92 
 
93 
typedef struct
94 
{
95 
  vu32 DMABMR;
96 
  vu32 DMATPDR;
97 
  vu32 DMARPDR;
98 
  vu32 DMARDLAR;
99 
  vu32 DMATDLAR;
100 
  vu32 DMASR;
101 
  vu32 DMAOMR;
102 
  vu32 DMAIER;
103 
  vu32 DMAMFBOCR;
104 
  vu32 RESERVED0[9];
105 
  vu32 DMACHTDR;
106 
  vu32 DMACHRDR;
107 
  vu32 DMACHTBAR;
108 
  vu32 DMACHRBAR;
109 
} ETH_DMA_TypeDef;
110 
 
111 
/******************************************************************************/
112 
/*                Ethernet MAC Registers bits definitions                     */
113 
/******************************************************************************/
114 
//#define  IPNAME_REGNAME_BITNAME   /* BIT MASK */
115 
 
116 
/* Bit definition for Ethernet MAC Control Register register */
117 
#define ETH_MACCR_WD      ((u32)0x00800000)  /* Watchdog disable */
118 
#define ETH_MACCR_JD      ((u32)0x00400000)  /* Jabber disable */
119 
#define ETH_MACCR_JFE     ((u32)0x00100000)  /* Jumbo frame enable */
120 
#define ETH_MACCR_IFG     ((u32)0x000E0000)  /* Inter-frame gap */
121 
  #define ETH_MACCR_IFG_96Bit     ((u32)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
122 
  #define ETH_MACCR_IFG_88Bit     ((u32)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
123 
  #define ETH_MACCR_IFG_80Bit     ((u32)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
124 
  #define ETH_MACCR_IFG_72Bit     ((u32)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
125 
  #define ETH_MACCR_IFG_64Bit     ((u32)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */
126 
  #define ETH_MACCR_IFG_56Bit     ((u32)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
127 
  #define ETH_MACCR_IFG_48Bit     ((u32)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
128 
  #define ETH_MACCR_IFG_40Bit     ((u32)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */
129 
#define ETH_MACCR_CSD     ((u32)0x00010000)  /* Carrier sense disable (during transmission) */
130 
#define ETH_MACCR_FES     ((u32)0x00004000)  /* Fast ethernet speed */
131 
#define ETH_MACCR_ROD     ((u32)0x00002000)  /* Receive own disable */
132 
#define ETH_MACCR_LM      ((u32)0x00001000)  /* loopback mode */
133 
#define ETH_MACCR_DM      ((u32)0x00000800)  /* Duplex mode */
134 
#define ETH_MACCR_IPCO    ((u32)0x00000400)  /* IP Checksum offload */
135 
#define ETH_MACCR_RD      ((u32)0x00000200)  /* Retry disable */
136 
#define ETH_MACCR_APCS    ((u32)0x00000080)  /* Automatic Pad/CRC stripping */
137 
#define ETH_MACCR_BL      ((u32)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
138 
                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
139 
  #define ETH_MACCR_BL_10    ((u32)0x00000000)  /* k = min (n, 10) */
140 
  #define ETH_MACCR_BL_8     ((u32)0x00000020)  /* k = min (n, 8) */
141 
  #define ETH_MACCR_BL_4     ((u32)0x00000040)  /* k = min (n, 4) */
142 
  #define ETH_MACCR_BL_1     ((u32)0x00000060)  /* k = min (n, 1) */
143 
#define ETH_MACCR_DC      ((u32)0x00000010)  /* Defferal check */
144 
#define ETH_MACCR_TE      ((u32)0x00000008)  /* Transmitter enable */
145 
#define ETH_MACCR_RE      ((u32)0x00000004)  /* Receiver enable */
146 
 
147 
/* Bit definition for Ethernet MAC Frame Filter Register */
148 
#define ETH_MACFFR_RA     ((u32)0x80000000)  /* Receive all */
149 
#define ETH_MACFFR_HPF    ((u32)0x00000400)  /* Hash or perfect filter */
150 
#define ETH_MACFFR_SAF    ((u32)0x00000200)  /* Source address filter enable */
151 
#define ETH_MACFFR_SAIF   ((u32)0x00000100)  /* SA inverse filtering */
152 
#define ETH_MACFFR_PCF    ((u32)0x000000C0)  /* Pass control frames: 3 cases */
153 
  #define ETH_MACFFR_PCF_BlockAll                ((u32)0x00000040)  /* MAC filters all control frames from reaching the application */
154 
  #define ETH_MACFFR_PCF_ForwardAll              ((u32)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
155 
  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((u32)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
156 
#define ETH_MACFFR_BFD    ((u32)0x00000020)  /* Broadcast frame disable */
157 
#define ETH_MACFFR_PAM    ((u32)0x00000010)  /* Pass all mutlicast */
158 
#define ETH_MACFFR_DAIF   ((u32)0x00000008)  /* DA Inverse filtering */
159 
#define ETH_MACFFR_HM     ((u32)0x00000004)  /* Hash multicast */
160 
#define ETH_MACFFR_HU     ((u32)0x00000002)  /* Hash unicast */
161 
#define ETH_MACFFR_PM     ((u32)0x00000001)  /* Promiscuous mode */
162 
 
163 
/* Bit definition for Ethernet MAC Hash Table High Register */
164 
#define ETH_MACHTHR_HTH   ((u32)0xFFFFFFFF)  /* Hash table high */
165 
 
166 
/* Bit definition for Ethernet MAC Hash Table Low Register */
167 
#define ETH_MACHTLR_HTL   ((u32)0xFFFFFFFF)  /* Hash table low */
168 
 
169 
/* Bit definition for Ethernet MAC MII Address Register */
170 
#define ETH_MACMIIAR_PA   ((u32)0x0000F800)  /* Physical layer address */
171 
#define ETH_MACMIIAR_MR   ((u32)0x000007C0)  /* MII register in the selected PHY */
172 
#define ETH_MACMIIAR_CR   ((u32)0x0000001C)  /* CR clock range: 6 cases */
173 
  #define ETH_MACMIIAR_CR_Div42   ((u32)0x00000000)  /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
174 
  #define ETH_MACMIIAR_CR_Div16   ((u32)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
175 
  #define ETH_MACMIIAR_CR_Div26   ((u32)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
176 
#define ETH_MACMIIAR_MW   ((u32)0x00000002)  /* MII write */
177 
#define ETH_MACMIIAR_MB   ((u32)0x00000001)  /* MII busy */
178 
 
179 
/* Bit definition for Ethernet MAC MII Data Register */
180 
#define ETH_MACMIIDR_MD   ((u32)0x0000FFFF)  /* MII data: read/write data from/to PHY */
181 
 
182 
/* Bit definition for Ethernet MAC Flow Control Register */
183 
#define ETH_MACFCR_PT     ((u32)0xFFFF0000)  /* Pause time */
184 
#define ETH_MACFCR_ZQPD   ((u32)0x00000080)  /* Zero-quanta pause disable */
185 
#define ETH_MACFCR_PLT    ((u32)0x00000030)  /* Pause low threshold: 4 cases */
186 
  #define ETH_MACFCR_PLT_Minus4   ((u32)0x00000000)  /* Pause time minus 4 slot times */
187 
  #define ETH_MACFCR_PLT_Minus28  ((u32)0x00000010)  /* Pause time minus 28 slot times */
188 
  #define ETH_MACFCR_PLT_Minus144 ((u32)0x00000020)  /* Pause time minus 144 slot times */
189 
  #define ETH_MACFCR_PLT_Minus256 ((u32)0x00000030)  /* Pause time minus 256 slot times */
190 
#define ETH_MACFCR_UPFD   ((u32)0x00000008)  /* Unicast pause frame detect */
191 
#define ETH_MACFCR_RFCE   ((u32)0x00000004)  /* Receive flow control enable */
192 
#define ETH_MACFCR_TFCE   ((u32)0x00000002)  /* Transmit flow control enable */
193 
#define ETH_MACFCR_FCBBPA ((u32)0x00000001)  /* Flow control busy/backpressure activate */
194 
 
195 
/* Bit definition for Ethernet MAC VLAN Tag Register */
196 
#define ETH_MACVLANTR_VLANTC ((u32)0x00010000)  /* 12-bit VLAN tag comparison */
197 
#define ETH_MACVLANTR_VLANTI ((u32)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
198 
 
199 
/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
200 
#define ETH_MACRWUFFR_D   ((u32)0xFFFFFFFF)  /* Wake-up frame filter register data */
201 
/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
202 
   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
203 
/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
204 
   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
205 
   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
206 
   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
207 
   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
208 
                              RSVD - Filter1 Command - RSVD - Filter0 Command
209 
   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
210 
   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
211 
   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
212 
 
213 
/* Bit definition for Ethernet MAC PMT Control and Status Register */
214 
#define ETH_MACPMTCSR_WFFRPR ((u32)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
215 
#define ETH_MACPMTCSR_GU     ((u32)0x00000200)  /* Global Unicast */
216 
#define ETH_MACPMTCSR_WFR    ((u32)0x00000040)  /* Wake-Up Frame Received */
217 
#define ETH_MACPMTCSR_MPR    ((u32)0x00000020)  /* Magic Packet Received */
218 
#define ETH_MACPMTCSR_WFE    ((u32)0x00000004)  /* Wake-Up Frame Enable */
219 
#define ETH_MACPMTCSR_MPE    ((u32)0x00000002)  /* Magic Packet Enable */
220 
#define ETH_MACPMTCSR_PD     ((u32)0x00000001)  /* Power Down */
221 
 
222 
/* Bit definition for Ethernet MAC Status Register */
223 
#define ETH_MACSR_TSTS      ((u32)0x00000200)  /* Time stamp trigger status */
224 
#define ETH_MACSR_MMCTS     ((u32)0x00000040)  /* MMC transmit status */
225 
#define ETH_MACSR_MMMCRS    ((u32)0x00000020)  /* MMC receive status */
226 
#define ETH_MACSR_MMCS      ((u32)0x00000010)  /* MMC status */
227 
#define ETH_MACSR_PMTS      ((u32)0x00000008)  /* PMT status */
228 
 
229 
/* Bit definition for Ethernet MAC Interrupt Mask Register */
230 
#define ETH_MACIMR_TSTIM     ((u32)0x00000200)  /* Time stamp trigger interrupt mask */
231 
#define ETH_MACIMR_PMTIM     ((u32)0x00000008)  /* PMT interrupt mask */
232 
 
233 
/* Bit definition for Ethernet MAC Address0 High Register */
234 
#define ETH_MACA0HR_MACA0H   ((u32)0x0000FFFF)  /* MAC address0 high */
235 
 
236 
/* Bit definition for Ethernet MAC Address0 Low Register */
237 
#define ETH_MACA0LR_MACA0L   ((u32)0xFFFFFFFF)  /* MAC address0 low */
238 
 
239 
/* Bit definition for Ethernet MAC Address1 High Register */
240 
#define ETH_MACA1HR_AE       ((u32)0x80000000)  /* Address enable */
241 
#define ETH_MACA1HR_SA       ((u32)0x40000000)  /* Source address */
242 
#define ETH_MACA1HR_MBC      ((u32)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
243 
  #define ETH_MACA1HR_MBC_HBits15_8    ((u32)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
244 
  #define ETH_MACA1HR_MBC_HBits7_0     ((u32)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
245 
  #define ETH_MACA1HR_MBC_LBits31_24   ((u32)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
246 
  #define ETH_MACA1HR_MBC_LBits23_16   ((u32)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
247 
  #define ETH_MACA1HR_MBC_LBits15_8    ((u32)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
248 
  #define ETH_MACA1HR_MBC_LBits7_0     ((u32)0x01000000)  /* Mask MAC Address low reg bits [7:0] */
249 
#define ETH_MACA1HR_MACA1H   ((u32)0x0000FFFF)  /* MAC address1 high */
250 
 
251 
/* Bit definition for Ethernet MAC Address1 Low Register */
252 
#define ETH_MACA1LR_MACA1L   ((u32)0xFFFFFFFF)  /* MAC address1 low */
253 
 
254 
/* Bit definition for Ethernet MAC Address2 High Register */
255 
#define ETH_MACA2HR_AE       ((u32)0x80000000)  /* Address enable */
256 
#define ETH_MACA2HR_SA       ((u32)0x40000000)  /* Source address */
257 
#define ETH_MACA2HR_MBC      ((u32)0x3F000000)  /* Mask byte control */
258 
  #define ETH_MACA2HR_MBC_HBits15_8    ((u32)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
259 
  #define ETH_MACA2HR_MBC_HBits7_0     ((u32)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
260 
  #define ETH_MACA2HR_MBC_LBits31_24   ((u32)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
261 
  #define ETH_MACA2HR_MBC_LBits23_16   ((u32)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
262 
  #define ETH_MACA2HR_MBC_LBits15_8    ((u32)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
263 
  #define ETH_MACA2HR_MBC_LBits7_0     ((u32)0x01000000)  /* Mask MAC Address low reg bits [70] */
264 
#define ETH_MACA2HR_MACA2H   ((u32)0x0000FFFF)  /* MAC address1 high */
265 
 
266 
/* Bit definition for Ethernet MAC Address2 Low Register */
267 
#define ETH_MACA2LR_MACA2L   ((u32)0xFFFFFFFF)  /* MAC address2 low */
268 
 
269 
/* Bit definition for Ethernet MAC Address3 High Register */
270 
#define ETH_MACA3HR_AE       ((u32)0x80000000)  /* Address enable */
271 
#define ETH_MACA3HR_SA       ((u32)0x40000000)  /* Source address */
272 
#define ETH_MACA3HR_MBC      ((u32)0x3F000000)  /* Mask byte control */
273 
  #define ETH_MACA2HR_MBC_HBits15_8    ((u32)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
274 
  #define ETH_MACA2HR_MBC_HBits7_0     ((u32)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
275 
  #define ETH_MACA2HR_MBC_LBits31_24   ((u32)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
276 
  #define ETH_MACA2HR_MBC_LBits23_16   ((u32)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
277 
  #define ETH_MACA2HR_MBC_LBits15_8    ((u32)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
278 
  #define ETH_MACA2HR_MBC_LBits7_0     ((u32)0x01000000)  /* Mask MAC Address low reg bits [70] */
279 
#define ETH_MACA3HR_MACA3H   ((u32)0x0000FFFF)  /* MAC address3 high */
280 
 
281 
/* Bit definition for Ethernet MAC Address3 Low Register */
282 
#define ETH_MACA3LR_MACA3L   ((u32)0xFFFFFFFF)  /* MAC address3 low */
283 
 
284 
/******************************************************************************/
285 
/*                Ethernet MMC Registers bits definition                      */
286 
/******************************************************************************/
287 
 
288 
/* Bit definition for Ethernet MMC Contol Register */
289 
#define ETH_MMCCR_MCF        ((u32)0x00000008)  /* MMC Counter Freeze */
290 
#define ETH_MMCCR_ROR        ((u32)0x00000004)  /* Reset on Read */
291 
#define ETH_MMCCR_CSR        ((u32)0x00000002)  /* Counter Stop Rollover */
292 
#define ETH_MMCCR_CR         ((u32)0x00000001)  /* Counters Reset */
293 
 
294 
/* Bit definition for Ethernet MMC Receive Interrupt Register */
295 
#define ETH_MMCRIR_RGUFS     ((u32)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
296 
#define ETH_MMCRIR_RFAES     ((u32)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
297 
#define ETH_MMCRIR_RFCES     ((u32)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
298 
 
299 
/* Bit definition for Ethernet MMC Transmit Interrupt Register */
300 
#define ETH_MMCTIR_TGFS      ((u32)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
301 
#define ETH_MMCTIR_TGFMSCS   ((u32)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
302 
#define ETH_MMCTIR_TGFSCS    ((u32)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
303 
 
304 
/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
305 
#define ETH_MMCRIMR_RGUFM    ((u32)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
306 
#define ETH_MMCRIMR_RFAEM    ((u32)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
307 
#define ETH_MMCRIMR_RFCEM    ((u32)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
308 
 
309 
/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
310 
#define ETH_MMCTIMR_TGFM     ((u32)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
311 
#define ETH_MMCTIMR_TGFMSCM  ((u32)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
312 
#define ETH_MMCTIMR_TGFSCM   ((u32)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
313 
 
314 
/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
315 
#define ETH_MMCTGFSCCR_TGFSCC     ((u32)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
316 
 
317 
/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
318 
#define ETH_MMCTGFMSCCR_TGFMSCC   ((u32)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
319 
 
320 
/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
321 
#define ETH_MMCTGFCR_TGFC    ((u32)0xFFFFFFFF)  /* Number of good frames transmitted. */
322 
 
323 
/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
324 
#define ETH_MMCRFCECR_RFCEC  ((u32)0xFFFFFFFF)  /* Number of frames received with CRC error. */
325 
 
326 
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
327 
#define ETH_MMCRFAECR_RFAEC  ((u32)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
328 
 
329 
/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
330 
#define ETH_MMCRGUFCR_RGUFC  ((u32)0xFFFFFFFF)  /* Number of good unicast frames received. */
331 
 
332 
/******************************************************************************/
333 
/*               Ethernet PTP Registers bits definition                       */
334 
/******************************************************************************/
335 
 
336 
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
337 
#define ETH_PTPTSCR_TSARU    ((u32)0x00000020)  /* Addend register update */
338 
#define ETH_PTPTSCR_TSITE    ((u32)0x00000010)  /* Time stamp interrupt trigger enable */
339 
#define ETH_PTPTSCR_TSSTU    ((u32)0x00000008)  /* Time stamp update */
340 
#define ETH_PTPTSCR_TSSTI    ((u32)0x00000004)  /* Time stamp initialize */
341 
#define ETH_PTPTSCR_TSFCU    ((u32)0x00000002)  /* Time stamp fine or coarse update */
342 
#define ETH_PTPTSCR_TSE      ((u32)0x00000001)  /* Time stamp enable */
343 
 
344 
/* Bit definition for Ethernet PTP Sub-Second Increment Register */
345 
#define ETH_PTPSSIR_STSSI    ((u32)0x000000FF)  /* System time Sub-second increment value */
346 
 
347 
/* Bit definition for Ethernet PTP Time Stamp High Register */
348 
#define ETH_PTPTSHR_STS      ((u32)0xFFFFFFFF)  /* System Time second */
349 
 
350 
/* Bit definition for Ethernet PTP Time Stamp Low Register */
351 
#define ETH_PTPTSLR_STPNS    ((u32)0x80000000)  /* System Time Positive or negative time */
352 
#define ETH_PTPTSLR_STSS     ((u32)0x7FFFFFFF)  /* System Time sub-seconds */
353 
 
354 
/* Bit definition for Ethernet PTP Time Stamp High Update Register */
355 
#define ETH_PTPTSHUR_TSUS    ((u32)0xFFFFFFFF)  /* Time stamp update seconds */
356 
 
357 
/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
358 
#define ETH_PTPTSLUR_TSUPNS  ((u32)0x80000000)  /* Time stamp update Positive or negative time */
359 
#define ETH_PTPTSLUR_TSUSS   ((u32)0x7FFFFFFF)  /* Time stamp update sub-seconds */
360 
 
361 
/* Bit definition for Ethernet PTP Time Stamp Addend Register */
362 
#define ETH_PTPTSAR_TSA      ((u32)0xFFFFFFFF)  /* Time stamp addend */
363 
 
364 
/* Bit definition for Ethernet PTP Target Time High Register */
365 
#define ETH_PTPTTHR_TTSH     ((u32)0xFFFFFFFF)  /* Target time stamp high */
366 
 
367 
/* Bit definition for Ethernet PTP Target Time Low Register */
368 
#define ETH_PTPTTLR_TTSL     ((u32)0xFFFFFFFF)  /* Target time stamp low */
369 
 
370 
/******************************************************************************/
371 
/*                 Ethernet DMA Registers bits definition                     */
372 
/******************************************************************************/
373 
 
374 
/* Bit definition for Ethernet DMA Bus Mode Register */
375 
#define ETH_DMABMR_AAB       ((u32)0x02000000)  /* Address-Aligned beats */
376 
#define ETH_DMABMR_FPM        ((u32)0x01000000)  /* 4xPBL mode */
377 
#define ETH_DMABMR_USP       ((u32)0x00800000)  /* Use separate PBL */
378 
#define ETH_DMABMR_RDP       ((u32)0x007E0000)  /* RxDMA PBL */
379 
  /* Values to be confirmed: maybe they are inversed */
380 
  #define ETH_DMABMR_RDP_1Beat    ((u32)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
381 
  #define ETH_DMABMR_RDP_2Beat    ((u32)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
382 
  #define ETH_DMABMR_RDP_4Beat    ((u32)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
383 
  #define ETH_DMABMR_RDP_8Beat    ((u32)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
384 
  #define ETH_DMABMR_RDP_16Beat   ((u32)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
385 
  #define ETH_DMABMR_RDP_32Beat   ((u32)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
386 
  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((u32)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
387 
  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((u32)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
388 
  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((u32)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
389 
  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((u32)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
390 
  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((u32)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
391 
  #define ETH_DMABMR_RDP_4xPBL_128Beat ((u32)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
392 
#define ETH_DMABMR_FB        ((u32)0x00010000)  /* Fixed Burst */
393 
#define ETH_DMABMR_RTPR      ((u32)0x0000C000)  /* Rx Tx priority ratio */
394 
  #define ETH_DMABMR_RTPR_1_1     ((u32)0x00000000)  /* Rx Tx priority ratio */
395 
  #define ETH_DMABMR_RTPR_2_1     ((u32)0x00004000)  /* Rx Tx priority ratio */
396 
  #define ETH_DMABMR_RTPR_3_1     ((u32)0x00008000)  /* Rx Tx priority ratio */
397 
  #define ETH_DMABMR_RTPR_4_1     ((u32)0x0000C000)  /* Rx Tx priority ratio */
398 
#define ETH_DMABMR_PBL    ((u32)0x00003F00)  /* Programmable burst length */
399 
  /* Values to be confirmed: maybe they are inversed */
400 
  #define ETH_DMABMR_PBL_1Beat    ((u32)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
401 
  #define ETH_DMABMR_PBL_2Beat    ((u32)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
402 
  #define ETH_DMABMR_PBL_4Beat    ((u32)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
403 
  #define ETH_DMABMR_PBL_8Beat    ((u32)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
404 
  #define ETH_DMABMR_PBL_16Beat   ((u32)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
405 
  #define ETH_DMABMR_PBL_32Beat   ((u32)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
406 
  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((u32)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
407 
  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((u32)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
408 
  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((u32)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
409 
  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((u32)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
410 
  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((u32)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
411 
  #define ETH_DMABMR_PBL_4xPBL_128Beat ((u32)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
412 
#define ETH_DMABMR_DSL       ((u32)0x0000007C)  /* Descriptor Skip Length */
413 
#define ETH_DMABMR_DA        ((u32)0x00000002)  /* DMA arbitration scheme */
414 
#define ETH_DMABMR_SR        ((u32)0x00000001)  /* Software reset */
415 
 
416 
/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
417 
#define ETH_DMATPDR_TPD      ((u32)0xFFFFFFFF)  /* Transmit poll demand */
418 
 
419 
/* Bit definition for Ethernet DMA Receive Poll Demand Register */
420 
#define ETH_DMARPDR_RPD      ((u32)0xFFFFFFFF)  /* Receive poll demand  */
421 
 
422 
/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
423 
#define ETH_DMARDLAR_SRL     ((u32)0xFFFFFFFF)  /* Start of receive list */
424 
 
425 
/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
426 
#define ETH_DMATDLAR_STL     ((u32)0xFFFFFFFF)  /* Start of transmit list */
427 
 
428 
/* Bit definition for Ethernet DMA Status Register */
429 
#define ETH_DMASR_TSTS       ((u32)0x20000000)  /* Time-stamp trigger status */
430 
#define ETH_DMASR_PMTS       ((u32)0x10000000)  /* PMT status */
431 
#define ETH_DMASR_MMCS       ((u32)0x08000000)  /* MMC status */
432 
#define ETH_DMASR_EBS        ((u32)0x03800000)  /* Error bits status */
433 
  /* combination with EBS[2:0] for GetFlagStatus function */
434 
  #define ETH_DMASR_EBS_DescAccess      ((u32)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
435 
  #define ETH_DMASR_EBS_ReadTransf      ((u32)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
436 
  #define ETH_DMASR_EBS_DataTransfTx    ((u32)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
437 
#define ETH_DMASR_TPS         ((u32)0x00700000)  /* Transmit process state */
438 
  #define ETH_DMASR_TPS_Stopped         ((u32)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
439 
  #define ETH_DMASR_TPS_Fetching        ((u32)0x00100000)  /* Running - fetching the Tx descriptor */
440 
  #define ETH_DMASR_TPS_Waiting         ((u32)0x00200000)  /* Running - waiting for status */
441 
  #define ETH_DMASR_TPS_Reading         ((u32)0x00300000)  /* Running - reading the data from host memory */
442 
  #define ETH_DMASR_TPS_Suspended       ((u32)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
443 
  #define ETH_DMASR_TPS_Closing         ((u32)0x00700000)  /* Running - closing Rx descriptor */
444 
#define ETH_DMASR_RPS         ((u32)0x000E0000)  /* Receive process state */
445 
  #define ETH_DMASR_RPS_Stopped         ((u32)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
446 
  #define ETH_DMASR_RPS_Fetching        ((u32)0x00020000)  /* Running - fetching the Rx descriptor */
447 
  #define ETH_DMASR_RPS_Waiting         ((u32)0x00060000)  /* Running - waiting for packet */
448 
  #define ETH_DMASR_RPS_Suspended       ((u32)0x00080000)  /* Suspended - Rx Descriptor unavailable */
449 
  #define ETH_DMASR_RPS_Closing         ((u32)0x000A0000)  /* Running - closing descriptor */
450 
  #define ETH_DMASR_RPS_Queuing         ((u32)0x000E0000)  /* Running - queuing the recieve frame into host memory */
451 
#define ETH_DMASR_NIS        ((u32)0x00010000)  /* Normal interrupt summary */
452 
#define ETH_DMASR_AIS        ((u32)0x00008000)  /* Abnormal interrupt summary */
453 
#define ETH_DMASR_ERS        ((u32)0x00004000)  /* Early receive status */
454 
#define ETH_DMASR_FBES       ((u32)0x00002000)  /* Fatal bus error status */
455 
#define ETH_DMASR_ETS        ((u32)0x00000400)  /* Early transmit status */
456 
#define ETH_DMASR_RWTS       ((u32)0x00000200)  /* Receive watchdog timeout status */
457 
#define ETH_DMASR_RPSS       ((u32)0x00000100)  /* Receive process stopped status */
458 
#define ETH_DMASR_RBUS       ((u32)0x00000080)  /* Receive buffer unavailable status */
459 
#define ETH_DMASR_RS         ((u32)0x00000040)  /* Receive status */
460 
#define ETH_DMASR_TUS        ((u32)0x00000020)  /* Transmit underflow status */
461 
#define ETH_DMASR_ROS        ((u32)0x00000010)  /* Receive overflow status */
462 
#define ETH_DMASR_TJTS       ((u32)0x00000008)  /* Transmit jabber timeout status */
463 
#define ETH_DMASR_TBUS       ((u32)0x00000004)  /* Transmit buffer unavailable status */
464 
#define ETH_DMASR_TPSS       ((u32)0x00000002)  /* Transmit process stopped status */
465 
#define ETH_DMASR_TS         ((u32)0x00000001)  /* Transmit status */
466 
 
467 
/* Bit definition for Ethernet DMA Operation Mode Register */
468 
#define ETH_DMAOMR_DTCEFD    ((u32)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
469 
#define ETH_DMAOMR_RSF       ((u32)0x02000000)  /* Receive store and forward */
470 
#define ETH_DMAOMR_DFRF      ((u32)0x01000000)  /* Disable flushing of received frames */
471 
#define ETH_DMAOMR_TSF       ((u32)0x00200000)  /* Transmit store and forward */
472 
#define ETH_DMAOMR_FTF       ((u32)0x00100000)  /* Flush transmit FIFO */
473 
#define ETH_DMAOMR_TTC       ((u32)0x0001C000)  /* Transmit threshold control */
474 
  #define ETH_DMAOMR_TTC_64Bytes       ((u32)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
475 
  #define ETH_DMAOMR_TTC_128Bytes      ((u32)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
476 
  #define ETH_DMAOMR_TTC_192Bytes      ((u32)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
477 
  #define ETH_DMAOMR_TTC_256Bytes      ((u32)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
478 
  #define ETH_DMAOMR_TTC_40Bytes       ((u32)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
479 
  #define ETH_DMAOMR_TTC_32Bytes       ((u32)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
480 
  #define ETH_DMAOMR_TTC_24Bytes       ((u32)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
481 
  #define ETH_DMAOMR_TTC_16Bytes       ((u32)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
482 
#define ETH_DMAOMR_ST        ((u32)0x00002000)  /* Start/stop transmission command */
483 
#define ETH_DMAOMR_FEF       ((u32)0x00000080)  /* Forward error frames */
484 
#define ETH_DMAOMR_FUGF      ((u32)0x00000040)  /* Forward undersized good frames */
485 
#define ETH_DMAOMR_RTC       ((u32)0x00000018)  /* receive threshold control */
486 
  #define ETH_DMAOMR_RTC_64Bytes       ((u32)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
487 
  #define ETH_DMAOMR_RTC_32Bytes       ((u32)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
488 
  #define ETH_DMAOMR_RTC_96Bytes       ((u32)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
489 
  #define ETH_DMAOMR_RTC_128Bytes      ((u32)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
490 
#define ETH_DMAOMR_OSF       ((u32)0x00000004)  /* operate on second frame */
491 
#define ETH_DMAOMR_SR        ((u32)0x00000002)  /* Start/stop receive */
492 
 
493 
/* Bit definition for Ethernet DMA Interrupt Enable Register */
494 
#define ETH_DMAIER_NISE      ((u32)0x00010000)  /* Normal interrupt summary enable */
495 
#define ETH_DMAIER_AISE      ((u32)0x00008000)  /* Abnormal interrupt summary enable */
496 
#define ETH_DMAIER_ERIE      ((u32)0x00004000)  /* Early receive interrupt enable */
497 
#define ETH_DMAIER_FBEIE     ((u32)0x00002000)  /* Fatal bus error interrupt enable */
498 
#define ETH_DMAIER_ETIE      ((u32)0x00000400)  /* Early transmit interrupt enable */
499 
#define ETH_DMAIER_RWTIE     ((u32)0x00000200)  /* Receive watchdog timeout interrupt enable */
500 
#define ETH_DMAIER_RPSIE     ((u32)0x00000100)  /* Receive process stopped interrupt enable */
501 
#define ETH_DMAIER_RBUIE     ((u32)0x00000080)  /* Receive buffer unavailable interrupt enable */
502 
#define ETH_DMAIER_RIE       ((u32)0x00000040)  /* Receive interrupt enable */
503 
#define ETH_DMAIER_TUIE      ((u32)0x00000020)  /* Transmit Underflow interrupt enable */
504 
#define ETH_DMAIER_ROIE      ((u32)0x00000010)  /* Receive Overflow interrupt enable */
505 
#define ETH_DMAIER_TJTIE     ((u32)0x00000008)  /* Transmit jabber timeout interrupt enable */
506 
#define ETH_DMAIER_TBUIE     ((u32)0x00000004)  /* Transmit buffer unavailable interrupt enable */
507 
#define ETH_DMAIER_TPSIE     ((u32)0x00000002)  /* Transmit process stopped interrupt enable */
508 
#define ETH_DMAIER_TIE       ((u32)0x00000001)  /* Transmit interrupt enable */
509 
 
510 
/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
511 
#define ETH_DMAMFBOCR_OFOC   ((u32)0x10000000)  /* Overflow bit for FIFO overflow counter */
512 
#define ETH_DMAMFBOCR_MFA    ((u32)0x0FFE0000)  /* Number of frames missed by the application */
513 
#define ETH_DMAMFBOCR_OMFC   ((u32)0x00010000)  /* Overflow bit for missed frame counter */
514 
#define ETH_DMAMFBOCR_MFC    ((u32)0x0000FFFF)  /* Number of frames missed by the controller */
515 
 
516 
/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
517 
#define ETH_DMACHTDR_HTDAP   ((u32)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
518 
 
519 
/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
520 
#define ETH_DMACHRDR_HRDAP   ((u32)0xFFFFFFFF)  /* Host receive descriptor address pointer */
521 
 
522 
/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
523 
#define ETH_DMACHTBAR_HTBAP  ((u32)0xFFFFFFFF)  /* Host transmit buffer address pointer */
524 
 
525 
/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
526 
#define ETH_DMACHRBAR_HRBAP  ((u32)0xFFFFFFFF)  /* Host receive buffer address pointer */
527 
 
528 
/******************************************************************************/
529 
/*                                      Macros                                */
530 
/******************************************************************************/
531 
#define  SET_BIT(REG, BIT)   ((REG) |= (BIT))
532 
#define  CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
533 
#define  READ_BIT(REG, BIT)  ((REG) & (BIT))
534 
 
535 
/******************************************************************************/
536 
/*                         Peripheral memory map                              */
537 
/******************************************************************************/
538 
/* ETHERNET registers base address */
539 
#define ETH_BASE             ((u32)0x40028000)
540 
#define ETH_MAC_BASE         (ETH_BASE)
541 
#define ETH_MMC_BASE         (ETH_BASE + 0x0100)
542 
#define ETH_PTP_BASE         (ETH_BASE + 0x0700)
543 
#define ETH_DMA_BASE         (ETH_BASE + 0x1000)
544 
 
545 
/******************************************************************************/
546 
/*                         Peripheral declaration                             */
547 
/******************************************************************************/
548 
 
549 
/*------------------------ Non Debug Mode ------------------------------------*/
550 
#ifndef ETH_DEBUG
551 
#ifdef _ETH_MAC
552 
  #define ETH_MAC            ((ETH_MAC_TypeDef *) ETH_MAC_BASE)
553 
#endif /*_ETH_MAC */
554 
 
555 
#ifdef _ETH_MMC
556 
  #define ETH_MMC            ((ETH_MMC_TypeDef *) ETH_MMC_BASE)
557 
#endif /*_ETH_MMC */
558 
 
559 
#ifdef _ETH_PTP
560 
  #define ETH_PTP            ((ETH_PTP_TypeDef *) ETH_PTP_BASE)
561 
#endif /*_ETH_PTP */
562 
 
563 
#ifdef _ETH_DMA
564 
  #define ETH_DMA            ((ETH_DMA_TypeDef *) ETH_DMA_BASE)
565 
#endif /*_ETH_DMA */
566 
 
567 
/*------------------------ Debug Mode ----------------------------------------*/
568 
#else   /* ETH_DEBUG */
569 
#ifdef _ETH_MAC
570 
  EXT ETH_MAC_TypeDef        *ETH_MAC;
571 
#endif /*_ETH_MAC */
572 
 
573 
#ifdef _ETH_MMC
574 
  EXT ETH_MMC_TypeDef        *ETH_MMC;
575 
#endif /*_ETH_MMC */
576 
 
577 
#ifdef _ETH_PTP
578 
  EXT ETH_PTP_TypeDef        *ETH_PTP;
579 
#endif /*_ETH_PTP */
580 
 
581 
#ifdef _ETH_DMA
582 
  EXT ETH_DMA_TypeDef        *ETH_DMA;
583 
#endif /*_ETH_DMA */
584 
 
585 
#endif  /* ETH_DEBUG */
586 
 
587 
/* Exported constants --------------------------------------------------------*/
588 
/* Exported macro ------------------------------------------------------------*/
589 
/* Exported functions ------------------------------------------------------- */
590 
 
591 
#endif /* __STM32FXXX_ETH_MAP_H */
592 
 
593 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

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