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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [ST/] [STM32F10xFWLib/] [src/] [stm32f10x_fsmc.c] - Blame information for rev 608

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1 608 jeremybenn 
/**
2 
  ******************************************************************************
3 
  * @file  stm32f10x_fsmc.c
4 
  * @author  MCD Application Team
5 
  * @version  V3.0.0
6 
  * @date  04/06/2009
7 
  * @brief  This file provides all the FSMC firmware functions.
8 
  ******************************************************************************
9 
  * @copy
10 
  *
11 
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 
  *
18 
  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
19 
  */
20 
 
21 
/* Includes ------------------------------------------------------------------*/
22 
#include "stm32f10x_fsmc.h"
23 
#include "stm32f10x_rcc.h"
24 
 
25 
/** @addtogroup StdPeriph_Driver
26 
  * @{
27 
  */
28 
 
29 
/** @defgroup FSMC
30 
  * @brief FSMC driver modules
31 
  * @{
32 
  */
33 
 
34 
/** @defgroup FSMC_Private_TypesDefinitions
35 
  * @{
36 
  */
37 
/**
38 
  * @}
39 
  */
40 
 
41 
/** @defgroup FSMC_Private_Defines
42 
  * @{
43 
  */
44 
 
45 
/* --------------------- FSMC registers bit mask ---------------------------- */
46 
 
47 
/* FSMC BCRx Mask */
48 
#define BCR_MBKEN_Set                       ((uint32_t)0x00000001)
49 
#define BCR_MBKEN_Reset                     ((uint32_t)0x000FFFFE)
50 
#define BCR_FACCEN_Set                      ((uint32_t)0x00000040)
51 
 
52 
/* FSMC PCRx Mask */
53 
#define PCR_PBKEN_Set                       ((uint32_t)0x00000004)
54 
#define PCR_PBKEN_Reset                     ((uint32_t)0x000FFFFB)
55 
#define PCR_ECCEN_Set                       ((uint32_t)0x00000040)
56 
#define PCR_ECCEN_Reset                     ((uint32_t)0x000FFFBF)
57 
#define PCR_MemoryType_NAND                 ((uint32_t)0x00000008)
58 
/**
59 
  * @}
60 
  */
61 
 
62 
/** @defgroup FSMC_Private_Macros
63 
  * @{
64 
  */
65 
 
66 
/**
67 
  * @}
68 
  */
69 
 
70 
/** @defgroup FSMC_Private_Variables
71 
  * @{
72 
  */
73 
 
74 
/**
75 
  * @}
76 
  */
77 
 
78 
/** @defgroup FSMC_Private_FunctionPrototypes
79 
  * @{
80 
  */
81 
 
82 
/**
83 
  * @}
84 
  */
85 
 
86 
/** @defgroup FSMC_Private_Functions
87 
  * @{
88 
  */
89 
 
90 
/**
91 
  * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default
92 
  *   reset values.
93 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
94 
  *   This parameter can be one of the following values:
95 
  * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
96 
  * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
97 
  * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
98 
  * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
99 
  * @retval : None
100 
  */
101 
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
102 
{
103 
  /* Check the parameter */
104 
  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
105 
 
106 
  /* FSMC_Bank1_NORSRAM1 */
107 
  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
108 
  {
109 
    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
110 
  }
111 
  /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
112 
  else
113 
  {
114 
    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
115 
  }
116 
  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
117 
  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
118 
}
119 
 
120 
/**
121 
  * @brief  Deinitializes the FSMC NAND Banks registers to their default
122 
  *   reset values.
123 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
124 
  *   This parameter can be one of the following values:
125 
  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
126 
  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
127 
  * @retval : None
128 
  */
129 
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
130 
{
131 
  /* Check the parameter */
132 
  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
133 
 
134 
  if(FSMC_Bank == FSMC_Bank2_NAND)
135 
  {
136 
    /* Set the FSMC_Bank2 registers to their reset values */
137 
    FSMC_Bank2->PCR2 = 0x00000018;
138 
    FSMC_Bank2->SR2 = 0x00000040;
139 
    FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
140 
    FSMC_Bank2->PATT2 = 0xFCFCFCFC;
141 
  }
142 
  /* FSMC_Bank3_NAND */
143 
  else
144 
  {
145 
    /* Set the FSMC_Bank3 registers to their reset values */
146 
    FSMC_Bank3->PCR3 = 0x00000018;
147 
    FSMC_Bank3->SR3 = 0x00000040;
148 
    FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
149 
    FSMC_Bank3->PATT3 = 0xFCFCFCFC;
150 
  }
151 
}
152 
 
153 
/**
154 
  * @brief  Deinitializes the FSMC PCCARD Bank registers to their default
155 
  *   reset values.
156 
  * @param  None
157 
  * @retval : None
158 
  */
159 
void FSMC_PCCARDDeInit(void)
160 
{
161 
  /* Set the FSMC_Bank4 registers to their reset values */
162 
  FSMC_Bank4->PCR4 = 0x00000018;
163 
  FSMC_Bank4->SR4 = 0x00000000;
164 
  FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
165 
  FSMC_Bank4->PATT4 = 0xFCFCFCFC;
166 
  FSMC_Bank4->PIO4 = 0xFCFCFCFC;
167 
}
168 
 
169 
/**
170 
  * @brief  Initializes the FSMC NOR/SRAM Banks according to the
171 
  *   specified parameters in the FSMC_NORSRAMInitStruct.
172 
  * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
173 
  *   structure that contains the configuration information for
174 
  *   the FSMC NOR/SRAM specified Banks.
175 
  * @retval : None
176 
  */
177 
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
178 
{
179 
  /* Check the parameters */
180 
  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
181 
  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
182 
  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
183 
  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
184 
  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
185 
  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
186 
  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
187 
  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
188 
  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
189 
  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
190 
  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
191 
  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
192 
  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
193 
  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
194 
  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
195 
  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
196 
  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
197 
  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
198 
  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
199 
 
200 
  /* Bank1 NOR/SRAM control register configuration */
201 
  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
202 
            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
203 
            FSMC_NORSRAMInitStruct->FSMC_MemoryType |
204 
            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
205 
            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
206 
            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
207 
            FSMC_NORSRAMInitStruct->FSMC_WrapMode |
208 
            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
209 
            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
210 
            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
211 
            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
212 
            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
213 
  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
214 
  {
215 
    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
216 
  }
217 
  /* Bank1 NOR/SRAM timing register configuration */
218 
  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
219 
            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
220 
            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
221 
            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
222 
            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
223 
            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
224 
            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
225 
             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
226 
 
227 
 
228 
  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
229 
  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
230 
  {
231 
    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
232 
    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
233 
    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
234 
    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
235 
    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
236 
    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
237 
    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
238 
              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
239 
              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
240 
              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
241 
              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
242 
              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
243 
               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
244 
  }
245 
  else
246 
  {
247 
    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
248 
  }
249 
}
250 
 
251 
/**
252 
  * @brief  Initializes the FSMC NAND Banks according to the specified
253 
  *   parameters in the FSMC_NANDInitStruct.
254 
  * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
255 
  *   structure that contains the configuration information for
256 
  *   the FSMC NAND specified Banks.
257 
  * @retval : None
258 
  */
259 
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
260 
{
261 
  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
262 
 
263 
  /* Check the parameters */
264 
  assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
265 
  assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
266 
  assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
267 
  assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
268 
  assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
269 
  assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
270 
  assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
271 
  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
272 
  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
273 
  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
274 
  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
275 
  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
276 
  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
277 
  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
278 
  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
279 
 
280 
  /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
281 
  tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
282 
            PCR_MemoryType_NAND |
283 
            FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
284 
            FSMC_NANDInitStruct->FSMC_ECC |
285 
            FSMC_NANDInitStruct->FSMC_ECCPageSize |
286 
            (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
287 
            (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
288 
 
289 
  /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
290 
  tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
291 
            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
292 
            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
293 
            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
294 
 
295 
  /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
296 
  tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
297 
            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
298 
            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
299 
            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
300 
 
301 
  if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
302 
  {
303 
    /* FSMC_Bank2_NAND registers configuration */
304 
    FSMC_Bank2->PCR2 = tmppcr;
305 
    FSMC_Bank2->PMEM2 = tmppmem;
306 
    FSMC_Bank2->PATT2 = tmppatt;
307 
  }
308 
  else
309 
  {
310 
    /* FSMC_Bank3_NAND registers configuration */
311 
    FSMC_Bank3->PCR3 = tmppcr;
312 
    FSMC_Bank3->PMEM3 = tmppmem;
313 
    FSMC_Bank3->PATT3 = tmppatt;
314 
  }
315 
}
316 
 
317 
/**
318 
  * @brief  Initializes the FSMC PCCARD Bank according to the specified
319 
  *   parameters in the FSMC_PCCARDInitStruct.
320 
  * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
321 
  *   structure that contains the configuration information for
322 
  *   the FSMC PCCARD Bank.
323 
  * @retval : None
324 
  */
325 
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
326 
{
327 
  /* Check the parameters */
328 
  assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
329 
  assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
330 
  assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
331 
 
332 
  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
333 
  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
334 
  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
335 
  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
336 
 
337 
  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
338 
  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
339 
  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
340 
  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
341 
  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
342 
  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
343 
  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
344 
  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
345 
 
346 
  /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
347 
  FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
348 
                     FSMC_MemoryDataWidth_16b |
349 
                     (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
350 
                     (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
351 
 
352 
  /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
353 
  FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
354 
                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
355 
                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
356 
                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
357 
 
358 
  /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
359 
  FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
360 
                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
361 
                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
362 
                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
363 
 
364 
  /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
365 
  FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
366 
                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
367 
                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
368 
                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
369 
}
370 
 
371 
/**
372 
  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
373 
  * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
374 
  *   structure which will be initialized.
375 
  * @retval : None
376 
  */
377 
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
378 
{
379 
  /* Reset NOR/SRAM Init structure parameters values */
380 
  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
381 
  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
382 
  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
383 
  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
384 
  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
385 
  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
386 
  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
387 
  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
388 
  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
389 
  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
390 
  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
391 
  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
392 
  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
393 
  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
394 
  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
395 
  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
396 
  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
397 
  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
398 
  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
399 
  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
400 
  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
401 
  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
402 
  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
403 
  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
404 
  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
405 
  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
406 
}
407 
 
408 
/**
409 
  * @brief  Fills each FSMC_NANDInitStruct member with its default value.
410 
  * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
411 
  *   structure which will be initialized.
412 
  * @retval : None
413 
  */
414 
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
415 
{
416 
  /* Reset NAND Init structure parameters values */
417 
  FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
418 
  FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
419 
  FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
420 
  FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
421 
  FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
422 
  FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
423 
  FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
424 
  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
425 
  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
426 
  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
427 
  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
428 
  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
429 
  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
430 
  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
431 
  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
432 
}
433 
 
434 
/**
435 
  * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
436 
  * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
437 
  *   structure which will be initialized.
438 
  * @retval : None
439 
  */
440 
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
441 
{
442 
  /* Reset PCCARD Init structure parameters values */
443 
  FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
444 
  FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
445 
  FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
446 
  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
447 
  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
448 
  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
449 
  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
450 
  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
451 
  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
452 
  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
453 
  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
454 
  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
455 
  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
456 
  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
457 
  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
458 
}
459 
 
460 
/**
461 
  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
462 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
463 
  *   This parameter can be one of the following values:
464 
  * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
465 
  * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
466 
  * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
467 
  * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
468 
  * @param NewState: new state of the FSMC_Bank.
469 
  *   This parameter can be: ENABLE or DISABLE.
470 
  * @retval : None
471 
  */
472 
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
473 
{
474 
  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
475 
  assert_param(IS_FUNCTIONAL_STATE(NewState));
476 
 
477 
  if (NewState != DISABLE)
478 
  {
479 
    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
480 
    FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
481 
  }
482 
  else
483 
  {
484 
    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
485 
    FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
486 
  }
487 
}
488 
 
489 
/**
490 
  * @brief  Enables or disables the specified NAND Memory Bank.
491 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
492 
  *   This parameter can be one of the following values:
493 
  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
494 
  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
495 
  * @param NewState: new state of the FSMC_Bank.
496 
  *   This parameter can be: ENABLE or DISABLE.
497 
  * @retval : None
498 
  */
499 
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
500 
{
501 
  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
502 
  assert_param(IS_FUNCTIONAL_STATE(NewState));
503 
 
504 
  if (NewState != DISABLE)
505 
  {
506 
    /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
507 
    if(FSMC_Bank == FSMC_Bank2_NAND)
508 
    {
509 
      FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
510 
    }
511 
    else
512 
    {
513 
      FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
514 
    }
515 
  }
516 
  else
517 
  {
518 
    /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
519 
    if(FSMC_Bank == FSMC_Bank2_NAND)
520 
    {
521 
      FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
522 
    }
523 
    else
524 
    {
525 
      FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
526 
    }
527 
  }
528 
}
529 
 
530 
/**
531 
  * @brief  Enables or disables the PCCARD Memory Bank.
532 
  * @param NewState: new state of the PCCARD Memory Bank.
533 
  *   This parameter can be: ENABLE or DISABLE.
534 
  * @retval : None
535 
  */
536 
void FSMC_PCCARDCmd(FunctionalState NewState)
537 
{
538 
  assert_param(IS_FUNCTIONAL_STATE(NewState));
539 
 
540 
  if (NewState != DISABLE)
541 
  {
542 
    /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
543 
    FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
544 
  }
545 
  else
546 
  {
547 
    /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
548 
    FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
549 
  }
550 
}
551 
 
552 
/**
553 
  * @brief  Enables or disables the FSMC NAND ECC feature.
554 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
555 
  *   This parameter can be one of the following values:
556 
  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
557 
  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
558 
  * @param NewState: new state of the FSMC NAND ECC feature.
559 
  *   This parameter can be: ENABLE or DISABLE.
560 
  * @retval : None
561 
  */
562 
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
563 
{
564 
  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
565 
  assert_param(IS_FUNCTIONAL_STATE(NewState));
566 
 
567 
  if (NewState != DISABLE)
568 
  {
569 
    /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
570 
    if(FSMC_Bank == FSMC_Bank2_NAND)
571 
    {
572 
      FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
573 
    }
574 
    else
575 
    {
576 
      FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
577 
    }
578 
  }
579 
  else
580 
  {
581 
    /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
582 
    if(FSMC_Bank == FSMC_Bank2_NAND)
583 
    {
584 
      FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
585 
    }
586 
    else
587 
    {
588 
      FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
589 
    }
590 
  }
591 
}
592 
 
593 
/**
594 
  * @brief  Returns the error correction code register value.
595 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
596 
  *   This parameter can be one of the following values:
597 
  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
598 
  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
599 
  * @retval : The Error Correction Code (ECC) value.
600 
  */
601 
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
602 
{
603 
  uint32_t eccval = 0x00000000;
604 
 
605 
  if(FSMC_Bank == FSMC_Bank2_NAND)
606 
  {
607 
    /* Get the ECCR2 register value */
608 
    eccval = FSMC_Bank2->ECCR2;
609 
  }
610 
  else
611 
  {
612 
    /* Get the ECCR3 register value */
613 
    eccval = FSMC_Bank3->ECCR3;
614 
  }
615 
  /* Return the error correction code value */
616 
  return(eccval);
617 
}
618 
 
619 
/**
620 
  * @brief  Enables or disables the specified FSMC interrupts.
621 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
622 
  *   This parameter can be one of the following values:
623 
  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
624 
  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
625 
  * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
626 
  * @param FSMC_IT: specifies the FSMC interrupt sources to be
627 
  *   enabled or disabled.
628 
  *   This parameter can be any combination of the following values:
629 
  * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
630 
  * @arg FSMC_IT_Level: Level edge detection interrupt.
631 
  * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
632 
  * @param NewState: new state of the specified FSMC interrupts.
633 
  *   This parameter can be: ENABLE or DISABLE.
634 
  * @retval : None
635 
  */
636 
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
637 
{
638 
  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
639 
  assert_param(IS_FSMC_IT(FSMC_IT));
640 
  assert_param(IS_FUNCTIONAL_STATE(NewState));
641 
 
642 
  if (NewState != DISABLE)
643 
  {
644 
    /* Enable the selected FSMC_Bank2 interrupts */
645 
    if(FSMC_Bank == FSMC_Bank2_NAND)
646 
    {
647 
      FSMC_Bank2->SR2 |= FSMC_IT;
648 
    }
649 
    /* Enable the selected FSMC_Bank3 interrupts */
650 
    else if (FSMC_Bank == FSMC_Bank3_NAND)
651 
    {
652 
      FSMC_Bank3->SR3 |= FSMC_IT;
653 
    }
654 
    /* Enable the selected FSMC_Bank4 interrupts */
655 
    else
656 
    {
657 
      FSMC_Bank4->SR4 |= FSMC_IT;
658 
    }
659 
  }
660 
  else
661 
  {
662 
    /* Disable the selected FSMC_Bank2 interrupts */
663 
    if(FSMC_Bank == FSMC_Bank2_NAND)
664 
    {
665 
 
666 
      FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
667 
    }
668 
    /* Disable the selected FSMC_Bank3 interrupts */
669 
    else if (FSMC_Bank == FSMC_Bank3_NAND)
670 
    {
671 
      FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
672 
    }
673 
    /* Disable the selected FSMC_Bank4 interrupts */
674 
    else
675 
    {
676 
      FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
677 
    }
678 
  }
679 
}
680 
 
681 
/**
682 
  * @brief  Checks whether the specified FSMC flag is set or not.
683 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
684 
  *   This parameter can be one of the following values:
685 
  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
686 
  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
687 
  * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
688 
  * @param FSMC_FLAG: specifies the flag to check.
689 
  *   This parameter can be one of the following values:
690 
  * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
691 
  * @arg FSMC_FLAG_Level: Level detection Flag.
692 
  * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
693 
  * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
694 
  * @retval : The new state of FSMC_FLAG (SET or RESET).
695 
  */
696 
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
697 
{
698 
  FlagStatus bitstatus = RESET;
699 
  uint32_t tmpsr = 0x00000000;
700 
 
701 
  /* Check the parameters */
702 
  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
703 
  assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
704 
 
705 
  if(FSMC_Bank == FSMC_Bank2_NAND)
706 
  {
707 
    tmpsr = FSMC_Bank2->SR2;
708 
  }
709 
  else if(FSMC_Bank == FSMC_Bank3_NAND)
710 
  {
711 
    tmpsr = FSMC_Bank3->SR3;
712 
  }
713 
  /* FSMC_Bank4_PCCARD*/
714 
  else
715 
  {
716 
    tmpsr = FSMC_Bank4->SR4;
717 
  }
718 
 
719 
  /* Get the flag status */
720 
  if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
721 
  {
722 
    bitstatus = SET;
723 
  }
724 
  else
725 
  {
726 
    bitstatus = RESET;
727 
  }
728 
  /* Return the flag status */
729 
  return bitstatus;
730 
}
731 
 
732 
/**
733 
  * @brief  Clears the FSMC’s pending flags.
734 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
735 
  *   This parameter can be one of the following values:
736 
  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
737 
  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
738 
  * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
739 
  * @param FSMC_FLAG: specifies the flag to clear.
740 
  *   This parameter can be any combination of the following values:
741 
  * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
742 
  * @arg FSMC_FLAG_Level: Level detection Flag.
743 
  * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
744 
  * @retval : None
745 
  */
746 
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
747 
{
748 
 /* Check the parameters */
749 
  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
750 
  assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
751 
 
752 
  if(FSMC_Bank == FSMC_Bank2_NAND)
753 
  {
754 
    FSMC_Bank2->SR2 &= ~FSMC_FLAG;
755 
  }
756 
  else if(FSMC_Bank == FSMC_Bank3_NAND)
757 
  {
758 
    FSMC_Bank3->SR3 &= ~FSMC_FLAG;
759 
  }
760 
  /* FSMC_Bank4_PCCARD*/
761 
  else
762 
  {
763 
    FSMC_Bank4->SR4 &= ~FSMC_FLAG;
764 
  }
765 
}
766 
 
767 
/**
768 
  * @brief  Checks whether the specified FSMC interrupt has occurred or not.
769 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
770 
  *   This parameter can be one of the following values:
771 
  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
772 
  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
773 
  * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
774 
  * @param FSMC_IT: specifies the FSMC interrupt source to check.
775 
  *   This parameter can be one of the following values:
776 
  * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
777 
  * @arg FSMC_IT_Level: Level edge detection interrupt.
778 
  * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
779 
  * @retval : The new state of FSMC_IT (SET or RESET).
780 
  */
781 
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
782 
{
783 
  ITStatus bitstatus = RESET;
784 
  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
785 
 
786 
  /* Check the parameters */
787 
  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
788 
  assert_param(IS_FSMC_GET_IT(FSMC_IT));
789 
 
790 
  if(FSMC_Bank == FSMC_Bank2_NAND)
791 
  {
792 
    tmpsr = FSMC_Bank2->SR2;
793 
  }
794 
  else if(FSMC_Bank == FSMC_Bank3_NAND)
795 
  {
796 
    tmpsr = FSMC_Bank3->SR3;
797 
  }
798 
  /* FSMC_Bank4_PCCARD*/
799 
  else
800 
  {
801 
    tmpsr = FSMC_Bank4->SR4;
802 
  }
803 
 
804 
  itstatus = tmpsr & FSMC_IT;
805 
 
806 
  itenable = tmpsr & (FSMC_IT >> 3);
807 
  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
808 
  {
809 
    bitstatus = SET;
810 
  }
811 
  else
812 
  {
813 
    bitstatus = RESET;
814 
  }
815 
  return bitstatus;
816 
}
817 
 
818 
/**
819 
  * @brief  Clears the FSMC’s interrupt pending bits.
820 
  * @param FSMC_Bank: specifies the FSMC Bank to be used
821 
  *   This parameter can be one of the following values:
822 
  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
823 
  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
824 
  * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
825 
  * @param FSMC_IT: specifies the interrupt pending bit to clear.
826 
  *   This parameter can be any combination of the following values:
827 
  * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
828 
  * @arg FSMC_IT_Level: Level edge detection interrupt.
829 
  * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
830 
  * @retval : None
831 
  */
832 
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
833 
{
834 
  /* Check the parameters */
835 
  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
836 
  assert_param(IS_FSMC_IT(FSMC_IT));
837 
 
838 
  if(FSMC_Bank == FSMC_Bank2_NAND)
839 
  {
840 
    FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
841 
  }
842 
  else if(FSMC_Bank == FSMC_Bank3_NAND)
843 
  {
844 
    FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
845 
  }
846 
  /* FSMC_Bank4_PCCARD*/
847 
  else
848 
  {
849 
    FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
850 
  }
851 
}
852 
 
853 
/**
854 
  * @}
855 
  */
856 
 
857 
/**
858 
  * @}
859 
  */
860 
 
861 
/**
862 
  * @}
863 
  */
864 
 
865 
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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