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jeremybenn |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
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* File Name : stm32f10x_tim1.c
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* Author : MCD Application Team
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* Date First Issued : 09/29/2006
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* Description : This file provides all the TIM1 software functions.
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********************************************************************************
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* History:
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* 04/02/2007: V0.2
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* mm/dd/yyyy: V0.1
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* 09/29/2006: V0.01
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********************************************************************************
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_tim1.h"
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#include "stm32f10x_rcc.h"
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* ------------ TIM1 registers bit address in the alias region ----------- */
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#define TIM1_OFFSET (TIM1_BASE - PERIPH_BASE)
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/* --- TIM1 CR1 Register ---*/
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/* Alias word address of CEN bit */
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#define CR1_OFFSET (TIM1_OFFSET + 0x00)
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#define CEN_BitNumber 0x00
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#define CR1_CEN_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (CEN_BitNumber * 4))
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/* Alias word address of UDIS bit */
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#define UDIS_BitNumber 0x01
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#define CR1_UDIS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (UDIS_BitNumber * 4))
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/* Alias word address of URS bit */
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#define URS_BitNumber 0x02
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#define CR1_URS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (URS_BitNumber * 4))
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/* Alias word address of OPM bit */
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#define OPM_BitNumber 0x03
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#define CR1_OPM_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (OPM_BitNumber * 4))
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/* Alias word address of ARPE bit */
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#define ARPE_BitNumber 0x07
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#define CR1_ARPE_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (ARPE_BitNumber * 4))
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/* --- TIM1 CR2 Register --- */
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/* Alias word address of CCPC bit */
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#define CR2_OFFSET (TIM1_OFFSET + 0x04)
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#define CCPC_BitNumber 0x00
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#define CR2_CCPC_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCPC_BitNumber * 4))
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/* Alias word address of CCUS bit */
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#define CCUS_BitNumber 0x02
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#define CR2_CCUS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCUS_BitNumber * 4))
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/* Alias word address of CCDS bit */
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#define CCDS_BitNumber 0x03
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#define CR2_CCDS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCDS_BitNumber * 4))
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/* Alias word address of TI1S bit */
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#define TI1S_BitNumber 0x07
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#define CR2_TI1S_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (TI1S_BitNumber * 4))
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/* Alias word address of OIS1 bit */
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#define OIS1_BitNumber 0x08
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#define CR2_OIS1_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1_BitNumber * 4))
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/* Alias word address of OIS1N bit */
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#define OIS1N_BitNumber 0x09
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#define CR2_OIS1N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1N_BitNumber * 4))
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/* Alias word address of OIS2 bit */
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#define OIS2_BitNumber 0x0A
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#define CR2_OIS2_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2_BitNumber * 4))
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/* Alias word address of OIS2N bit */
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#define OIS2N_BitNumber 0x0B
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#define CR2_OIS2N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2N_BitNumber * 4))
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/* Alias word address of OIS3 bit */
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#define OIS3_BitNumber 0x0C
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#define CR2_OIS3_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3_BitNumber * 4))
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/* Alias word address of OIS3N bit */
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#define OIS3N_BitNumber 0x0D
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#define CR2_OIS3N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3N_BitNumber * 4))
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/* Alias word address of OIS4 bit */
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#define OIS4_BitNumber 0x0E
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#define CR2_OIS4_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS4_BitNumber * 4))
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/* --- TIM1 SMCR Register --- */
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/* Alias word address of MSM bit */
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#define SMCR_OFFSET (TIM1_OFFSET + 0x08)
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#define MSM_BitNumber 0x07
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#define SMCR_MSM_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (MSM_BitNumber * 4))
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/* Alias word address of ECE bit */
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#define ECE_BitNumber 0x0E
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#define SMCR_ECE_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (ECE_BitNumber * 4))
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/* --- TIM1 EGR Register --- */
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/* Alias word address of UG bit */
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#define EGR_OFFSET (TIM1_OFFSET + 0x14)
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#define UG_BitNumber 0x00
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#define EGR_UG_BB (PERIPH_BB_BASE + (EGR_OFFSET * 32) + (UG_BitNumber * 4))
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/* --- TIM1 CCER Register --- */
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/* Alias word address of CC1E bit */
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#define CCER_OFFSET (TIM1_OFFSET + 0x20)
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#define CC1E_BitNumber 0x00
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#define CCER_CC1E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1E_BitNumber * 4))
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/* Alias word address of CC1P bit */
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#define CC1P_BitNumber 0x01
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#define CCER_CC1P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1P_BitNumber * 4))
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/* Alias word address of CC1NE bit */
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#define CC1NE_BitNumber 0x02
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#define CCER_CC1NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NE_BitNumber * 4))
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/* Alias word address of CC1NP bit */
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#define CC1NP_BitNumber 0x03
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#define CCER_CC1NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NP_BitNumber * 4))
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/* Alias word address of CC2E bit */
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#define CC2E_BitNumber 0x04
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#define CCER_CC2E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2E_BitNumber * 4))
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/* Alias word address of CC2P bit */
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#define CC2P_BitNumber 0x05
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#define CCER_CC2P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2P_BitNumber * 4))
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/* Alias word address of CC2NE bit */
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#define CC2NE_BitNumber 0x06
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#define CCER_CC2NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NE_BitNumber * 4))
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/* Alias word address of CC2NP bit */
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#define CC2NP_BitNumber 0x07
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#define CCER_CC2NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NP_BitNumber * 4))
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/* Alias word address of CC3E bit */
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#define CC3E_BitNumber 0x08
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#define CCER_CC3E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3E_BitNumber * 4))
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/* Alias word address of CC3P bit */
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#define CC3P_BitNumber 0x09
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#define CCER_CC3P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3P_BitNumber * 4))
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/* Alias word address of CC3NE bit */
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#define CC3NE_BitNumber 0x0A
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#define CCER_CC3NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NE_BitNumber * 4))
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/* Alias word address of CC3NP bit */
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#define CC3NP_BitNumber 0x0B
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#define CCER_CC3NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NP_BitNumber * 4))
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/* Alias word address of CC4E bit */
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#define CC4E_BitNumber 0x0C
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#define CCER_CC4E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4E_BitNumber * 4))
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/* Alias word address of CC4P bit */
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#define CC4P_BitNumber 0x0D
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#define CCER_CC4P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4P_BitNumber * 4))
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/* --- TIM1 BDTR Register --- */
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/* Alias word address of MOE bit */
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#define BDTR_OFFSET (TIM1_OFFSET + 0x44)
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#define MOE_BitNumber 0x0F
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#define BDTR_MOE_BB (PERIPH_BB_BASE + (BDTR_OFFSET * 32) + (MOE_BitNumber * 4))
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/* --- TIM1 CCMR1 Register --- */
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/* Alias word address of OC1FE bit */
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#define CCMR1_OFFSET (TIM1_OFFSET + 0x18)
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#define OC1FE_BitNumber 0x02
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#define CCMR1_OC1FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1FE_BitNumber * 4))
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/* Alias word address of OC1PE bit */
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#define OC1PE_BitNumber 0x03
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#define CCMR1_OC1PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1PE_BitNumber * 4))
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/* Alias word address of OC2FE bit */
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#define OC2FE_BitNumber 0x0A
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#define CCMR1_OC2FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2FE_BitNumber * 4))
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/* Alias word address of OC2PE bit */
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#define OC2PE_BitNumber 0x0B
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#define CCMR1_OC2PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2PE_BitNumber * 4))
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/* --- TIM1 CCMR2 Register ---- */
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/* Alias word address of OC3FE bit */
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#define CCMR2_OFFSET (TIM1_OFFSET + 0x1C)
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#define OC3FE_BitNumber 0x02
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#define CCMR2_OC3FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3FE_BitNumber * 4))
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/* Alias word address of OC3PE bit */
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#define OC3PE_BitNumber 0x03
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#define CCMR2_OC3PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3PE_BitNumber * 4))
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/* Alias word address of OC4FE bit */
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#define OC4FE_BitNumber 0x0A
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#define CCMR2_OC4FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4FE_BitNumber * 4))
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/* Alias word address of OC4PE bit */
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#define OC4PE_BitNumber 0x0B
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#define CCMR2_OC4PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4PE_BitNumber * 4))
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/* --------------------- TIM1 registers bit mask ------------------------- */
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/* TIM1 CR1 Mask */
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#define CR1_CounterMode_Mask ((u16)0x039F)
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#define CR1_CKD_Mask ((u16)0x00FF)
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/* TIM1 CR2 Mask */
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#define CR2_MMS_Mask ((u16)0x0080)
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/* TIM1 SMCR Mask */
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#define SMCR_SMS_Mask ((u16)0xFFF0)
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#define SMCR_ETR_Mask ((u16)0x40F7)
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#define SMCR_TS_Mask ((u16)0xFF87)
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#define SMCR_ECE_Set ((u16)0x0001)
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/* TIM1 CCMRx Mask */
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#define CCMR_CC13S_Mask ((u16)0xFFFC)
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#define CCMR_CC24S_Mask ((u16)0xFCFF)
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#define CCMR_TI13Direct_Set ((u16)0x0001)
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#define CCMR_TI24Direct_Set ((u16)0x0100)
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#define CCMR_OCM13_Mask ((u16)0x7F0F)
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#define CCMR_OCM24_Mask ((u16)0x0F7F)
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#define CCMR_IC13PSC_Mask ((u16)0xFFF3)
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#define CCMR_IC24PSC_Mask ((u16)0xF3FF)
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#define CCMR_IC13F_Mask ((u16)0xFF0F)
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#define CCMR_IC24F_Mask ((u16)0x0FFF)
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#define OC13Mode_Mask ((u16)0xFF00)
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#define OC24Mode_Mask ((u16)0x00FF)
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/* TIM1 CCER Set/Reset Bit */
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#define CCER_CCE_Set ((u16)0x0001)
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#define CCER_CCE_Reset ((u16)0x0000)
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/* TIM1 DMA Mask */
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#define DCR_DMA_Mask ((u16)0x0000)
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/* TIM1 private Masks */
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#define TIM1_Period_Reset_Mask ((u16)0xFFFF)
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#define TIM1_Prescaler_Reset_Mask ((u16)0x0000)
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#define TIM1_RepetitionCounter_Reset_Mask ((u16)0x0000)
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#define TIM1_Pulse_Reset_Mask ((u16)0x0000)
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#define TIM1_ICFilter_Mask ((u8)0x00)
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#define TIM1_DeadTime_Reset_Mask ((u16)0x0000)
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
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u16 ExtTRGFilter);
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static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
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u8 TIM1_ICFilter);
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static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
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u8 TIM1_ICFilter);
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static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
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u8 TIM1_ICFilter);
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static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
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u8 TIM1_ICFilter);
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/*******************************************************************************
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* Function Name : TIM1_DeInit
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* Description : Deinitializes the TIM1 peripheral registers to their default
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* reset values.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void TIM1_DeInit(void)
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{
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
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}
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/*******************************************************************************
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* Function Name : TIM1_TimeBaseInit
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* Description : Initializes the TIM1 Time Base Unit according to the specified
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* parameters in the TIM1_TimeBaseInitStruct.
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|
|
* Input : - TIM1_TimeBaseInitStruct: pointer to a TIM1_TimeBaseInitTypeDef
|
290 |
|
|
* structure that contains the configuration information for
|
291 |
|
|
* the specified TIM1 peripheral.
|
292 |
|
|
* Output : None
|
293 |
|
|
* Return : None
|
294 |
|
|
*******************************************************************************/
|
295 |
|
|
void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)
|
296 |
|
|
{
|
297 |
|
|
/* Check the parameters */
|
298 |
|
|
assert(IS_TIM1_COUNTER_MODE(TIM1_TimeBaseInitStruct->TIM1_CounterMode));
|
299 |
|
|
assert(IS_TIM1_CKD_DIV(TIM1_TimeBaseInitStruct->TIM1_ClockDivision));
|
300 |
|
|
|
301 |
|
|
/* Set the Autoreload value */
|
302 |
|
|
TIM1->ARR = TIM1_TimeBaseInitStruct->TIM1_Period ;
|
303 |
|
|
|
304 |
|
|
/* Set the Prescaler value */
|
305 |
|
|
TIM1->PSC = TIM1_TimeBaseInitStruct->TIM1_Prescaler;
|
306 |
|
|
|
307 |
|
|
/* Select the Counter Mode and set the clock division */
|
308 |
|
|
TIM1->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
|
309 |
|
|
TIM1->CR1 |= (u32)TIM1_TimeBaseInitStruct->TIM1_ClockDivision |
|
310 |
|
|
TIM1_TimeBaseInitStruct->TIM1_CounterMode;
|
311 |
|
|
|
312 |
|
|
/* Set the Repetition Counter value */
|
313 |
|
|
TIM1->RCR = TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter;
|
314 |
|
|
}
|
315 |
|
|
|
316 |
|
|
/*******************************************************************************
|
317 |
|
|
* Function Name : TIM1_OC1Init
|
318 |
|
|
* Description : Initializes the TIM1 Channel1 according to the specified
|
319 |
|
|
* parameters in the TIM1_OCInitStruct.
|
320 |
|
|
* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
|
321 |
|
|
* contains the configuration information for the TIM1 peripheral.
|
322 |
|
|
* Output : None
|
323 |
|
|
* Return : None
|
324 |
|
|
*******************************************************************************/
|
325 |
|
|
void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
|
326 |
|
|
{
|
327 |
|
|
u16 tmpccmr = 0;
|
328 |
|
|
|
329 |
|
|
/* Check the parameters */
|
330 |
|
|
assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
|
331 |
|
|
assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
|
332 |
|
|
assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
|
333 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
|
334 |
|
|
assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
|
335 |
|
|
assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
|
336 |
|
|
assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
|
337 |
|
|
|
338 |
|
|
tmpccmr = TIM1->CCMR1;
|
339 |
|
|
|
340 |
|
|
/* Disable the Channel 1: Reset the CCE Bit */
|
341 |
|
|
*(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
|
342 |
|
|
|
343 |
|
|
/* Reset the Output Compare Bits */
|
344 |
|
|
tmpccmr &= OC13Mode_Mask;
|
345 |
|
|
|
346 |
|
|
/* Set the Ouput Compare Mode */
|
347 |
|
|
tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
|
348 |
|
|
|
349 |
|
|
TIM1->CCMR1 = tmpccmr;
|
350 |
|
|
|
351 |
|
|
/* Set the Output State */
|
352 |
|
|
*(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState;
|
353 |
|
|
|
354 |
|
|
/* Set the Output N State */
|
355 |
|
|
*(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
|
356 |
|
|
|
357 |
|
|
/* Set the Output Polarity */
|
358 |
|
|
*(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
|
359 |
|
|
|
360 |
|
|
/* Set the Output N Polarity */
|
361 |
|
|
*(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
|
362 |
|
|
|
363 |
|
|
/* Set the Output Idle state */
|
364 |
|
|
*(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
|
365 |
|
|
|
366 |
|
|
/* Set the Output N Idle state */
|
367 |
|
|
*(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
|
368 |
|
|
|
369 |
|
|
/* Set the Pulse value */
|
370 |
|
|
TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse;
|
371 |
|
|
}
|
372 |
|
|
|
373 |
|
|
/*******************************************************************************
|
374 |
|
|
* Function Name : TIM1_OC2Init
|
375 |
|
|
* Description : Initializes the TIM1 Channel2 according to the specified
|
376 |
|
|
* parameters in the TIM1_OCInitStruct.
|
377 |
|
|
* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
|
378 |
|
|
* contains the configuration information for the TIM1 peripheral.
|
379 |
|
|
* Output : None
|
380 |
|
|
* Return : None
|
381 |
|
|
*******************************************************************************/
|
382 |
|
|
void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
|
383 |
|
|
{
|
384 |
|
|
u32 tmpccmr = 0;
|
385 |
|
|
|
386 |
|
|
/* Check the parameters */
|
387 |
|
|
assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
|
388 |
|
|
assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
|
389 |
|
|
assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
|
390 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
|
391 |
|
|
assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
|
392 |
|
|
assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
|
393 |
|
|
assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
|
394 |
|
|
|
395 |
|
|
tmpccmr = TIM1->CCMR1;
|
396 |
|
|
|
397 |
|
|
/* Disable the Channel 2: Reset the CCE Bit */
|
398 |
|
|
*(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
|
399 |
|
|
|
400 |
|
|
/* Reset the Output Compare Bits */
|
401 |
|
|
tmpccmr &= OC24Mode_Mask;
|
402 |
|
|
|
403 |
|
|
/* Set the Ouput Compare Mode */
|
404 |
|
|
tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
|
405 |
|
|
|
406 |
|
|
TIM1->CCMR1 = (u16)tmpccmr;
|
407 |
|
|
|
408 |
|
|
/* Set the Output State */
|
409 |
|
|
*(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState;
|
410 |
|
|
|
411 |
|
|
/* Set the Output N State */
|
412 |
|
|
*(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
|
413 |
|
|
|
414 |
|
|
/* Set the Output Polarity */
|
415 |
|
|
*(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
|
416 |
|
|
|
417 |
|
|
/* Set the Output N Polarity */
|
418 |
|
|
*(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
|
419 |
|
|
|
420 |
|
|
/* Set the Output Idle state */
|
421 |
|
|
*(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
|
422 |
|
|
|
423 |
|
|
/* Set the Output N Idle state */
|
424 |
|
|
*(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
|
425 |
|
|
|
426 |
|
|
/* Set the Pulse value */
|
427 |
|
|
TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse;
|
428 |
|
|
}
|
429 |
|
|
|
430 |
|
|
/*******************************************************************************
|
431 |
|
|
* Function Name : TIM1_OC3Init
|
432 |
|
|
* Description : Initializes the TIM1 Channel3 according to the specified
|
433 |
|
|
* parameters in the TIM1_OCInitStruct.
|
434 |
|
|
* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
|
435 |
|
|
* contains the configuration information for the TIM1 peripheral.
|
436 |
|
|
* Output : None
|
437 |
|
|
* Return : None
|
438 |
|
|
*******************************************************************************/
|
439 |
|
|
void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
|
440 |
|
|
{
|
441 |
|
|
u16 tmpccmr = 0;
|
442 |
|
|
|
443 |
|
|
/* Check the parameters */
|
444 |
|
|
assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
|
445 |
|
|
assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
|
446 |
|
|
assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
|
447 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
|
448 |
|
|
assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
|
449 |
|
|
assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
|
450 |
|
|
assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
|
451 |
|
|
|
452 |
|
|
tmpccmr = TIM1->CCMR2;
|
453 |
|
|
|
454 |
|
|
/* Disable the Channel 3: Reset the CCE Bit */
|
455 |
|
|
*(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
|
456 |
|
|
|
457 |
|
|
/* Reset the Output Compare Bits */
|
458 |
|
|
tmpccmr &= OC13Mode_Mask;
|
459 |
|
|
|
460 |
|
|
/* Set the Ouput Compare Mode */
|
461 |
|
|
tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
|
462 |
|
|
|
463 |
|
|
TIM1->CCMR2 = tmpccmr;
|
464 |
|
|
|
465 |
|
|
/* Set the Output State */
|
466 |
|
|
*(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState;
|
467 |
|
|
|
468 |
|
|
/* Set the Output N State */
|
469 |
|
|
*(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
|
470 |
|
|
|
471 |
|
|
/* Set the Output Polarity */
|
472 |
|
|
*(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
|
473 |
|
|
|
474 |
|
|
/* Set the Output N Polarity */
|
475 |
|
|
*(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
|
476 |
|
|
|
477 |
|
|
/* Set the Output Idle state */
|
478 |
|
|
*(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
|
479 |
|
|
|
480 |
|
|
/* Set the Output N Idle state */
|
481 |
|
|
*(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
|
482 |
|
|
|
483 |
|
|
/* Set the Pulse value */
|
484 |
|
|
TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse;
|
485 |
|
|
}
|
486 |
|
|
|
487 |
|
|
/*******************************************************************************
|
488 |
|
|
* Function Name : TIM1_OC4Init
|
489 |
|
|
* Description : Initializes the TIM1 Channel4 according to the specified
|
490 |
|
|
* parameters in the TIM1_OCInitStruct.
|
491 |
|
|
* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
|
492 |
|
|
* contains the configuration information for the TIM1 peripheral.
|
493 |
|
|
* Output : None
|
494 |
|
|
* Return : None
|
495 |
|
|
*******************************************************************************/
|
496 |
|
|
void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
|
497 |
|
|
{
|
498 |
|
|
u32 tmpccmr = 0;
|
499 |
|
|
|
500 |
|
|
/* Check the parameters */
|
501 |
|
|
assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
|
502 |
|
|
assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
|
503 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
|
504 |
|
|
assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
|
505 |
|
|
|
506 |
|
|
tmpccmr = TIM1->CCMR2;
|
507 |
|
|
|
508 |
|
|
/* Disable the Channel 4: Reset the CCE Bit */
|
509 |
|
|
*(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
|
510 |
|
|
|
511 |
|
|
/* Reset the Output Compare Bits */
|
512 |
|
|
tmpccmr &= OC24Mode_Mask;
|
513 |
|
|
|
514 |
|
|
/* Set the Ouput Compare Mode */
|
515 |
|
|
tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
|
516 |
|
|
|
517 |
|
|
TIM1->CCMR2 = (u16)tmpccmr;
|
518 |
|
|
|
519 |
|
|
/* Set the Output State */
|
520 |
|
|
*(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState;
|
521 |
|
|
|
522 |
|
|
/* Set the Output Polarity */
|
523 |
|
|
*(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
|
524 |
|
|
|
525 |
|
|
/* Set the Output Idle state */
|
526 |
|
|
*(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
|
527 |
|
|
|
528 |
|
|
/* Set the Pulse value */
|
529 |
|
|
TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse;
|
530 |
|
|
}
|
531 |
|
|
|
532 |
|
|
/*******************************************************************************
|
533 |
|
|
* Function Name : TIM1_BDTRConfig
|
534 |
|
|
* Description : Configures the: Break feature, dead time, Lock level, the OSSI,
|
535 |
|
|
* the OSSR State and the AOE(automatic output enable).
|
536 |
|
|
* Input : - TIM1_BDTRInitStruct: pointer to a TIM1_BDTRInitTypeDef
|
537 |
|
|
* structure that contains the BDTR Register configuration
|
538 |
|
|
* information for the TIM1 peripheral.
|
539 |
|
|
* Output : None
|
540 |
|
|
* Return : None
|
541 |
|
|
*******************************************************************************/
|
542 |
|
|
void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct)
|
543 |
|
|
{
|
544 |
|
|
u16 tmpbdtr = 0;
|
545 |
|
|
|
546 |
|
|
/* Check the parameters */
|
547 |
|
|
assert(IS_TIM1_OSSR_STATE(TIM1_BDTRInitStruct->TIM1_OSSRState));
|
548 |
|
|
assert(IS_TIM1_OSSI_STATE(TIM1_BDTRInitStruct->TIM1_OSSIState));
|
549 |
|
|
assert(IS_TIM1_LOCK_LEVEL(TIM1_BDTRInitStruct->TIM1_LOCKLevel));
|
550 |
|
|
assert(IS_TIM1_BREAK_STATE(TIM1_BDTRInitStruct->TIM1_Break));
|
551 |
|
|
assert(IS_TIM1_BREAK_POLARITY(TIM1_BDTRInitStruct->TIM1_BreakPolarity));
|
552 |
|
|
assert(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_BDTRInitStruct->TIM1_AutomaticOutput));
|
553 |
|
|
|
554 |
|
|
tmpbdtr = TIM1->BDTR;
|
555 |
|
|
|
556 |
|
|
/* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
|
557 |
|
|
the OSSI State, the dead time value and the Automatic Output Enable Bit */
|
558 |
|
|
|
559 |
|
|
tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState |
|
560 |
|
|
TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime |
|
561 |
|
|
TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity |
|
562 |
|
|
TIM1_BDTRInitStruct->TIM1_AutomaticOutput;
|
563 |
|
|
|
564 |
|
|
TIM1->BDTR = tmpbdtr;
|
565 |
|
|
}
|
566 |
|
|
|
567 |
|
|
/*******************************************************************************
|
568 |
|
|
* Function Name : TIM1_ICInit
|
569 |
|
|
* Description : Initializes the TIM1 peripheral according to the specified
|
570 |
|
|
* parameters in the TIM1_ICInitStruct.
|
571 |
|
|
* Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure
|
572 |
|
|
* that contains the configuration information for the specified
|
573 |
|
|
* TIM1 peripheral.
|
574 |
|
|
* Output : None
|
575 |
|
|
* Return : None
|
576 |
|
|
*******************************************************************************/
|
577 |
|
|
void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
|
578 |
|
|
{
|
579 |
|
|
/* Check the parameters */
|
580 |
|
|
assert(IS_TIM1_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
|
581 |
|
|
assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
|
582 |
|
|
assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
|
583 |
|
|
assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
|
584 |
|
|
assert(IS_TIM1_IC_FILTER(TIM1_ICInitStruct->TIM1_ICFilter));
|
585 |
|
|
|
586 |
|
|
if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
|
587 |
|
|
{
|
588 |
|
|
/* TI1 Configuration */
|
589 |
|
|
TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
|
590 |
|
|
TIM1_ICInitStruct->TIM1_ICSelection,
|
591 |
|
|
TIM1_ICInitStruct->TIM1_ICFilter);
|
592 |
|
|
|
593 |
|
|
/* Set the Input Capture Prescaler value */
|
594 |
|
|
TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
|
595 |
|
|
}
|
596 |
|
|
else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_2)
|
597 |
|
|
{
|
598 |
|
|
/* TI2 Configuration */
|
599 |
|
|
TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
|
600 |
|
|
TIM1_ICInitStruct->TIM1_ICSelection,
|
601 |
|
|
TIM1_ICInitStruct->TIM1_ICFilter);
|
602 |
|
|
|
603 |
|
|
/* Set the Input Capture Prescaler value */
|
604 |
|
|
TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
|
605 |
|
|
}
|
606 |
|
|
else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_3)
|
607 |
|
|
{
|
608 |
|
|
/* TI3 Configuration */
|
609 |
|
|
TI3_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
|
610 |
|
|
TIM1_ICInitStruct->TIM1_ICSelection,
|
611 |
|
|
TIM1_ICInitStruct->TIM1_ICFilter);
|
612 |
|
|
|
613 |
|
|
/* Set the Input Capture Prescaler value */
|
614 |
|
|
TIM1_SetIC3Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
|
615 |
|
|
}
|
616 |
|
|
else
|
617 |
|
|
{
|
618 |
|
|
/* TI4 Configuration */
|
619 |
|
|
TI4_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
|
620 |
|
|
TIM1_ICInitStruct->TIM1_ICSelection,
|
621 |
|
|
TIM1_ICInitStruct->TIM1_ICFilter);
|
622 |
|
|
|
623 |
|
|
/* Set the Input Capture Prescaler value */
|
624 |
|
|
TIM1_SetIC4Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
|
625 |
|
|
}
|
626 |
|
|
}
|
627 |
|
|
|
628 |
|
|
/*******************************************************************************
|
629 |
|
|
* Function Name : TIM1_PWMIConfig
|
630 |
|
|
* Description : Configures the TIM1 peripheral in PWM Input Mode according
|
631 |
|
|
* to the specified parameters in the TIM1_ICInitStruct.
|
632 |
|
|
* Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure
|
633 |
|
|
* that contains the configuration information for the specified
|
634 |
|
|
* TIM1 peripheral.
|
635 |
|
|
* Output : None
|
636 |
|
|
* Return : None
|
637 |
|
|
*******************************************************************************/
|
638 |
|
|
void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
|
639 |
|
|
{
|
640 |
|
|
u8 ICPolarity = TIM1_ICPolarity_Rising;
|
641 |
|
|
u8 ICSelection = TIM1_ICSelection_DirectTI;
|
642 |
|
|
|
643 |
|
|
/* Check the parameters */
|
644 |
|
|
assert(IS_TIM1_PWMI_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
|
645 |
|
|
assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
|
646 |
|
|
assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
|
647 |
|
|
assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
|
648 |
|
|
|
649 |
|
|
/* Select the Opposite Input Polarity */
|
650 |
|
|
if (TIM1_ICInitStruct->TIM1_ICPolarity == TIM1_ICPolarity_Rising)
|
651 |
|
|
{
|
652 |
|
|
ICPolarity = TIM1_ICPolarity_Falling;
|
653 |
|
|
}
|
654 |
|
|
else
|
655 |
|
|
{
|
656 |
|
|
ICPolarity = TIM1_ICPolarity_Rising;
|
657 |
|
|
}
|
658 |
|
|
|
659 |
|
|
/* Select the Opposite Input */
|
660 |
|
|
if (TIM1_ICInitStruct->TIM1_ICSelection == TIM1_ICSelection_DirectTI)
|
661 |
|
|
{
|
662 |
|
|
ICSelection = TIM1_ICSelection_IndirectTI;
|
663 |
|
|
}
|
664 |
|
|
else
|
665 |
|
|
{
|
666 |
|
|
ICSelection = TIM1_ICSelection_DirectTI;
|
667 |
|
|
}
|
668 |
|
|
|
669 |
|
|
if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
|
670 |
|
|
{
|
671 |
|
|
/* TI1 Configuration */
|
672 |
|
|
TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection,
|
673 |
|
|
TIM1_ICInitStruct->TIM1_ICFilter);
|
674 |
|
|
|
675 |
|
|
/* Set the Input Capture Prescaler value */
|
676 |
|
|
TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
|
677 |
|
|
|
678 |
|
|
/* TI2 Configuration */
|
679 |
|
|
TI2_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter);
|
680 |
|
|
|
681 |
|
|
/* Set the Input Capture Prescaler value */
|
682 |
|
|
TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
|
683 |
|
|
}
|
684 |
|
|
else
|
685 |
|
|
{
|
686 |
|
|
/* TI2 Configuration */
|
687 |
|
|
TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection,
|
688 |
|
|
TIM1_ICInitStruct->TIM1_ICFilter);
|
689 |
|
|
|
690 |
|
|
/* Set the Input Capture Prescaler value */
|
691 |
|
|
TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
|
692 |
|
|
|
693 |
|
|
/* TI1 Configuration */
|
694 |
|
|
TI1_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter);
|
695 |
|
|
|
696 |
|
|
/* Set the Input Capture Prescaler value */
|
697 |
|
|
TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
|
698 |
|
|
}
|
699 |
|
|
}
|
700 |
|
|
/*******************************************************************************
|
701 |
|
|
* Function Name : TIM1_OCStructInit
|
702 |
|
|
* Description : Fills each TIM1_OCInitStruct member with its default value.
|
703 |
|
|
* Input : - TIM1_OCInitStruct : pointer to a TIM1_OCInitTypeDef structure
|
704 |
|
|
* which will be initialized.
|
705 |
|
|
* Output : None
|
706 |
|
|
* Return : None
|
707 |
|
|
*******************************************************************************/
|
708 |
|
|
void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
|
709 |
|
|
{
|
710 |
|
|
/* Set the default configuration */
|
711 |
|
|
TIM1_OCInitStruct->TIM1_OCMode = TIM1_OCMode_Timing;
|
712 |
|
|
TIM1_OCInitStruct->TIM1_OutputState = TIM1_OutputState_Disable;
|
713 |
|
|
TIM1_OCInitStruct->TIM1_OutputNState = TIM1_OutputNState_Disable;
|
714 |
|
|
TIM1_OCInitStruct->TIM1_Pulse = TIM1_Pulse_Reset_Mask;
|
715 |
|
|
TIM1_OCInitStruct->TIM1_OCPolarity = TIM1_OCPolarity_High;
|
716 |
|
|
TIM1_OCInitStruct->TIM1_OCNPolarity = TIM1_OCPolarity_High;
|
717 |
|
|
TIM1_OCInitStruct->TIM1_OCIdleState = TIM1_OCIdleState_Reset;
|
718 |
|
|
TIM1_OCInitStruct->TIM1_OCNIdleState = TIM1_OCNIdleState_Reset;
|
719 |
|
|
}
|
720 |
|
|
|
721 |
|
|
/*******************************************************************************
|
722 |
|
|
* Function Name : TIM1_ICStructInit
|
723 |
|
|
* Description : Fills each TIM1_ICInitStruct member with its default value.
|
724 |
|
|
* Input : - TIM1_ICInitStruct : pointer to a TIM1_ICInitTypeDef structure
|
725 |
|
|
* which will be initialized.
|
726 |
|
|
* Output : None
|
727 |
|
|
* Return : None
|
728 |
|
|
*******************************************************************************/
|
729 |
|
|
void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
|
730 |
|
|
{
|
731 |
|
|
/* Set the default configuration */
|
732 |
|
|
TIM1_ICInitStruct->TIM1_Channel = TIM1_Channel_1;
|
733 |
|
|
TIM1_ICInitStruct->TIM1_ICSelection = TIM1_ICSelection_DirectTI;
|
734 |
|
|
TIM1_ICInitStruct->TIM1_ICPolarity = TIM1_ICPolarity_Rising;
|
735 |
|
|
TIM1_ICInitStruct->TIM1_ICPrescaler = TIM1_ICPSC_DIV1;
|
736 |
|
|
TIM1_ICInitStruct->TIM1_ICFilter = TIM1_ICFilter_Mask;
|
737 |
|
|
}
|
738 |
|
|
|
739 |
|
|
/*******************************************************************************
|
740 |
|
|
* Function Name : TIM1_TimeBaseStructInit
|
741 |
|
|
* Description : Fills each TIM1_TimeBaseInitStruct member with its default value.
|
742 |
|
|
* Input : - TIM1_TimeBaseInitStruct : pointer to a TIM1_TimeBaseInitTypeDef
|
743 |
|
|
* structure which will be initialized.
|
744 |
|
|
* Output : None
|
745 |
|
|
* Return : None
|
746 |
|
|
*******************************************************************************/
|
747 |
|
|
void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)
|
748 |
|
|
{
|
749 |
|
|
/* Set the default configuration */
|
750 |
|
|
TIM1_TimeBaseInitStruct->TIM1_Period = TIM1_Period_Reset_Mask;
|
751 |
|
|
TIM1_TimeBaseInitStruct->TIM1_Prescaler = TIM1_Prescaler_Reset_Mask;
|
752 |
|
|
TIM1_TimeBaseInitStruct->TIM1_ClockDivision = TIM1_CKD_DIV1;
|
753 |
|
|
TIM1_TimeBaseInitStruct->TIM1_CounterMode = TIM1_CounterMode_Up;
|
754 |
|
|
TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter = TIM1_RepetitionCounter_Reset_Mask;
|
755 |
|
|
}
|
756 |
|
|
|
757 |
|
|
/*******************************************************************************
|
758 |
|
|
* Function Name : TIM1_BDTRStructInit
|
759 |
|
|
* Description : Fills each TIM1_BDTRInitStruct member with its default value.
|
760 |
|
|
* Input : - TIM1_BDTRInitStruct : pointer to a TIM1_BDTRInitTypeDef
|
761 |
|
|
* structure which will be initialized.
|
762 |
|
|
* Output : None
|
763 |
|
|
* Return : None
|
764 |
|
|
*******************************************************************************/
|
765 |
|
|
void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct)
|
766 |
|
|
{
|
767 |
|
|
/* Set the default configuration */
|
768 |
|
|
TIM1_BDTRInitStruct->TIM1_OSSRState = TIM1_OSSRState_Disable;
|
769 |
|
|
TIM1_BDTRInitStruct->TIM1_OSSIState = TIM1_OSSIState_Disable;
|
770 |
|
|
TIM1_BDTRInitStruct->TIM1_LOCKLevel = TIM1_LOCKLevel_OFF;
|
771 |
|
|
TIM1_BDTRInitStruct->TIM1_DeadTime = TIM1_DeadTime_Reset_Mask;
|
772 |
|
|
TIM1_BDTRInitStruct->TIM1_Break = TIM1_Break_Disable;
|
773 |
|
|
TIM1_BDTRInitStruct->TIM1_BreakPolarity = TIM1_BreakPolarity_Low;
|
774 |
|
|
TIM1_BDTRInitStruct->TIM1_AutomaticOutput = TIM1_AutomaticOutput_Disable;
|
775 |
|
|
}
|
776 |
|
|
|
777 |
|
|
/*******************************************************************************
|
778 |
|
|
* Function Name : TIM1_Cmd
|
779 |
|
|
* Description : Enables or disables the TIM1 peripheral.
|
780 |
|
|
* Input : - Newstate: new state of the TIM1 peripheral.
|
781 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
782 |
|
|
* Output : None
|
783 |
|
|
* Return : None
|
784 |
|
|
*******************************************************************************/
|
785 |
|
|
void TIM1_Cmd(FunctionalState NewState)
|
786 |
|
|
{
|
787 |
|
|
/* Check the parameters */
|
788 |
|
|
assert(IS_FUNCTIONAL_STATE(NewState));
|
789 |
|
|
|
790 |
|
|
/* set or Reset the CEN Bit */
|
791 |
|
|
*(vu32 *) CR1_CEN_BB = (u16)NewState;
|
792 |
|
|
}
|
793 |
|
|
|
794 |
|
|
/*******************************************************************************
|
795 |
|
|
* Function Name : TIM1_CtrlPWMOutputs
|
796 |
|
|
* Description : Enables or disables the TIM1 peripheral Main Outputs.
|
797 |
|
|
* Input : - Newstate: new state of the TIM1 peripheral Main Outputs.
|
798 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
799 |
|
|
* Output : None
|
800 |
|
|
* Return : None
|
801 |
|
|
*******************************************************************************/
|
802 |
|
|
void TIM1_CtrlPWMOutputs(FunctionalState Newstate)
|
803 |
|
|
{
|
804 |
|
|
/* Check the parameters */
|
805 |
|
|
assert(IS_FUNCTIONAL_STATE(Newstate));
|
806 |
|
|
|
807 |
|
|
/* Set or Reset the MOE Bit */
|
808 |
|
|
*(vu32 *) BDTR_MOE_BB = (u16)Newstate;
|
809 |
|
|
}
|
810 |
|
|
|
811 |
|
|
/*******************************************************************************
|
812 |
|
|
* Function Name : TIM1_ITConfig
|
813 |
|
|
* Description : Enables or disables the specified TIM1 interrupts.
|
814 |
|
|
* Input : - TIM1_IT: specifies the TIM1 interrupts sources to be enabled
|
815 |
|
|
* or disabled.
|
816 |
|
|
* This parameter can be any combination of the following values:
|
817 |
|
|
* - TIM1_IT_Update: TIM1 update Interrupt source
|
818 |
|
|
* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
|
819 |
|
|
* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
|
820 |
|
|
* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
|
821 |
|
|
* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
|
822 |
|
|
* - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt
|
823 |
|
|
* source
|
824 |
|
|
* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source
|
825 |
|
|
* - TIM1_IT_Break: TIM1 Break Interrupt source
|
826 |
|
|
* - Newstate: new state of the TIM1 interrupts.
|
827 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
828 |
|
|
* Output : None
|
829 |
|
|
* Return : None
|
830 |
|
|
*******************************************************************************/
|
831 |
|
|
void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState)
|
832 |
|
|
{
|
833 |
|
|
/* Check the parameters */
|
834 |
|
|
assert(IS_TIM1_IT(TIM1_IT));
|
835 |
|
|
assert(IS_FUNCTIONAL_STATE(NewState));
|
836 |
|
|
|
837 |
|
|
if (NewState == ENABLE)
|
838 |
|
|
{
|
839 |
|
|
/* Enable the Interrupt sources */
|
840 |
|
|
TIM1->DIER |= TIM1_IT;
|
841 |
|
|
}
|
842 |
|
|
else
|
843 |
|
|
{
|
844 |
|
|
/* Disable the Interrupt sources */
|
845 |
|
|
TIM1->DIER &= (u16)~TIM1_IT;
|
846 |
|
|
}
|
847 |
|
|
}
|
848 |
|
|
|
849 |
|
|
/*******************************************************************************
|
850 |
|
|
* Function Name : TIM1_DMAConfig
|
851 |
|
|
* Description : Configures the TIM1’s DMA interface.
|
852 |
|
|
* Input : - TIM1_DMABase: DMA Base address.
|
853 |
|
|
* This parameter can be one of the following values:
|
854 |
|
|
* - TIM1_DMABase_CR1, TIM1_DMABase_CR2, TIM1_DMABase_SMCR,
|
855 |
|
|
* TIM1_DMABase_DIER, TIM1_DMABase_SR, TIM1_DMABase_EGR,
|
856 |
|
|
* TIM1_DMABase_CCMR1, TIM1_DMABase_CCMR2, TIM1_DMABase_CCER,
|
857 |
|
|
* TIM1_DMABase_CNT, TIM1_DMABase_PSC, TIM1_DMABase_ARR,
|
858 |
|
|
* TIM1_DMABase_RCR, TIM1_DMABase_CCR1, TIM1_DMABase_CCR2,
|
859 |
|
|
* TIM1_DMABase_CCR3, TIM1_DMABase_CCR4, TIM1_DMABase_BDTR,
|
860 |
|
|
* TIM1_DMABase_DCR.
|
861 |
|
|
* - TIM1_DMABurstLength: DMA Burst length.
|
862 |
|
|
* This parameter can be one value between:
|
863 |
|
|
* TIM1_DMABurstLength_1Byte and TIM1_DMABurstLength_18Bytes.
|
864 |
|
|
* Output : None
|
865 |
|
|
* Return : None
|
866 |
|
|
*******************************************************************************/
|
867 |
|
|
void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength)
|
868 |
|
|
{
|
869 |
|
|
u32 tmpdcr = 0;
|
870 |
|
|
|
871 |
|
|
/* Check the parameters */
|
872 |
|
|
assert(IS_TIM1_DMA_BASE(TIM1_DMABase));
|
873 |
|
|
assert(IS_TIM1_DMA_LENGTH(TIM1_DMABurstLength));
|
874 |
|
|
|
875 |
|
|
tmpdcr = TIM1->DCR;
|
876 |
|
|
|
877 |
|
|
/* Reset the DBA and the DBL Bits */
|
878 |
|
|
tmpdcr &= DCR_DMA_Mask;
|
879 |
|
|
|
880 |
|
|
/* Set the DMA Base and the DMA Burst Length */
|
881 |
|
|
tmpdcr |= TIM1_DMABase | TIM1_DMABurstLength;
|
882 |
|
|
|
883 |
|
|
TIM1->DCR = (u16)tmpdcr;
|
884 |
|
|
}
|
885 |
|
|
|
886 |
|
|
/*******************************************************************************
|
887 |
|
|
* Function Name : TIM1_DMACmd
|
888 |
|
|
* Description : Enables or disables the TIM1’s DMA Requests.
|
889 |
|
|
* Input : - TIM1_DMASources: specifies the DMA Request sources.
|
890 |
|
|
* This parameter can be any combination of the following values:
|
891 |
|
|
* - TIM1_DMA_Update: TIM1 update Interrupt source
|
892 |
|
|
* - TIM1_DMA_CC1: TIM1 Capture Compare 1 DMA source
|
893 |
|
|
* - TIM1_DMA_CC2: TIM1 Capture Compare 2 DMA source
|
894 |
|
|
* - TIM1_DMA_CC3: TIM1 Capture Compare 3 DMA source
|
895 |
|
|
* - TIM1_DMA_CC4: TIM1 Capture Compare 4 DMA source
|
896 |
|
|
* - TIM1_DMA_COM: TIM1 Capture Compare Update DMA
|
897 |
|
|
* source
|
898 |
|
|
* - TIM1_DMA_Trigger: TIM1 Trigger DMA source
|
899 |
|
|
* - Newstate: new state of the DMA Request sources.
|
900 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
901 |
|
|
* Output : None
|
902 |
|
|
* Return : None
|
903 |
|
|
*******************************************************************************/
|
904 |
|
|
void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate)
|
905 |
|
|
{
|
906 |
|
|
u32 tmpdier = 0;
|
907 |
|
|
|
908 |
|
|
/* Check the parameters */
|
909 |
|
|
assert(IS_TIM1_DMA_SOURCE(TIM1_DMASource));
|
910 |
|
|
assert(IS_FUNCTIONAL_STATE(Newstate));
|
911 |
|
|
|
912 |
|
|
tmpdier = TIM1->DIER;
|
913 |
|
|
|
914 |
|
|
if (Newstate == ENABLE)
|
915 |
|
|
{
|
916 |
|
|
/* Enable the DMA sources */
|
917 |
|
|
tmpdier |= TIM1_DMASource;
|
918 |
|
|
}
|
919 |
|
|
else
|
920 |
|
|
{
|
921 |
|
|
/* Disable the DMA sources */
|
922 |
|
|
tmpdier &= (u16)~TIM1_DMASource;
|
923 |
|
|
}
|
924 |
|
|
TIM1->DIER = (u16)tmpdier;
|
925 |
|
|
}
|
926 |
|
|
|
927 |
|
|
/*******************************************************************************
|
928 |
|
|
* Function Name : TIM1_InternalClockConfig
|
929 |
|
|
* Description : Configures the TIM1 interrnal Clock
|
930 |
|
|
* Input : None
|
931 |
|
|
* Output : None
|
932 |
|
|
* Return : None
|
933 |
|
|
*******************************************************************************/
|
934 |
|
|
void TIM1_InternalClockConfig(void)
|
935 |
|
|
{
|
936 |
|
|
/* Disable slave mode to clock the prescaler directly with the internal clock */
|
937 |
|
|
TIM1->SMCR &= SMCR_SMS_Mask;
|
938 |
|
|
}
|
939 |
|
|
/*******************************************************************************
|
940 |
|
|
* Function Name : TIM1_ETRClockMode1Config
|
941 |
|
|
* Description : Configures the TIM1 External clock Mode1
|
942 |
|
|
* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.
|
943 |
|
|
* It can be one of the following values:
|
944 |
|
|
* - TIM1_ExtTRGPSC_OFF
|
945 |
|
|
* - TIM1_ExtTRGPSC_DIV2
|
946 |
|
|
* - TIM1_ExtTRGPSC_DIV4
|
947 |
|
|
* - TIM1_ExtTRGPSC_DIV8.
|
948 |
|
|
* - TIM1_ExtTRGPolarity: The external Trigger Polarity.
|
949 |
|
|
* It can be one of the following values:
|
950 |
|
|
* - TIM1_ExtTRGPolarity_Inverted
|
951 |
|
|
* - TIM1_ExtTRGPolarity_NonInverted
|
952 |
|
|
* - ExtTRGFilter: External Trigger Filter.
|
953 |
|
|
* This parameter must be a value between 0x00 and 0x0F
|
954 |
|
|
* Output : None
|
955 |
|
|
* Return : None
|
956 |
|
|
*******************************************************************************/
|
957 |
|
|
void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
|
958 |
|
|
u16 ExtTRGFilter)
|
959 |
|
|
{
|
960 |
|
|
/* Check the parameters */
|
961 |
|
|
assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));
|
962 |
|
|
assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));
|
963 |
|
|
|
964 |
|
|
/* Configure the ETR Clock source */
|
965 |
|
|
ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
|
966 |
|
|
|
967 |
|
|
/* Select the External clock mode1 */
|
968 |
|
|
TIM1->SMCR &= SMCR_SMS_Mask;
|
969 |
|
|
TIM1->SMCR |= TIM1_SlaveMode_External1;
|
970 |
|
|
|
971 |
|
|
/* Select the Trigger selection : ETRF */
|
972 |
|
|
TIM1->SMCR &= SMCR_TS_Mask;
|
973 |
|
|
TIM1->SMCR |= TIM1_TS_ETRF;
|
974 |
|
|
}
|
975 |
|
|
|
976 |
|
|
/*******************************************************************************
|
977 |
|
|
* Function Name : TIM1_ETRClockMode2Config
|
978 |
|
|
* Description : Configures the TIM1 External clock Mode2
|
979 |
|
|
* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.
|
980 |
|
|
* It can be one of the following values:
|
981 |
|
|
* - TIM1_ExtTRGPSC_OFF
|
982 |
|
|
* - TIM1_ExtTRGPSC_DIV2
|
983 |
|
|
* - TIM1_ExtTRGPSC_DIV4
|
984 |
|
|
* - TIM1_ExtTRGPSC_DIV8
|
985 |
|
|
* - TIM1_ExtTRGPolarity: The external Trigger Polarity.
|
986 |
|
|
* It can be one of the following values:
|
987 |
|
|
* - TIM1_ExtTRGPolarity_Inverted
|
988 |
|
|
* - TIM1_ExtTRGPolarity_NonInverted
|
989 |
|
|
* - ExtTRGFilter: External Trigger Filter.
|
990 |
|
|
* This parameter must be a value between 0x00 and 0x0F
|
991 |
|
|
* Output : None
|
992 |
|
|
* Return : None
|
993 |
|
|
*******************************************************************************/
|
994 |
|
|
void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
|
995 |
|
|
u16 ExtTRGFilter)
|
996 |
|
|
{
|
997 |
|
|
/* Check the parameters */
|
998 |
|
|
assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));
|
999 |
|
|
assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));
|
1000 |
|
|
|
1001 |
|
|
/* Configure the ETR Clock source */
|
1002 |
|
|
ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
|
1003 |
|
|
|
1004 |
|
|
/* Enable the External clock mode2 */
|
1005 |
|
|
*(vu32 *) SMCR_ECE_BB = SMCR_ECE_Set;
|
1006 |
|
|
}
|
1007 |
|
|
|
1008 |
|
|
/*******************************************************************************
|
1009 |
|
|
* Function Name : TIM1_ITRxExternalClockConfig
|
1010 |
|
|
* Description : Configures the TIM1 Internal Trigger as External Clock
|
1011 |
|
|
* Input : - TIM1_ITRSource: Internal Trigger source.
|
1012 |
|
|
* This parameter can be one of the following values:
|
1013 |
|
|
* - TIM1_TS_ITR0: Internal Trigger 0
|
1014 |
|
|
* - TIM1_TS_ITR1: Internal Trigger 1
|
1015 |
|
|
* - TIM1_TS_ITR2: Internal Trigger 2
|
1016 |
|
|
* - TIM1_TS_ITR3: Internal Trigger 3
|
1017 |
|
|
* Output : None
|
1018 |
|
|
* Return : None
|
1019 |
|
|
*******************************************************************************/
|
1020 |
|
|
void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource)
|
1021 |
|
|
{
|
1022 |
|
|
/* Check the parameters */
|
1023 |
|
|
assert(IS_TIM1_INTERNAL_TRIGGER_SELECTION(TIM1_InputTriggerSource));
|
1024 |
|
|
|
1025 |
|
|
/* Select the Internal Trigger */
|
1026 |
|
|
TIM1_SelectInputTrigger(TIM1_InputTriggerSource);
|
1027 |
|
|
|
1028 |
|
|
/* Select the External clock mode1 */
|
1029 |
|
|
TIM1->SMCR |= TIM1_SlaveMode_External1;
|
1030 |
|
|
}
|
1031 |
|
|
|
1032 |
|
|
/*******************************************************************************
|
1033 |
|
|
* Function Name : TIM1_TIxExternalClockConfig
|
1034 |
|
|
* Description : Configures the TIM1 Trigger as External Clock
|
1035 |
|
|
* Input : - TIM1_TIxExternalCLKSource: Trigger source.
|
1036 |
|
|
* This parameter can be one of the following values:
|
1037 |
|
|
* - TIM1_TS_TI1F_ED: TI1 Edge Detector
|
1038 |
|
|
* - TIM1_TS_TI1FP1: Filtered TIM1 Input 1
|
1039 |
|
|
* - TIM1_TS_TI2FP2: Filtered TIM1 Input 2
|
1040 |
|
|
* - TIM1_ICPolarity: specifies the TIx Polarity.
|
1041 |
|
|
* This parameter can be:
|
1042 |
|
|
* - TIM1_ICPolarity_Rising
|
1043 |
|
|
* - TIM1_ICPolarity_Falling
|
1044 |
|
|
* - ICFilter : specifies the filter value.
|
1045 |
|
|
* This parameter must be a value between 0x0 and 0xF.
|
1046 |
|
|
* Output : None
|
1047 |
|
|
* Return : None
|
1048 |
|
|
*******************************************************************************/
|
1049 |
|
|
void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource,
|
1050 |
|
|
u16 TIM1_ICPolarity, u8 ICFilter)
|
1051 |
|
|
{
|
1052 |
|
|
/* Check the parameters */
|
1053 |
|
|
assert(IS_TIM1_TIX_TRIGGER_SELECTION(TIM1_TIxExternalCLKSource));
|
1054 |
|
|
assert(IS_TIM1_IC_POLARITY(TIM1_ICPolarity));
|
1055 |
|
|
assert(IS_TIM1_IC_FILTER(ICFilter));
|
1056 |
|
|
|
1057 |
|
|
/* Configure the TIM1 Input Clock Source */
|
1058 |
|
|
if (TIM1_TIxExternalCLKSource == TIM1_TIxExternalCLK1Source_TI2)
|
1059 |
|
|
{
|
1060 |
|
|
TI2_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);
|
1061 |
|
|
}
|
1062 |
|
|
else
|
1063 |
|
|
{
|
1064 |
|
|
TI1_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);
|
1065 |
|
|
}
|
1066 |
|
|
|
1067 |
|
|
/* Select the Trigger source */
|
1068 |
|
|
TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);
|
1069 |
|
|
|
1070 |
|
|
/* Select the External clock mode1 */
|
1071 |
|
|
TIM1->SMCR |= TIM1_SlaveMode_External1;
|
1072 |
|
|
}
|
1073 |
|
|
/*******************************************************************************
|
1074 |
|
|
* Function Name : TIM1_SelectInputTrigger
|
1075 |
|
|
* Description : Selects the TIM1 Input Trigger source
|
1076 |
|
|
* Input : - TIM1_InputTriggerSource: The Trigger source.
|
1077 |
|
|
* This parameter can be one of the following values:
|
1078 |
|
|
* - TIM1_TS_ITR0: Internal Trigger 0
|
1079 |
|
|
* - TIM1_TS_ITR1: Internal Trigger 1
|
1080 |
|
|
* - TIM1_TS_ITR2: Internal Trigger 2
|
1081 |
|
|
* - TIM1_TS_ITR3: Internal Trigger 3
|
1082 |
|
|
* - TIM1_TS_TI1F_ED: TI1 Edge Detector
|
1083 |
|
|
* - TIM1_TS_TI1FP1: Filtered Timer Input 1
|
1084 |
|
|
* - TIM1_TS_TI2FP2: Filtered Timer Input 2
|
1085 |
|
|
* - TIM1_TS_ETRF: External Trigger input
|
1086 |
|
|
* Output : None
|
1087 |
|
|
* Return : None
|
1088 |
|
|
*******************************************************************************/
|
1089 |
|
|
void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource)
|
1090 |
|
|
{
|
1091 |
|
|
u32 tmpsmcr = 0;
|
1092 |
|
|
|
1093 |
|
|
/* Check the parameters */
|
1094 |
|
|
assert(IS_TIM1_TRIGGER_SELECTION(TIM1_InputTriggerSource));
|
1095 |
|
|
|
1096 |
|
|
tmpsmcr = TIM1->SMCR;
|
1097 |
|
|
|
1098 |
|
|
/* Select the Tgigger Source */
|
1099 |
|
|
tmpsmcr &= SMCR_TS_Mask;
|
1100 |
|
|
tmpsmcr |= TIM1_InputTriggerSource;
|
1101 |
|
|
|
1102 |
|
|
TIM1->SMCR = (u16)tmpsmcr;
|
1103 |
|
|
}
|
1104 |
|
|
|
1105 |
|
|
/*******************************************************************************
|
1106 |
|
|
* Function Name : TIM1_UpdateDisableConfig
|
1107 |
|
|
* Description : Enables or Disables the TIM1 Update event.
|
1108 |
|
|
* Input : - Newstate: new state of the TIM1 peripheral Preload register
|
1109 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1110 |
|
|
* Output : None
|
1111 |
|
|
* Return : None
|
1112 |
|
|
*******************************************************************************/
|
1113 |
|
|
void TIM1_UpdateDisableConfig(FunctionalState Newstate)
|
1114 |
|
|
{
|
1115 |
|
|
/* Check the parameters */
|
1116 |
|
|
assert(IS_FUNCTIONAL_STATE(Newstate));
|
1117 |
|
|
|
1118 |
|
|
/* Set or Reset the UDIS Bit */
|
1119 |
|
|
*(vu32 *) CR1_UDIS_BB = (u16)Newstate;
|
1120 |
|
|
}
|
1121 |
|
|
|
1122 |
|
|
/*******************************************************************************
|
1123 |
|
|
* Function Name : TIM1_UpdateRequestConfig
|
1124 |
|
|
* Description : Selects the TIM1 Update Request Interrupt source.
|
1125 |
|
|
* Input : - TIM1_UpdateSource: specifies the Update source.
|
1126 |
|
|
* This parameter can be one of the following values:
|
1127 |
|
|
* - TIM1_UpdateSource_Regular
|
1128 |
|
|
* - TIM1_UpdateSource_Global
|
1129 |
|
|
* Output : None
|
1130 |
|
|
* Return : None
|
1131 |
|
|
*******************************************************************************/
|
1132 |
|
|
void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource)
|
1133 |
|
|
{
|
1134 |
|
|
/* Check the parameters */
|
1135 |
|
|
assert(IS_TIM1_UPDATE_SOURCE(TIM1_UpdateSource));
|
1136 |
|
|
|
1137 |
|
|
/* Set or Reset the URS Bit */
|
1138 |
|
|
*(vu32 *) CR1_URS_BB = TIM1_UpdateSource;
|
1139 |
|
|
}
|
1140 |
|
|
|
1141 |
|
|
/*******************************************************************************
|
1142 |
|
|
* Function Name : TIM1_SelectHallSensor
|
1143 |
|
|
* Description : Enables or disables the TIM1’s Hall sensor interface.
|
1144 |
|
|
* Input : - Newstate: new state of the TIM1 Hall sensor interface
|
1145 |
|
|
* Output : None
|
1146 |
|
|
* Return : None
|
1147 |
|
|
*******************************************************************************/
|
1148 |
|
|
void TIM1_SelectHallSensor(FunctionalState Newstate)
|
1149 |
|
|
{
|
1150 |
|
|
/* Check the parameters */
|
1151 |
|
|
assert(IS_FUNCTIONAL_STATE(Newstate));
|
1152 |
|
|
|
1153 |
|
|
/* Set or Reset the TI1S Bit */
|
1154 |
|
|
*(vu32 *) CR2_TI1S_BB = (u16)Newstate;
|
1155 |
|
|
}
|
1156 |
|
|
|
1157 |
|
|
/*******************************************************************************
|
1158 |
|
|
* Function Name : TIM1_SelectOPM
|
1159 |
|
|
* Description : Enables or disables the TIM1’s One Pulse Mode.
|
1160 |
|
|
* Input : - TIM1_OPMode: specifies the OPM Mode to be used.
|
1161 |
|
|
* This parameter can be one of the following values:
|
1162 |
|
|
* - TIM1_OPMode_Single
|
1163 |
|
|
* - TIM1_OPMode_Repetitive
|
1164 |
|
|
* Output : None
|
1165 |
|
|
* Return : None
|
1166 |
|
|
*******************************************************************************/
|
1167 |
|
|
void TIM1_SelectOnePulseMode(u16 TIM1_OPMode)
|
1168 |
|
|
{
|
1169 |
|
|
/* Check the parameters */
|
1170 |
|
|
assert(IS_TIM1_OPM_MODE(TIM1_OPMode));
|
1171 |
|
|
|
1172 |
|
|
/* Set or Reset the OPM Bit */
|
1173 |
|
|
*(vu32 *) CR1_OPM_BB = TIM1_OPMode;
|
1174 |
|
|
}
|
1175 |
|
|
|
1176 |
|
|
/*******************************************************************************
|
1177 |
|
|
* Function Name : TIM1_SelectOutputTrigger
|
1178 |
|
|
* Description : Selects the TIM1 Trigger Output Mode.
|
1179 |
|
|
* Input : - TIM1_TRGOSource: specifies the Trigger Output source.
|
1180 |
|
|
* This paramter can be one of the following values:
|
1181 |
|
|
* - TIM1_TRGOSource_Reset
|
1182 |
|
|
* - TIM1_TRGOSource_Enable
|
1183 |
|
|
* - TIM1_TRGOSource_Update
|
1184 |
|
|
* - TIM1_TRGOSource_OC1
|
1185 |
|
|
* - TIM1_TRGOSource_OC1Ref
|
1186 |
|
|
* - TIM1_TRGOSource_OC2Ref
|
1187 |
|
|
* - TIM1_TRGOSource_OC3Ref
|
1188 |
|
|
* - TIM1_TRGOSource_OC4Ref
|
1189 |
|
|
* Output : None
|
1190 |
|
|
* Return : None
|
1191 |
|
|
*******************************************************************************/
|
1192 |
|
|
void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource)
|
1193 |
|
|
{
|
1194 |
|
|
u32 tmpcr2 = 0;
|
1195 |
|
|
|
1196 |
|
|
/* Check the parameters */
|
1197 |
|
|
assert(IS_TIM1_TRGO_SOURCE(TIM1_TRGOSource));
|
1198 |
|
|
|
1199 |
|
|
tmpcr2 = TIM1->CR2;
|
1200 |
|
|
|
1201 |
|
|
/* Reset the MMS Bits */
|
1202 |
|
|
tmpcr2 &= CR2_MMS_Mask;
|
1203 |
|
|
|
1204 |
|
|
/* Select the TRGO source */
|
1205 |
|
|
tmpcr2 |= TIM1_TRGOSource;
|
1206 |
|
|
|
1207 |
|
|
TIM1->CR2 = (u16)tmpcr2;
|
1208 |
|
|
}
|
1209 |
|
|
|
1210 |
|
|
/*******************************************************************************
|
1211 |
|
|
* Function Name : TIM1_SelectSlaveMode
|
1212 |
|
|
* Description : Selects the TIM1 Slave Mode.
|
1213 |
|
|
* Input : - TIM1_SlaveMode: specifies the TIM1 Slave Mode.
|
1214 |
|
|
* This paramter can be one of the following values:
|
1215 |
|
|
* - TIM1_SlaveMode_Reset
|
1216 |
|
|
* - TIM1_SlaveMode_Gated
|
1217 |
|
|
* - TIM1_SlaveMode_Trigger
|
1218 |
|
|
* - TIM1_SlaveMode_External1
|
1219 |
|
|
* Output : None
|
1220 |
|
|
* Return : None
|
1221 |
|
|
*******************************************************************************/
|
1222 |
|
|
void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode)
|
1223 |
|
|
{
|
1224 |
|
|
u32 tmpsmcr = 0;
|
1225 |
|
|
|
1226 |
|
|
/* Check the parameters */
|
1227 |
|
|
assert(IS_TIM1_SLAVE_MODE(TIM1_SlaveMode));
|
1228 |
|
|
|
1229 |
|
|
tmpsmcr = TIM1->SMCR;
|
1230 |
|
|
|
1231 |
|
|
/* Reset the SMS Bits */
|
1232 |
|
|
tmpsmcr &= SMCR_SMS_Mask;
|
1233 |
|
|
|
1234 |
|
|
/* Select the Slave Mode */
|
1235 |
|
|
tmpsmcr |= TIM1_SlaveMode;
|
1236 |
|
|
|
1237 |
|
|
TIM1->SMCR = (u16)tmpsmcr;
|
1238 |
|
|
}
|
1239 |
|
|
|
1240 |
|
|
/*******************************************************************************
|
1241 |
|
|
* Function Name : TIM1_SelectMasterSlaveMode
|
1242 |
|
|
* Description : Sets or Resets the TIM1 Master/Slave Mode.
|
1243 |
|
|
* Input : - TIM1_MasterSlaveMode: specifies the TIM1 Master Slave Mode.
|
1244 |
|
|
* This paramter can be one of the following values:
|
1245 |
|
|
* - TIM1_MasterSlaveMode_Enable: synchronization between
|
1246 |
|
|
* the current timer and its slaves (through TRGO).
|
1247 |
|
|
* - TIM1_MasterSlaveMode_Disable: No action
|
1248 |
|
|
* Output : None
|
1249 |
|
|
* Return : None
|
1250 |
|
|
*******************************************************************************/
|
1251 |
|
|
void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode)
|
1252 |
|
|
{
|
1253 |
|
|
/* Check the parameters */
|
1254 |
|
|
assert(IS_TIM1_MSM_STATE(TIM1_MasterSlaveMode));
|
1255 |
|
|
|
1256 |
|
|
/* Set or Reset the MSM Bit */
|
1257 |
|
|
*(vu32 *) SMCR_MSM_BB = TIM1_MasterSlaveMode;
|
1258 |
|
|
}
|
1259 |
|
|
|
1260 |
|
|
/*******************************************************************************
|
1261 |
|
|
* Function Name : TIM1_EncoderInterfaceConfig
|
1262 |
|
|
* Description : Configures the TIM1 Encoder Interface.
|
1263 |
|
|
* Input : - TIM1_EncoderMode: specifies the TIM1 Encoder Mode.
|
1264 |
|
|
* This parameter can be one of the following values:
|
1265 |
|
|
* - TIM1_EncoderMode_TI1: Counter counts on TI1FP1 edge
|
1266 |
|
|
* depending on TI2FP2 level.
|
1267 |
|
|
* - TIM1_EncoderMode_TI2: Counter counts on TI2FP2 edge
|
1268 |
|
|
* depending on TI1FP1 level.
|
1269 |
|
|
* - TIM1_EncoderMode_TI12: Counter counts on both TI1FP1 and
|
1270 |
|
|
* TI2FP2 edges depending on the level of the other input.
|
1271 |
|
|
* - TIM1_IC1Polarity: specifies the IC1 Polarity
|
1272 |
|
|
* This parmeter can be one of the following values:
|
1273 |
|
|
* - TIM1_ICPolarity_Falling
|
1274 |
|
|
* - TIM1_ICPolarity_Rising
|
1275 |
|
|
* - TIM1_IC2Polarity: specifies the IC2 Polarity
|
1276 |
|
|
* This parmeter can be one of the following values:
|
1277 |
|
|
* - TIM1_ICPolarity_Falling
|
1278 |
|
|
* - TIM1_ICPolarity_Rising
|
1279 |
|
|
* Output : None
|
1280 |
|
|
* Return : None
|
1281 |
|
|
*******************************************************************************/
|
1282 |
|
|
void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity,
|
1283 |
|
|
u16 TIM1_IC2Polarity)
|
1284 |
|
|
{
|
1285 |
|
|
u32 tmpsmcr = 0;
|
1286 |
|
|
u32 tmpccmr1 = 0;
|
1287 |
|
|
|
1288 |
|
|
/* Check the parameters */
|
1289 |
|
|
assert(IS_TIM1_ENCODER_MODE(TIM1_EncoderMode));
|
1290 |
|
|
assert(IS_TIM1_IC_POLARITY(TIM1_IC1Polarity));
|
1291 |
|
|
assert(IS_TIM1_IC_POLARITY(TIM1_IC2Polarity));
|
1292 |
|
|
|
1293 |
|
|
tmpsmcr = TIM1->SMCR;
|
1294 |
|
|
tmpccmr1 = TIM1->CCMR1;
|
1295 |
|
|
|
1296 |
|
|
/* Set the encoder Mode */
|
1297 |
|
|
tmpsmcr &= SMCR_SMS_Mask;
|
1298 |
|
|
tmpsmcr |= TIM1_EncoderMode;
|
1299 |
|
|
|
1300 |
|
|
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
1301 |
|
|
tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
|
1302 |
|
|
tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
|
1303 |
|
|
|
1304 |
|
|
/* Set the TI1 and the TI2 Polarities */
|
1305 |
|
|
*(vu32 *) CCER_CC1P_BB = TIM1_IC1Polarity;
|
1306 |
|
|
*(vu32 *) CCER_CC2P_BB = TIM1_IC2Polarity;
|
1307 |
|
|
|
1308 |
|
|
TIM1->SMCR = (u16)tmpsmcr;
|
1309 |
|
|
|
1310 |
|
|
TIM1->CCMR1 = (u16)tmpccmr1;
|
1311 |
|
|
}
|
1312 |
|
|
|
1313 |
|
|
/*******************************************************************************
|
1314 |
|
|
* Function Name : TIM1_PrescalerConfig
|
1315 |
|
|
* Description : Configures the TIM1 Prescaler.
|
1316 |
|
|
* Input : - Prescaler: specifies the Prescaler Register value
|
1317 |
|
|
* - TIM1_PSCReloadMode: specifies the TIM1 Prescaler Reload mode.
|
1318 |
|
|
* This parmeter can be one of the following values:
|
1319 |
|
|
* - TIM1_PSCReloadMode_Update: The Prescaler is loaded at
|
1320 |
|
|
* the update event.
|
1321 |
|
|
* - TIM1_PSCReloadMode_Immediate: The Prescaler is loaded
|
1322 |
|
|
* immediatly.
|
1323 |
|
|
* Output : None
|
1324 |
|
|
* Return : None
|
1325 |
|
|
*******************************************************************************/
|
1326 |
|
|
void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode)
|
1327 |
|
|
{
|
1328 |
|
|
/* Check the parameters */
|
1329 |
|
|
assert(IS_TIM1_PRESCALER_RELOAD(TIM1_PSCReloadMode));
|
1330 |
|
|
|
1331 |
|
|
/* Set the Prescaler value */
|
1332 |
|
|
TIM1->PSC = Prescaler;
|
1333 |
|
|
|
1334 |
|
|
/* Set or reset the UG Bit */
|
1335 |
|
|
*(vu32 *) EGR_UG_BB = TIM1_PSCReloadMode;
|
1336 |
|
|
}
|
1337 |
|
|
/*******************************************************************************
|
1338 |
|
|
* Function Name : TIM1_CounterModeConfig
|
1339 |
|
|
* Description : Specifies the TIM1 Counter Mode to be used.
|
1340 |
|
|
* Input : - TIM1_CounterMode: specifies the Counter Mode to be used
|
1341 |
|
|
* This parameter can be one of the following values:
|
1342 |
|
|
* - TIM1_CounterMode_Up: TIM1 Up Counting Mode
|
1343 |
|
|
* - TIM1_CounterMode_Down: TIM1 Down Counting Mode
|
1344 |
|
|
* - TIM1_CounterMode_CenterAligned1: TIM1 Center Aligned Mode1
|
1345 |
|
|
* - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
|
1346 |
|
|
* - TIM1_CounterMode_CenterAligned3: TIM1 Center Aligned Mode3
|
1347 |
|
|
* Output : None
|
1348 |
|
|
* Return : None
|
1349 |
|
|
*******************************************************************************/
|
1350 |
|
|
void TIM1_CounterModeConfig(u16 TIM1_CounterMode)
|
1351 |
|
|
{
|
1352 |
|
|
u32 tmpcr1 = 0;
|
1353 |
|
|
|
1354 |
|
|
/* Check the parameters */
|
1355 |
|
|
assert(IS_TIM1_COUNTER_MODE(TIM1_CounterMode));
|
1356 |
|
|
|
1357 |
|
|
tmpcr1 = TIM1->CR1;
|
1358 |
|
|
|
1359 |
|
|
/* Reset the CMS and DIR Bits */
|
1360 |
|
|
tmpcr1 &= CR1_CounterMode_Mask;
|
1361 |
|
|
|
1362 |
|
|
/* Set the Counter Mode */
|
1363 |
|
|
tmpcr1 |= TIM1_CounterMode;
|
1364 |
|
|
|
1365 |
|
|
TIM1->CR1 = (u16)tmpcr1;
|
1366 |
|
|
}
|
1367 |
|
|
|
1368 |
|
|
/*******************************************************************************
|
1369 |
|
|
* Function Name : TIM1_ForcedOC1Config
|
1370 |
|
|
* Description : Forces the TIM1 Channel1 output waveform to active or inactive
|
1371 |
|
|
* level.
|
1372 |
|
|
* Input : - TIM1_ForcedAction: specifies the forced Action to be set to
|
1373 |
|
|
* the output waveform.
|
1374 |
|
|
* This parameter can be one of the following values:
|
1375 |
|
|
* - TIM1_ForcedAction_Active: Force active level on OC1REF
|
1376 |
|
|
* - TIM1_ForcedAction_InActive: Force inactive level on
|
1377 |
|
|
* OC1REF.
|
1378 |
|
|
* Output : None
|
1379 |
|
|
* Return : None
|
1380 |
|
|
*******************************************************************************/
|
1381 |
|
|
void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction)
|
1382 |
|
|
{
|
1383 |
|
|
u32 tmpccmr1 = 0;
|
1384 |
|
|
|
1385 |
|
|
/* Check the parameters */
|
1386 |
|
|
assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
|
1387 |
|
|
|
1388 |
|
|
tmpccmr1 = TIM1->CCMR1;
|
1389 |
|
|
|
1390 |
|
|
/* Reset the OCM Bits */
|
1391 |
|
|
tmpccmr1 &= CCMR_OCM13_Mask;
|
1392 |
|
|
|
1393 |
|
|
/* Configure The Forced output Mode */
|
1394 |
|
|
tmpccmr1 |= TIM1_ForcedAction;
|
1395 |
|
|
|
1396 |
|
|
TIM1->CCMR1 = (u16)tmpccmr1;
|
1397 |
|
|
}
|
1398 |
|
|
|
1399 |
|
|
/*******************************************************************************
|
1400 |
|
|
* Function Name : TIM1_ForcedOC2Config
|
1401 |
|
|
* Description : Forces the TIM1 Channel2 output waveform to active or inactive
|
1402 |
|
|
* level.
|
1403 |
|
|
* Input : - TIM1_ForcedAction: specifies the forced Action to be set to
|
1404 |
|
|
* the output waveform.
|
1405 |
|
|
* This parameter can be one of the following values:
|
1406 |
|
|
* - TIM1_ForcedAction_Active: Force active level on OC2REF
|
1407 |
|
|
* - TIM1_ForcedAction_InActive: Force inactive level on
|
1408 |
|
|
* OC2REF.
|
1409 |
|
|
* Output : None
|
1410 |
|
|
* Return : None
|
1411 |
|
|
*******************************************************************************/
|
1412 |
|
|
void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction)
|
1413 |
|
|
{
|
1414 |
|
|
u32 tmpccmr1 = 0;
|
1415 |
|
|
|
1416 |
|
|
/* Check the parameters */
|
1417 |
|
|
assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
|
1418 |
|
|
|
1419 |
|
|
tmpccmr1 = TIM1->CCMR1;
|
1420 |
|
|
|
1421 |
|
|
/* Reset the OCM Bits */
|
1422 |
|
|
tmpccmr1 &= CCMR_OCM24_Mask;
|
1423 |
|
|
|
1424 |
|
|
/* Configure The Forced output Mode */
|
1425 |
|
|
tmpccmr1 |= (u32)TIM1_ForcedAction << 8;
|
1426 |
|
|
|
1427 |
|
|
TIM1->CCMR1 = (u16)tmpccmr1;
|
1428 |
|
|
}
|
1429 |
|
|
|
1430 |
|
|
/*******************************************************************************
|
1431 |
|
|
* Function Name : TIM1_ForcedOC3Config
|
1432 |
|
|
* Description : Forces the TIM1 Channel3 output waveform to active or inactive
|
1433 |
|
|
* level.
|
1434 |
|
|
* Input : - TIM1_ForcedAction: specifies the forced Action to be set to
|
1435 |
|
|
* the output waveform.
|
1436 |
|
|
* This parameter can be one of the following values:
|
1437 |
|
|
* - TIM1_ForcedAction_Active: Force active level on OC3REF
|
1438 |
|
|
* - TIM1_ForcedAction_InActive: Force inactive level on
|
1439 |
|
|
* OC3REF.
|
1440 |
|
|
* Output : None
|
1441 |
|
|
* Return : None
|
1442 |
|
|
*******************************************************************************/
|
1443 |
|
|
void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction)
|
1444 |
|
|
{
|
1445 |
|
|
u32 tmpccmr2 = 0;
|
1446 |
|
|
|
1447 |
|
|
/* Check the parameters */
|
1448 |
|
|
assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
|
1449 |
|
|
|
1450 |
|
|
tmpccmr2 = TIM1->CCMR2;
|
1451 |
|
|
|
1452 |
|
|
/* Reset the OCM Bits */
|
1453 |
|
|
tmpccmr2 &= CCMR_OCM13_Mask;
|
1454 |
|
|
|
1455 |
|
|
/* Configure The Forced output Mode */
|
1456 |
|
|
tmpccmr2 |= TIM1_ForcedAction;
|
1457 |
|
|
|
1458 |
|
|
TIM1->CCMR2 = (u16)tmpccmr2;
|
1459 |
|
|
}
|
1460 |
|
|
|
1461 |
|
|
/*******************************************************************************
|
1462 |
|
|
* Function Name : TIM1_ForcedOC4Config
|
1463 |
|
|
* Description : Forces the TIM1 Channel4 output waveform to active or inactive
|
1464 |
|
|
* level.
|
1465 |
|
|
* Input : - TIM1_ForcedAction: specifies the forced Action to be set to
|
1466 |
|
|
* the output waveform.
|
1467 |
|
|
* This parameter can be one of the following values:
|
1468 |
|
|
* - TIM1_ForcedAction_Active: Force active level on OC4REF
|
1469 |
|
|
* - TIM1_ForcedAction_InActive: Force inactive level on
|
1470 |
|
|
* OC4REF.
|
1471 |
|
|
* Output : None
|
1472 |
|
|
* Return : None
|
1473 |
|
|
*******************************************************************************/
|
1474 |
|
|
void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction)
|
1475 |
|
|
{
|
1476 |
|
|
u32 tmpccmr2 = 0;
|
1477 |
|
|
|
1478 |
|
|
/* Check the parameters */
|
1479 |
|
|
assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
|
1480 |
|
|
|
1481 |
|
|
tmpccmr2 = TIM1->CCMR1;
|
1482 |
|
|
|
1483 |
|
|
/* Reset the OCM Bits */
|
1484 |
|
|
tmpccmr2 &= CCMR_OCM24_Mask;
|
1485 |
|
|
|
1486 |
|
|
/* Configure The Forced output Mode */
|
1487 |
|
|
tmpccmr2 |= (u16)((u16)TIM1_ForcedAction << 8);
|
1488 |
|
|
|
1489 |
|
|
TIM1->CCMR2 = (u16)tmpccmr2;
|
1490 |
|
|
}
|
1491 |
|
|
|
1492 |
|
|
/*******************************************************************************
|
1493 |
|
|
* Function Name : TIM1_ARRPreloadConfig
|
1494 |
|
|
* Description : Enables or disables TIM1 peripheral Preload register on ARR.
|
1495 |
|
|
* Input : - Newstate: new state of the TIM1 peripheral Preload register
|
1496 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1497 |
|
|
* Output : None
|
1498 |
|
|
* Return : None
|
1499 |
|
|
*******************************************************************************/
|
1500 |
|
|
void TIM1_ARRPreloadConfig(FunctionalState Newstate)
|
1501 |
|
|
{
|
1502 |
|
|
/* Check the parameters */
|
1503 |
|
|
assert(IS_FUNCTIONAL_STATE(Newstate));
|
1504 |
|
|
|
1505 |
|
|
/* Set or Reset the ARPE Bit */
|
1506 |
|
|
*(vu32 *) CR1_ARPE_BB = (u16)Newstate;
|
1507 |
|
|
}
|
1508 |
|
|
|
1509 |
|
|
/*******************************************************************************
|
1510 |
|
|
* Function Name : TIM1_SelectCOM
|
1511 |
|
|
* Description : Selects the TIM1 peripheral Commutation event.
|
1512 |
|
|
* Input : - Newstate: new state of the Commutation event.
|
1513 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1514 |
|
|
* Output : None
|
1515 |
|
|
* Return : None
|
1516 |
|
|
*******************************************************************************/
|
1517 |
|
|
void TIM1_SelectCOM(FunctionalState Newstate)
|
1518 |
|
|
{
|
1519 |
|
|
/* Check the parameters */
|
1520 |
|
|
assert(IS_FUNCTIONAL_STATE(Newstate));
|
1521 |
|
|
|
1522 |
|
|
/* Set or Reset the CCUS Bit */
|
1523 |
|
|
*(vu32 *) CR2_CCUS_BB = (u16)Newstate;
|
1524 |
|
|
}
|
1525 |
|
|
|
1526 |
|
|
/*******************************************************************************
|
1527 |
|
|
* Function Name : TIM1_SelectCCDMA
|
1528 |
|
|
* Description : Selects the TIM1 peripheral Capture Compare DMA source.
|
1529 |
|
|
* Input : - Newstate: new state of the Capture Compare DMA source
|
1530 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1531 |
|
|
* Output : None
|
1532 |
|
|
* Return : None
|
1533 |
|
|
*******************************************************************************/
|
1534 |
|
|
void TIM1_SelectCCDMA(FunctionalState Newstate)
|
1535 |
|
|
{
|
1536 |
|
|
/* Check the parameters */
|
1537 |
|
|
assert(IS_FUNCTIONAL_STATE(Newstate));
|
1538 |
|
|
|
1539 |
|
|
/* Set or Reset the CCDS Bit */
|
1540 |
|
|
*(vu32 *) CR2_CCDS_BB = (u16)Newstate;
|
1541 |
|
|
}
|
1542 |
|
|
|
1543 |
|
|
/*******************************************************************************
|
1544 |
|
|
* Function Name : TIM1_CCPreloadControl
|
1545 |
|
|
* Description : Sets or Resets the TIM1 peripheral Capture Compare Preload
|
1546 |
|
|
* Control bit.
|
1547 |
|
|
* Input : - Newstate: new state of the Capture Compare Preload Control bit
|
1548 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1549 |
|
|
* Output : None
|
1550 |
|
|
* Return : None
|
1551 |
|
|
*******************************************************************************/
|
1552 |
|
|
void TIM1_CCPreloadControl(FunctionalState Newstate)
|
1553 |
|
|
{
|
1554 |
|
|
/* Check the parameters */
|
1555 |
|
|
assert(IS_FUNCTIONAL_STATE(Newstate));
|
1556 |
|
|
|
1557 |
|
|
/* Set or Reset the CCPC Bit */
|
1558 |
|
|
*(vu32 *) CR2_CCPC_BB = (u16)Newstate;
|
1559 |
|
|
}
|
1560 |
|
|
|
1561 |
|
|
/*******************************************************************************
|
1562 |
|
|
* Function Name : TIM1_OC1PreloadConfig
|
1563 |
|
|
* Description : Enables or disables the TIM1 peripheral Preload Register on CCR1.
|
1564 |
|
|
* Input : - TIM1_OCPreload: new state of the Capture Compare Preload
|
1565 |
|
|
* register.
|
1566 |
|
|
* This parameter can be one of the following values:
|
1567 |
|
|
* - TIM1_OCPreload_Enable
|
1568 |
|
|
* - TIM1_OCPreload_Disable
|
1569 |
|
|
* Output : None
|
1570 |
|
|
* Return : None
|
1571 |
|
|
*******************************************************************************/
|
1572 |
|
|
void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload)
|
1573 |
|
|
{
|
1574 |
|
|
/* Check the parameters */
|
1575 |
|
|
assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
|
1576 |
|
|
|
1577 |
|
|
/* Set or Reset the OC1PE Bit */
|
1578 |
|
|
*(vu32 *) CCMR1_OC1PE_BB = (u16)TIM1_OCPreload;
|
1579 |
|
|
}
|
1580 |
|
|
|
1581 |
|
|
/*******************************************************************************
|
1582 |
|
|
* Function Name : TIM1_OC2PreloadConfig
|
1583 |
|
|
* Description : Enables or disables the TIM1 peripheral Preload Register on CCR2.
|
1584 |
|
|
* Input : - TIM1_OCPreload: new state of the Capture Compare Preload
|
1585 |
|
|
* register.
|
1586 |
|
|
* This parameter can be one of the following values:
|
1587 |
|
|
* - TIM1_OCPreload_Enable
|
1588 |
|
|
* - TIM1_OCPreload_Disable
|
1589 |
|
|
* Output : None
|
1590 |
|
|
* Return : None
|
1591 |
|
|
*******************************************************************************/
|
1592 |
|
|
void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload)
|
1593 |
|
|
{
|
1594 |
|
|
/* Check the parameters */
|
1595 |
|
|
assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
|
1596 |
|
|
|
1597 |
|
|
/* Set or Reset the OC2PE Bit */
|
1598 |
|
|
*(vu32 *) CCMR1_OC2PE_BB = (u16)TIM1_OCPreload;
|
1599 |
|
|
}
|
1600 |
|
|
|
1601 |
|
|
/*******************************************************************************
|
1602 |
|
|
* Function Name : TIM1_OC3PreloadConfig
|
1603 |
|
|
* Description : Enables or disables the TIM1 peripheral Preload Register on CCR3.
|
1604 |
|
|
* Input : - TIM1_OCPreload: new state of the Capture Compare Preload
|
1605 |
|
|
* register.
|
1606 |
|
|
* This parameter can be one of the following values:
|
1607 |
|
|
* - TIM1_OCPreload_Enable
|
1608 |
|
|
* - TIM1_OCPreload_Disable
|
1609 |
|
|
* Output : None
|
1610 |
|
|
* Return : None
|
1611 |
|
|
*******************************************************************************/
|
1612 |
|
|
void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload)
|
1613 |
|
|
{
|
1614 |
|
|
/* Check the parameters */
|
1615 |
|
|
assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
|
1616 |
|
|
|
1617 |
|
|
/* Set or Reset the OC3PE Bit */
|
1618 |
|
|
*(vu32 *) CCMR2_OC3PE_BB = (u16)TIM1_OCPreload;
|
1619 |
|
|
}
|
1620 |
|
|
|
1621 |
|
|
/*******************************************************************************
|
1622 |
|
|
* Function Name : TIM1_OC4PreloadConfig
|
1623 |
|
|
* Description : Enables or disables the TIM1 peripheral Preload Register on CCR4.
|
1624 |
|
|
* Input : - TIM1_OCPreload: new state of the Capture Compare Preload
|
1625 |
|
|
* register.
|
1626 |
|
|
* This parameter can be one of the following values:
|
1627 |
|
|
* - TIM1_OCPreload_Enable
|
1628 |
|
|
* - TIM1_OCPreload_Disable
|
1629 |
|
|
* Output : None
|
1630 |
|
|
* Return : None
|
1631 |
|
|
*******************************************************************************/
|
1632 |
|
|
void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload)
|
1633 |
|
|
{
|
1634 |
|
|
/* Check the parameters */
|
1635 |
|
|
assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
|
1636 |
|
|
|
1637 |
|
|
/* Set or Reset the OC4PE Bit */
|
1638 |
|
|
*(vu32 *) CCMR2_OC4PE_BB = (u16)TIM1_OCPreload;
|
1639 |
|
|
}
|
1640 |
|
|
|
1641 |
|
|
/*******************************************************************************
|
1642 |
|
|
* Function Name : TIM1_OC1FastConfig
|
1643 |
|
|
* Description : Configures the TIM1 Capture Compare 1 Fast feature.
|
1644 |
|
|
* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
|
1645 |
|
|
* This parameter can be one of the following values:
|
1646 |
|
|
* - TIM1_OCFast_Enable
|
1647 |
|
|
* - TIM1_OCFast_Disable
|
1648 |
|
|
* Output : None
|
1649 |
|
|
* Return : None
|
1650 |
|
|
*******************************************************************************/
|
1651 |
|
|
void TIM1_OC1FastConfig(u16 TIM1_OCFast)
|
1652 |
|
|
{
|
1653 |
|
|
/* Check the parameters */
|
1654 |
|
|
assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
|
1655 |
|
|
|
1656 |
|
|
/* Set or Reset the OC1FE Bit */
|
1657 |
|
|
*(vu32 *) CCMR1_OC1FE_BB = (u16)TIM1_OCFast;
|
1658 |
|
|
}
|
1659 |
|
|
|
1660 |
|
|
/*******************************************************************************
|
1661 |
|
|
* Function Name : TIM1_OC2FastConfig
|
1662 |
|
|
* Description : Configures the TIM1 Capture Compare Fast feature.
|
1663 |
|
|
* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
|
1664 |
|
|
* This parameter can be one of the following values:
|
1665 |
|
|
* - TIM1_OCFast_Enable
|
1666 |
|
|
* - TIM1_OCFast_Disable
|
1667 |
|
|
* Output : None
|
1668 |
|
|
* Return : None
|
1669 |
|
|
*******************************************************************************/
|
1670 |
|
|
void TIM1_OC2FastConfig(u16 TIM1_OCFast)
|
1671 |
|
|
{
|
1672 |
|
|
/* Check the parameters */
|
1673 |
|
|
assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
|
1674 |
|
|
|
1675 |
|
|
/* Set or Reset the OC2FE Bit */
|
1676 |
|
|
*(vu32 *) CCMR1_OC2FE_BB = (u16)TIM1_OCFast;
|
1677 |
|
|
}
|
1678 |
|
|
|
1679 |
|
|
/*******************************************************************************
|
1680 |
|
|
* Function Name : TIM1_OC3FastConfig
|
1681 |
|
|
* Description : Configures the TIM1 Capture Compare Fast feature.
|
1682 |
|
|
* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
|
1683 |
|
|
* This parameter can be one of the following values:
|
1684 |
|
|
* - TIM1_OCFast_Enable
|
1685 |
|
|
* - TIM1_OCFast_Disable
|
1686 |
|
|
* Output : None
|
1687 |
|
|
* Return : None
|
1688 |
|
|
*******************************************************************************/
|
1689 |
|
|
void TIM1_OC3FastConfig(u16 TIM1_OCFast)
|
1690 |
|
|
{
|
1691 |
|
|
/* Check the parameters */
|
1692 |
|
|
assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
|
1693 |
|
|
|
1694 |
|
|
/* Set or Reset the OC3FE Bit */
|
1695 |
|
|
*(vu32 *) CCMR2_OC3FE_BB = (u16)TIM1_OCFast;
|
1696 |
|
|
}
|
1697 |
|
|
|
1698 |
|
|
/*******************************************************************************
|
1699 |
|
|
* Function Name : TIM1_OC4FastConfig
|
1700 |
|
|
* Description : Configures the TIM1 Capture Compare Fast feature.
|
1701 |
|
|
* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
|
1702 |
|
|
* This parameter can be one of the following values:
|
1703 |
|
|
* - TIM1_OCFast_Enable
|
1704 |
|
|
* - TIM1_OCFast_Disable
|
1705 |
|
|
* Output : None
|
1706 |
|
|
* Return : None
|
1707 |
|
|
*******************************************************************************/
|
1708 |
|
|
void TIM1_OC4FastConfig(u16 TIM1_OCFast)
|
1709 |
|
|
{
|
1710 |
|
|
/* Check the parameters */
|
1711 |
|
|
assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
|
1712 |
|
|
|
1713 |
|
|
/* Set or Reset the OC4FE Bit */
|
1714 |
|
|
*(vu32 *) CCMR2_OC4FE_BB = (u16)TIM1_OCFast;
|
1715 |
|
|
}
|
1716 |
|
|
|
1717 |
|
|
/*******************************************************************************
|
1718 |
|
|
* Function Name : TIM1_GenerateEvent
|
1719 |
|
|
* Description : Configures the TIM1 event to be generate by software.
|
1720 |
|
|
* Input : - TIM1_EventSource: specifies the event source.
|
1721 |
|
|
* This parameter can be one or more of the following values:
|
1722 |
|
|
* - TIM1_EventSource_Update: TIM1 update Event source
|
1723 |
|
|
* - TIM1_EventSource_CC1: TIM1 Capture Compare 1 Event source
|
1724 |
|
|
* - TIM1_EventSource_CC2: TIM1 Capture Compare 2 Event source
|
1725 |
|
|
* - TIM1_EventSource_CC3: TIM1 Capture Compare 3 Event source
|
1726 |
|
|
* - TIM1_EventSource_CC4: TIM1 Capture Compare 4 Event source
|
1727 |
|
|
* - TIM1_EventSource_COM: TIM1 COM Event source
|
1728 |
|
|
* - TIM1_EventSource_Trigger: TIM1 Trigger Event source
|
1729 |
|
|
* - TIM1_EventSourceBreak: TIM1 Break Event source
|
1730 |
|
|
* Output : None
|
1731 |
|
|
* Return : None
|
1732 |
|
|
*******************************************************************************/
|
1733 |
|
|
void TIM1_GenerateEvent(u16 TIM1_EventSource)
|
1734 |
|
|
{
|
1735 |
|
|
/* Check the parameters */
|
1736 |
|
|
assert(IS_TIM1_EVENT_SOURCE(TIM1_EventSource));
|
1737 |
|
|
|
1738 |
|
|
/* Set the event sources */
|
1739 |
|
|
TIM1->EGR |= TIM1_EventSource;
|
1740 |
|
|
}
|
1741 |
|
|
|
1742 |
|
|
/*******************************************************************************
|
1743 |
|
|
* Function Name : TIM1_OC1PolarityConfig
|
1744 |
|
|
* Description : Configures the TIM1 Channel 1 polarity.
|
1745 |
|
|
* Input : - TIM1_OCPolarity: specifies the OC1 Polarity
|
1746 |
|
|
* This parmeter can be one of the following values:
|
1747 |
|
|
* - TIM1_OCPolarity_High: Output Compare active high
|
1748 |
|
|
* - TIM1_OCPolarity_Low: Output Compare active low
|
1749 |
|
|
* Output : None
|
1750 |
|
|
* Return : None
|
1751 |
|
|
*******************************************************************************/
|
1752 |
|
|
void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity)
|
1753 |
|
|
{
|
1754 |
|
|
/* Check the parameters */
|
1755 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
|
1756 |
|
|
|
1757 |
|
|
/* Set or Reset the CC1P Bit */
|
1758 |
|
|
*(vu32 *) CCER_CC1P_BB = (u16)TIM1_OCPolarity;
|
1759 |
|
|
}
|
1760 |
|
|
|
1761 |
|
|
/*******************************************************************************
|
1762 |
|
|
* Function Name : TIM1_OC1NPolarityConfig
|
1763 |
|
|
* Description : Configures the TIM1 Channel 1N polarity.
|
1764 |
|
|
* Input : - TIM1_OCPolarity: specifies the OC1N Polarity
|
1765 |
|
|
* This parmeter can be one of the following values:
|
1766 |
|
|
* - TIM1_OCPolarity_High: Output Compare active high
|
1767 |
|
|
* - TIM1_OCPolarity_Low: Output Compare active low
|
1768 |
|
|
* Output : None
|
1769 |
|
|
* Return : None
|
1770 |
|
|
*******************************************************************************/
|
1771 |
|
|
void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity)
|
1772 |
|
|
{
|
1773 |
|
|
/* Check the parameters */
|
1774 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
|
1775 |
|
|
|
1776 |
|
|
/* Set or Reset the CC3P Bit */
|
1777 |
|
|
*(vu32 *) CCER_CC1NP_BB = (u16)TIM1_OCPolarity;
|
1778 |
|
|
}
|
1779 |
|
|
|
1780 |
|
|
/*******************************************************************************
|
1781 |
|
|
* Function Name : TIM1_OC2PolarityConfig
|
1782 |
|
|
* Description : Configures the TIM1 Channel 2 polarity.
|
1783 |
|
|
* Input : - TIM1_OCPolarity: specifies the OC2 Polarity
|
1784 |
|
|
* This parmeter can be one of the following values:
|
1785 |
|
|
* - TIM1_OCPolarity_High: Output Compare active high
|
1786 |
|
|
* - TIM1_OCPolarity_Low: Output Compare active low
|
1787 |
|
|
* Output : None
|
1788 |
|
|
* Return : None
|
1789 |
|
|
*******************************************************************************/
|
1790 |
|
|
void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity)
|
1791 |
|
|
{
|
1792 |
|
|
/* Check the parameters */
|
1793 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
|
1794 |
|
|
|
1795 |
|
|
/* Set or Reset the CC2P Bit */
|
1796 |
|
|
*(vu32 *) CCER_CC2P_BB = (u16)TIM1_OCPolarity;
|
1797 |
|
|
}
|
1798 |
|
|
|
1799 |
|
|
/*******************************************************************************
|
1800 |
|
|
* Function Name : TIM1_OC2NPolarityConfig
|
1801 |
|
|
* Description : Configures the TIM1 Channel 2N polarity.
|
1802 |
|
|
* Input : - TIM1_OCPolarity: specifies the OC2N Polarity
|
1803 |
|
|
* This parmeter can be one of the following values:
|
1804 |
|
|
* - TIM1_OCPolarity_High: Output Compare active high
|
1805 |
|
|
* - TIM1_OCPolarity_Low: Output Compare active low
|
1806 |
|
|
* Output : None
|
1807 |
|
|
* Return : None
|
1808 |
|
|
*******************************************************************************/
|
1809 |
|
|
void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity)
|
1810 |
|
|
{
|
1811 |
|
|
/* Check the parameters */
|
1812 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
|
1813 |
|
|
|
1814 |
|
|
/* Set or Reset the CC3P Bit */
|
1815 |
|
|
*(vu32 *) CCER_CC2NP_BB = (u16)TIM1_OCPolarity;
|
1816 |
|
|
}
|
1817 |
|
|
|
1818 |
|
|
/*******************************************************************************
|
1819 |
|
|
* Function Name : TIM1_OC3PolarityConfig
|
1820 |
|
|
* Description : Configures the TIM1 Channel 3 polarity.
|
1821 |
|
|
* Input : - TIM1_OCPolarity: specifies the OC3 Polarity
|
1822 |
|
|
* This parmeter can be one of the following values:
|
1823 |
|
|
* - TIM1_OCPolarity_High: Output Compare active high
|
1824 |
|
|
* - TIM1_OCPolarity_Low: Output Compare active low
|
1825 |
|
|
* Output : None
|
1826 |
|
|
* Return : None
|
1827 |
|
|
*******************************************************************************/
|
1828 |
|
|
void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity)
|
1829 |
|
|
{
|
1830 |
|
|
/* Check the parameters */
|
1831 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
|
1832 |
|
|
|
1833 |
|
|
/* Set or Reset the CC3P Bit */
|
1834 |
|
|
*(vu32 *) CCER_CC3P_BB = (u16)TIM1_OCPolarity;
|
1835 |
|
|
}
|
1836 |
|
|
|
1837 |
|
|
/*******************************************************************************
|
1838 |
|
|
* Function Name : TIM1_OC3NPolarityConfig
|
1839 |
|
|
* Description : Configures the TIM1 Channel 3N polarity.
|
1840 |
|
|
* Input : - TIM1_OCPolarity: specifies the OC3N Polarity
|
1841 |
|
|
* This parmeter can be one of the following values:
|
1842 |
|
|
* - TIM1_OCPolarity_High: Output Compare active high
|
1843 |
|
|
* - TIM1_OCPolarity_Low: Output Compare active low
|
1844 |
|
|
* Output : None
|
1845 |
|
|
* Return : None
|
1846 |
|
|
*******************************************************************************/
|
1847 |
|
|
void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity)
|
1848 |
|
|
{
|
1849 |
|
|
/* Check the parameters */
|
1850 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
|
1851 |
|
|
|
1852 |
|
|
/* Set or Reset the CC3P Bit */
|
1853 |
|
|
*(vu32 *) CCER_CC3NP_BB = (u16)TIM1_OCPolarity;
|
1854 |
|
|
}
|
1855 |
|
|
|
1856 |
|
|
/*******************************************************************************
|
1857 |
|
|
* Function Name : TIM1_OC4PolarityConfig
|
1858 |
|
|
* Description : Configures the TIM1 Channel 4 polarity.
|
1859 |
|
|
* Input : - TIM1_OCPolarity: specifies the OC4 Polarity
|
1860 |
|
|
* This parmeter can be one of the following values:
|
1861 |
|
|
* - TIM1_OCPolarity_High: Output Compare active high
|
1862 |
|
|
* - TIM1_OCPolarity_Low: Output Compare active low
|
1863 |
|
|
* Output : None
|
1864 |
|
|
* Return : None
|
1865 |
|
|
*******************************************************************************/
|
1866 |
|
|
void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity)
|
1867 |
|
|
{
|
1868 |
|
|
/* Check the parameters */
|
1869 |
|
|
assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
|
1870 |
|
|
|
1871 |
|
|
/* Set or Reset the CC4P Bit */
|
1872 |
|
|
*(vu32 *) CCER_CC4P_BB = (u16)TIM1_OCPolarity;
|
1873 |
|
|
}
|
1874 |
|
|
|
1875 |
|
|
/*******************************************************************************
|
1876 |
|
|
* Function Name : TIM1_CCxCmd
|
1877 |
|
|
* Description : Enables or disables the TIM1 Capture Compare Channel x.
|
1878 |
|
|
* Input : - TIM1_Channel: specifies the TIM1 Channel
|
1879 |
|
|
* This parmeter can be one of the following values:
|
1880 |
|
|
* - TIM1_Channel1: TIM1 Channel1
|
1881 |
|
|
* - TIM1_Channel2: TIM1 Channel2
|
1882 |
|
|
* - TIM1_Channel3: TIM1 Channel3
|
1883 |
|
|
* - TIM1_Channel4: TIM1 Channel4
|
1884 |
|
|
* - Newstate: specifies the TIM1 Channel CCxE bit new state.
|
1885 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1886 |
|
|
* Output : None
|
1887 |
|
|
* Return : None
|
1888 |
|
|
*******************************************************************************/
|
1889 |
|
|
void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate)
|
1890 |
|
|
{
|
1891 |
|
|
/* Check the parameters */
|
1892 |
|
|
assert(IS_TIM1_CHANNEL(TIM1_Channel));
|
1893 |
|
|
assert(IS_FUNCTIONAL_STATE(Newstate));
|
1894 |
|
|
|
1895 |
|
|
if(TIM1_Channel == TIM1_Channel_1)
|
1896 |
|
|
{
|
1897 |
|
|
/* Set or Reset the CC1E Bit */
|
1898 |
|
|
*(vu32 *) CCER_CC1E_BB = (u16)Newstate;
|
1899 |
|
|
}
|
1900 |
|
|
else if(TIM1_Channel == TIM1_Channel_2)
|
1901 |
|
|
{
|
1902 |
|
|
/* Set or Reset the CC2E Bit */
|
1903 |
|
|
*(vu32 *) CCER_CC2E_BB = (u16)Newstate;
|
1904 |
|
|
}
|
1905 |
|
|
else if(TIM1_Channel == TIM1_Channel_3)
|
1906 |
|
|
{
|
1907 |
|
|
/* Set or Reset the CC3E Bit */
|
1908 |
|
|
*(vu32 *) CCER_CC3E_BB = (u16)Newstate;
|
1909 |
|
|
}
|
1910 |
|
|
else
|
1911 |
|
|
{
|
1912 |
|
|
/* Set or Reset the CC4E Bit */
|
1913 |
|
|
*(vu32 *) CCER_CC4E_BB = (u16)Newstate;
|
1914 |
|
|
}
|
1915 |
|
|
}
|
1916 |
|
|
|
1917 |
|
|
/*******************************************************************************
|
1918 |
|
|
* Function Name : TIM1_CCxNCmd
|
1919 |
|
|
* Description : Enables or disables the TIM1 Capture Compare Channel xN.
|
1920 |
|
|
* Input : - TIM1_Channel: specifies the TIM1 Channel
|
1921 |
|
|
* This parmeter can be one of the following values:
|
1922 |
|
|
* - TIM1_Channel1: TIM1 Channel1
|
1923 |
|
|
* - TIM1_Channel2: TIM1 Channel2
|
1924 |
|
|
* - TIM1_Channel3: TIM1 Channel3
|
1925 |
|
|
* - Newstate: specifies the TIM1 Channel CCxNE bit new state.
|
1926 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1927 |
|
|
* Output : None
|
1928 |
|
|
* Return : None
|
1929 |
|
|
*******************************************************************************/
|
1930 |
|
|
void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate)
|
1931 |
|
|
{
|
1932 |
|
|
/* Check the parameters */
|
1933 |
|
|
assert(IS_TIM1_COMPLEMENTARY_CHANNEL(TIM1_Channel));
|
1934 |
|
|
assert(IS_FUNCTIONAL_STATE(Newstate));
|
1935 |
|
|
|
1936 |
|
|
if(TIM1_Channel == TIM1_Channel_1)
|
1937 |
|
|
{
|
1938 |
|
|
/* Set or Reset the CC1NE Bit */
|
1939 |
|
|
*(vu32 *) CCER_CC1NE_BB = (u16)Newstate;
|
1940 |
|
|
}
|
1941 |
|
|
else if(TIM1_Channel == TIM1_Channel_2)
|
1942 |
|
|
{
|
1943 |
|
|
/* Set or Reset the CC2NE Bit */
|
1944 |
|
|
*(vu32 *) CCER_CC2NE_BB = (u16)Newstate;
|
1945 |
|
|
}
|
1946 |
|
|
else
|
1947 |
|
|
{
|
1948 |
|
|
/* Set or Reset the CC3NE Bit */
|
1949 |
|
|
*(vu32 *) CCER_CC3NE_BB = (u16)Newstate;
|
1950 |
|
|
}
|
1951 |
|
|
}
|
1952 |
|
|
|
1953 |
|
|
/*******************************************************************************
|
1954 |
|
|
* Function Name : TIM1_SelectOCxM
|
1955 |
|
|
* Description : Selects the TIM1 Ouput Compare Mode.
|
1956 |
|
|
* This function disables the selected channel before changing
|
1957 |
|
|
* the Ouput Compare Mode. User has to enable this channel using
|
1958 |
|
|
* TIM1_CCxCmd and TIM1_CCxNCmd functions.
|
1959 |
|
|
* Input : - TIM1_Channel: specifies the TIM1 Channel
|
1960 |
|
|
* This parmeter can be one of the following values:
|
1961 |
|
|
* - TIM1_Channel1: TIM1 Channel1
|
1962 |
|
|
* - TIM1_Channel2: TIM1 Channel2
|
1963 |
|
|
* - TIM1_Channel3: TIM1 Channel3
|
1964 |
|
|
* - TIM1_Channel4: TIM1 Channel4
|
1965 |
|
|
* - TIM1_OCMode: specifies the TIM1 Output Compare Mode.
|
1966 |
|
|
* This paramter can be one of the following values:
|
1967 |
|
|
* - TIM1_OCMode_Timing
|
1968 |
|
|
* - TIM1_OCMode_Active
|
1969 |
|
|
* - TIM1_OCMode_Toggle
|
1970 |
|
|
* - TIM1_OCMode_PWM1
|
1971 |
|
|
* - TIM1_OCMode_PWM2
|
1972 |
|
|
* - TIM1_ForcedAction_Active
|
1973 |
|
|
* - TIM1_ForcedAction_InActive
|
1974 |
|
|
* Output : None
|
1975 |
|
|
* Return : None
|
1976 |
|
|
*******************************************************************************/
|
1977 |
|
|
void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode)
|
1978 |
|
|
{
|
1979 |
|
|
/* Check the parameters */
|
1980 |
|
|
assert(IS_TIM1_CHANNEL(TIM1_Channel));
|
1981 |
|
|
assert(IS_TIM1_OCM(TIM1_OCMode));
|
1982 |
|
|
|
1983 |
|
|
if(TIM1_Channel == TIM1_Channel_1)
|
1984 |
|
|
{
|
1985 |
|
|
/* Disable the Channel 1: Reset the CCE Bit */
|
1986 |
|
|
*(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
|
1987 |
|
|
|
1988 |
|
|
/* Reset the Output Compare Bits */
|
1989 |
|
|
TIM1->CCMR1 &= OC13Mode_Mask;
|
1990 |
|
|
|
1991 |
|
|
/* Set the Ouput Compare Mode */
|
1992 |
|
|
TIM1->CCMR1 |= TIM1_OCMode;
|
1993 |
|
|
}
|
1994 |
|
|
else if(TIM1_Channel == TIM1_Channel_2)
|
1995 |
|
|
{
|
1996 |
|
|
/* Disable the Channel 2: Reset the CCE Bit */
|
1997 |
|
|
*(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
|
1998 |
|
|
|
1999 |
|
|
/* Reset the Output Compare Bits */
|
2000 |
|
|
TIM1->CCMR1 &= OC24Mode_Mask;
|
2001 |
|
|
|
2002 |
|
|
/* Set the Ouput Compare Mode */
|
2003 |
|
|
TIM1->CCMR1 |= (u16)((u16)TIM1_OCMode << 8);
|
2004 |
|
|
}
|
2005 |
|
|
else if(TIM1_Channel == TIM1_Channel_3)
|
2006 |
|
|
{
|
2007 |
|
|
/* Disable the Channel 3: Reset the CCE Bit */
|
2008 |
|
|
*(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
|
2009 |
|
|
|
2010 |
|
|
/* Reset the Output Compare Bits */
|
2011 |
|
|
TIM1->CCMR2 &= OC13Mode_Mask;
|
2012 |
|
|
|
2013 |
|
|
/* Set the Ouput Compare Mode */
|
2014 |
|
|
TIM1->CCMR2 |= TIM1_OCMode;
|
2015 |
|
|
}
|
2016 |
|
|
else
|
2017 |
|
|
{
|
2018 |
|
|
/* Disable the Channel 4: Reset the CCE Bit */
|
2019 |
|
|
*(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
|
2020 |
|
|
|
2021 |
|
|
/* Reset the Output Compare Bits */
|
2022 |
|
|
TIM1->CCMR2 &= OC24Mode_Mask;
|
2023 |
|
|
|
2024 |
|
|
/* Set the Ouput Compare Mode */
|
2025 |
|
|
TIM1->CCMR2 |= (u16)((u16)TIM1_OCMode << 8);
|
2026 |
|
|
}
|
2027 |
|
|
}
|
2028 |
|
|
|
2029 |
|
|
/*******************************************************************************
|
2030 |
|
|
* Function Name : TIM1_SetAutoreload
|
2031 |
|
|
* Description : Sets the TIM1 Autoreload Register value.
|
2032 |
|
|
* Input : - Autoreload: specifies the Autoreload register new value.
|
2033 |
|
|
* Output : None
|
2034 |
|
|
* Return : None
|
2035 |
|
|
*******************************************************************************/
|
2036 |
|
|
void TIM1_SetAutoreload(u16 Autoreload)
|
2037 |
|
|
{
|
2038 |
|
|
/* Set the Autoreload Register value */
|
2039 |
|
|
TIM1->ARR = Autoreload;
|
2040 |
|
|
}
|
2041 |
|
|
|
2042 |
|
|
/*******************************************************************************
|
2043 |
|
|
* Function Name : TIM1_SetCompare1
|
2044 |
|
|
* Description : Sets the TIM1 Capture Compare1 Register value.
|
2045 |
|
|
* Input : - Compare1: specifies the Capture Compare1 register new value.
|
2046 |
|
|
* Output : None
|
2047 |
|
|
* Return : None
|
2048 |
|
|
*******************************************************************************/
|
2049 |
|
|
void TIM1_SetCompare1(u16 Compare1)
|
2050 |
|
|
{
|
2051 |
|
|
/* Set the Capture Compare1 Register value */
|
2052 |
|
|
TIM1->CCR1 = Compare1;
|
2053 |
|
|
}
|
2054 |
|
|
|
2055 |
|
|
/*******************************************************************************
|
2056 |
|
|
* Function Name : TIM1_SetCompare2
|
2057 |
|
|
* Description : Sets the TIM1 Capture Compare2 Register value.
|
2058 |
|
|
* Input : - Compare2: specifies the Capture Compare2 register new value.
|
2059 |
|
|
* Output : None
|
2060 |
|
|
* Return : None
|
2061 |
|
|
*******************************************************************************/
|
2062 |
|
|
void TIM1_SetCompare2(u16 Compare2)
|
2063 |
|
|
{
|
2064 |
|
|
/* Set the Capture Compare2 Register value */
|
2065 |
|
|
TIM1->CCR2 = Compare2;
|
2066 |
|
|
}
|
2067 |
|
|
|
2068 |
|
|
/*******************************************************************************
|
2069 |
|
|
* Function Name : TIM1_SetCompare3
|
2070 |
|
|
* Description : Sets the TIM1 Capture Compare3 Register value.
|
2071 |
|
|
* Input : - Compare3: specifies the Capture Compare3 register new value.
|
2072 |
|
|
* Output : None
|
2073 |
|
|
* Return : None
|
2074 |
|
|
*******************************************************************************/
|
2075 |
|
|
void TIM1_SetCompare3(u16 Compare3)
|
2076 |
|
|
{
|
2077 |
|
|
/* Set the Capture Compare3 Register value */
|
2078 |
|
|
TIM1->CCR3 = Compare3;
|
2079 |
|
|
}
|
2080 |
|
|
|
2081 |
|
|
/*******************************************************************************
|
2082 |
|
|
* Function Name : TIM1_SetCompare4
|
2083 |
|
|
* Description : Sets the TIM1 Capture Compare4 Register value.
|
2084 |
|
|
* Input : - Compare4: specifies the Capture Compare4 register new value.
|
2085 |
|
|
* Output : None
|
2086 |
|
|
* Return : None
|
2087 |
|
|
*******************************************************************************/
|
2088 |
|
|
void TIM1_SetCompare4(u16 Compare4)
|
2089 |
|
|
{
|
2090 |
|
|
/* Set the Capture Compare4 Register value */
|
2091 |
|
|
TIM1->CCR4 = Compare4;
|
2092 |
|
|
}
|
2093 |
|
|
|
2094 |
|
|
/*******************************************************************************
|
2095 |
|
|
* Function Name : TIM1_SetIC1Prescaler
|
2096 |
|
|
* Description : Sets the TIM1 Input Capture 1 prescaler.
|
2097 |
|
|
* Input : - TIM1_IC1Prescaler: specifies the Input Capture prescaler
|
2098 |
|
|
* new value.
|
2099 |
|
|
* This parameter can be one of the following values:
|
2100 |
|
|
* - TIM1_ICPSC_DIV1: no prescaler
|
2101 |
|
|
* - TIM1_ICPSC_DIV2: capture is done once every 2 events
|
2102 |
|
|
* - TIM1_ICPSC_DIV4: capture is done once every 4 events
|
2103 |
|
|
* - TIM1_ICPSC_DIV8: capture is done once every 8 events
|
2104 |
|
|
* Output : None
|
2105 |
|
|
* Return : None
|
2106 |
|
|
*******************************************************************************/
|
2107 |
|
|
void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler)
|
2108 |
|
|
{
|
2109 |
|
|
u32 tmpccmr1 = 0;
|
2110 |
|
|
|
2111 |
|
|
/* Check the parameters */
|
2112 |
|
|
assert(IS_TIM1_IC_PRESCALER(TIM1_IC1Prescaler));
|
2113 |
|
|
|
2114 |
|
|
tmpccmr1 = TIM1->CCMR1;
|
2115 |
|
|
|
2116 |
|
|
/* Reset the IC1PSC Bits */
|
2117 |
|
|
tmpccmr1 &= CCMR_IC13PSC_Mask;
|
2118 |
|
|
|
2119 |
|
|
/* Set the IC1PSC value */
|
2120 |
|
|
tmpccmr1 |= TIM1_IC1Prescaler;
|
2121 |
|
|
|
2122 |
|
|
TIM1->CCMR1 = (u16)tmpccmr1;
|
2123 |
|
|
}
|
2124 |
|
|
|
2125 |
|
|
/*******************************************************************************
|
2126 |
|
|
* Function Name : TIM1_SetIC2Prescaler
|
2127 |
|
|
* Description : Sets the TIM1 Input Capture 2 prescaler.
|
2128 |
|
|
* Input : - TIM1_IC2Prescaler: specifies the Input Capture prescaler
|
2129 |
|
|
* new value.
|
2130 |
|
|
* This parameter can be one of the following values:
|
2131 |
|
|
* - TIM1_ICPSC_DIV1: no prescaler
|
2132 |
|
|
* - TIM1_ICPSC_DIV2: capture is done once every 2 events
|
2133 |
|
|
* - TIM1_ICPSC_DIV4: capture is done once every 4 events
|
2134 |
|
|
* - TIM1_ICPSC_DIV8: capture is done once every 8 events
|
2135 |
|
|
* Output : None
|
2136 |
|
|
* Return : None
|
2137 |
|
|
*******************************************************************************/
|
2138 |
|
|
void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler)
|
2139 |
|
|
{
|
2140 |
|
|
u32 tmpccmr1 = 0;
|
2141 |
|
|
|
2142 |
|
|
/* Check the parameters */
|
2143 |
|
|
assert(IS_TIM1_IC_PRESCALER(TIM1_IC2Prescaler));
|
2144 |
|
|
|
2145 |
|
|
tmpccmr1 = TIM1->CCMR1;
|
2146 |
|
|
|
2147 |
|
|
/* Reset the IC2PSC Bits */
|
2148 |
|
|
tmpccmr1 &= CCMR_IC24PSC_Mask;
|
2149 |
|
|
|
2150 |
|
|
/* Set the IC2PSC value */
|
2151 |
|
|
tmpccmr1 |= (u16)((u16)TIM1_IC2Prescaler << 8);
|
2152 |
|
|
|
2153 |
|
|
TIM1->CCMR1 = (u16)tmpccmr1;
|
2154 |
|
|
}
|
2155 |
|
|
|
2156 |
|
|
/*******************************************************************************
|
2157 |
|
|
* Function Name : TIM1_SetIC3Prescaler
|
2158 |
|
|
* Description : Sets the TIM1 Input Capture 3 prescaler.
|
2159 |
|
|
* Input : - TIM1_IC3Prescaler: specifies the Input Capture prescaler
|
2160 |
|
|
* new value.
|
2161 |
|
|
* This parameter can be one of the following values:
|
2162 |
|
|
* - TIM1_ICPSC_DIV1: no prescaler
|
2163 |
|
|
* - TIM1_ICPSC_DIV2: capture is done once every 2 events
|
2164 |
|
|
* - TIM1_ICPSC_DIV4: capture is done once every 4 events
|
2165 |
|
|
* - TIM1_ICPSC_DIV8: capture is done once every 8 events
|
2166 |
|
|
* Output : None
|
2167 |
|
|
* Return : None
|
2168 |
|
|
*******************************************************************************/
|
2169 |
|
|
void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler)
|
2170 |
|
|
{
|
2171 |
|
|
u32 tmpccmr2 = 0;
|
2172 |
|
|
|
2173 |
|
|
/* Check the parameters */
|
2174 |
|
|
assert(IS_TIM1_IC_PRESCALER(TIM1_IC3Prescaler));
|
2175 |
|
|
|
2176 |
|
|
tmpccmr2 = TIM1->CCMR2;
|
2177 |
|
|
|
2178 |
|
|
/* Reset the IC3PSC Bits */
|
2179 |
|
|
tmpccmr2 &= CCMR_IC13PSC_Mask;
|
2180 |
|
|
|
2181 |
|
|
/* Set the IC3PSC value */
|
2182 |
|
|
tmpccmr2 |= TIM1_IC3Prescaler;
|
2183 |
|
|
|
2184 |
|
|
TIM1->CCMR2 = (u16)tmpccmr2;
|
2185 |
|
|
}
|
2186 |
|
|
|
2187 |
|
|
/*******************************************************************************
|
2188 |
|
|
* Function Name : TIM1_SetIC4Prescaler
|
2189 |
|
|
* Description : Sets the TIM1 Input Capture 4 prescaler.
|
2190 |
|
|
* Input : - TIM1_IC4Prescaler: specifies the Input Capture prescaler
|
2191 |
|
|
* new value.
|
2192 |
|
|
* This parameter can be one of the following values:
|
2193 |
|
|
* - TIM1_ICPSC_DIV1: no prescaler
|
2194 |
|
|
* - TIM1_ICPSC_DIV2: capture is done once every 2 events
|
2195 |
|
|
* - TIM1_ICPSC_DIV4: capture is done once every 4 events
|
2196 |
|
|
* - TIM1_ICPSC_DIV8: capture is done once every 8 events
|
2197 |
|
|
* Output : None
|
2198 |
|
|
* Return : None
|
2199 |
|
|
*******************************************************************************/
|
2200 |
|
|
void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler)
|
2201 |
|
|
{
|
2202 |
|
|
u32 tmpccmr2 = 0;
|
2203 |
|
|
|
2204 |
|
|
/* Check the parameters */
|
2205 |
|
|
assert(IS_TIM1_IC_PRESCALER(TIM1_IC4Prescaler));
|
2206 |
|
|
|
2207 |
|
|
tmpccmr2 = TIM1->CCMR2;
|
2208 |
|
|
|
2209 |
|
|
/* Reset the IC4PSC Bits */
|
2210 |
|
|
tmpccmr2 &= CCMR_IC24PSC_Mask;
|
2211 |
|
|
|
2212 |
|
|
/* Set the IC4PSC value */
|
2213 |
|
|
tmpccmr2 |= (u16)((u16)TIM1_IC4Prescaler << 8);
|
2214 |
|
|
|
2215 |
|
|
TIM1->CCMR2 = (u16)tmpccmr2;
|
2216 |
|
|
}
|
2217 |
|
|
|
2218 |
|
|
/*******************************************************************************
|
2219 |
|
|
* Function Name : TIM1_SetClockDivision
|
2220 |
|
|
* Description : Sets the TIM1 Clock Division value.
|
2221 |
|
|
* Input : - TIM1_CKD: specifies the clock division value.
|
2222 |
|
|
* This parameter can be one of the following value:
|
2223 |
|
|
* - TIM1_CKD_DIV1: TDTS = Tck_tim
|
2224 |
|
|
* - TIM1_CKD_DIV2: TDTS = 2*Tck_tim
|
2225 |
|
|
* - TIM1_CKD_DIV4: TDTS = 4*Tck_tim
|
2226 |
|
|
* Output : None
|
2227 |
|
|
* Return : None
|
2228 |
|
|
*******************************************************************************/
|
2229 |
|
|
void TIM1_SetClockDivision(u16 TIM1_CKD)
|
2230 |
|
|
{
|
2231 |
|
|
u32 tmpcr1 = 0;
|
2232 |
|
|
|
2233 |
|
|
/* Check the parameters */
|
2234 |
|
|
assert(IS_TIM1_CKD_DIV(TIM1_CKD));
|
2235 |
|
|
|
2236 |
|
|
tmpcr1 = TIM1->CR1;
|
2237 |
|
|
|
2238 |
|
|
/* Reset the CKD Bits */
|
2239 |
|
|
tmpcr1 &= CR1_CKD_Mask;
|
2240 |
|
|
|
2241 |
|
|
/* Set the CKD value */
|
2242 |
|
|
tmpcr1 |= TIM1_CKD;
|
2243 |
|
|
|
2244 |
|
|
TIM1->CR1 = (u16)tmpcr1;
|
2245 |
|
|
}
|
2246 |
|
|
|
2247 |
|
|
/*******************************************************************************
|
2248 |
|
|
* Function Name : TIM1_GetCapture1
|
2249 |
|
|
* Description : Gets the TIM1 Input Capture 1 value.
|
2250 |
|
|
* Input : None
|
2251 |
|
|
* Output : None
|
2252 |
|
|
* Return : Capture Compare 1 Register value.
|
2253 |
|
|
*******************************************************************************/
|
2254 |
|
|
u16 TIM1_GetCapture1(void)
|
2255 |
|
|
{
|
2256 |
|
|
/* Get the Capture 1 Register value */
|
2257 |
|
|
return TIM1->CCR1;
|
2258 |
|
|
}
|
2259 |
|
|
|
2260 |
|
|
/*******************************************************************************
|
2261 |
|
|
* Function Name : TIM1_GetCapture2
|
2262 |
|
|
* Description : Gets the TIM1 Input Capture 2 value.
|
2263 |
|
|
* Input : None
|
2264 |
|
|
* Output : None
|
2265 |
|
|
* Return : Capture Compare 2 Register value.
|
2266 |
|
|
*******************************************************************************/
|
2267 |
|
|
u16 TIM1_GetCapture2(void)
|
2268 |
|
|
{
|
2269 |
|
|
/* Get the Capture 2 Register value */
|
2270 |
|
|
return TIM1->CCR2;
|
2271 |
|
|
}
|
2272 |
|
|
|
2273 |
|
|
/*******************************************************************************
|
2274 |
|
|
* Function Name : TIM1_GetCapture3
|
2275 |
|
|
* Description : Gets the TIM1 Input Capture 3 value.
|
2276 |
|
|
* Input : None
|
2277 |
|
|
* Output : None
|
2278 |
|
|
* Return : Capture Compare 3 Register value.
|
2279 |
|
|
*******************************************************************************/
|
2280 |
|
|
u16 TIM1_GetCapture3(void)
|
2281 |
|
|
{
|
2282 |
|
|
/* Get the Capture 3 Register value */
|
2283 |
|
|
return TIM1->CCR3;
|
2284 |
|
|
}
|
2285 |
|
|
|
2286 |
|
|
/*******************************************************************************
|
2287 |
|
|
* Function Name : TIM1_GetCapture4
|
2288 |
|
|
* Description : Gets the TIM1 Input Capture 4 value.
|
2289 |
|
|
* Input : None
|
2290 |
|
|
* Output : None
|
2291 |
|
|
* Return : Capture Compare 4 Register value.
|
2292 |
|
|
*******************************************************************************/
|
2293 |
|
|
u16 TIM1_GetCapture4(void)
|
2294 |
|
|
{
|
2295 |
|
|
/* Get the Capture 4 Register value */
|
2296 |
|
|
return TIM1->CCR4;
|
2297 |
|
|
}
|
2298 |
|
|
|
2299 |
|
|
/*******************************************************************************
|
2300 |
|
|
* Function Name : TIM1_GetCounter
|
2301 |
|
|
* Description : Gets the TIM1 Counter value.
|
2302 |
|
|
* Input : None
|
2303 |
|
|
* Output : None
|
2304 |
|
|
* Return : Counter Register value.
|
2305 |
|
|
*******************************************************************************/
|
2306 |
|
|
u16 TIM1_GetCounter(void)
|
2307 |
|
|
{
|
2308 |
|
|
/* Get the Counter Register value */
|
2309 |
|
|
return TIM1->CNT;
|
2310 |
|
|
}
|
2311 |
|
|
|
2312 |
|
|
/*******************************************************************************
|
2313 |
|
|
* Function Name : TIM1_GetPrescaler
|
2314 |
|
|
* Description : Gets the TIM1 Prescaler value.
|
2315 |
|
|
* Input : None
|
2316 |
|
|
* Output : None
|
2317 |
|
|
* Return : Prescaler Register value.
|
2318 |
|
|
*******************************************************************************/
|
2319 |
|
|
u16 TIM1_GetPrescaler(void)
|
2320 |
|
|
{
|
2321 |
|
|
/* Get the Prescaler Register value */
|
2322 |
|
|
return TIM1->PSC;
|
2323 |
|
|
}
|
2324 |
|
|
|
2325 |
|
|
/*******************************************************************************
|
2326 |
|
|
* Function Name : TIM1_GetFlagStatus
|
2327 |
|
|
* Description : Checks whether the specified TIM1 flag is set or not.
|
2328 |
|
|
* Input : - TIM1_FLAG: specifies the flag to check.
|
2329 |
|
|
* This parameter can be one of the following values:
|
2330 |
|
|
* - TIM1_FLAG_Update: TIM1 update Flag
|
2331 |
|
|
* - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
|
2332 |
|
|
* - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
|
2333 |
|
|
* - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
|
2334 |
|
|
* - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
|
2335 |
|
|
* - TIM1_FLAG_COM: TIM1 Commutation Flag
|
2336 |
|
|
* - TIM1_FLAG_Trigger: TIM1 Trigger Flag
|
2337 |
|
|
* - TIM1_FLAG_Break: TIM1 Break Flag
|
2338 |
|
|
* - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
|
2339 |
|
|
* - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
|
2340 |
|
|
* - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
|
2341 |
|
|
* - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
|
2342 |
|
|
* Output : None
|
2343 |
|
|
* Return : The new state of TIM1_FLAG (SET or RESET).
|
2344 |
|
|
*******************************************************************************/
|
2345 |
|
|
FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG)
|
2346 |
|
|
{
|
2347 |
|
|
FlagStatus bitstatus = RESET;
|
2348 |
|
|
|
2349 |
|
|
/* Check the parameters */
|
2350 |
|
|
assert(IS_TIM1_GET_FLAG(TIM1_FLAG));
|
2351 |
|
|
|
2352 |
|
|
if ((TIM1->SR & TIM1_FLAG) != (u16)RESET )
|
2353 |
|
|
{
|
2354 |
|
|
bitstatus = SET;
|
2355 |
|
|
}
|
2356 |
|
|
else
|
2357 |
|
|
{
|
2358 |
|
|
bitstatus = RESET;
|
2359 |
|
|
}
|
2360 |
|
|
return bitstatus;
|
2361 |
|
|
}
|
2362 |
|
|
|
2363 |
|
|
/*******************************************************************************
|
2364 |
|
|
* Function Name : TIM1_ClearFlag
|
2365 |
|
|
* Description : Clears the TIM1’s pending flags.
|
2366 |
|
|
* Input : - TIM1_FLAG: specifies the flag to clear.
|
2367 |
|
|
* This parameter can be any combination of the following values:
|
2368 |
|
|
* - TIM1_FLAG_Update: TIM1 update Flag
|
2369 |
|
|
* - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
|
2370 |
|
|
* - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
|
2371 |
|
|
* - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
|
2372 |
|
|
* - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
|
2373 |
|
|
* - TIM1_FLAG_COM: TIM1 Commutation Flag
|
2374 |
|
|
* - TIM1_FLAG_Trigger: TIM1 Trigger Flag
|
2375 |
|
|
* - TIM1_FLAG_Break: TIM1 Break Flag
|
2376 |
|
|
* - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
|
2377 |
|
|
* - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
|
2378 |
|
|
* - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
|
2379 |
|
|
* - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
|
2380 |
|
|
* Output : None
|
2381 |
|
|
* Return : None
|
2382 |
|
|
*******************************************************************************/
|
2383 |
|
|
void TIM1_ClearFlag(u16 TIM1_FLAG)
|
2384 |
|
|
{
|
2385 |
|
|
/* Check the parameters */
|
2386 |
|
|
assert(IS_TIM1_CLEAR_FLAG(TIM1_FLAG));
|
2387 |
|
|
|
2388 |
|
|
/* Clear the flags */
|
2389 |
|
|
TIM1->SR &= (u16)~TIM1_FLAG;
|
2390 |
|
|
}
|
2391 |
|
|
|
2392 |
|
|
/*******************************************************************************
|
2393 |
|
|
* Function Name : TIM1_GetITStatus
|
2394 |
|
|
* Description : Checks whether the TIM1 interrupt has occurred or not.
|
2395 |
|
|
* Input : - TIM1_IT: specifies the TIM1 interrupt source to check.
|
2396 |
|
|
* This parameter can be one of the following values:
|
2397 |
|
|
* - TIM1_IT_Update: TIM1 update Interrupt source
|
2398 |
|
|
* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
|
2399 |
|
|
* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
|
2400 |
|
|
* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
|
2401 |
|
|
* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
|
2402 |
|
|
* - TIM1_IT_COM: TIM1 Commutation Interrupt
|
2403 |
|
|
* source
|
2404 |
|
|
* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source
|
2405 |
|
|
* - TIM1_IT_Break: TIM1 Break Interrupt source
|
2406 |
|
|
* Output : None
|
2407 |
|
|
* Return : The new state of the TIM1_IT(SET or RESET).
|
2408 |
|
|
*******************************************************************************/
|
2409 |
|
|
ITStatus TIM1_GetITStatus(u16 TIM1_IT)
|
2410 |
|
|
{
|
2411 |
|
|
ITStatus bitstatus = RESET;
|
2412 |
|
|
|
2413 |
|
|
u16 TIM1_itStatus = 0x0, TIM1_itEnable = 0x0;
|
2414 |
|
|
|
2415 |
|
|
/* Check the parameters */
|
2416 |
|
|
assert(IS_TIM1_GET_IT(TIM1_IT));
|
2417 |
|
|
|
2418 |
|
|
TIM1_itStatus = TIM1->SR & TIM1_IT;
|
2419 |
|
|
|
2420 |
|
|
TIM1_itEnable = TIM1->DIER & TIM1_IT;
|
2421 |
|
|
|
2422 |
|
|
if ((TIM1_itStatus != (u16)RESET ) && (TIM1_itEnable != (u16)RESET ))
|
2423 |
|
|
{
|
2424 |
|
|
bitstatus = SET;
|
2425 |
|
|
}
|
2426 |
|
|
else
|
2427 |
|
|
{
|
2428 |
|
|
bitstatus = RESET;
|
2429 |
|
|
}
|
2430 |
|
|
return bitstatus;
|
2431 |
|
|
}
|
2432 |
|
|
|
2433 |
|
|
/*******************************************************************************
|
2434 |
|
|
* Function Name : TIM1_ClearITPendingBit
|
2435 |
|
|
* Description : Clears the TIM1's interrupt pending bits.
|
2436 |
|
|
* Input : - TIM1_IT: specifies the pending bit to clear.
|
2437 |
|
|
* This parameter can be any combination of the following values:
|
2438 |
|
|
* - TIM1_IT_Update: TIM1 update Interrupt source
|
2439 |
|
|
* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
|
2440 |
|
|
* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
|
2441 |
|
|
* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
|
2442 |
|
|
* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
|
2443 |
|
|
* - TIM1_IT_COM: TIM1 Commutation Interrupt
|
2444 |
|
|
* source
|
2445 |
|
|
* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source
|
2446 |
|
|
* - TIM1_IT_Break: TIM1 Break Interrupt source
|
2447 |
|
|
* Output : None
|
2448 |
|
|
* Return : None
|
2449 |
|
|
*******************************************************************************/
|
2450 |
|
|
void TIM1_ClearITPendingBit(u16 TIM1_IT)
|
2451 |
|
|
{
|
2452 |
|
|
/* Check the parameters */
|
2453 |
|
|
assert(IS_TIM1_IT(TIM1_IT));
|
2454 |
|
|
|
2455 |
|
|
/* Clear the IT pending Bit */
|
2456 |
|
|
TIM1->SR &= (u16)~TIM1_IT;
|
2457 |
|
|
}
|
2458 |
|
|
|
2459 |
|
|
/*******************************************************************************
|
2460 |
|
|
* Function Name : TI1_Config
|
2461 |
|
|
* Description : Configure the TI1 as Input.
|
2462 |
|
|
* Input : - TIM1_ICPolarity : The Input Polarity.
|
2463 |
|
|
* This parameter can be one of the following values:
|
2464 |
|
|
* - TIM1_ICPolarity_Rising
|
2465 |
|
|
* - TIM1_ICPolarity_Falling
|
2466 |
|
|
* - TIM1_ICSelection: specifies the input to be used.
|
2467 |
|
|
* This parameter can be one of the following values:
|
2468 |
|
|
* - TIM1_ICSelection_DirectTI: TIM1 Input 1 is selected to
|
2469 |
|
|
* be connected to IC1.
|
2470 |
|
|
* - TIM1_ICSelection_IndirectTI: TIM1 Input 1 is selected to
|
2471 |
|
|
* be connected to IC2.
|
2472 |
|
|
* - TIM1_ICSelection_TRGI:TIM1 Input 1 is selected to be
|
2473 |
|
|
* connected to TRGI.
|
2474 |
|
|
* - TIM1_ICFilter: Specifies the Input Capture Filter.
|
2475 |
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
2476 |
|
|
* Output : None
|
2477 |
|
|
* Return : None
|
2478 |
|
|
*******************************************************************************/
|
2479 |
|
|
static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
|
2480 |
|
|
u8 TIM1_ICFilter)
|
2481 |
|
|
{
|
2482 |
|
|
u32 tmpccmr1 = 0;
|
2483 |
|
|
|
2484 |
|
|
tmpccmr1 = TIM1->CCMR1;
|
2485 |
|
|
|
2486 |
|
|
/* Disable the Channel 1: Reset the CCE Bit */
|
2487 |
|
|
*(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
|
2488 |
|
|
|
2489 |
|
|
/* Select the Input and set the filter */
|
2490 |
|
|
tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
|
2491 |
|
|
tmpccmr1 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4);
|
2492 |
|
|
|
2493 |
|
|
TIM1->CCMR1 = (u16)tmpccmr1;
|
2494 |
|
|
|
2495 |
|
|
/* Select the Polarity */
|
2496 |
|
|
*(vu32 *) CCER_CC1P_BB = TIM1_ICPolarity;
|
2497 |
|
|
|
2498 |
|
|
/* Set the CCE Bit */
|
2499 |
|
|
*(vu32 *) CCER_CC1E_BB = CCER_CCE_Set;
|
2500 |
|
|
}
|
2501 |
|
|
|
2502 |
|
|
/*******************************************************************************
|
2503 |
|
|
* Function Name : TI2_Config
|
2504 |
|
|
* Description : Configure the TI2 as Input.
|
2505 |
|
|
* Input : - TIM1_ICPolarity : The Input Polarity.
|
2506 |
|
|
* This parameter can be one of the following values:
|
2507 |
|
|
* - TIM1_ICPolarity_Rising
|
2508 |
|
|
* - TIM1_ICPolarity_Falling
|
2509 |
|
|
* - TIM1_ICSelection: specifies the input to be used.
|
2510 |
|
|
* This parameter can be one of the following values:
|
2511 |
|
|
* - TIM1_ICSelection_DirectTI: TIM1 Input 2 is selected to
|
2512 |
|
|
* be connected to IC2.
|
2513 |
|
|
* - TIM1_ICSelection_IndirectTI: TIM1 Input 2 is selected to
|
2514 |
|
|
* be connected to IC1.
|
2515 |
|
|
* - TIM1_ICSelection_TRGI: TIM1 Input 2 is selected to be
|
2516 |
|
|
* connected to TRGI.
|
2517 |
|
|
* - TIM1_ICFilter: Specifies the Input Capture Filter.
|
2518 |
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
2519 |
|
|
* Output : None
|
2520 |
|
|
* Return : None
|
2521 |
|
|
*******************************************************************************/
|
2522 |
|
|
static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
|
2523 |
|
|
u8 TIM1_ICFilter)
|
2524 |
|
|
{
|
2525 |
|
|
u32 tmpccmr1 = 0;
|
2526 |
|
|
|
2527 |
|
|
tmpccmr1 = TIM1->CCMR1;
|
2528 |
|
|
|
2529 |
|
|
/* Disable the Channel 2: Reset the CCE Bit */
|
2530 |
|
|
*(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
|
2531 |
|
|
|
2532 |
|
|
/* Select the Input and set the filter */
|
2533 |
|
|
tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
|
2534 |
|
|
tmpccmr1 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter <<12);
|
2535 |
|
|
|
2536 |
|
|
TIM1->CCMR1 = (u16)tmpccmr1;
|
2537 |
|
|
|
2538 |
|
|
/* Select the Polarity */
|
2539 |
|
|
*(vu32 *) CCER_CC2P_BB = TIM1_ICPolarity;
|
2540 |
|
|
|
2541 |
|
|
/* Set the CCE Bit */
|
2542 |
|
|
*(vu32 *) CCER_CC2E_BB = CCER_CCE_Set;
|
2543 |
|
|
|
2544 |
|
|
}
|
2545 |
|
|
|
2546 |
|
|
/*******************************************************************************
|
2547 |
|
|
* Function Name : TI3_Config
|
2548 |
|
|
* Description : Configure the TI3 as Input.
|
2549 |
|
|
* Input : - TIM1_ICPolarity : The Input Polarity.
|
2550 |
|
|
* This parameter can be one of the following values:
|
2551 |
|
|
* - TIM1_ICPolarity_Rising
|
2552 |
|
|
* - TIM1_ICPolarity_Falling
|
2553 |
|
|
* - TIM1_ICSelection: specifies the input to be used.
|
2554 |
|
|
* This parameter can be one of the following values:
|
2555 |
|
|
* - TIM1_ICSelection_DirectTI: TIM1 Input 3 is selected to
|
2556 |
|
|
* be connected to IC3.
|
2557 |
|
|
* - TIM1_ICSelection_IndirectTI: TIM1 Input 3 is selected to
|
2558 |
|
|
* be connected to IC4.
|
2559 |
|
|
* - TIM1_ICSelection_TRGI: TIM1 Input 3 is selected to be
|
2560 |
|
|
* connected to TRGI.
|
2561 |
|
|
* - TIM1_ICFilter: Specifies the Input Capture Filter.
|
2562 |
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
2563 |
|
|
* Output : None
|
2564 |
|
|
* Return : None
|
2565 |
|
|
*******************************************************************************/
|
2566 |
|
|
static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
|
2567 |
|
|
u8 TIM1_ICFilter)
|
2568 |
|
|
{
|
2569 |
|
|
u32 tmpccmr2 = 0;
|
2570 |
|
|
|
2571 |
|
|
tmpccmr2 = TIM1->CCMR2;
|
2572 |
|
|
|
2573 |
|
|
/* Disable the Channel 3: Reset the CCE Bit */
|
2574 |
|
|
*(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
|
2575 |
|
|
|
2576 |
|
|
/* Select the Input and set the filter */
|
2577 |
|
|
tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
|
2578 |
|
|
tmpccmr2 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4);
|
2579 |
|
|
|
2580 |
|
|
TIM1->CCMR2 = (u16)tmpccmr2;
|
2581 |
|
|
|
2582 |
|
|
/* Select the Polarity */
|
2583 |
|
|
*(vu32 *) CCER_CC3P_BB = TIM1_ICPolarity;
|
2584 |
|
|
|
2585 |
|
|
/* Set the CCE Bit */
|
2586 |
|
|
*(vu32 *) CCER_CC3E_BB = CCER_CCE_Set;
|
2587 |
|
|
}
|
2588 |
|
|
|
2589 |
|
|
/*******************************************************************************
|
2590 |
|
|
* Function Name : TI4_Config
|
2591 |
|
|
* Description : Configure the TI4 as Input.
|
2592 |
|
|
* Input : - TIM1_ICPolarity : The Input Polarity.
|
2593 |
|
|
* This parameter can be one of the following values:
|
2594 |
|
|
* - TIM1_ICPolarity_Rising
|
2595 |
|
|
* - TIM1_ICPolarity_Falling
|
2596 |
|
|
* - TIM1_ICSelection: specifies the input to be used.
|
2597 |
|
|
* This parameter can be one of the following values:
|
2598 |
|
|
* - TIM1_ICSelection_DirectTI: TIM1 Input 4 is selected to
|
2599 |
|
|
* be connected to IC4.
|
2600 |
|
|
* - TIM1_ICSelection_IndirectTI: TIM1 Input 4 is selected to
|
2601 |
|
|
* be connected to IC3.
|
2602 |
|
|
* - TIM1_ICSelection_TRGI: TIM1 Input 4 is selected to be
|
2603 |
|
|
* connected to TRGI.
|
2604 |
|
|
* - TIM1_ICFilter: Specifies the Input Capture Filter.
|
2605 |
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
2606 |
|
|
* Output : None
|
2607 |
|
|
* Return : None
|
2608 |
|
|
*******************************************************************************/
|
2609 |
|
|
static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
|
2610 |
|
|
u8 TIM1_ICFilter)
|
2611 |
|
|
{
|
2612 |
|
|
u32 tmpccmr2 = 0;
|
2613 |
|
|
|
2614 |
|
|
tmpccmr2 = TIM1->CCMR2;
|
2615 |
|
|
|
2616 |
|
|
/* Disable the Channel 4: Reset the CCE Bit */
|
2617 |
|
|
*(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
|
2618 |
|
|
|
2619 |
|
|
/* Select the Input and set the filter */
|
2620 |
|
|
tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
|
2621 |
|
|
tmpccmr2 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter << 12);
|
2622 |
|
|
|
2623 |
|
|
TIM1->CCMR2 = (u16)tmpccmr2;
|
2624 |
|
|
|
2625 |
|
|
/* Select the Polarity */
|
2626 |
|
|
*(vu32 *) CCER_CC4P_BB = TIM1_ICPolarity;
|
2627 |
|
|
|
2628 |
|
|
/* Set the CCE Bit */
|
2629 |
|
|
*(vu32 *) CCER_CC4E_BB = CCER_CCE_Set;
|
2630 |
|
|
}
|
2631 |
|
|
|
2632 |
|
|
/*******************************************************************************
|
2633 |
|
|
* Function Name : ETR_Config
|
2634 |
|
|
* Description : Configure the External Trigger
|
2635 |
|
|
* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.
|
2636 |
|
|
* This parameter can be one of the following values:
|
2637 |
|
|
* - TIM1_ExtTRGPSC_OFF
|
2638 |
|
|
* - TIM1_ExtTRGPSC_DIV2
|
2639 |
|
|
* - TIM1_ExtTRGPSC_DIV4
|
2640 |
|
|
* - TIM1_ExtTRGPSC_DIV8
|
2641 |
|
|
* - TIM1_ExtTRGPolarity: The external Trigger Polarity.
|
2642 |
|
|
* This parameter can be one of the following values:
|
2643 |
|
|
* - TIM1_ExtTRGPolarity_Inverted
|
2644 |
|
|
* - TIM1_ExtTRGPolarity_NonInverted
|
2645 |
|
|
* - ExtTRGFilter: External Trigger Filter.
|
2646 |
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
2647 |
|
|
* Output : None
|
2648 |
|
|
* Return : None
|
2649 |
|
|
*******************************************************************************/
|
2650 |
|
|
static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
|
2651 |
|
|
u16 ExtTRGFilter)
|
2652 |
|
|
{
|
2653 |
|
|
u32 tmpsmcr = 0;
|
2654 |
|
|
|
2655 |
|
|
tmpsmcr = TIM1->SMCR;
|
2656 |
|
|
|
2657 |
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
2658 |
|
|
tmpsmcr &= SMCR_ETR_Mask;
|
2659 |
|
|
tmpsmcr |= TIM1_ExtTRGPrescaler | TIM1_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8);
|
2660 |
|
|
|
2661 |
|
|
TIM1->SMCR = (u16)tmpsmcr;
|
2662 |
|
|
}
|
2663 |
|
|
|
2664 |
|
|
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
|