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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [drivers/] [ST/] [STM32F10xFWLib/] [src/] [stm32fxxx_eth.c] - Blame information for rev 608

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1 608 jeremybenn
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
2
* File Name          : stm32fxxx_eth.c
3
* Author             : MCD Application Team
4
* Version            : V1.0.0
5
* Date               : 12/17/2008
6
* Updates            : 05/2009 Driver optimization.
7
*                      - No copy. DMA directly uses Stack packets.
8
* Desciption        : This file provides all the ETHERNET firmware functions.
9
********************************************************************************
10
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
11
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
12
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
13
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
14
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
15
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
16
*******************************************************************************/
17
 
18
/* For the delays. */
19
#include "FreeRTOS.h"
20
#include "task.h"
21
 
22
/* Includes ------------------------------------------------------------------*/
23
#include "stm32fxxx_eth.h"
24
#include "stm32f10x_rcc.h"
25
 
26
/* Private typedef -----------------------------------------------------------*/
27
/* Private define ------------------------------------------------------------*/
28
/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
29
ETH_DMADESCTypeDef  *DMATxDescToSet;
30
ETH_DMADESCTypeDef  *DMARxDescToGet;
31
 
32
ETH_DMADESCTypeDef  *DMAPTPTxDescToSet;
33
ETH_DMADESCTypeDef  *DMAPTPRxDescToGet;
34
 
35
/* ETHERNET MAC address offsets */
36
#define ETH_MAC_AddrHighBase   (ETH_MAC_BASE + 0x40)  /* ETHERNET MAC address high offset */
37
#define ETH_MAC_AddrLowBase    (ETH_MAC_BASE + 0x44)  /* ETHERNET MAC address low offset */
38
 
39
/* ETHERNET MACMIIAR register Mask */
40
#define MACMIIAR_CR_Mask    ((u32)0xFFFFFFE3)
41
/* ETHERNET MACCR register Mask */
42
#define MACCR_CLEAR_Mask    ((u32)0xFF20810F)
43
/* ETHERNET MACFCR register Mask */
44
#define MACFCR_CLEAR_Mask   ((u32)0x0000FF41)
45
/* ETHERNET DMAOMR register Mask */
46
#define DMAOMR_CLEAR_Mask   ((u32)0xF8DE3F23)
47
 
48
/* ETHERNET Remote Wake-up frame register length */
49
#define ETH_WakeupRegisterLength      8
50
 
51
/* ETHERNET Missed frames counter Shift */
52
#define  ETH_DMA_RxOverflowMissedFramesCounterShift     17
53
 
54
/* ETHERNET DMA Tx descriptors Collision Count Shift */
55
#define  ETH_DMATxDesc_CollisionCountShift        3
56
/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
57
#define  ETH_DMATxDesc_BufferSize2Shift           16
58
/* ETHERNET DMA Rx descriptors Frame Length Shift */
59
#define  ETH_DMARxDesc_FrameLengthShift           16
60
/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
61
#define  ETH_DMARxDesc_Buffer2SizeShift           16
62
 
63
/* ETHERNET errors */
64
#define  ETH_ERROR              ((u32)0)
65
#define  ETH_SUCCESS            ((u32)1)
66
 
67
#define ethFIVE_SECONDS                 ( 5000 / portTICK_RATE_MS )
68
#define ethHUNDRED_MS                   ( 100 / portTICK_RATE_MS )
69
 
70
/* Private macro -------------------------------------------------------------*/
71
/* Private variables ---------------------------------------------------------*/
72
/* Private function prototypes -----------------------------------------------*/
73
/* Private functions ---------------------------------------------------------*/
74
 
75
/*******************************************************************************
76
* Function Name  : ETH_DeInit
77
* Desciption     : Deinitializes the ETHERNET peripheral registers to their
78
*                  default reset values.
79
* Input          : None
80
* Output         : None
81
* Return         : None
82
*******************************************************************************/
83
void ETH_DeInit(void)
84
{
85
//  RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);
86
//  RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);
87
}
88
 
89
/*******************************************************************************
90
* Function Name  : ETH_Init
91
* Desciption     : Initializes the ETHERNET peripheral according to the specified
92
*                  parameters in the ETH_InitStruct .
93
* Input          : - ETH_InitStruct: pointer to a ETH_InitTypeDef structure
94
*                    that contains the configuration information for the
95
*                    specified ETHERNET peripheral.
96
* Output         : None
97
* Return         : None
98
*******************************************************************************/
99
u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress)
100
{
101
  u32 RegValue = 0, tmpreg = 0;
102
  RCC_ClocksTypeDef  rcc_clocks;
103
  u32 hclk = 60000000;
104
  u32 timeout = 0;
105
 
106
  /* Check the parameters */
107
  /* MAC --------------------------*/
108
  eth_assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
109
  eth_assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
110
  eth_assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
111
  eth_assert_param(IS_ETH_JUMBO_FRAME(ETH_InitStruct->ETH_JumboFrame));
112
  eth_assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
113
  eth_assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
114
  eth_assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
115
  eth_assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
116
  eth_assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
117
  eth_assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
118
  eth_assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
119
  eth_assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
120
  eth_assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
121
  eth_assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
122
  eth_assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
123
  eth_assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
124
  eth_assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
125
  eth_assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
126
  eth_assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
127
  eth_assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
128
  eth_assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
129
  eth_assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));
130
  eth_assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
131
  eth_assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
132
  eth_assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
133
  eth_assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
134
  eth_assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
135
  eth_assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
136
  eth_assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
137
  eth_assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
138
  eth_assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
139
  /* DMA --------------------------*/
140
  eth_assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
141
  eth_assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
142
  eth_assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
143
  eth_assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
144
  eth_assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
145
  eth_assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
146
  eth_assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
147
  eth_assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
148
  eth_assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
149
  eth_assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
150
  eth_assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
151
  eth_assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
152
  eth_assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength));
153
  eth_assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
154
  eth_assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
155
 
156
/*--------------------------------- MAC Config -------------------------------*/
157
/*----------------------- ETHERNET MACMIIAR Configuration --------------------*/
158
  /* Get the ETHERNET MACMIIAR value */
159
  tmpreg = ETH_MAC->MACMIIAR;
160
  /* Clear CSR Clock Range CR[2:0] bits */
161
  tmpreg &= MACMIIAR_CR_Mask;
162
  /* Get hclk frequency value */
163
  RCC_GetClocksFreq(&rcc_clocks);
164
  hclk = rcc_clocks.HCLK_Frequency;
165
 
166
  /* Set CR bits depending on hclk value */
167
  if((hclk >= 20000000)&&(hclk < 35000000))
168
  {
169
    /* CSR Clock Range between 20-35 MHz */
170
    tmpreg |= (u32)ETH_MACMIIAR_CR_Div16;
171
  }
172
  else if((hclk >= 35000000)&&(hclk < 60000000))
173
  {
174
    /* CSR Clock Range between 35-60 MHz */
175
    tmpreg |= (u32)ETH_MACMIIAR_CR_Div26;
176
  }
177
  else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */
178
  {
179
    /* CSR Clock Range between 60-72 MHz */
180
    tmpreg |= (u32)ETH_MACMIIAR_CR_Div42;
181
  }
182
  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
183
  ETH_MAC->MACMIIAR = (u32)tmpreg;
184
 
185
/*--------------------- PHY initialization and configuration -----------------*/
186
  /* Put the PHY in reset mode */
187
  if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
188
  {
189
    /* Return ERROR in case of write timeout */
190
    return ETH_ERROR;
191
  }
192
 
193
  /* Delay to assure PHY reset */
194
  vTaskDelay( 250 / portTICK_RATE_MS );
195
 
196
  if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
197
  {
198
    /* We wait for linked satus... */
199
        timeout = 0;
200
    do
201
    {
202
      /* Wait 100ms before checking for a link again. */
203
      vTaskDelay( ethHUNDRED_MS );
204
          timeout++;
205
 
206
          /* Don't wait any longer than 5 seconds. */
207
    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < ( ethFIVE_SECONDS / ethHUNDRED_MS ) ) );
208
 
209
    /* Return ERROR in case of timeout */
210
    if(timeout == ( ethFIVE_SECONDS / ethHUNDRED_MS ))
211
    {
212
      return ETH_ERROR;
213
    }
214
 
215
    /* Enable Auto-Negotiation */
216
    if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
217
    {
218
      /* Return ERROR in case of write timeout */
219
      return ETH_ERROR;
220
    }
221
 
222
    /* Reset Timeout counter */
223
    timeout = 0;
224
 
225
    /* Wait until the autonegotiation will be completed */
226
    do
227
    {
228
      /* Wait 100ms before checking for negotiation to complete. */
229
      vTaskDelay( ethHUNDRED_MS );
230
          timeout++;
231
 
232
          /* Don't wait longer than 5 seconds. */
233
    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < ( ethFIVE_SECONDS / ethHUNDRED_MS ) ) );
234
 
235
    /* Return ERROR in case of timeout */
236
    if(timeout == ( ethFIVE_SECONDS / ethHUNDRED_MS ))
237
    {
238
      return ETH_ERROR;
239
    }
240
 
241
    /* Reset Timeout counter */
242
    timeout = 0;
243
 
244
    /* Read the result of the autonegotiation */
245
    RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
246
 
247
    /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
248
    if((RegValue & PHY_Duplex_Status) != (u32)RESET)
249
    {
250
      /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
251
      ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
252
 
253
    }
254
    else
255
    {
256
      /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
257
      ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
258
    }
259
    /* Configure the MAC with the speed fixed by the autonegotiation process */
260
    if(RegValue & PHY_Speed_Status)
261
    {
262
      /* Set Ethernet speed to 100M following the autonegotiation */
263
      ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
264
    }
265
    else
266
    {
267
      /* Set Ethernet speed to 10M following the autonegotiation */
268
      ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
269
    }
270
  }
271
//  else
272
  {
273
    if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((u16)(ETH_InitStruct->ETH_Mode >> 3) |
274
                                                   (u16)(ETH_InitStruct->ETH_Speed >> 1))))
275
    {
276
      /* Return ERROR in case of write timeout */
277
      return ETH_ERROR;
278
    }
279
 
280
    vTaskDelay( 250 / portTICK_RATE_MS );
281
  }
282
 
283
/*------------------------- ETHERNET MACCR Configuration ---------------------*/
284
  /* Get the ETHERNET MACCR value */
285
  tmpreg = ETH_MAC->MACCR;
286
  /* Clear WD, PCE, PS, TE and RE bits */
287
  tmpreg &= MACCR_CLEAR_Mask;
288
 
289
  /* Set the WD bit according to ETH_Watchdog value */
290
  /* Set the JD: bit according to ETH_Jabber value */
291
  /* Set the JE bit according to ETH_JumboFrame value */
292
  /* Set the IFG bit according to ETH_InterFrameGap value */
293
  /* Set the DCRS bit according to ETH_CarrierSense value */
294
  /* Set the FES bit according to ETH_Speed value */
295
  /* Set the DO bit according to ETH_ReceiveOwn value */
296
  /* Set the LM bit according to ETH_LoopbackMode value */
297
  /* Set the DM bit according to ETH_Mode value */
298
  /* Set the IPC bit according to ETH_ChecksumOffload value */
299
  /* Set the DR bit according to ETH_RetryTransmission value */
300
  /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
301
  /* Set the BL bit according to ETH_BackOffLimit value */
302
  /* Set the DC bit according to ETH_DeferralCheck value */
303
  tmpreg |= (u32)(ETH_InitStruct->ETH_Watchdog |
304
                  ETH_InitStruct->ETH_Jabber |
305
                  ETH_InitStruct->ETH_JumboFrame |
306
                  ETH_InitStruct->ETH_InterFrameGap |
307
                  ETH_InitStruct->ETH_CarrierSense |
308
                  ETH_InitStruct->ETH_Speed |
309
                  ETH_InitStruct->ETH_ReceiveOwn |
310
                  ETH_InitStruct->ETH_LoopbackMode |
311
                  ETH_InitStruct->ETH_Mode |
312
                  ETH_InitStruct->ETH_ChecksumOffload |
313
                  ETH_InitStruct->ETH_RetryTransmission |
314
                  ETH_InitStruct->ETH_AutomaticPadCRCStrip |
315
                  ETH_InitStruct->ETH_BackOffLimit |
316
                  ETH_InitStruct->ETH_DeferralCheck);
317
 
318
  /* Write to ETHERNET MACCR */
319
  ETH_MAC->MACCR = (u32)tmpreg;
320
 
321
/*------------------------ ETHERNET MACFFR Configuration ---------------------*/
322
  /* Set the RA bit according to ETH_ReceiveAll value */
323
  /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
324
  /* Set the PCF bit according to ETH_PassControlFrames value */
325
  /* Set the DBF bit according to ETH_BroadcastFramesReception value */
326
  /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
327
  /* Set the PR bit according to ETH_PromiscuousMode value */
328
  /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
329
  /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
330
  /* Write to ETHERNET MACFFR */
331
  ETH_MAC->MACFFR = (u32)(ETH_InitStruct->ETH_ReceiveAll |
332
                          ETH_InitStruct->ETH_SourceAddrFilter |
333
                          ETH_InitStruct->ETH_PassControlFrames |
334
                          ETH_InitStruct->ETH_BroadcastFramesReception |
335
                          ETH_InitStruct->ETH_DestinationAddrFilter |
336
                          ETH_InitStruct->ETH_PromiscuousMode |
337
                          ETH_InitStruct->ETH_MulticastFramesFilter |
338
                          ETH_InitStruct->ETH_UnicastFramesFilter);
339
 
340
/*---------------- ETHERNET MACHTHR and MACHTLR Configuration ----------------*/
341
  /* Write to ETHERNET MACHTHR */
342
  ETH_MAC->MACHTHR = (u32)ETH_InitStruct->ETH_HashTableHigh;
343
  /* Write to ETHERNET MACHTLR */
344
  ETH_MAC->MACHTLR = (u32)ETH_InitStruct->ETH_HashTableLow;
345
 
346
/*------------------------ ETHERNET MACFCR Configuration ---------------------*/
347
  /* Get the ETHERNET MACFCR value */
348
  tmpreg = ETH_MAC->MACFCR;
349
  /* Clear xx bits */
350
  tmpreg &= MACFCR_CLEAR_Mask;
351
 
352
  /* Set the PT bit according to ETH_PauseTime value */
353
  /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
354
  /* Set the PLT bit according to ETH_PauseLowThreshold value */
355
  /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
356
  /* Set the RFE bit according to ETH_ReceiveFlowControl value */
357
  /* Set the TFE bit according to ETH_TransmitFlowControl value */
358
  tmpreg |= (u32)((ETH_InitStruct->ETH_PauseTime << 16) |
359
                   ETH_InitStruct->ETH_ZeroQuantaPause |
360
                   ETH_InitStruct->ETH_PauseLowThreshold |
361
                   ETH_InitStruct->ETH_UnicastPauseFrameDetect |
362
                   ETH_InitStruct->ETH_ReceiveFlowControl |
363
                   ETH_InitStruct->ETH_TransmitFlowControl);
364
 
365
  /* Write to ETHERNET MACFCR */
366
  ETH_MAC->MACFCR = (u32)tmpreg;
367
 
368
/*------------------------ ETHERNET MACVLANTR Configuration ------------------*/
369
  /* Set the ETV bit according to ETH_VLANTagComparison value */
370
  /* Set the VL bit according to ETH_VLANTagIdentifier value */
371
  ETH_MAC->MACVLANTR = (u32)(ETH_InitStruct->ETH_VLANTagComparison |
372
                             ETH_InitStruct->ETH_VLANTagIdentifier);
373
 
374
#ifdef _ETH_DMA
375
/*--------------------------------- DMA Config -------------------------------*/
376
/*------------------------ ETHERNET DMAOMR Configuration ---------------------*/
377
  /* Get the ETHERNET DMAOMR value */
378
  tmpreg = ETH_DMA->DMAOMR;
379
  /* Clear xx bits */
380
  tmpreg &= DMAOMR_CLEAR_Mask;
381
 
382
  /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
383
  /* Set the RSF bit according to ETH_ReceiveStoreForward value */
384
  /* Set the DFF bit according to ETH_FlushReceivedFrame value */
385
  /* Set the TSF bit according to ETH_TransmitStoreForward value */
386
  /* Set the TTC bit according to ETH_TransmitThresholdControl value */
387
  /* Set the FEF bit according to ETH_ForwardErrorFrames value */
388
  /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
389
  /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
390
  /* Set the OSF bit according to ETH_SecondFrameOperate value */
391
  tmpreg |= (u32)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
392
                  ETH_InitStruct->ETH_ReceiveStoreForward |
393
                  ETH_InitStruct->ETH_FlushReceivedFrame |
394
                  ETH_InitStruct->ETH_TransmitStoreForward |
395
                  ETH_InitStruct->ETH_TransmitThresholdControl |
396
                  ETH_InitStruct->ETH_ForwardErrorFrames |
397
                  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
398
                  ETH_InitStruct->ETH_ReceiveThresholdControl |
399
                  ETH_InitStruct->ETH_SecondFrameOperate);
400
 
401
  /* Write to ETHERNET DMAOMR */
402
  ETH_DMA->DMAOMR = (u32)tmpreg;
403
 
404
/*------------------------ ETHERNET DMABMR Configuration ---------------------*/
405
  /* Set the AAL bit according to ETH_AddressAlignedBeats value */
406
  /* Set the FB bit according to ETH_FixedBurst value */
407
  /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
408
  /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
409
  /* Set the DSL bit according to ETH_DesciptorSkipLength value */
410
  /* Set the PR and DA bits according to ETH_DMAArbitration value */
411
  ETH_DMA->DMABMR = (u32)(ETH_InitStruct->ETH_AddressAlignedBeats |
412
                          ETH_InitStruct->ETH_FixedBurst |
413
                          ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
414
                          ETH_InitStruct->ETH_TxDMABurstLength |
415
                         (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
416
                          ETH_InitStruct->ETH_DMAArbitration |
417
                                                  ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
418
#endif /* _ETH_DMA */
419
 
420
  /* Return Ethernet configuration success */
421
  return ETH_SUCCESS;
422
}
423
 
424
/*******************************************************************************
425
* Function Name  : ETH_StructInit
426
* Desciption    : Fills each ETH_InitStruct member with its default value.
427
* Input          : - ETH_InitStruct: pointer to a ETH_InitTypeDef structure
428
*                    which will be initialized.
429
* Output         : None
430
* Return         : None
431
*******************************************************************************/
432
void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
433
{
434
  /* ETH_InitStruct members default value */
435
  /*------------------------   MAC   -----------------------------------*/
436
  ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
437
  ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
438
  ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
439
  ETH_InitStruct->ETH_JumboFrame = ETH_JumboFrame_Disable;
440
  ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
441
  ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
442
  ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
443
  ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
444
  ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
445
  ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
446
  ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
447
  ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
448
  ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
449
  ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
450
  ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
451
  ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
452
  ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
453
  ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
454
  ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
455
  ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
456
  ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
457
  ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
458
  ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
459
  ETH_InitStruct->ETH_HashTableHigh = 0x0;
460
  ETH_InitStruct->ETH_HashTableLow = 0x0;
461
  ETH_InitStruct->ETH_PauseTime = 0x0;
462
  ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
463
  ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
464
  ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
465
  ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
466
  ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
467
  ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
468
  ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
469
 
470
#ifdef _ETH_DMA
471
/*------------------------   DMA   -----------------------------------*/
472
  ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
473
  ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
474
  ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
475
  ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
476
  ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
477
  ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
478
  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
479
  ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
480
  ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
481
  ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
482
  ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
483
  ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
484
  ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
485
  ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
486
  ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
487
 
488
#endif /* _ETH_DMA */
489
}
490
 
491
/*******************************************************************************
492
* Function Name  : ETH_Start
493
* Desciption     : Enables ENET MAC and DMA reception/transmission
494
* Input          : None
495
* Output         : None
496
* Return         : None
497
*******************************************************************************/
498
void ETH_Start(void)
499
{
500
  /* Enable transmit state machine of the MAC for transmission on the MII */
501
  ETH_MACTransmissionCmd(ENABLE);
502
  /* Flush Transmit FIFO */
503
  ETH_FlushTransmitFIFO();
504
  /* Enable receive state machine of the MAC for reception from the MII */
505
  ETH_MACReceptionCmd(ENABLE);
506
 
507
#ifdef _ETH_DMA
508
  /* Start DMA transmission */
509
  ETH_DMATransmissionCmd(ENABLE);
510
  /* Start DMA reception */
511
  ETH_DMAReceptionCmd(ENABLE);
512
#endif /* _ETH_DMA */
513
}
514
 
515
#ifdef _ETH_DMA
516
/*******************************************************************************
517
* Function Name  : ETH_HandleTxPkt
518
* Desciption     : Transmits a packet, from application buffer, pointed by ppkt.
519
* Input          : - ppkt: pointer to application packet Buffer.
520
*                  - FrameLength: Tx Packet size.
521
* Output         : None
522
* Return         : ETH_ERROR: in case of Tx desc owned by DMA
523
*                  ETH_SUCCESS: for correct transmission
524
*******************************************************************************/
525
u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength)
526
{
527
 
528
  // Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset)
529
  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
530
  {
531
    // Return ERROR: OWN bit set
532
    return ETH_ERROR;
533
  }
534
 
535
  //Set the DMA buffer address to send to the Packet we received from stack
536
  DMATxDescToSet->Buffer1Addr = (u32)addr;
537
 
538
  // Setting the Frame Length: bits[12:0]
539
  DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
540
 
541
  // Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor)
542
  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
543
 
544
  // Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA
545
  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
546
 
547
  // When Tx Buffer unavailable flag is set: clear it and resume transmission
548
  if ((ETH_DMA->DMASR & ETH_DMASR_TBUS) != (u32)RESET)
549
  {
550
    // Clear TBUS ETHERNET DMA flag
551
    ETH_DMA->DMASR = ETH_DMASR_TBUS;
552
    // Resume DMA transmission
553
    ETH_DMA->DMATPDR = 0;
554
  }
555
 
556
  // Update the ETHERNET DMA global Tx descriptor with next Tx decriptor
557
  // Chained Mode
558
  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (u32)RESET)
559
  {
560
    // Selects the next DMA Tx descriptor list for next buffer to send
561
    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
562
  }
563
  else // Ring Mode
564
  {
565
    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (u32)RESET)
566
    {
567
      // Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used
568
      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);
569
    }
570
    else
571
    {
572
      // Selects the next DMA Tx descriptor list for next buffer to send
573
      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMATxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
574
    }
575
  }
576
 
577
 
578
  // Return SUCCESS
579
  return ETH_SUCCESS;
580
}
581
 
582
/*******************************************************************************
583
* Function Name  : ETH_HandleRxPkt
584
* Desciption     : Receives a packet and copies it to memory pointed by ppkt.
585
* Input          : None
586
* Output         : ppkt: pointer on application receive buffer.
587
* Return         : ETH_ERROR: if there is error in reception
588
*                  Received packet size: if packet reception is correct
589
*******************************************************************************/
590
u32 ETH_HandleRxPkt(u32 addr)
591
{
592
  // Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset)
593
  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET)
594
  {
595
    // Return error: OWN bit set
596
    return ETH_ERROR;
597
  }
598
 
599
  //Set the buffer address to rcv frame for the same descriptor (reserved packet)
600
  DMARxDescToGet->Buffer1Addr = addr;
601
 
602
  if(addr) {
603
   // Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA
604
   DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
605
  }
606
 
607
  // Update the ETHERNET DMA global Rx descriptor with next Rx decriptor
608
  // Chained Mode
609
  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)
610
  {
611
    // Selects the next DMA Rx descriptor list for next buffer to read
612
    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
613
  }
614
  else // Ring Mode
615
  {
616
    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)
617
    {
618
      // Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used
619
      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);
620
    }
621
    else
622
    {
623
      // Selects the next DMA Rx descriptor list for next buffer to read
624
      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
625
    }
626
  }
627
 
628
  return(1);
629
}
630
 
631
 
632
/*******************************************************************************
633
* Function Name  : ETH_GetRxPktSize
634
* Desciption     : Get the size of received the received packet.
635
* Input          : None
636
* Output         : None
637
* Return         : Rx packet size
638
*******************************************************************************/
639
u32 ETH_GetRxPktSize(void)
640
{
641
  u32 FrameLength = 0;
642
 
643
  //Test DMARxDescToGet is not NULL
644
  if(DMARxDescToGet)
645
  {
646
    /* Get the size of the packet: including 4 bytes of the CRC */
647
    FrameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
648
 
649
  }
650
 
651
 /* Return Frame Length */
652
 return FrameLength;
653
}
654
 
655
/*******************************************************************************
656
* Function Name  : ETH_DropRxPkt
657
* Desciption     : Drop a Received packet (too small packet, etc...)
658
* Input          : None
659
* Output         : None
660
* Return         : None
661
*******************************************************************************/
662
void ETH_DropRxPkt(void)
663
{
664
 
665
  // Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA
666
  DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
667
 
668
 
669
  // Chained Mode
670
  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)
671
  {
672
    // Selects the next DMA Rx descriptor list for next buffer read
673
    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
674
  }
675
  else // Ring Mode
676
  {
677
    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)
678
    {
679
      // Selects the next DMA Rx descriptor list for next buffer read: this will
680
      //   be the first Rx descriptor in this case
681
      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);
682
    }
683
    else
684
    {
685
      // Selects the next DMA Rx descriptor list for next buffer read
686
      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
687
    }
688
  }
689
}
690
 
691
#endif /* _ETH_DMA */
692
/*---------------------------------  PHY  ------------------------------------*/
693
 
694
/*******************************************************************************
695
* Function Name  : ETH_ReadPHYRegister
696
* Desciption     : Read a PHY register
697
* Input          : - PHYAddress: PHY device address, is the index of one of supported
698
*                    32 PHY devices.
699
*                    This parameter can be one of the following values: 0,..,31
700
*                  - PHYReg: PHY register address, is the index of one of the 32
701
*                    PHY register.
702
*                    This parameter can be one of the following values:
703
*                       - PHY_BCR    : Tranceiver Basic Control Register
704
*                       - PHY_BSR    : Tranceiver Basic Status Register
705
*                       - PHY_SR     : Tranceiver Status Register
706
*                       - More PHY register could be read depending on the used PHY
707
* Output         : None
708
* Return         : ETH_ERROR: in case of timeout
709
*                  Data read from the selected PHY register: for correct read
710
*******************************************************************************/
711
u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg)
712
{
713
  u32 tmpreg = 0;
714
  u32 timeout = 0;
715
 
716
  /* Check the parameters */
717
  eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
718
  eth_assert_param(IS_ETH_PHY_REG(PHYReg));
719
 
720
  /* Get the ETHERNET MACMIIAR value */
721
  tmpreg = ETH_MAC->MACMIIAR;
722
  /* Keep only the CSR Clock Range CR[2:0] bits value */
723
  tmpreg &= ~MACMIIAR_CR_Mask;
724
 
725
  /* Prepare the MII address register value */
726
  tmpreg |=(((u32)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
727
  tmpreg |=(((u32)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
728
  tmpreg &= ~ETH_MACMIIAR_MW;                         /* Set the read mode */
729
  tmpreg |= ETH_MACMIIAR_MB;                                              /* Set the MII Busy bit */
730
 
731
  /* Write the result value into the MII Address register */
732
  ETH_MAC->MACMIIAR = tmpreg;
733
 
734
  /* Check for the Busy flag */
735
  do
736
  {
737
    timeout++;
738
    tmpreg = ETH_MAC->MACMIIAR;
739
  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (u32)PHY_READ_TO));
740
 
741
  /* Return ERROR in case of timeout */
742
  if(timeout == PHY_READ_TO)
743
  {
744
    return (u16)ETH_ERROR;
745
  }
746
 
747
  /* Return data register value */
748
  return (u16)(ETH_MAC->MACMIIDR);
749
}
750
 
751
/*******************************************************************************
752
* Function Name  : ETH_WritePHYRegister
753
* Desciption     : Write to a PHY register
754
* Input          : - PHYAddress: PHY device address, is the index of one of supported
755
*                    32 PHY devices.
756
*                    This parameter can be one of the following values: 0,..,31
757
*                  - PHYReg: PHY register address, is the index of one of the 32
758
*                    PHY register.
759
*                    This parameter can be one of the following values:
760
*                       - PHY_BCR    : Tranceiver Control Register
761
*                       - More PHY register could be written depending on the used PHY
762
*                  - PHYValue: the value to write
763
* Output         : None
764
* Return         : ETH_ERROR: in case of timeout
765
*                  ETH_SUCCESS: for correct read
766
*******************************************************************************/
767
u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue)
768
{
769
  u32 tmpreg = 0;
770
  u32 timeout = 0;
771
 
772
  /* Check the parameters */
773
  eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
774
  eth_assert_param(IS_ETH_PHY_REG(PHYReg));
775
 
776
  /* Get the ETHERNET MACMIIAR value */
777
  tmpreg = ETH_MAC->MACMIIAR;
778
  /* Keep only the CSR Clock Range CR[2:0] bits value */
779
  tmpreg &= ~MACMIIAR_CR_Mask;
780
 
781
  /* Prepare the MII register address value */
782
  tmpreg |=(((u32)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
783
  tmpreg |=(((u32)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
784
  tmpreg |= ETH_MACMIIAR_MW;                          /* Set the write mode */
785
  tmpreg |= ETH_MACMIIAR_MB;                                  /* Set the MII Busy bit */
786
 
787
  /* Give the value to the MII data register */
788
  ETH_MAC->MACMIIDR = PHYValue;
789
 
790
  /* Write the result value into the MII Address register */
791
  ETH_MAC->MACMIIAR = tmpreg;
792
 
793
  /* Check for the Busy flag */
794
  do
795
  {
796
    timeout++;
797
    tmpreg = ETH_MAC->MACMIIAR;
798
  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (u32)PHY_WRITE_TO));
799
 
800
  /* Return ERROR in case of timeout */
801
  if(timeout == PHY_WRITE_TO)
802
  {
803
    return ETH_ERROR;
804
  }
805
 
806
  /* Return SUCCESS */
807
  return ETH_SUCCESS;
808
}
809
 
810
/*******************************************************************************
811
* Function Name  : ETH_PHYLoopBackCmd
812
* Desciption     : Enables or disables the PHY loopBack mode.
813
* Input          : - PHYAddress: PHY device address, is the index of one of supported
814
*                    32 PHY devices.
815
*                    This parameter can be one of the following values:
816
*                  - NewState: new state of the PHY loopBack mode.
817
*                    This parameter can be: ENABLE or DISABLE.
818
*                  Note: Don't be confused with ETH_MACLoopBackCmd function
819
*                        which enables internal loopback at MII level
820
* Output         : None
821
* Return         : None
822
*******************************************************************************/
823
u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState)
824
{
825
  u16 tmpreg = 0;
826
 
827
  /* Check the parameters */
828
  eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
829
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
830
 
831
  /* Get the PHY configuration to update it */
832
  tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR);
833
 
834
  if (NewState != DISABLE)
835
  {
836
    /* Enable the PHY loopback mode */
837
    tmpreg |= PHY_Loopback;
838
  }
839
  else
840
  {
841
    /* Disable the PHY loopback mode: normal mode */
842
    tmpreg &= (u16)(~(u16)PHY_Loopback);
843
  }
844
 
845
  /* Update the PHY control register with the new configuration */
846
  if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (u32)RESET)
847
  {
848
    return ETH_SUCCESS;
849
  }
850
  else
851
  {
852
    /* Return SUCCESS */
853
    return ETH_ERROR;
854
  }
855
}
856
 
857
/*---------------------------------  MAC  ------------------------------------*/
858
 
859
/*******************************************************************************
860
* Function Name  : ETH_MACTransmissionCmd
861
* Desciption     : Enables or disables the MAC transmission.
862
* Input          : - NewState: new state of the MAC transmission.
863
*                    This parameter can be: ENABLE or DISABLE.
864
* Output         : None
865
* Return         : None
866
*******************************************************************************/
867
void ETH_MACTransmissionCmd(FunctionalState NewState)
868
{
869
  /* Check the parameters */
870
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
871
 
872
  if (NewState != DISABLE)
873
  {
874
    /* Enable the MAC transmission */
875
    ETH_MAC->MACCR |= ETH_MACCR_TE;
876
  }
877
  else
878
  {
879
    /* Disable the MAC transmission */
880
    ETH_MAC->MACCR &= ~ETH_MACCR_TE;
881
  }
882
}
883
 
884
/*******************************************************************************
885
* Function Name  : ETH_MACReceptionCmd
886
* Desciption     : Enables or disables the MAC reception.
887
* Input          : - NewState: new state of the MAC reception.
888
*                    This parameter can be: ENABLE or DISABLE.
889
* Output         : None
890
* Return         : None
891
*******************************************************************************/
892
void ETH_MACReceptionCmd(FunctionalState NewState)
893
{
894
  /* Check the parameters */
895
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
896
 
897
  if (NewState != DISABLE)
898
  {
899
    /* Enable the MAC reception */
900
    ETH_MAC->MACCR |= ETH_MACCR_RE;
901
  }
902
  else
903
  {
904
    /* Disable the MAC reception */
905
    ETH_MAC->MACCR &= ~ETH_MACCR_RE;
906
  }
907
}
908
 
909
/*******************************************************************************
910
* Function Name  : ETH_GetFlowControlBusyStatus
911
* Desciption     : Checks whether the ETHERNET flow control busy bit is set or not.
912
* Input          : None
913
* Output         : None
914
* Return         : The new state of flow control busy status bit (SET or RESET).
915
*******************************************************************************/
916
FlagStatus ETH_GetFlowControlBusyStatus(void)
917
{
918
  FlagStatus bitstatus = RESET;
919
 
920
  /* The Flow Control register should not be written to until this bit is cleared */
921
  if ((ETH_MAC->MACFCR & ETH_MACFCR_FCBBPA) != (u32)RESET)
922
  {
923
    bitstatus = SET;
924
  }
925
  else
926
  {
927
    bitstatus = RESET;
928
  }
929
  return bitstatus;
930
}
931
 
932
/*******************************************************************************
933
* Function Name  : ETH_InitiatePauseControlFrame
934
* Desciption     : Initiate a Pause Control Frame (Full-duplex only).
935
* Input          : None
936
* Output         : None
937
* Return         : None
938
*******************************************************************************/
939
void ETH_InitiatePauseControlFrame(void)
940
{
941
  /* When Set In full duplex MAC initiates pause control frame */
942
  ETH_MAC->MACFCR |= ETH_MACFCR_FCBBPA;
943
}
944
 
945
/*******************************************************************************
946
* Function Name  : ETH_BackPressureActivationCmd
947
* Desciption     : Enables or disables the MAC BackPressure operation activation (Half-duplex only).
948
* Input          : - NewState: new state of the MAC BackPressure operation activation.
949
*                    This parameter can be: ENABLE or DISABLE.
950
* Output         : None
951
* Return         : None
952
*******************************************************************************/
953
void ETH_BackPressureActivationCmd(FunctionalState NewState)
954
{
955
  /* Check the parameters */
956
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
957
 
958
  if (NewState != DISABLE)
959
  {
960
    /* Activate the MAC BackPressure operation */
961
    /* In Half duplex: during backpressure, when the MAC receives a new frame,
962
    the transmitter starts sending a JAM pattern resulting in a collision */
963
    ETH_MAC->MACFCR |= ETH_MACFCR_FCBBPA;
964
  }
965
  else
966
  {
967
    /* Desactivate the MAC BackPressure operation */
968
    ETH_MAC->MACFCR &= ~ETH_MACFCR_FCBBPA;
969
  }
970
}
971
 
972
/*******************************************************************************
973
* Function Name  : ETH_GetMACFlagStatus
974
* Desciption     : Checks whether the specified ETHERNET MAC flag is set or not.
975
* Input          : - ETH_MAC_FLAG: specifies the flag to check.
976
*                    This parameter can be one of the following values:
977
*                       - ETH_MAC_FLAG_TST  : Time stamp trigger flag
978
*                       - ETH_MAC_FLAG_MMCT : MMC transmit flag
979
*                       - ETH_MAC_FLAG_MMCR : MMC receive flag
980
*                       - ETH_MAC_FLAG_MMC  : MMC flag
981
*                       - ETH_MAC_FLAG_PMT  : PMT flag
982
* Output         : None
983
* Return         : The new state of ETHERNET MAC flag (SET or RESET).
984
*******************************************************************************/
985
FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG)
986
{
987
  FlagStatus bitstatus = RESET;
988
 
989
  /* Check the parameters */
990
  eth_assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG));
991
 
992
  if ((ETH_MAC->MACSR & ETH_MAC_FLAG) != (u32)RESET)
993
  {
994
    bitstatus = SET;
995
  }
996
  else
997
  {
998
    bitstatus = RESET;
999
  }
1000
  return bitstatus;
1001
}
1002
 
1003
/*******************************************************************************
1004
* Function Name  : ETH_GetMACITStatus
1005
* Desciption     : Checks whether the specified ETHERNET MAC interrupt has occurred or not.
1006
* Input          : - ETH_MAC_IT: specifies the interrupt source to check.
1007
*                    This parameter can be one of the following values:
1008
*                       - ETH_MAC_IT_TST   : Time stamp trigger interrupt
1009
*                       - ETH_MAC_IT_MMCT : MMC transmit interrupt
1010
*                       - ETH_MAC_IT_MMCR : MMC receive interrupt
1011
*                       - ETH_MAC_IT_MMC  : MMC interrupt
1012
*                       - ETH_MAC_IT_PMT  : PMT interrupt
1013
* Output         : None
1014
* Return         : The new state of ETHERNET MAC interrupt (SET or RESET).
1015
*******************************************************************************/
1016
ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT)
1017
{
1018
  ITStatus bitstatus = RESET;
1019
 
1020
  /* Check the parameters */
1021
  eth_assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT));
1022
 
1023
  if ((ETH_MAC->MACSR & ETH_MAC_IT) != (u32)RESET)
1024
  {
1025
    bitstatus = SET;
1026
  }
1027
  else
1028
  {
1029
    bitstatus = RESET;
1030
  }
1031
  return bitstatus;
1032
}
1033
 
1034
/*******************************************************************************
1035
* Function Name  : ETH_MACITConfig
1036
* Desciption     : Enables or disables the specified ETHERNET MAC interrupts.
1037
* Input          : - ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
1038
*                    enabled or disabled.
1039
*                    This parameter can be any combination of the following values:
1040
*                       - ETH_MAC_IT_TST : Time stamp trigger interrupt
1041
*                       - ETH_MAC_IT_PMT : PMT interrupt
1042
*                  - NewState: new state of the specified ETHERNET MAC interrupts.
1043
*                    This parameter can be: ENABLE or DISABLE.
1044
* Output         : None
1045
* Return         : None
1046
*******************************************************************************/
1047
void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState)
1048
{
1049
  /* Check the parameters */
1050
  eth_assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
1051
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1052
 
1053
  if (NewState != DISABLE)
1054
  {
1055
    /* Enable the selected ETHERNET MAC interrupts */
1056
    ETH_MAC->MACIMR &= (~(u32)ETH_MAC_IT);
1057
  }
1058
  else
1059
  {
1060
    /* Disable the selected ETHERNET MAC interrupts */
1061
    ETH_MAC->MACIMR |= ETH_MAC_IT;
1062
  }
1063
}
1064
 
1065
/*******************************************************************************
1066
* Function Name  : ETH_MACAddressConfig
1067
* Desciption     : Configures the selected MAC address.
1068
* Input          : - MacAddr: The MAC addres to configure.
1069
*                    This parameter can be one of the following values:
1070
*                     - ETH_MAC_Address0 : MAC Address0
1071
*                     - ETH_MAC_Address1 : MAC Address1
1072
*                     - ETH_MAC_Address2 : MAC Address2
1073
*                     - ETH_MAC_Address3 : MAC Address3
1074
*                  - Addr: Pointer on MAC address buffer data (6 bytes).
1075
* Output         : None
1076
* Return         : None
1077
*******************************************************************************/
1078
void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr)
1079
{
1080
  u32 tmpreg;
1081
 
1082
  /* Check the parameters */
1083
  eth_assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1084
 
1085
  /* Calculate the selectecd MAC address high register */
1086
  tmpreg = ((u32)Addr[5] << 8) | (u32)Addr[4];
1087
 
1088
  /* Load the selectecd MAC address high register */
1089
  (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg;
1090
 
1091
  /* Calculate the selectecd MAC address low register */
1092
  tmpreg = ((u32)Addr[3] << 24) | ((u32)Addr[2] << 16) | ((u32)Addr[1] << 8) | Addr[0];
1093
 
1094
  /* Load the selectecd MAC address low register */
1095
  (*(vu32 *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg;
1096
}
1097
 
1098
/*******************************************************************************
1099
* Function Name  : ETH_GetMACAddress
1100
* Desciption     : Get the selected MAC address.
1101
* Input          : - MacAddr: The MAC addres to return.
1102
*                    This parameter can be one of the following values:
1103
*                     - ETH_MAC_Address0 : MAC Address0
1104
*                     - ETH_MAC_Address1 : MAC Address1
1105
*                     - ETH_MAC_Address2 : MAC Address2
1106
*                     - ETH_MAC_Address3 : MAC Address3
1107
*                  - Addr: Pointer on MAC address buffer data (6 bytes).
1108
* Output         : None
1109
* Return         : None
1110
*******************************************************************************/
1111
void ETH_GetMACAddress(u32 MacAddr, u8 *Addr)
1112
{
1113
  u32 tmpreg;
1114
 
1115
  /* Check the parameters */
1116
  eth_assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1117
 
1118
  /* Get the selectecd MAC address high register */
1119
  tmpreg =(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr));
1120
 
1121
  /* Calculate the selectecd MAC address buffer */
1122
  Addr[5] = ((tmpreg >> 8) & (u8)0xFF);
1123
  Addr[4] = (tmpreg & (u8)0xFF);
1124
 
1125
  /* Load the selectecd MAC address low register */
1126
  tmpreg =(*(vu32 *) (ETH_MAC_AddrLowBase + MacAddr));
1127
 
1128
  /* Calculate the selectecd MAC address buffer */
1129
  Addr[3] = ((tmpreg >> 24) & (u8)0xFF);
1130
  Addr[2] = ((tmpreg >> 16) & (u8)0xFF);
1131
  Addr[1] = ((tmpreg >> 8 ) & (u8)0xFF);
1132
  Addr[0] = (tmpreg & (u8)0xFF);
1133
}
1134
 
1135
/*******************************************************************************
1136
* Function Name  : ETH_MACAddressPerfectFilterCmd
1137
* Desciption     : Enables or disables the Address filter module uses the specified
1138
*                  ETHERNET MAC address for perfect filtering
1139
* Input          : - MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.
1140
*                    This parameter can be one of the following values:
1141
*                     - ETH_MAC_Address1 : MAC Address1
1142
*                     - ETH_MAC_Address2 : MAC Address2
1143
*                     - ETH_MAC_Address3 : MAC Address3
1144
*                  - NewState: new state of the specified ETHERNET MAC address use.
1145
*                    This parameter can be: ENABLE or DISABLE.
1146
* Output         : None
1147
* Return         : None
1148
*******************************************************************************/
1149
void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState)
1150
{
1151
  /* Check the parameters */
1152
  eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1153
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1154
 
1155
  if (NewState != DISABLE)
1156
  {
1157
    /* Enable the selected ETHERNET MAC address for perfect filtering */
1158
    (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE;
1159
  }
1160
  else
1161
  {
1162
    /* Disable the selected ETHERNET MAC address for perfect filtering */
1163
    (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_AE);
1164
  }
1165
}
1166
 
1167
/*******************************************************************************
1168
* Function Name  : ETH_MACAddressFilterConfig
1169
* Desciption     : Set the filter type for the specified ETHERNET MAC address
1170
* Input          : - MacAddr: specifies the ETHERNET MAC address
1171
*                    This parameter can be one of the following values:
1172
*                     - ETH_MAC_Address1 : MAC Address1
1173
*                     - ETH_MAC_Address2 : MAC Address2
1174
*                     - ETH_MAC_Address3 : MAC Address3
1175
*                  - Filter: specifies the used frame received field for comparaison
1176
*                    This parameter can be one of the following values:
1177
*                     - ETH_MAC_AddressFilter_SA : MAC Address is used to compare
1178
*                       with the SA fields of the received frame.
1179
*                     - ETH_MAC_AddressFilter_DA : MAC Address is used to compare
1180
*                       with the DA fields of the received frame.
1181
* Output         : None
1182
* Return         : None
1183
*******************************************************************************/
1184
void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter)
1185
{
1186
  /* Check the parameters */
1187
  eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1188
  eth_assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
1189
 
1190
  if (Filter != ETH_MAC_AddressFilter_DA)
1191
  {
1192
    /* The selected ETHERNET MAC address is used to compare with the SA fields of the
1193
       received frame. */
1194
    (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA;
1195
  }
1196
  else
1197
  {
1198
    /* The selected ETHERNET MAC address is used to compare with the DA fields of the
1199
       received frame. */
1200
    (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_SA);
1201
  }
1202
}
1203
 
1204
/*******************************************************************************
1205
* Function Name  : ETH_MACAddressMaskBytesFilterConfig
1206
* Desciption     : Set the filter type for the specified ETHERNET MAC address
1207
* Input          : - MacAddr: specifies the ETHERNET MAC address
1208
*                    This parameter can be one of the following values:
1209
*                     - ETH_MAC_Address1 : MAC Address1
1210
*                     - ETH_MAC_Address2 : MAC Address2
1211
*                     - ETH_MAC_Address3 : MAC Address3
1212
*                  - MaskByte: specifies the used address bytes for comparaison
1213
*                    This parameter can be any combination of the following values:
1214
*                     - ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
1215
*                     - ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
1216
*                     - ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
1217
*                     - ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
1218
*                     - ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
1219
*                     - ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
1220
* Output         : None
1221
* Return         : None
1222
*******************************************************************************/
1223
void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte)
1224
{
1225
  /* Check the parameters */
1226
  eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1227
  eth_assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
1228
 
1229
  /* Clear MBC bits in the selected MAC address  high register */
1230
  (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_MBC);
1231
 
1232
  /* Set the selected Filetr mask bytes */
1233
  (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte;
1234
}
1235
 
1236
/*------------------------  DMA Tx/Rx Desciptors ----------------------------*/
1237
#ifdef _ETH_DMA
1238
/*******************************************************************************
1239
* Function Name  : ETH_DMATxDescChainInit
1240
* Desciption     : Initializes the DMA Tx descriptors in chain mode.
1241
* Input          : - DMATxDescTab: Pointer on the first Tx desc list
1242
*                  - TxBuff: Pointer on the first TxBuffer list
1243
*                  - TxBuffCount: Number of the used Tx desc in the list
1244
* Output         : None
1245
* Return         : None
1246
*******************************************************************************/
1247
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8* TxBuff, u32 TxBuffCount)
1248
{
1249
  u32 i = 0;
1250
  ETH_DMADESCTypeDef *DMATxDesc;
1251
 
1252
  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
1253
  DMATxDescToSet = DMATxDescTab;
1254
 
1255
  /* Fill each DMATxDesc descriptor with the right values */
1256
  for(i=0; i < TxBuffCount; i++)
1257
  {
1258
    /* Get the pointer on the ith member of the Tx Desc list */
1259
    DMATxDesc = DMATxDescTab + i;
1260
 
1261
    /* Set Second Address Chained bit */
1262
    DMATxDesc->Status = ETH_DMATxDesc_TCH;
1263
 
1264
    /* Set Buffer1 address pointer */
1265
    DMATxDesc->Buffer1Addr = (u32)*((u32*)TxBuff + i);
1266
 
1267
    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
1268
    if(i < (TxBuffCount-1))
1269
    {
1270
      /* Set next descriptor address register with next descriptor base address */
1271
      DMATxDesc->Buffer2NextDescAddr = (u32)(DMATxDescTab+i+1);
1272
    }
1273
    else
1274
    {
1275
      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
1276
      DMATxDesc->Buffer2NextDescAddr = (u32) DMATxDescTab;
1277
    }
1278
  }
1279
 
1280
  /* Set Transmit Desciptor List Address Register */
1281
  ETH_DMA->DMATDLAR = (u32) DMATxDescTab;
1282
}
1283
 
1284
/*******************************************************************************
1285
* Function Name  : ETH_DMATxDescRingInit
1286
* Desciption     : Initializes the DMA Tx descriptors in ring mode.
1287
* Input          : - DMATxDescTab: Pointer on the first Tx desc list
1288
*                  - TxBuff1: Pointer on the first TxBuffer1 list
1289
*                  - TxBuff2: Pointer on the first TxBuffer2 list
1290
*                  - TxBuffCount: Number of the used Tx desc in the list
1291
*                Note: see decriptor skip length defined in ETH_DMA_InitStruct
1292
                       for the number of Words to skip between two unchained descriptors.
1293
* Output         : None
1294
* Return         : None
1295
*******************************************************************************/
1296
void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount)
1297
{
1298
  u32 i = 0;
1299
  ETH_DMADESCTypeDef *DMATxDesc;
1300
 
1301
  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
1302
  DMATxDescToSet = DMATxDescTab;
1303
 
1304
  /* Fill each DMATxDesc descriptor with the right values */
1305
  for(i=0; i < TxBuffCount; i++)
1306
  {
1307
    /* Get the pointer on the ith member of the Tx Desc list */
1308
    DMATxDesc = DMATxDescTab + i;
1309
 
1310
    /* Set Buffer1 address pointer */
1311
    DMATxDesc->Buffer1Addr = (u32)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);
1312
 
1313
    /* Set Buffer2 address pointer */
1314
    DMATxDesc->Buffer2NextDescAddr = (u32)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);
1315
 
1316
    /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base
1317
       address of the list, creating a Desciptor Ring */
1318
    if(i == (TxBuffCount-1))
1319
    {
1320
      /* Set Transmit End of Ring bit */
1321
      DMATxDesc->Status = ETH_DMATxDesc_TER;
1322
    }
1323
  }
1324
 
1325
  /* Set Transmit Desciptor List Address Register */
1326
  ETH_DMA->DMATDLAR =  (u32) DMATxDescTab;
1327
}
1328
 
1329
/*******************************************************************************
1330
* Function Name  : ETH_GetDMATxDescFlagStatus
1331
* Desciption     : Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
1332
* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
1333
*                  - ETH_DMATxDescFlag: specifies the flag to check.
1334
*                    This parameter can be one of the following values:
1335
*                       - ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
1336
*                       - ETH_DMATxDesc_IC  : Interrupt on completetion
1337
*                       - ETH_DMATxDesc_LS  : Last Segment
1338
*                       - ETH_DMATxDesc_FS  : First Segment
1339
*                       - ETH_DMATxDesc_DC  : Disable CRC
1340
*                       - ETH_DMATxDesc_DP  : Disable Pad
1341
*                       - ETH_DMATxDesc_TTSE: Transmit Time Stamp       Enable
1342
*                       - ETH_DMATxDesc_TER : Transmit End of Ring
1343
*                       - ETH_DMATxDesc_TCH : Second Address Chained
1344
*                       - ETH_DMATxDesc_TTSS: Tx Time Stamp Status
1345
*                       - ETH_DMATxDesc_IHE : IP Header Error
1346
*                       - ETH_DMATxDesc_ES  : Error summary
1347
*                       - ETH_DMATxDesc_JT  : Jabber Timeout
1348
*                       - ETH_DMATxDesc_FF  : Frame Flushed: DMA/MTL flushed the frame due to SW flush
1349
*                       - ETH_DMATxDesc_PCE : Payload Checksum Error
1350
*                       - ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission
1351
*                       - ETH_DMATxDesc_NC  : No Carrier: no carrier signal from the tranceiver
1352
*                       - ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
1353
*                       - ETH_DMATxDesc_EC  : Excessive Collision: transmission aborted after 16 collisions
1354
*                       - ETH_DMATxDesc_VF  : VLAN Frame
1355
*                       - ETH_DMATxDesc_CC  : Collision Count
1356
*                       - ETH_DMATxDesc_ED  : Excessive Deferral
1357
*                       - ETH_DMATxDesc_UF  : Underflow Error: late data arrival from the memory
1358
*                       - ETH_DMATxDesc_DB  : Deferred Bit
1359
* Output         : None
1360
* Return         : The new state of ETH_DMATxDescFlag (SET or RESET).
1361
*******************************************************************************/
1362
FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag)
1363
{
1364
  FlagStatus bitstatus = RESET;
1365
 
1366
  /* Check the parameters */
1367
  eth_assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
1368
 
1369
  if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (u32)RESET)
1370
  {
1371
    bitstatus = SET;
1372
  }
1373
  else
1374
  {
1375
    bitstatus = RESET;
1376
  }
1377
  return bitstatus;
1378
}
1379
 
1380
/*******************************************************************************
1381
* Function Name  : ETH_GetDMATxDescCollisionCount
1382
* Desciption     : Returns the specified ETHERNET DMA Tx Desc collision count.
1383
* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
1384
* Output         : None
1385
* Return         : The Transmit descriptor collision counter value.
1386
*******************************************************************************/
1387
u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
1388
{
1389
  /* Return the Receive descriptor frame length */
1390
  return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift);
1391
}
1392
 
1393
/*******************************************************************************
1394
* Function Name  : ETH_SetDMATxDescOwnBit
1395
* Desciption     : Set the specified DMA Tx Desc Own bit.
1396
* Input          : - DMATxDesc: Pointer on a Tx desc
1397
* Output         : None
1398
* Return         : None
1399
*******************************************************************************/
1400
void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
1401
{
1402
  /* Set the DMA Tx Desc Own bit */
1403
  DMATxDesc->Status |= ETH_DMATxDesc_OWN;
1404
}
1405
 
1406
/*******************************************************************************
1407
* Function Name  : ETH_DMATxDescTransmitITConfig
1408
* Desciption     : Enables or disables the specified DMA Tx Desc Transmit interrupt.
1409
* Input          : - DMATxDesc: Pointer on a Tx desc
1410
*                  - NewState: new state of the DMA Tx Desc transmit interrupt.
1411
*                    This parameter can be: ENABLE or DISABLE.
1412
* Output         : None
1413
* Return         : None
1414
*******************************************************************************/
1415
void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1416
{
1417
  /* Check the parameters */
1418
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1419
 
1420
  if (NewState != DISABLE)
1421
  {
1422
    /* Enable the DMA Tx Desc Transmit interrupt */
1423
    DMATxDesc->Status |= ETH_DMATxDesc_IC;
1424
  }
1425
  else
1426
  {
1427
    /* Disable the DMA Tx Desc Transmit interrupt */
1428
    DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_IC);
1429
  }
1430
}
1431
 
1432
/*******************************************************************************
1433
* Function Name  : ETH_DMATxDescFrameSegmentConfig
1434
* Desciption     : Enables or disables the specified DMA Tx Desc Transmit interrupt.
1435
* Input          : - DMATxDesc: Pointer on a Tx desc
1436
*                  - FrameSegment: specifies is the actual Tx desc contain last or first segment.
1437
*                    This parameter can be one of the following values:
1438
*                       - ETH_DMATxDesc_LastSegment  : actual Tx desc contain last segment
1439
*                       - ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment
1440
* Output         : None
1441
* Return         : None
1442
*******************************************************************************/
1443
void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment)
1444
{
1445
  /* Check the parameters */
1446
  eth_assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
1447
 
1448
  /* Selects the DMA Tx Desc Frame segment */
1449
  DMATxDesc->Status |= DMATxDesc_FrameSegment;
1450
}
1451
 
1452
/*******************************************************************************
1453
* Function Name  : ETH_DMATxDescChecksumInsertionConfig
1454
* Desciption     : Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
1455
* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
1456
*                  - Checksum: specifies is the DMA Tx desc checksum insertion.
1457
*                    This parameter can be one of the following values:
1458
*                       - ETH_DMATxDesc_ChecksumByPass : Checksum bypass
1459
*                       - ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
1460
*                       - ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1461
*                       - ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header
1462
* Output         : None
1463
* Return         : The Transmit descriptor collision.
1464
*******************************************************************************/
1465
void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum)
1466
{
1467
  /* Check the parameters */
1468
  eth_assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
1469
 
1470
  /* Set the selected DMA Tx desc checksum insertion control */
1471
  DMATxDesc->Status |= DMATxDesc_Checksum;
1472
}
1473
 
1474
/*******************************************************************************
1475
* Function Name  : ETH_DMATxDescCRCCmd
1476
* Desciption     : Enables or disables the DMA Tx Desc CRC.
1477
* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
1478
*                  - NewState: new state of the specified DMA Tx Desc CRC.
1479
*                    This parameter can be: ENABLE or DISABLE.
1480
* Output         : None
1481
* Return         : None
1482
*******************************************************************************/
1483
void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1484
{
1485
  /* Check the parameters */
1486
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1487
 
1488
  if (NewState != DISABLE)
1489
  {
1490
    /* Enable the selected DMA Tx Desc CRC */
1491
    DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_DC);
1492
  }
1493
  else
1494
  {
1495
    /* Disable the selected DMA Tx Desc CRC */
1496
    DMATxDesc->Status |= ETH_DMATxDesc_DC;
1497
  }
1498
}
1499
 
1500
/*******************************************************************************
1501
* Function Name  : ETH_DMATxDescEndOfRingCmd
1502
* Desciption     : Enables or disables the DMA Tx Desc end of ring.
1503
* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
1504
*                  - NewState: new state of the specified DMA Tx Desc end of ring.
1505
*                    This parameter can be: ENABLE or DISABLE.
1506
* Output         : NoneH
1507
* Return         : None
1508
*******************************************************************************/
1509
void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1510
{
1511
  /* Check the parameters */
1512
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1513
 
1514
  if (NewState != DISABLE)
1515
  {
1516
    /* Enable the selected DMA Tx Desc end of ring */
1517
    DMATxDesc->Status |= ETH_DMATxDesc_TER;
1518
  }
1519
  else
1520
  {
1521
    /* Disable the selected DMA Tx Desc end of ring */
1522
    DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_TER);
1523
  }
1524
}
1525
 
1526
/*******************************************************************************
1527
* Function Name  : ETH_DMATxDescSecondAddressChainedCmd
1528
* Desciption     : Enables or disables the DMA Tx Desc second address chained.
1529
* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
1530
*                  - NewState: new state of the specified DMA Tx Desc second address chained.
1531
*                    This parameter can be: ENABLE or DISABLE.
1532
* Output         : None
1533
* Return         : None
1534
*******************************************************************************/
1535
void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1536
{
1537
  /* Check the parameters */
1538
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1539
 
1540
  if (NewState != DISABLE)
1541
  {
1542
    /* Enable the selected DMA Tx Desc second address chained */
1543
    DMATxDesc->Status |= ETH_DMATxDesc_TCH;
1544
  }
1545
  else
1546
  {
1547
    /* Disable the selected DMA Tx Desc second address chained */
1548
    DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_TCH);
1549
  }
1550
}
1551
 
1552
/*******************************************************************************
1553
* Function Name  : ETH_DMATxDescShortFramePaddingCmd
1554
* Desciption     : Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1555
* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
1556
*                  - NewState: new state of the specified DMA Tx Desc padding for
1557
*                    frame shorter than 64 bytes.
1558
*                    This parameter can be: ENABLE or DISABLE.
1559
* Output         : None
1560
* Return         : None
1561
*******************************************************************************/
1562
void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1563
{
1564
  /* Check the parameters */
1565
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1566
 
1567
  if (NewState != DISABLE)
1568
  {
1569
    /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
1570
    DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_DP);
1571
  }
1572
  else
1573
  {
1574
    /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
1575
    DMATxDesc->Status |= ETH_DMATxDesc_DP;
1576
  }
1577
}
1578
 
1579
/*******************************************************************************
1580
* Function Name  : ETH_DMATxDescTimeStampCmd
1581
* Desciption     : Enables or disables the DMA Tx Desc time stamp.
1582
* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
1583
*                  - NewState: new state of the specified DMA Tx Desc time stamp.
1584
*                    This parameter can be: ENABLE or DISABLE.
1585
* Output         : None
1586
* Return         : None
1587
*******************************************************************************/
1588
void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1589
{
1590
  /* Check the parameters */
1591
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1592
 
1593
  if (NewState != DISABLE)
1594
  {
1595
    /* Enable the selected DMA Tx Desc time stamp */
1596
    DMATxDesc->Status |= ETH_DMATxDesc_TTSE;
1597
  }
1598
  else
1599
  {
1600
    /* Disable the selected DMA Tx Desc time stamp */
1601
    DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_TTSE);
1602
  }
1603
}
1604
 
1605
/*******************************************************************************
1606
* Function Name  : ETH_DMATxDescBufferSizeConfig
1607
* Desciption     : Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
1608
* Input          : - DMATxDesc: Pointer on a Tx desc
1609
*                  - BufferSize1: specifies the Tx desc buffer1 size.
1610
*                  - BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
1611
* Output         : None
1612
* Return         : None
1613
*******************************************************************************/
1614
void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2)
1615
{
1616
  /* Check the parameters */
1617
  eth_assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
1618
  eth_assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
1619
 
1620
  /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
1621
  DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift));
1622
}
1623
 
1624
/*******************************************************************************
1625
* Function Name  : ETH_DMARxDescChainInit
1626
* Desciption     : Initializes the DMA Rx descriptors in chain mode.
1627
* Input          : - DMARxDescTab: Pointer on the first Rx desc list
1628
*                  - RxBuff: Pointer on the first RxBuffer list
1629
*                  - RxBuffCount: Number of the used Rx desc in the list
1630
* Output         : None
1631
* Return         : None
1632
*******************************************************************************/
1633
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount)
1634
{
1635
  u32 i = 0;
1636
  ETH_DMADESCTypeDef *DMARxDesc;
1637
 
1638
  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
1639
  DMARxDescToGet = DMARxDescTab;
1640
 
1641
  /* Fill each DMARxDesc descriptor with the right values */
1642
  for(i=0; i < RxBuffCount; i++)
1643
  {
1644
    /* Get the pointer on the ith member of the Rx Desc list */
1645
    DMARxDesc = DMARxDescTab+i;
1646
 
1647
    /* Set Own bit of the Rx descriptor Status */
1648
    DMARxDesc->Status = ETH_DMARxDesc_OWN;
1649
//    DMARxDesc->Status = 0;
1650
 
1651
    /* Set Buffer1 size and Second Address Chained bit */
1652
    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (u32)ETH_MAX_PACKET_SIZE;
1653
 
1654
    /* Set Buffer1 address pointer */
1655
    DMARxDesc->Buffer1Addr = (u32)*((u32*)RxBuff + i);
1656
 
1657
    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
1658
    if(i < (RxBuffCount-1))
1659
    {
1660
      /* Set next descriptor address register with next descriptor base address */
1661
      DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab+i+1);
1662
    }
1663
    else
1664
    {
1665
      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
1666
      DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab);
1667
    }
1668
  }
1669
 
1670
  /* Set Receive Desciptor List Address Register */
1671
  ETH_DMA->DMARDLAR = (u32) DMARxDescTab;
1672
}
1673
 
1674
/*******************************************************************************
1675
* Function Name  : ETH_DMARxDescRingInit
1676
* Desciption     : Initializes the DMA Rx descriptors in ring mode.
1677
* Input          : - DMARxDescTab: Pointer on the first Rx desc list
1678
*                  - RxBuff1: Pointer on the first RxBuffer1 list
1679
*                  - RxBuff2: Pointer on the first RxBuffer2 list
1680
*                  - RxBuffCount: Number of the used Rx desc in the list
1681
*                Note: see decriptor skip length defined in ETH_DMA_InitStruct
1682
                       for the number of Words to skip between two unchained descriptors.
1683
* Output         : None
1684
* Return         : None
1685
*******************************************************************************/
1686
void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount)
1687
{
1688
  u32 i = 0;
1689
  ETH_DMADESCTypeDef *DMARxDesc;
1690
 
1691
  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
1692
  DMARxDescToGet = DMARxDescTab;
1693
 
1694
  /* Fill each DMARxDesc descriptor with the right values */
1695
  for(i=0; i < RxBuffCount; i++)
1696
  {
1697
    /* Get the pointer on the ith member of the Rx Desc list */
1698
    DMARxDesc = DMARxDescTab+i;
1699
 
1700
    /* Set Own bit of the Rx descriptor Status */
1701
    DMARxDesc->Status = ETH_DMARxDesc_OWN;
1702
 
1703
    /* Set Buffer1 size */
1704
    DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;
1705
 
1706
    /* Set Buffer1 address pointer */
1707
    DMARxDesc->Buffer1Addr = (u32)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]);
1708
 
1709
    /* Set Buffer2 address pointer */
1710
    DMARxDesc->Buffer2NextDescAddr = (u32)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]);
1711
 
1712
    /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base
1713
       address of the list, creating a Desciptor Ring */
1714
    if(i == (RxBuffCount-1))
1715
    {
1716
      /* Set Receive End of Ring bit */
1717
      DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
1718
    }
1719
  }
1720
 
1721
  /* Set Receive Desciptor List Address Register */
1722
  ETH_DMA->DMARDLAR = (u32) DMARxDescTab;
1723
}
1724
 
1725
/*******************************************************************************
1726
* Function Name  : ETH_GetDMARxDescFlagStatus
1727
* Desciption     : Checks whether the specified ETHERNET Rx Desc flag is set or not.
1728
* Input          : - DMARxDesc: pointer on a DMA Rx descriptor
1729
*                  - ETH_DMARxDescFlag: specifies the flag to check.
1730
*                    This parameter can be one of the following values:
1731
*                       - ETH_DMARxDesc_OWN:         OWN bit: descriptor is owned by DMA engine
1732
*                       - ETH_DMARxDesc_AFM:         DA Filter Fail for the rx frame
1733
*                       - ETH_DMARxDesc_ES:          Error summary
1734
*                       - ETH_DMARxDesc_DE:          Desciptor error: no more descriptors for receive frame
1735
*                       - ETH_DMARxDesc_SAF:         SA Filter Fail for the received frame
1736
*                       - ETH_DMARxDesc_LE:          Frame size not matching with length field
1737
*                       - ETH_DMARxDesc_OE:          Overflow Error: Frame was damaged due to buffer overflow
1738
*                       - ETH_DMARxDesc_VLAN:        VLAN Tag: received frame is a VLAN frame
1739
*                       - ETH_DMARxDesc_FS:          First descriptor of the frame
1740
*                       - ETH_DMARxDesc_LS:          Last descriptor of the frame
1741
*                       - ETH_DMARxDesc_IPV4HCE:     IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
1742
*                       - ETH_DMARxDesc_RxLongFrame: (Giant Frame)Rx - frame is longer than 1518/1522
1743
*                       - ETH_DMARxDesc_LC:          Late collision occurred during reception
1744
*                       - ETH_DMARxDesc_FT:          Frame type - Ethernet, otherwise 802.3
1745
*                       - ETH_DMARxDesc_RWT:         Receive Watchdog Timeout: watchdog timer expired during reception
1746
*                       - ETH_DMARxDesc_RE:          Receive error: error reported by MII interface
1747
*                       - ETH_DMARxDesc_DE:          Dribble bit error: frame contains non int multiple of 8 bits
1748
*                       - ETH_DMARxDesc_CE:          CRC error
1749
*                       - ETH_DMARxDesc_MAMPCE:      Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
1750
* Output         : None
1751
* Return         : The new state of ETH_DMARxDescFlag (SET or RESET).
1752
*******************************************************************************/
1753
FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag)
1754
{
1755
  FlagStatus bitstatus = RESET;
1756
 
1757
  /* Check the parameters */
1758
  eth_assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
1759
 
1760
  if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (u32)RESET)
1761
  {
1762
    bitstatus = SET;
1763
  }
1764
  else
1765
  {
1766
    bitstatus = RESET;
1767
  }
1768
  return bitstatus;
1769
}
1770
 
1771
/*******************************************************************************
1772
* Function Name  : ETH_SetDMARxDescOwnBit
1773
* Desciption     : Set the specified DMA Rx Desc Own bit.
1774
* Input          : - DMARxDesc: Pointer on a Rx desc
1775
* Output         : None
1776
* Return         : None
1777
*******************************************************************************/
1778
void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
1779
{
1780
  /* Set the DMA Rx Desc Own bit */
1781
  DMARxDesc->Status |= ETH_DMARxDesc_OWN;
1782
}
1783
 
1784
/*******************************************************************************
1785
* Function Name  : ETH_GetDMARxDescFrameLength
1786
* Desciption     : Returns the specified DMA Rx Desc frame length.
1787
* Input          : - DMARxDesc: pointer on a DMA Rx descriptor
1788
* Output         : None
1789
* Return         : The Rx descriptor received frame length.
1790
*******************************************************************************/
1791
u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
1792
{
1793
  /* Return the Receive descriptor frame length */
1794
  return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift);
1795
}
1796
 
1797
/*******************************************************************************
1798
* Function Name  : ETH_DMARxDescReceiveITConfig
1799
* Desciption     : Enables or disables the specified DMA Rx Desc receive interrupt.
1800
* Input          : - DMARxDesc: Pointer on a Rx desc
1801
*                  - NewState: new state of the specified DMA Rx Desc interrupt.
1802
*                    This parameter can be: ENABLE or DISABLE.
1803
* Output         : None
1804
* Return         : None
1805
*******************************************************************************/
1806
void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1807
{
1808
  /* Check the parameters */
1809
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1810
 
1811
  if (NewState != DISABLE)
1812
  {
1813
    /* Enable the DMA Rx Desc receive interrupt */
1814
    DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_DIC);
1815
  }
1816
  else
1817
  {
1818
    /* Disable the DMA Rx Desc receive interrupt */
1819
    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
1820
  }
1821
}
1822
 
1823
/*******************************************************************************
1824
* Function Name  : ETH_DMARxDescEndOfRingCmd
1825
* Desciption     : Enables or disables the DMA Rx Desc end of ring.
1826
* Input          : - DMARxDesc: pointer on a DMA Rx descriptor
1827
*                  - NewState: new state of the specified DMA Rx Desc end of ring.
1828
*                    This parameter can be: ENABLE or DISABLE.
1829
* Output         : None
1830
* Return         : None
1831
*******************************************************************************/
1832
void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1833
{
1834
  /* Check the parameters */
1835
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1836
 
1837
  if (NewState != DISABLE)
1838
  {
1839
    /* Enable the selected DMA Rx Desc end of ring */
1840
    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
1841
  }
1842
  else
1843
  {
1844
    /* Disable the selected DMA Rx Desc end of ring */
1845
    DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_RER);
1846
  }
1847
}
1848
 
1849
/*******************************************************************************
1850
* Function Name  : ETH_DMARxDescSecondAddressChainedCmd
1851
* Desciption     : Enables or disables the DMA Rx Desc second address chained.
1852
* Input          : - DMARxDesc: pointer on a DMA Rx descriptor
1853
*                  - NewState: new state of the specified DMA Rx Desc second address chained.
1854
*                    This parameter can be: ENABLE or DISABLE.
1855
* Output         : None
1856
* Return         : None
1857
*******************************************************************************/
1858
void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1859
{
1860
  /* Check the parameters */
1861
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
1862
 
1863
  if (NewState != DISABLE)
1864
  {
1865
    /* Enable the selected DMA Rx Desc second address chained */
1866
    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;
1867
  }
1868
  else
1869
  {
1870
    /* Disable the selected DMA Rx Desc second address chained */
1871
    DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_RCH);
1872
  }
1873
}
1874
 
1875
/*******************************************************************************
1876
* Function Name  : ETH_GetDMARxDescBufferSize
1877
* Desciption     : Returns the specified ETHERNET DMA Rx Desc buffer size.
1878
* Input          : - DMARxDesc: pointer on a DMA Rx descriptor
1879
*                  - DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
1880
*                    This parameter can be any one of the following values:
1881
*                       - ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
1882
*                       - ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2
1883
* Output         : None
1884
* Return         : The Receive descriptor frame length.
1885
*******************************************************************************/
1886
u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer)
1887
{
1888
  /* Check the parameters */
1889
  eth_assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
1890
 
1891
  if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
1892
  {
1893
    /* Return the DMA Rx Desc buffer2 size */
1894
    return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift);
1895
  }
1896
  else
1897
  {
1898
    /* Return the DMA Rx Desc buffer1 size */
1899
    return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1);
1900
  }
1901
}
1902
 
1903
/*---------------------------------  DMA  ------------------------------------*/
1904
/*******************************************************************************
1905
* Function Name  : ETH_SoftwareReset
1906
* Desciption     : Resets all MAC subsystem internal registers and logic.
1907
* Input          : None
1908
* Output         : None
1909
* Return         : None
1910
*******************************************************************************/
1911
void ETH_SoftwareReset(void)
1912
{
1913
  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
1914
  /* After reset all the registers holds their respective reset values */
1915
  ETH_DMA->DMABMR |= ETH_DMABMR_SR;
1916
}
1917
 
1918
/*******************************************************************************
1919
* Function Name  : ETH_GetSoftwareResetStatus
1920
* Desciption     : Checks whether the ETHERNET software reset bit is set or not.
1921
* Input          : None
1922
* Output         : None
1923
* Return         : The new state of DMA Bus Mode register SR bit (SET or RESET).
1924
*******************************************************************************/
1925
FlagStatus ETH_GetSoftwareResetStatus(void)
1926
{
1927
  FlagStatus bitstatus = RESET;
1928
 
1929
  if((ETH_DMA->DMABMR & ETH_DMABMR_SR) != (u32)RESET)
1930
  {
1931
    bitstatus = SET;
1932
  }
1933
  else
1934
  {
1935
    bitstatus = RESET;
1936
  }
1937
  return bitstatus;
1938
}
1939
 
1940
/*******************************************************************************
1941
* Function Name  : ETH_GetDMAFlagStatus
1942
* Desciption     : Checks whether the specified ETHERNET DMA flag is set or not.
1943
* Input          : - ETH_DMA_IT: specifies the flag to check.
1944
*                    This parameter can be one of the following values:
1945
*                       - ETH_DMA_FLAG_TST : Time-stamp trigger flag
1946
*                       - ETH_DMA_FLAG_PMT : PMT flag
1947
*                       - ETH_DMA_FLAG_MMC : MMC flag
1948
*                       - ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
1949
*                       - ETH_DMA_FLAG_ReadWriteError    : Error bits 0-write trnsf, 1-read transfr
1950
*                       - ETH_DMA_FLAG_AccessError       : Error bits 0-Rx DMA, 1-Tx DMA
1951
*                       - ETH_DMA_FLAG_NIS : Normal interrupt summary flag
1952
*                       - ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
1953
*                       - ETH_DMA_FLAG_ER  : Early receive flag
1954
*                       - ETH_DMA_FLAG_FBE : Fatal bus error flag
1955
*                       - ETH_DMA_FLAG_ET  : Early transmit flag
1956
*                       - ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
1957
*                       - ETH_DMA_FLAG_RPS : Receive process stopped flag
1958
*                       - ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
1959
*                       - ETH_DMA_FLAG_R   : Receive flag
1960
*                       - ETH_DMA_FLAG_TU  : Underflow flag
1961
*                       - ETH_DMA_FLAG_RO  : Overflow flag
1962
*                       - ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
1963
*                       - ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
1964
*                       - ETH_DMA_FLAG_TPS : Transmit process stopped flag
1965
*                       - ETH_DMA_FLAG_T   : Transmit flag
1966
* Output         : None
1967
* Return         : The new state of ETH_DMA_FLAG (SET or RESET).
1968
*******************************************************************************/
1969
FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG)
1970
{
1971
  FlagStatus bitstatus = RESET;
1972
 
1973
  /* Check the parameters */
1974
  eth_assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
1975
 
1976
  if ((ETH_DMA->DMASR & ETH_DMA_FLAG) != (u32)RESET)
1977
  {
1978
    bitstatus = SET;
1979
  }
1980
  else
1981
  {
1982
    bitstatus = RESET;
1983
  }
1984
  return bitstatus;
1985
}
1986
 
1987
/*******************************************************************************
1988
* Function Name  : ETH_DMAClearFlag
1989
* Desciption     : Clears the ETHERNET?s DMA pending flag.
1990
* Input          : - ETH_DMA_FLAG: specifies the flag to clear.
1991
*                    This parameter can be any combination of the following values:
1992
*                       - ETH_DMA_FLAG_NIS : Normal interrupt summary flag
1993
*                       - ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
1994
*                       - ETH_DMA_FLAG_ER  : Early receive flag
1995
*                       - ETH_DMA_FLAG_FBE : Fatal bus error flag
1996
*                       - ETH_DMA_FLAG_ETI : Early transmit flag
1997
*                       - ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
1998
*                       - ETH_DMA_FLAG_RPS : Receive process stopped flag
1999
*                       - ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
2000
*                       - ETH_DMA_FLAG_R   : Receive flag
2001
*                       - ETH_DMA_FLAG_TU  : Transmit Underflow flag
2002
*                       - ETH_DMA_FLAG_RO  : Receive Overflow flag
2003
*                       - ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
2004
*                       - ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
2005
*                       - ETH_DMA_FLAG_TPS : Transmit process stopped flag
2006
*                       - ETH_DMA_FLAG_T   : Transmit flag
2007
* Output         : None
2008
* Return         : None
2009
*******************************************************************************/
2010
void ETH_DMAClearFlag(u32 ETH_DMA_FLAG)
2011
{
2012
  /* Check the parameters */
2013
  eth_assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
2014
 
2015
  /* Clear the selected ETHERNET DMA FLAG */
2016
  ETH_DMA->DMASR = (u32) ETH_DMA_FLAG;
2017
}
2018
 
2019
/*******************************************************************************
2020
* Function Name  : ETH_GetDMAITStatus
2021
* Desciption     : Checks whether the specified ETHERNET DMA interrupt has occured or not.
2022
* Input          : - ETH_DMA_IT: specifies the interrupt source to check.
2023
*                    This parameter can be one of the following values:
2024
*                       - ETH_DMA_IT_TST : Time-stamp trigger interrupt
2025
*                       - ETH_DMA_IT_PMT : PMT interrupt
2026
*                       - ETH_DMA_IT_MMC : MMC interrupt
2027
*                       - ETH_DMA_IT_NIS : Normal interrupt summary
2028
*                       - ETH_DMA_IT_AIS : Abnormal interrupt summary
2029
*                       - ETH_DMA_IT_ER  : Early receive interrupt
2030
*                       - ETH_DMA_IT_FBE : Fatal bus error interrupt
2031
*                       - ETH_DMA_IT_ET  : Early transmit interrupt
2032
*                       - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
2033
*                       - ETH_DMA_IT_RPS : Receive process stopped interrupt
2034
*                       - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
2035
*                       - ETH_DMA_IT_R   : Receive interrupt
2036
*                       - ETH_DMA_IT_TU  : Underflow interrupt
2037
*                       - ETH_DMA_IT_RO  : Overflow interrupt
2038
*                       - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
2039
*                       - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
2040
*                       - ETH_DMA_IT_TPS : Transmit process stopped interrupt
2041
*                       - ETH_DMA_IT_T   : Transmit interrupt
2042
* Output         : None
2043
* Return         : The new state of ETH_DMA_IT (SET or RESET).
2044
*******************************************************************************/
2045
ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT)
2046
{
2047
  ITStatus bitstatus = RESET;
2048
 
2049
  /* Check the parameters */
2050
  eth_assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
2051
 
2052
  if ((ETH_DMA->DMASR & ETH_DMA_IT) != (u32)RESET)
2053
  {
2054
    bitstatus = SET;
2055
  }
2056
  else
2057
  {
2058
    bitstatus = RESET;
2059
  }
2060
  return bitstatus;
2061
}
2062
 
2063
/*******************************************************************************
2064
* Function Name  : ETH_DMAClearITPendingBit
2065
* Desciption     : Clears the ETHERNET?s DMA IT pending bit.
2066
* Input          : - ETH_DMA_IT: specifies the interrupt pending bit to clear.
2067
*                    This parameter can be any combination of the following values:
2068
*                       - ETH_DMA_IT_NIS : Normal interrupt summary
2069
*                       - ETH_DMA_IT_AIS : Abnormal interrupt summary
2070
*                       - ETH_DMA_IT_ER  : Early receive interrupt
2071
*                       - ETH_DMA_IT_FBE : Fatal bus error interrupt
2072
*                       - ETH_DMA_IT_ETI : Early transmit interrupt
2073
*                       - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
2074
*                       - ETH_DMA_IT_RPS : Receive process stopped interrupt
2075
*                       - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
2076
*                       - ETH_DMA_IT_R   : Receive interrupt
2077
*                       - ETH_DMA_IT_TU  : Transmit Underflow interrupt
2078
*                       - ETH_DMA_IT_RO  : Receive Overflow interrupt
2079
*                       - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
2080
*                       - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
2081
*                       - ETH_DMA_IT_TPS : Transmit process stopped interrupt
2082
*                       - ETH_DMA_IT_T   : Transmit interrupt
2083
* Output         : None
2084
* Return         : None
2085
*******************************************************************************/
2086
void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT)
2087
{
2088
  /* Check the parameters */
2089
  eth_assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
2090
 
2091
  /* Clear the selected ETHERNET DMA IT */
2092
  ETH_DMA->DMASR = (u32) ETH_DMA_IT;
2093
}
2094
 
2095
/*******************************************************************************
2096
* Function Name  : ETH_GetDMATransmitProcessState
2097
* Desciption     : Returns the ETHERNET DMA Transmit Process State.
2098
* Input          : None
2099
* Output         : None
2100
* Return         : The new ETHERNET DMA Transmit Process State:
2101
*                  This can be one of the following values:
2102
*                     - ETH_DMA_TransmitProcess_Stopped   : Stopped - Reset or Stop Tx Command issued
2103
*                     - ETH_DMA_TransmitProcess_Fetching  : Running - fetching the Tx descriptor
2104
*                     - ETH_DMA_TransmitProcess_Waiting   : Running - waiting for status
2105
*                     - ETH_DMA_TransmitProcess_Reading   : unning - reading the data from host memory
2106
*                     - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
2107
*                     - ETH_DMA_TransmitProcess_Closing   : Running - closing Rx descriptor
2108
*******************************************************************************/
2109
u32 ETH_GetTransmitProcessState(void)
2110
{
2111
  return ((u32)(ETH_DMA->DMASR & ETH_DMASR_TS));
2112
}
2113
 
2114
/*******************************************************************************
2115
* Function Name  : ETH_GetDMAReceiveProcessState
2116
* Desciption     : Returns the ETHERNET DMA Receive Process State.
2117
* Input          : None
2118
* Output         : None
2119
* Return         : The new ETHERNET DMA Receive Process State:
2120
*                  This can be one of the following values:
2121
*                     - ETH_DMA_ReceiveProcess_Stopped   : Stopped - Reset or Stop Rx Command issued
2122
*                     - ETH_DMA_ReceiveProcess_Fetching  : Running - fetching the Rx descriptor
2123
*                     - ETH_DMA_ReceiveProcess_Waiting   : Running - waiting for packet
2124
*                     - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
2125
*                     - ETH_DMA_ReceiveProcess_Closing   : Running - closing descriptor
2126
*                     - ETH_DMA_ReceiveProcess_Queuing   : Running - queuing the recieve frame into host memory
2127
*******************************************************************************/
2128
u32 ETH_GetReceiveProcessState(void)
2129
{
2130
  return ((u32)(ETH_DMA->DMASR & ETH_DMASR_RS));
2131
}
2132
 
2133
/*******************************************************************************
2134
* Function Name  : ETH_FlushTransmitFIFO
2135
* Desciption     : Clears the ETHERNET transmit FIFO.
2136
* Input          : None
2137
* Output         : None
2138
* Return         : None
2139
*******************************************************************************/
2140
void ETH_FlushTransmitFIFO(void)
2141
{
2142
  /* Set the Flush Transmit FIFO bit */
2143
  ETH_DMA->DMAOMR |= ETH_DMAOMR_FTF;
2144
}
2145
 
2146
/*******************************************************************************
2147
* Function Name  : ETH_GetFlushTransmitFIFOStatus
2148
* Desciption     : Checks whether the ETHERNET transmit FIFO bit is cleared or not.
2149
* Input          : None
2150
* Output         : None
2151
* Return         : The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
2152
*******************************************************************************/
2153
FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
2154
{
2155
  FlagStatus bitstatus = RESET;
2156
 
2157
  if ((ETH_DMA->DMAOMR & ETH_DMAOMR_FTF) != (u32)RESET)
2158
  {
2159
    bitstatus = SET;
2160
  }
2161
  else
2162
  {
2163
    bitstatus = RESET;
2164
  }
2165
  return bitstatus;
2166
}
2167
 
2168
/*******************************************************************************
2169
* Function Name  : ETH_DMATransmissionCmd
2170
* Desciption     : Enables or disables the DMA transmission.
2171
* Input          : - NewState: new state of the DMA transmission.
2172
*                    This parameter can be: ENABLE or DISABLE.
2173
* Output         : None
2174
* Return         : None
2175
*******************************************************************************/
2176
void ETH_DMATransmissionCmd(FunctionalState NewState)
2177
{
2178
  /* Check the parameters */
2179
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2180
 
2181
  if (NewState != DISABLE)
2182
  {
2183
    /* Enable the DMA transmission */
2184
    ETH_DMA->DMAOMR |= ETH_DMAOMR_ST;
2185
  }
2186
  else
2187
  {
2188
    /* Disable the DMA transmission */
2189
    ETH_DMA->DMAOMR &= ~ETH_DMAOMR_ST;
2190
  }
2191
}
2192
 
2193
/*******************************************************************************
2194
* Function Name  : ETH_DMAReceptionCmd
2195
* Desciption     : Enables or disables the DMA reception.
2196
* Input          : - NewState: new state of the DMA reception.
2197
*                    This parameter can be: ENABLE or DISABLE.
2198
* Output         : None
2199
* Return         : None
2200
*******************************************************************************/
2201
void ETH_DMAReceptionCmd(FunctionalState NewState)
2202
{
2203
  /* Check the parameters */
2204
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2205
 
2206
  if (NewState != DISABLE)
2207
  {
2208
    /* Enable the DMA reception */
2209
    ETH_DMA->DMAOMR |= ETH_DMAOMR_SR;
2210
  }
2211
  else
2212
  {
2213
    /* Disable the DMA reception */
2214
    ETH_DMA->DMAOMR &= ~ETH_DMAOMR_SR;
2215
  }
2216
}
2217
 
2218
/*******************************************************************************
2219
* Function Name  : ETH_DMAITConfig
2220
* Desciption     : Enables or disables the specified ETHERNET DMA interrupts.
2221
* Input          : - ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
2222
*                    enabled or disabled.
2223
*                    This parameter can be any combination of the following values:
2224
*                       - ETH_DMA_IT_NIS : Normal interrupt summary
2225
*                       - ETH_DMA_IT_AIS : Abnormal interrupt summary
2226
*                       - ETH_DMA_IT_ER  : Early receive interrupt
2227
*                       - ETH_DMA_IT_FBE : Fatal bus error interrupt
2228
*                       - ETH_DMA_IT_ET  : Early transmit interrupt
2229
*                       - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
2230
*                       - ETH_DMA_IT_RPS : Receive process stopped interrupt
2231
*                       - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
2232
*                       - ETH_DMA_IT_R   : Receive interrupt
2233
*                       - ETH_DMA_IT_TU  : Underflow interrupt
2234
*                       - ETH_DMA_IT_RO  : Overflow interrupt
2235
*                       - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
2236
*                       - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
2237
*                       - ETH_DMA_IT_TPS : Transmit process stopped interrupt
2238
*                       - ETH_DMA_IT_T   : Transmit interrupt
2239
*                  - NewState: new state of the specified ETHERNET DMA interrupts.
2240
*                    This parameter can be: ENABLE or DISABLE.
2241
* Output         : None
2242
* Return         : None
2243
*******************************************************************************/
2244
void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState)
2245
{
2246
  /* Check the parameters */
2247
  eth_assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
2248
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2249
 
2250
  if (NewState != DISABLE)
2251
  {
2252
    /* Enable the selected ETHERNET DMA interrupts */
2253
    ETH_DMA->DMAIER |= ETH_DMA_IT;
2254
  }
2255
  else
2256
  {
2257
    /* Disable the selected ETHERNET DMA interrupts */
2258
    ETH_DMA->DMAIER &=(~(u32)ETH_DMA_IT);
2259
  }
2260
}
2261
 
2262
/*******************************************************************************
2263
* Function Name  : ETH_GetDMAOverflowStatus
2264
* Desciption     : Checks whether the specified ETHERNET DMA overflow flag is set or not.
2265
* Input          : - ETH_DMA_Overflow: specifies the DMA overflow flag to check.
2266
*                    This parameter can be one of the following values:
2267
*                       - ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter
2268
*                       - ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter
2269
* Output         : None
2270
* Return         : The new state of ETHERNET DMA overflow Flag (SET or RESET).
2271
*******************************************************************************/
2272
FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow)
2273
{
2274
  FlagStatus bitstatus = RESET;
2275
 
2276
  /* Check the parameters */
2277
  eth_assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
2278
 
2279
  if ((ETH_DMA->DMAMFBOCR & ETH_DMA_Overflow) != (u32)RESET)
2280
  {
2281
    bitstatus = SET;
2282
  }
2283
  else
2284
  {
2285
    bitstatus = RESET;
2286
  }
2287
  return bitstatus;
2288
}
2289
 
2290
/*******************************************************************************
2291
* Function Name  : ETH_GetRxOverflowMissedFrameCounter
2292
* Desciption     : Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
2293
* Input          : None
2294
* Output         : None
2295
* Return         : The value of Rx overflow Missed Frame Counter.
2296
*******************************************************************************/
2297
u32 ETH_GetRxOverflowMissedFrameCounter(void)
2298
{
2299
  return ((u32)((ETH_DMA->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift));
2300
}
2301
 
2302
/*******************************************************************************
2303
* Function Name  : ETH_GetBufferUnavailableMissedFrameCounter
2304
* Desciption     : Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
2305
* Input          : None
2306
* Output         : None
2307
* Return         : The value of Buffer unavailable Missed Frame Counter.
2308
*******************************************************************************/
2309
u32 ETH_GetBufferUnavailableMissedFrameCounter(void)
2310
{
2311
  return ((u32)(ETH_DMA->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
2312
}
2313
 
2314
/*******************************************************************************
2315
* Function Name  : ETH_GetCurrentTxDescStartAddress
2316
* Desciption     : Get the ETHERNET DMA DMACHTDR register value.
2317
* Input          : None
2318
* Output         : None
2319
* Return         : The value of the current Tx desc start address.
2320
*******************************************************************************/
2321
u32 ETH_GetCurrentTxDescStartAddress(void)
2322
{
2323
  return ((u32)(ETH_DMA->DMACHTDR));
2324
}
2325
 
2326
/*******************************************************************************
2327
* Function Name  : ETH_GetCurrentRxDescStartAddress
2328
* Desciption     : Get the ETHERNET DMA DMACHRDR register value.
2329
* Input          : None
2330
* Output         : None
2331
* Return         : The value of the current Rx desc start address.
2332
*******************************************************************************/
2333
u32 ETH_GetCurrentRxDescStartAddress(void)
2334
{
2335
  return ((u32)(ETH_DMA->DMACHRDR));
2336
}
2337
 
2338
/*******************************************************************************
2339
* Function Name  : ETH_GetCurrentTxBufferAddress
2340
* Desciption     : Get the ETHERNET DMA DMACHTBAR register value.
2341
* Input          : None
2342
* Output         : None
2343
* Return         : The value of the current Tx desc buffer address.
2344
*******************************************************************************/
2345
u32 ETH_GetCurrentTxBufferAddress(void)
2346
{
2347
  return ((u32)(ETH_DMA->DMACHTBAR));
2348
}
2349
 
2350
/*******************************************************************************
2351
* Function Name  : ETH_GetCurrentRxBufferAddress
2352
* Desciption     : Get the ETHERNET DMA DMACHRBAR register value.
2353
* Input          : None
2354
* Output         : None
2355
* Return         : The value of the current Rx desc buffer address.
2356
*******************************************************************************/
2357
u32 ETH_GetCurrentRxBufferAddress(void)
2358
{
2359
  return ((u32)(ETH_DMA->DMACHRBAR));
2360
}
2361
 
2362
/*******************************************************************************
2363
* Function Name  : ETH_ResumeDMATransmission
2364
* Desciption     : Resumes the DMA Transmission by writing to the DmaTxPollDemand
2365
*                  register: (the data written could be anything). This forces
2366
*                  the DMA to resume transmission.
2367
* Input          : None
2368
* Output         : None
2369
* Return         : None.
2370
*******************************************************************************/
2371
void ETH_ResumeDMATransmission(void)
2372
{
2373
  ETH_DMA->DMATPDR = 0;
2374
}
2375
 
2376
/*******************************************************************************
2377
* Function Name  : ETH_ResumeDMAReception
2378
* Desciption     : Resumes the DMA Transmission by writing to the DmaRxPollDemand
2379
*                  register: (the data written could be anything). This forces
2380
*                  the DMA to resume reception.
2381
* Input          : None
2382
* Output         : None
2383
* Return         : None.
2384
*******************************************************************************/
2385
void ETH_ResumeDMAReception(void)
2386
{
2387
  ETH_DMA->DMARPDR = 0;
2388
}
2389
 
2390
#endif /* _ETH_DMA */
2391
/*---------------------------------  PMT  ------------------------------------*/
2392
/*******************************************************************************
2393
* Function Name  : ETH_ResetWakeUpFrameFilterRegisterPointer
2394
* Desciption     : Reset Wakeup frame filter register pointer.
2395
* Input          : None
2396
* Output         : None
2397
* Return         : None
2398
*******************************************************************************/
2399
void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
2400
{
2401
  /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
2402
  ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
2403
}
2404
 
2405
/*******************************************************************************
2406
* Function Name  : ETH_SetWakeUpFrameFilterRegister
2407
* Desciption     : Populates the remote wakeup frame registers.
2408
* Input          : - Buffer: Pointer on remote WakeUp Frame Filter Register buffer
2409
*                    data (8 words).
2410
* Output         : None
2411
* Return         : None
2412
*******************************************************************************/
2413
void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer)
2414
{
2415
  u32 i = 0;
2416
 
2417
  /* Fill Remote Wake-up Frame Filter register with Buffer data */
2418
  for(i =0; i<ETH_WakeupRegisterLength; i++)
2419
  {
2420
    /* Write each time to the same register */
2421
    ETH_MAC->MACRWUFFR = Buffer[i];
2422
  }
2423
}
2424
 
2425
/*******************************************************************************
2426
* Function Name  : ETH_GlobalUnicastWakeUpCmd
2427
* Desciption     : Enables or disables any unicast packet filtered by the MAC
2428
*                 (DAF) address recognition to be a wake-up frame.
2429
* Input          : - NewState: new state of the MAC Global Unicast Wake-Up.
2430
*                    This parameter can be: ENABLE or DISABLE.
2431
* Output         : None
2432
* Return         : None
2433
*******************************************************************************/
2434
void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
2435
{
2436
  /* Check the parameters */
2437
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2438
 
2439
  if (NewState != DISABLE)
2440
  {
2441
    /* Enable the MAC Global Unicast Wake-Up */
2442
    ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_GU;
2443
  }
2444
  else
2445
  {
2446
    /* Disable the MAC Global Unicast Wake-Up */
2447
    ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
2448
  }
2449
}
2450
 
2451
/*******************************************************************************
2452
* Function Name  : ETH_GetPMTFlagStatus
2453
* Desciption     : Checks whether the specified ETHERNET PMT flag is set or not.
2454
* Input          : - ETH_PMT_FLAG: specifies the flag to check.
2455
*                    This parameter can be one of the following values:
2456
*                       - ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset
2457
*                       - ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received
2458
*                       - ETH_PMT_FLAG_MPR     : Magic Packet Received
2459
* Output         : None
2460
* Return         : The new state of ETHERNET PMT Flag (SET or RESET).
2461
*******************************************************************************/
2462
FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG)
2463
{
2464
  FlagStatus bitstatus = RESET;
2465
 
2466
  /* Check the parameters */
2467
  eth_assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
2468
 
2469
  if ((ETH_MAC->MACPMTCSR & ETH_PMT_FLAG) != (u32)RESET)
2470
  {
2471
    bitstatus = SET;
2472
  }
2473
  else
2474
  {
2475
    bitstatus = RESET;
2476
  }
2477
  return bitstatus;
2478
}
2479
 
2480
/*******************************************************************************
2481
* Function Name  : ETH_WakeUpFrameDetectionCmd
2482
* Desciption     : Enables or disables the MAC Wake-Up Frame Detection.
2483
* Input          : - NewState: new state of the MAC Wake-Up Frame Detection.
2484
*                    This parameter can be: ENABLE or DISABLE.
2485
* Output         : None
2486
* Return         : None
2487
*******************************************************************************/
2488
void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
2489
{
2490
  /* Check the parameters */
2491
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2492
 
2493
  if (NewState != DISABLE)
2494
  {
2495
    /* Enable the MAC Wake-Up Frame Detection */
2496
    ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_WFE;
2497
  }
2498
  else
2499
  {
2500
    /* Disable the MAC Wake-Up Frame Detection */
2501
    ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
2502
  }
2503
}
2504
 
2505
/*******************************************************************************
2506
* Function Name  : ETH_MagicPacketDetectionCmd
2507
* Desciption     : Enables or disables the MAC Magic Packet Detection.
2508
* Input          : - NewState: new state of the MAC Magic Packet Detection.
2509
*                    This parameter can be: ENABLE or DISABLE.
2510
* Output         : None
2511
* Return         : None
2512
*******************************************************************************/
2513
void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
2514
{
2515
  /* Check the parameters */
2516
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2517
 
2518
  if (NewState != DISABLE)
2519
  {
2520
    /* Enable the MAC Magic Packet Detection */
2521
    ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_MPE;
2522
  }
2523
  else
2524
  {
2525
    /* Disable the MAC Magic Packet Detection */
2526
    ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
2527
  }
2528
}
2529
 
2530
/*******************************************************************************
2531
* Function Name  : ETH_PowerDownCmd
2532
* Desciption     : Enables or disables the MAC Power Down.
2533
* Input          : - NewState: new state of the MAC Power Down.
2534
*                    This parameter can be: ENABLE or DISABLE.
2535
* Output         : None
2536
* Return         : None
2537
*******************************************************************************/
2538
void ETH_PowerDownCmd(FunctionalState NewState)
2539
{
2540
  /* Check the parameters */
2541
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2542
 
2543
  if (NewState != DISABLE)
2544
  {
2545
    /* Enable the MAC Power Down */
2546
    /* This puts the MAC in power down mode */
2547
    ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_PD;
2548
  }
2549
  else
2550
  {
2551
    /* Disable the MAC Power Down */
2552
    ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
2553
  }
2554
}
2555
 
2556
/*---------------------------------  MMC  ------------------------------------*/
2557
#ifdef _ETH_MMC
2558
 
2559
/*******************************************************************************
2560
* Function Name  : ETH_MMCCounterFreezeCmd
2561
* Desciption     : Enables or disables the MMC Counter Freeze.
2562
* Input          : - NewState: new state of the MMC Counter Freeze.
2563
*                    This parameter can be: ENABLE or DISABLE.
2564
* Output         : None
2565
* Return         : None
2566
*******************************************************************************/
2567
void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
2568
{
2569
  /* Check the parameters */
2570
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2571
 
2572
  if (NewState != DISABLE)
2573
  {
2574
    /* Enable the MMC Counter Freeze */
2575
    ETH_MMC->MMCCR |= ETH_MMCCR_MCF;
2576
  }
2577
  else
2578
  {
2579
    /* Disable the MMC Counter Freeze */
2580
    ETH_MMC->MMCCR &= ~ETH_MMCCR_MCF;
2581
  }
2582
}
2583
 
2584
/*******************************************************************************
2585
* Function Name  : ETH_MMCResetOnReadCmd
2586
* Desciption     : Enables or disables the MMC Reset On Read.
2587
* Input          : - NewState: new state of the MMC Reset On Read.
2588
*                    This parameter can be: ENABLE or DISABLE.
2589
* Output         : None
2590
* Return         : None
2591
*******************************************************************************/
2592
void ETH_MMCResetOnReadCmd(FunctionalState NewState)
2593
{
2594
  /* Check the parameters */
2595
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2596
 
2597
  if (NewState != DISABLE)
2598
  {
2599
    /* Enable the MMC Counter reset on read */
2600
    ETH_MMC->MMCCR |= ETH_MMCCR_ROR;
2601
  }
2602
  else
2603
  {
2604
    /* Disable the MMC Counter reset on read */
2605
    ETH_MMC->MMCCR &= ~ETH_MMCCR_ROR;
2606
  }
2607
}
2608
 
2609
/*******************************************************************************
2610
* Function Name  : ETH_MMCCounterRolloverCmd
2611
* Desciption     : Enables or disables the MMC Counter Stop Rollover.
2612
* Input          : - NewState: new state of the MMC Counter Stop Rollover.
2613
*                    This parameter can be: ENABLE or DISABLE.
2614
* Output         : None
2615
* Return         : None
2616
*******************************************************************************/
2617
void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
2618
{
2619
  /* Check the parameters */
2620
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2621
 
2622
  if (NewState != DISABLE)
2623
  {
2624
    /* Disable the MMC Counter Stop Rollover  */
2625
    ETH_MMC->MMCCR &= ~ETH_MMCCR_CSR;
2626
  }
2627
  else
2628
  {
2629
    /* Enable the MMC Counter Stop Rollover */
2630
    ETH_MMC->MMCCR |= ETH_MMCCR_CSR;
2631
  }
2632
}
2633
 
2634
/*******************************************************************************
2635
* Function Name  : ETH_MMCCountersReset
2636
* Desciption     : Resets the MMC Counters.
2637
* Input          : None
2638
* Output         : None
2639
* Return         : None
2640
*******************************************************************************/
2641
void ETH_MMCCountersReset(void)
2642
{
2643
  /* Resets the MMC Counters */
2644
  ETH_MMC->MMCCR |= ETH_MMCCR_CR;
2645
}
2646
 
2647
/*******************************************************************************
2648
* Function Name  : ETH_MMCITConfig
2649
* Desciption     : Enables or disables the specified ETHERNET MMC interrupts.
2650
* Input          : - ETH_MMC_IT: specifies the ETHERNET MMC interrupt
2651
*                    sources to be enabled or disabled.
2652
*                    This parameter can be any combination of Tx interrupt or
2653
*                    any combination of Rx interrupt (but not both)of the following values:
2654
*                       - ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
2655
*                       - ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2656
*                       - ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2657
*                       - ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
2658
*                       - ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
2659
*                       - ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
2660
*                  - NewState: new state of the specified ETHERNET MMC interrupts.
2661
*                    This parameter can be: ENABLE or DISABLE.
2662
* Output         : None
2663
* Return         : None
2664
*******************************************************************************/
2665
void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState)
2666
{
2667
  /* Check the parameters */
2668
  eth_assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));
2669
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2670
 
2671
  if ((ETH_MMC_IT & (u32)0x10000000) != (u32)RESET)
2672
  {
2673
    /* Remove egister mak from IT */
2674
    ETH_MMC_IT &= 0xEFFFFFFF;
2675
 
2676
    /* ETHERNET MMC Rx interrupts selected */
2677
    if (NewState != DISABLE)
2678
    {
2679
      /* Enable the selected ETHERNET MMC interrupts */
2680
      ETH_MMC->MMCRIMR &=(~(u32)ETH_MMC_IT);
2681
    }
2682
    else
2683
    {
2684
      /* Disable the selected ETHERNET MMC interrupts */
2685
      ETH_MMC->MMCRIMR |= ETH_MMC_IT;
2686
    }
2687
  }
2688
  else
2689
  {
2690
    /* ETHERNET MMC Tx interrupts selected */
2691
    if (NewState != DISABLE)
2692
    {
2693
      /* Enable the selected ETHERNET MMC interrupts */
2694
      ETH_MMC->MMCTIMR &=(~(u32)ETH_MMC_IT);
2695
    }
2696
    else
2697
    {
2698
      /* Disable the selected ETHERNET MMC interrupts */
2699
      ETH_MMC->MMCTIMR |= ETH_MMC_IT;
2700
    }
2701
  }
2702
}
2703
 
2704
/*******************************************************************************
2705
* Function Name  : ETH_GetMMCITStatus
2706
* Desciption     : Checks whether the specified ETHERNET MMC IT is set or not.
2707
* Input          : - ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
2708
*                    This parameter can be one of the following values:
2709
*                       - ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value
2710
*                       - ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value
2711
*                       - ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value
2712
*                       - ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value
2713
*                       - ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value
2714
*                       - ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value
2715
* Output         : None
2716
* Return         : The value of ETHERNET MMC IT (SET or RESET).
2717
*******************************************************************************/
2718
ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT)
2719
{
2720
  ITStatus bitstatus = RESET;
2721
 
2722
  /* Check the parameters */
2723
  eth_assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT));
2724
 
2725
  if ((ETH_MMC_IT & (u32)0x10000000) != (u32)RESET)
2726
  {
2727
    /* ETHERNET MMC Rx interrupts selected */
2728
    /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */
2729
    if ((((ETH_MMC->MMCRIR & ETH_MMC_IT) != (u32)RESET)) && ((ETH_MMC->MMCRIMR & ETH_MMC_IT) != (u32)RESET))
2730
    {
2731
      bitstatus = SET;
2732
    }
2733
    else
2734
    {
2735
      bitstatus = RESET;
2736
    }
2737
  }
2738
  else
2739
  {
2740
    /* ETHERNET MMC Tx interrupts selected */
2741
    /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */
2742
    if ((((ETH_MMC->MMCTIR & ETH_MMC_IT) != (u32)RESET)) && ((ETH_MMC->MMCRIMR & ETH_MMC_IT) != (u32)RESET))
2743
    {
2744
      bitstatus = SET;
2745
    }
2746
    else
2747
    {
2748
      bitstatus = RESET;
2749
    }
2750
  }
2751
 
2752
  return bitstatus;
2753
}
2754
 
2755
/*******************************************************************************
2756
* Function Name  : ETH_GetMMCRegister
2757
* Desciption     : Get the specified ETHERNET MMC register value.
2758
* Input          : - ETH_MMCReg: specifies the ETHERNET MMC register.
2759
*                    This parameter can be one of the following values:
2760
*                       - ETH_MMCCR      : MMC CR register
2761
*                       - ETH_MMCRIR     : MMC RIR register
2762
*                       - ETH_MMCTIR     : MMC TIR register
2763
*                       - ETH_MMCRIMR    : MMC RIMR register
2764
*                       - ETH_MMCTIMR    : MMC TIMR register
2765
*                       - ETH_MMCTGFSCCR : MMC TGFSCCR register
2766
*                       - ETH_MMCTGFMSCCR: MMC TGFMSCCR register
2767
*                       - ETH_MMCTGFCR   : MMC TGFCR register
2768
*                       - ETH_MMCRFCECR  : MMC RFCECR register
2769
*                       - ETH_MMCRFAECR  : MMC RFAECR register
2770
*                       - ETH_MMCRGUFCR  : MMC RGUFCRregister
2771
* Output         : None
2772
* Return         : The value of ETHERNET MMC Register value.
2773
*******************************************************************************/
2774
u32 ETH_GetMMCRegister(u32 ETH_MMCReg)
2775
{
2776
  /* Check the parameters */
2777
  eth_assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
2778
 
2779
  /* Return the selected register value */
2780
  return (*(vu32 *)(ETH_MAC_BASE + ETH_MMCReg));
2781
}
2782
#endif /* _ETH_MMC */
2783
 
2784
/*---------------------------------  PTP  ------------------------------------*/
2785
#ifdef _ETH_PTP
2786
 
2787
/*******************************************************************************
2788
* Function Name  : ETH_EnablePTPTimeStampAddend
2789
* Desciption     : Updated the PTP block for fine correction with the Time Stamp
2790
*                  Addend register value.
2791
* Input          : None
2792
* Output         : None
2793
* Return         : None
2794
*******************************************************************************/
2795
void ETH_EnablePTPTimeStampAddend(void)
2796
{
2797
  /* Enable the PTP block update with the Time Stamp Addend register value */
2798
  ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSARU;
2799
}
2800
 
2801
/*******************************************************************************
2802
* Function Name  : ETH_EnablePTPTimeStampInterruptTrigger
2803
* Desciption     : Enable the PTP Time Stamp interrupt trigger
2804
* Input          : None
2805
* Output         : None
2806
* Return         : None
2807
*******************************************************************************/
2808
void ETH_EnablePTPTimeStampInterruptTrigger(void)
2809
{
2810
  /* Enable the PTP target time interrupt */
2811
  ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSITE;
2812
}
2813
 
2814
/*******************************************************************************
2815
* Function Name  : ETH_EnablePTPTimeStampUpdate
2816
* Desciption     : Updated the PTP system time with the Time Stamp Update register
2817
*                  value.
2818
* Input          : None
2819
* Output         : None
2820
* Return         : None
2821
*******************************************************************************/
2822
void ETH_EnablePTPTimeStampUpdate(void)
2823
{
2824
  /* Enable the PTP system time update with the Time Stamp Update register value */
2825
  ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSSTU;
2826
}
2827
 
2828
/*******************************************************************************
2829
* Function Name  : ETH_InitializePTPTimeStamp
2830
* Desciption     : Initialize the PTP Time Stamp
2831
* Input          : None
2832
* Output         : None
2833
* Return         : None
2834
*******************************************************************************/
2835
void ETH_InitializePTPTimeStamp(void)
2836
{
2837
  /* Initialize the PTP Time Stamp */
2838
  ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSSTI;
2839
}
2840
 
2841
/*******************************************************************************
2842
* Function Name  : ETH_PTPUpdateMethodConfig
2843
* Desciption     : Selects the PTP Update method
2844
* Input          : - UpdateMethod: the PTP Update method
2845
*                    This parameter can be one of the following values:
2846
*                       - ETH_PTP_FineUpdate   : Fine Update method
2847
*                       - ETH_PTP_CoarseUpdate : Coarse Update method
2848
* Output         : None
2849
* Return         : None
2850
*******************************************************************************/
2851
void ETH_PTPUpdateMethodConfig(u32 UpdateMethod)
2852
{
2853
  /* Check the parameters */
2854
  eth_assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));
2855
 
2856
  if (UpdateMethod != ETH_PTP_CoarseUpdate)
2857
  {
2858
    /* Enable the PTP Fine Update method */
2859
    ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSFCU;
2860
  }
2861
  else
2862
  {
2863
    /* Disable the PTP Coarse Update method */
2864
    ETH_PTP->PTPTSCR &= (~(u32)ETH_PTPTSCR_TSFCU);
2865
  }
2866
}
2867
 
2868
/*******************************************************************************
2869
* Function Name  : ETH_PTPTimeStampCmd
2870
* Desciption     : Enables or disables the PTP time stamp for transmit and receive frames.
2871
* Input          : - NewState: new state of the PTP time stamp for transmit and receive frames
2872
*                    This parameter can be: ENABLE or DISABLE.
2873
* Output         : None
2874
* Return         : None
2875
*******************************************************************************/
2876
void ETH_PTPTimeStampCmd(FunctionalState NewState)
2877
{
2878
  /* Check the parameters */
2879
  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
2880
 
2881
  if (NewState != DISABLE)
2882
  {
2883
    /* Enable the PTP time stamp for transmit and receive frames */
2884
    ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSE;
2885
  }
2886
  else
2887
  {
2888
    /* Disable the PTP time stamp for transmit and receive frames */
2889
    ETH_PTP->PTPTSCR &= (~(u32)ETH_PTPTSCR_TSE);
2890
  }
2891
}
2892
 
2893
/*******************************************************************************
2894
* Function Name  : ETH_GetPTPFlagStatus
2895
* Desciption     : Checks whether the specified ETHERNET PTP flag is set or not.
2896
* Input          : - ETH_PTP_FLAG: specifies the flag to check.
2897
*                    This parameter can be one of the following values:
2898
*                       - ETH_PTP_FLAG_TSARU : Addend Register Update
2899
*                       - ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable
2900
*                       - ETH_PTP_FLAG_TSSTU : Time Stamp Update
2901
*                       - ETH_PTP_FLAG_TSSTI  : Time Stamp Initialize
2902
* Output         : None
2903
* Return         : The new state of ETHERNET PTP Flag (SET or RESET).
2904
*******************************************************************************/
2905
FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG)
2906
{
2907
  FlagStatus bitstatus = RESET;
2908
 
2909
  /* Check the parameters */
2910
  eth_assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));
2911
 
2912
  if ((ETH_PTP->PTPTSCR & ETH_PTP_FLAG) != (u32)RESET)
2913
  {
2914
    bitstatus = SET;
2915
  }
2916
  else
2917
  {
2918
    bitstatus = RESET;
2919
  }
2920
  return bitstatus;
2921
}
2922
 
2923
/*******************************************************************************
2924
* Function Name  : ETH_SetPTPSubSecondIncrement
2925
* Desciption     : Sets the system time Sub-Second Increment value.
2926
* Input          : - SubSecondValue: specifies the PTP Sub-Second Increment Register value.
2927
* Output         : None
2928
* Return         : None
2929
*******************************************************************************/
2930
void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue)
2931
{
2932
  /* Check the parameters */
2933
  eth_assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));
2934
 
2935
  /* Set the PTP Sub-Second Increment Register */
2936
  ETH_PTP->PTPSSIR = SubSecondValue;
2937
}
2938
 
2939
/*******************************************************************************
2940
* Function Name  : ETH_SetPTPTimeStampUpdate
2941
* Desciption     : Sets the Time Stamp update sign and values.
2942
* Input          : - Sign: specifies the PTP Time update value sign.
2943
*                    This parameter can be one of the following values:
2944
*                       - ETH_PTP_PositiveTime : positive time value.
2945
*                       - ETH_PTP_NegativeTime : negative time value.
2946
*                  - SecondValue: specifies the PTP Time update second value.
2947
*                  - SubSecondValue: specifies the PTP Time update sub-second value.
2948
*                    this is a 31 bit value. bit32 correspond to the sign.
2949
* Output         : None
2950
* Return         : None
2951
*******************************************************************************/
2952
void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue)
2953
{
2954
  /* Check the parameters */
2955
  eth_assert_param(IS_ETH_PTP_TIME_SIGN(Sign));
2956
  eth_assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue));
2957
 
2958
  /* Set the PTP Time Update High Register */
2959
  ETH_PTP->PTPTSHUR = SecondValue;
2960
 
2961
  /* Set the PTP Time Update Low Register with sign */
2962
  ETH_PTP->PTPTSLUR = Sign | SubSecondValue;
2963
}
2964
 
2965
/*******************************************************************************
2966
* Function Name  : ETH_SetPTPTimeStampAddend
2967
* Desciption     : Sets the Time Stamp Addend value.
2968
* Input          : - Value: specifies the PTP Time Stamp Addend Register value.
2969
* Output         : None
2970
* Return         : None
2971
*******************************************************************************/
2972
void ETH_SetPTPTimeStampAddend(u32 Value)
2973
{
2974
  /* Set the PTP Time Stamp Addend Register */
2975
  ETH_PTP->PTPTSAR = Value;
2976
}
2977
 
2978
/*******************************************************************************
2979
* Function Name  : ETH_SetPTPTargetTime
2980
* Desciption     : Sets the Target Time registers values.
2981
* Input          : - HighValue: specifies the PTP Target Time High Register value.
2982
*                  - LowValue: specifies the PTP Target Time Low Register value.
2983
* Output         : None
2984
* Return         : None
2985
*******************************************************************************/
2986
void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue)
2987
{
2988
  /* Set the PTP Target Time High Register */
2989
  ETH_PTP->PTPTTHR = HighValue;
2990
  /* Set the PTP Target Time Low Register */
2991
  ETH_PTP->PTPTTLR = LowValue;
2992
}
2993
 
2994
/*******************************************************************************
2995
* Function Name  : ETH_GetPTPRegister
2996
* Desciption     : Get the specified ETHERNET PTP register value.
2997
* Input          : - ETH_PTPReg: specifies the ETHERNET PTP register.
2998
*                    This parameter can be one of the following values:
2999
*                       - ETH_PTPTSCR  : Sub-Second Increment Register
3000
*                       - ETH_PTPSSIR  : Sub-Second Increment Register
3001
*                       - ETH_PTPTSHR  : Time Stamp High Register
3002
*                       - ETH_PTPTSLR  : Time Stamp Low Register
3003
*                       - ETH_PTPTSHUR : Time Stamp High Update Register
3004
*                       - ETH_PTPTSLUR : Time Stamp Low Update Register
3005
*                       - ETH_PTPTSAR  : Time Stamp Addend Register
3006
*                       - ETH_PTPTTHR  : Target Time High Register
3007
*                       - ETH_PTPTTLR  : Target Time Low Register
3008
* Output         : None
3009
* Return         : The value of ETHERNET PTP Register value.
3010
*******************************************************************************/
3011
u32 ETH_GetPTPRegister(u32 ETH_PTPReg)
3012
{
3013
  /* Check the parameters */
3014
  eth_assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));
3015
 
3016
  /* Return the selected register value */
3017
  return (*(vu32 *)(ETH_MAC_BASE + ETH_PTPReg));
3018
}
3019
 
3020
/*******************************************************************************
3021
* Function Name  : ETH_DMAPTPTxDescChainInit
3022
* Desciption     : Initializes the DMA Tx descriptors in chain mode with PTP.
3023
* Input          : - DMATxDescTab: Pointer on the first Tx desc list
3024
*                  - DMAPTPTxDescTab: Pointer on the first PTP Tx desc list
3025
*                  - TxBuff: Pointer on the first TxBuffer list
3026
*                  - TxBuffCount: Number of the used Tx desc in the list
3027
* Output         : None
3028
* Return         : None
3029
*******************************************************************************/
3030
void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount)
3031
{
3032
  u32 i = 0;
3033
  ETH_DMADESCTypeDef *DMATxDesc;
3034
 
3035
  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
3036
  DMATxDescToSet = DMATxDescTab;
3037
  DMAPTPTxDescToSet = DMAPTPTxDescTab;
3038
 
3039
  /* Fill each DMATxDesc descriptor with the right values */
3040
  for(i=0; i < TxBuffCount; i++)
3041
  {
3042
    /* Get the pointer on the ith member of the Tx Desc list */
3043
    DMATxDesc = DMATxDescTab+i;
3044
 
3045
    /* Set Second Address Chained bit and enable PTP */
3046
    DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;
3047
 
3048
    /* Set Buffer1 address pointer */
3049
    DMATxDesc->Buffer1Addr =(u32)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
3050
 
3051
    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
3052
    if(i < (TxBuffCount-1))
3053
    {
3054
      /* Set next descriptor address register with next descriptor base address */
3055
      DMATxDesc->Buffer2NextDescAddr = (u32)(DMATxDescTab+i+1);
3056
    }
3057
    else
3058
    {
3059
      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
3060
      DMATxDesc->Buffer2NextDescAddr = (u32) DMATxDescTab;
3061
    }
3062
 
3063
        /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */
3064
        (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;
3065
        (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
3066
  }
3067
 
3068
  /* Store on the last DMAPTPTxDescTab desc status record the first list address */
3069
  (&DMAPTPTxDescTab[i-1])->Status = (u32) DMAPTPTxDescTab;
3070
 
3071
  /* Set Transmit Desciptor List Address Register */
3072
  ETH_DMA->DMATDLAR = (u32) DMATxDescTab;
3073
}
3074
 
3075
/*******************************************************************************
3076
* Function Name  : ETH_DMAPTPRxDescChainInit
3077
* Desciption     : Initializes the DMA Rx descriptors in chain mode.
3078
* Input          : - DMARxDescTab: Pointer on the first Rx desc list
3079
*                  - DMAPTPRxDescTab: Pointer on the first PTP Rx desc list
3080
*                  - RxBuff: Pointer on the first RxBuffer list
3081
*                  - RxBuffCount: Number of the used Rx desc in the list
3082
* Output         : None
3083
* Return         : None
3084
*******************************************************************************/
3085
void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount)
3086
{
3087
  u32 i = 0;
3088
  ETH_DMADESCTypeDef *DMARxDesc;
3089
 
3090
  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
3091
  DMARxDescToGet = DMARxDescTab;
3092
  DMAPTPRxDescToGet = DMAPTPRxDescTab;
3093
 
3094
  /* Fill each DMARxDesc descriptor with the right values */
3095
  for(i=0; i < RxBuffCount; i++)
3096
  {
3097
    /* Get the pointer on the ith member of the Rx Desc list */
3098
    DMARxDesc = DMARxDescTab+i;
3099
 
3100
    /* Set Own bit of the Rx descriptor Status */
3101
    DMARxDesc->Status = ETH_DMARxDesc_OWN;
3102
 
3103
    /* Set Buffer1 size and Second Address Chained bit */
3104
    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (u32)ETH_MAX_PACKET_SIZE;
3105
 
3106
    /* Set Buffer1 address pointer */
3107
    DMARxDesc->Buffer1Addr = (u32)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
3108
 
3109
    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
3110
    if(i < (RxBuffCount-1))
3111
    {
3112
      /* Set next descriptor address register with next descriptor base address */
3113
      DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab+i+1);
3114
    }
3115
    else
3116
    {
3117
      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
3118
      DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab);
3119
    }
3120
 
3121
        /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */
3122
        (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;
3123
        (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
3124
  }
3125
 
3126
  /* Store on the last DMAPTPRxDescTab desc status record the first list address */
3127
  (&DMAPTPRxDescTab[i-1])->Status = (u32) DMAPTPRxDescTab;
3128
 
3129
  /* Set Receive Desciptor List Address Register */
3130
  ETH_DMA->DMARDLAR = (u32) DMARxDescTab;
3131
}
3132
 
3133
/*******************************************************************************
3134
* Function Name  : ETH_HandlePTPTxPkt
3135
* Desciption     : Transmits a packet, from application buffer, pointed by ppkt with
3136
*                  Time Stamp values.
3137
* Input          : - ppkt: pointer to application packet Buffer.
3138
*                  - FrameLength: Tx Packet size.
3139
*                  - PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.
3140
* Output         : None
3141
* Return         : ETH_ERROR: in case of Tx desc owned by DMA
3142
*                  ETH_SUCCESS: for correct transmission
3143
*******************************************************************************/
3144
u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab)
3145
{
3146
  u32 offset = 0, timeout = 0;
3147
 
3148
  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
3149
  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
3150
  {
3151
    /* Return ERROR: OWN bit set */
3152
    return ETH_ERROR;
3153
  }
3154
 
3155
  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
3156
  for(offset=0; offset<FrameLength; offset++)
3157
  {
3158
    (*(vu8 *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
3159
  }
3160
 
3161
  /* Setting the Frame Length: bits[12:0] */
3162
  DMATxDescToSet->ControlBufferSize = (FrameLength & (u32)0x1FFF);
3163
 
3164
  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
3165
  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
3166
 
3167
  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
3168
  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
3169
 
3170
  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
3171
  if ((ETH_DMA->DMASR & ETH_DMASR_TBUS) != (u32)RESET)
3172
  {
3173
    /* Clear TBUS ETHERNET DMA flag */
3174
    ETH_DMA->DMASR = ETH_DMASR_TBUS;
3175
    /* Resume DMA transmission*/
3176
    ETH_DMA->DMATPDR = 0;
3177
  }
3178
 
3179
  /* Wait for ETH_DMATxDesc_TTSS flag to be set */
3180
  do
3181
  {
3182
    timeout++;
3183
  } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
3184
 
3185
  /* Return ERROR in case of timeout */
3186
  if(timeout == PHY_READ_TO)
3187
  {
3188
    return ETH_ERROR;
3189
  }
3190
 
3191
  *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;
3192
  *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;
3193
 
3194
  /* Update the ENET DMA current descriptor */
3195
  /* Chained Mode */
3196
  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (u32)RESET)
3197
  {
3198
    /* Selects the next DMA Tx descriptor list for next buffer read */
3199
    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);
3200
 
3201
    if(DMAPTPTxDescToSet->Status != 0)
3202
    {
3203
      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);
3204
    }
3205
    else
3206
    {
3207
      DMAPTPTxDescToSet++;
3208
    }
3209
  }
3210
  else /* Ring Mode */
3211
  {
3212
    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (u32)RESET)
3213
    {
3214
      /* Selects the next DMA Tx descriptor list for next buffer read: this will
3215
         be the first Tx descriptor in this case */
3216
      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);
3217
      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);
3218
    }
3219
    else
3220
    {
3221
      /* Selects the next DMA Tx descriptor list for next buffer read */
3222
      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMATxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
3223
      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMAPTPTxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
3224
    }
3225
  }
3226
 
3227
  /* Return SUCCESS */
3228
  return ETH_SUCCESS;
3229
}
3230
 
3231
/*******************************************************************************
3232
* Function Name  : ETH_HandlePTPRxPkt
3233
* Desciption     : Receives a packet and copies it to memory pointed by ppkt with
3234
*                 Time Stamp values.
3235
* Input          : - PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.
3236
* Output         : ppkt: pointer on application receive buffer.
3237
* Return         : ETH_ERROR: if there is error in reception
3238
*                  Received packet size: if packet reception is correct
3239
*******************************************************************************/
3240
u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab)
3241
{
3242
  u32 offset = 0, FrameLength = 0;
3243
 
3244
  /* Check if the descriptor is owned by the ENET or CPU */
3245
  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET)
3246
  {
3247
    /* Return error: OWN bit set */
3248
    return ETH_ERROR;
3249
  }
3250
 
3251
  if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (u32)RESET) &&
3252
     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (u32)RESET) &&
3253
     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (u32)RESET))
3254
  {
3255
    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
3256
    FrameLength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
3257
 
3258
    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
3259
    for(offset=0; offset<FrameLength; offset++)
3260
    {
3261
      (*(ppkt + offset)) = (*(vu8 *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));
3262
    }
3263
  }
3264
  else
3265
  {
3266
    /* Return ERROR */
3267
    FrameLength = ETH_ERROR;
3268
  }
3269
 
3270
  /* When Rx Buffer unavailable flag is set: clear it and resume reception */
3271
  if ((ETH_DMA->DMASR & ETH_DMASR_RBUS) != (u32)RESET)
3272
  {
3273
    /* Clear RBUS ETHERNET DMA flag */
3274
    ETH_DMA->DMASR = ETH_DMASR_RBUS;
3275
    /* Resume DMA reception */
3276
    ETH_DMA->DMARPDR = 0;
3277
  }
3278
 
3279
  *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;
3280
  *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;
3281
 
3282
  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
3283
  DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;
3284
 
3285
  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
3286
  /* Chained Mode */
3287
  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)
3288
  {
3289
    /* Selects the next DMA Rx descriptor list for next buffer read */
3290
    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);
3291
 
3292
    if(DMAPTPRxDescToGet->Status != 0)
3293
    {
3294
      DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);
3295
    }
3296
    else
3297
    {
3298
      DMAPTPRxDescToGet++;
3299
    }
3300
  }
3301
  else /* Ring Mode */
3302
  {
3303
    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)
3304
    {
3305
      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
3306
      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);
3307
    }
3308
    else
3309
    {
3310
      /* Selects the next DMA Rx descriptor list for next buffer to read */
3311
      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
3312
    }
3313
  }
3314
 
3315
  /* Return Frame Length/ERROR */
3316
  return (FrameLength);
3317
}
3318
 
3319
#endif /* _ETH_PTP */
3320
 
3321
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

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