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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [ethernet/] [lwIP_130/] [contrib/] [port/] [FreeRTOS/] [ColdFire/] [fec.h] - Blame information for rev 606

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/*
 * File:    fec.h
 * Purpose: Driver for the Fast Ethernet Controller (FEC)
 *
 * Notes:
 */
 
#ifndef _FEC_H_
#define _FEC_H_
 
#include "eth.h"
#include "fecbd.h"
#include "mii.h"
#include "eth_phy.h"
 
/********************************************************************/
 
/* External Interface Modes */
#define FEC_MODE_7WIRE          0   /* Old 7-wire (AMD) mode */
#define FEC_MODE_MII            1   /* Media Independent Interface */
#define FEC_MODE_RMII           2   /* Reduced MII */
#define FEC_MODE_LOOPBACK       3   /* Internal Loopback */
 
#define INTC_LVL_FEC                    3
/*
 * FEC Configuration Parameters
 */
typedef struct
{
    uint8      ch;       /* FEC channel              */
    uint8      mode;     /* Transceiver mode         */
    MII_SPEED  speed;    /* Ethernet Speed           */
    MII_DUPLEX duplex;   /* Ethernet Duplex          */
    uint8      prom;     /* Promiscuous Mode?        */
    uint8      mac[6];   /* Ethernet Address         */
    uint8      phyaddr;  /* PHY address              */
    uint8      initphy;  /* Init PHY?                */
    int        nrxbd;    /* Number of RxBDs          */
    int        ntxbd;    /* Number of TxBDs          */
} FEC_CONFIG;
#define YES 1
#define NO 0
/*
 * FEC Event Log
 */
typedef struct {
    int errors;     /* total count of errors   */
    int hberr;      /* heartbeat error         */
    int babr;       /* babbling receiver       */
    int babt;       /* babbling transmitter    */
    int gra;        /* graceful stop complete  */
    int txf;        /* transmit frame          */
    int txb;        /* transmit buffer         */
    int rxf;        /* receive frame           */
    int rxb;        /* received buffer         */
    int mii;        /* MII                     */
    int eberr;      /* FEC/DMA fatal bus error */
    int lc;         /* late collision          */
    int rl;         /* collision retry limit   */
    int un;         /* Tx FIFO underflow       */
    int rfsw_inv;   /* Invalid bit in RFSW     */
    int rfsw_l;     /* RFSW Last in Frame      */
    int rfsw_m;     /* RFSW Miss               */
    int rfsw_bc;    /* RFSW Broadcast          */
    int rfsw_mc;    /* RFSW Multicast          */
    int rfsw_lg;    /* RFSW Length Violation   */
    int rfsw_no;    /* RFSW Non-octet          */
    int rfsw_cr;    /* RFSW Bad CRC            */
    int rfsw_ov;    /* RFSW Overflow           */
    int rfsw_tr;    /* RFSW Truncated          */
} FEC_EVENT_LOG;
 
#if 0
 
int
fec_mii_write( int, int, int);
 
int
fec_mii_read(int, int, uint16*);
 
void
fec_mii_init(int, int);
 
void
fec_mib_init(void);
 
void
fec_mib_dump(void);
 
void
fec_log_init(int);
 
void
fec_log_dump(int);
 
void
fec_reg_dump(int);
 
void
fec_duplex (int, MII_DUPLEX);
 
void
fec_rmii_speed (int, MII_SPEED);
 
uint8
fec_hash_address(const uint8*);
 
void
fec_set_address (const uint8*);
 
void
fec_reset ( void );
 
void
fec_init (int, const uint8*);
 
void
fec_rx_start(int, uint8*, int);
 
void
fec_rx_continue( void );
 
void
fec_rx_handler(void);
 
void
fec0_rx_handler(void);
 
void
fec1_rx_handler(void);
 
void
fec_tx_continue( void );
 
void
fec_tx_stop (int);
 
void
fec_tx_handler(NIF*, int);
 
int
fec_send (uint8*, uint8*, uint16 , NBUF*);
 
int
fec0_send(uint8*, uint8*, uint16 , NBUF*);
 
int
fec1_send(uint8*, uint8*, uint16 , NBUF*);
 
void
fec_irq_enable( void );
 
void
fec_irq_disable(int);
 
int
fec_eth_start(FEC_CONFIG*, int);
 
void
fec_eth_stop(int);
 
#endif
 
/********************************************************************/
 
#endif /* _FEC_H_ */

Line No.	Rev	Author	Line
1	606	jeremybenn	`/*`
2			`* File: fec.h`
3			`* Purpose: Driver for the Fast Ethernet Controller (FEC)`
4			`*`
5			`* Notes:`
6			`*/`
7
8			`#ifndef _FEC_H_`
9			`#define _FEC_H_`
10
11			`#include "eth.h"`
12			`#include "fecbd.h"`
13			`#include "mii.h"`
14			`#include "eth_phy.h"`
15
16			`/********************************************************************/`
17
18			`/* External Interface Modes */`
19			`#define FEC_MODE_7WIRE 0 /* Old 7-wire (AMD) mode */`
20			`#define FEC_MODE_MII 1 /* Media Independent Interface */`
21			`#define FEC_MODE_RMII 2 /* Reduced MII */`
22			`#define FEC_MODE_LOOPBACK 3 /* Internal Loopback */`
23
24			`#define INTC_LVL_FEC 3`
25			`/*`
26			`* FEC Configuration Parameters`
27			`*/`
28			`typedef struct`
29			`{`
30			`uint8 ch; /* FEC channel */`
31			`uint8 mode; /* Transceiver mode */`
32			`MII_SPEED speed; /* Ethernet Speed */`
33			`MII_DUPLEX duplex; /* Ethernet Duplex */`
34			`uint8 prom; /* Promiscuous Mode? */`
35			`uint8 mac[6]; /* Ethernet Address */`
36			`uint8 phyaddr; /* PHY address */`
37			`uint8 initphy; /* Init PHY? */`
38			`int nrxbd; /* Number of RxBDs */`
39			`int ntxbd; /* Number of TxBDs */`
40			`} FEC_CONFIG;`
41			`#define YES 1`
42			`#define NO 0`
43			`/*`
44			`* FEC Event Log`
45			`*/`
46			`typedef struct {`
47			`int errors; /* total count of errors */`
48			`int hberr; /* heartbeat error */`
49			`int babr; /* babbling receiver */`
50			`int babt; /* babbling transmitter */`
51			`int gra; /* graceful stop complete */`
52			`int txf; /* transmit frame */`
53			`int txb; /* transmit buffer */`
54			`int rxf; /* receive frame */`
55			`int rxb; /* received buffer */`
56			`int mii; /* MII */`
57			`int eberr; /* FEC/DMA fatal bus error */`
58			`int lc; /* late collision */`
59			`int rl; /* collision retry limit */`
60			`int un; /* Tx FIFO underflow */`
61			`int rfsw_inv; /* Invalid bit in RFSW */`
62			`int rfsw_l; /* RFSW Last in Frame */`
63			`int rfsw_m; /* RFSW Miss */`
64			`int rfsw_bc; /* RFSW Broadcast */`
65			`int rfsw_mc; /* RFSW Multicast */`
66			`int rfsw_lg; /* RFSW Length Violation */`
67			`int rfsw_no; /* RFSW Non-octet */`
68			`int rfsw_cr; /* RFSW Bad CRC */`
69			`int rfsw_ov; /* RFSW Overflow */`
70			`int rfsw_tr; /* RFSW Truncated */`
71			`} FEC_EVENT_LOG;`
72
73			`#if 0`
74
75			`int`
76			`fec_mii_write( int, int, int);`
77
78			`int`
79			`fec_mii_read(int, int, uint16*);`
80
81			`void`
82			`fec_mii_init(int, int);`
83
84			`void`
85			`fec_mib_init(void);`
86
87			`void`
88			`fec_mib_dump(void);`
89
90			`void`
91			`fec_log_init(int);`
92
93			`void`
94			`fec_log_dump(int);`
95
96			`void`
97			`fec_reg_dump(int);`
98
99			`void`
100			`fec_duplex (int, MII_DUPLEX);`
101
102			`void`
103			`fec_rmii_speed (int, MII_SPEED);`
104
105			`uint8`
106			`fec_hash_address(const uint8*);`
107
108			`void`
109			`fec_set_address (const uint8*);`
110
111			`void`
112			`fec_reset ( void );`
113
114			`void`
115			`fec_init (int, const uint8*);`
116
117			`void`
118			`fec_rx_start(int, uint8*, int);`
119
120			`void`
121			`fec_rx_continue( void );`
122
123			`void`
124			`fec_rx_handler(void);`
125
126			`void`
127			`fec0_rx_handler(void);`
128
129			`void`
130			`fec1_rx_handler(void);`
131
132			`void`
133			`fec_tx_continue( void );`
134
135			`void`
136			`fec_tx_stop (int);`
137
138			`void`
139			`fec_tx_handler(NIF*, int);`
140
141			`int`
142			`fec_send (uint8, uint8, uint16 , NBUF*);`
143
144			`int`
145			`fec0_send(uint8, uint8, uint16 , NBUF*);`
146
147			`int`
148			`fec1_send(uint8, uint8, uint16 , NBUF*);`
149
150			`void`
151			`fec_irq_enable( void );`
152
153			`void`
154			`fec_irq_disable(int);`
155
156			`int`
157			`fec_eth_start(FEC_CONFIG*, int);`
158
159			`void`
160			`fec_eth_stop(int);`
161
162			`#endif`
163
164			`/********************************************************************/`
165
166			`#endif /* _FEC_H_ */`

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [ethernet/] [lwIP_130/] [contrib/] [port/] [FreeRTOS/] [ColdFire/] [fec.h] - Blame information for rev 606