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jeremybenn |
/*-------------------------------------------------------------------------
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Register Declarations for the Cygnal C8051F12x Processor Range
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Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------*/
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#ifndef C8051F120_H
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#define C8051F120_H
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| 24 |
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| 25 |
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/* BYTE Registers */
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| 26 |
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| 27 |
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/* All Pages */
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| 28 |
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sfr at 0x80 P0 ; /* PORT 0 */
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| 29 |
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sfr at 0x81 SP ; /* STACK POINTER */
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| 30 |
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sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
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| 31 |
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sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
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| 32 |
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sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
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| 33 |
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sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
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| 34 |
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sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
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| 35 |
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sfr at 0x87 PCON ; /* POWER CONTROL */
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| 36 |
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sfr at 0x90 P1 ; /* PORT 1 */
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| 37 |
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sfr at 0xA0 P2 ; /* PORT 2 */
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| 38 |
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sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
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| 39 |
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sfr at 0xB0 P3 ; /* PORT 3 */
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| 40 |
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sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */
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| 41 |
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sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
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| 42 |
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sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
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| 43 |
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sfr at 0xE0 ACC ; /* ACCUMULATOR */
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| 44 |
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sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
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| 45 |
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sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
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| 46 |
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sfr at 0xF0 B ; /* B REGISTER */
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| 47 |
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sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
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| 48 |
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sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
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| 49 |
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sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
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| 50 |
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| 51 |
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/* Page 0x00 */
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| 52 |
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sfr at 0x88 TCON ; /* TIMER CONTROL */
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sfr at 0x89 TMOD ; /* TIMER MODE */
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| 54 |
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sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
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sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
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| 56 |
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sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
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| 57 |
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sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
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| 58 |
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sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
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| 59 |
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sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
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| 60 |
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sfr at 0x91 SSTA0 ; /* UART 0 STATUS */
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| 61 |
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sfr at 0x98 SCON0 ; /* UART 0 CONTROL */
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| 62 |
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sfr at 0x98 SCON ; /* UART 0 CONTROL */
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| 63 |
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sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */
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| 64 |
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sfr at 0x99 SBUF ; /* UART 0 BUFFER */
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| 65 |
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sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
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| 66 |
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sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */
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| 67 |
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sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
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| 68 |
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sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
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| 69 |
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sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */
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| 70 |
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sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
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| 71 |
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sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
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sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
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sfr at 0xB7 FLSCL ; /* FLASH SCALE */
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| 74 |
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sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
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| 75 |
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sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
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| 76 |
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sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
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| 77 |
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sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
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| 78 |
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sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
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| 79 |
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sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
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| 80 |
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sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
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| 81 |
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sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
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| 82 |
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sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
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| 83 |
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sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
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| 84 |
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sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
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| 85 |
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sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
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| 86 |
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sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
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| 87 |
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sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
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| 88 |
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sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
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| 89 |
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sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
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| 90 |
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sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
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| 91 |
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sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
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| 92 |
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sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
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| 93 |
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sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
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| 94 |
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sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
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| 95 |
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sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
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| 96 |
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sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
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| 97 |
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sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
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| 98 |
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sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
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| 99 |
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sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
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| 100 |
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sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
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| 101 |
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sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
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| 102 |
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sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
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| 103 |
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sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
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| 104 |
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sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
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| 105 |
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sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
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| 106 |
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sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
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| 107 |
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sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
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| 108 |
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sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
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| 109 |
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sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
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| 110 |
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sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
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| 111 |
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sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
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| 112 |
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sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
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| 113 |
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sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
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| 114 |
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sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
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| 115 |
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sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
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| 116 |
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sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
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| 117 |
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sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
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| 118 |
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sfr at 0xEF RSTSRC ; /* RESET SOURCE */
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| 119 |
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sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
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| 120 |
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sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
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| 121 |
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sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
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| 122 |
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sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
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| 123 |
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sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
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| 124 |
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sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
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| 125 |
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sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
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| 126 |
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| 127 |
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/* Page 0x01 */
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| 128 |
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sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
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| 129 |
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sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
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| 130 |
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sfr at 0x98 SCON1 ; /* UART 1 CONTROL */
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| 131 |
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sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */
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| 132 |
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sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
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| 133 |
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sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
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| 134 |
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sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
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| 135 |
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sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
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| 136 |
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sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
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| 137 |
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sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
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| 138 |
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sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
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| 139 |
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sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
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| 140 |
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sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
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| 141 |
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| 142 |
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/* Page 0x02 */
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| 143 |
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sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
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| 144 |
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sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
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| 145 |
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sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
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| 146 |
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sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
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| 147 |
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sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
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| 148 |
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sfr at 0xBE ADC2 ; /* ADC 2 DATA */
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| 149 |
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sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
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| 150 |
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sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
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| 151 |
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sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
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| 152 |
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sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
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| 153 |
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sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
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| 154 |
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sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
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| 155 |
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sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
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| 156 |
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sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
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| 157 |
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| 158 |
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/* Page 0x02 */
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| 159 |
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sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */
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| 160 |
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sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */
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| 161 |
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sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */
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| 162 |
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sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */
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| 163 |
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sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */
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| 164 |
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sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */
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| 165 |
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sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */
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| 166 |
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sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */
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| 167 |
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sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */
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| 168 |
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sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */
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| 169 |
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sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */
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| 170 |
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sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */
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| 171 |
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sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */
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| 172 |
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| 173 |
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/* Page 0x0F */
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| 174 |
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sfr at 0x88 FLSTAT ; /* FLASH STATUS */
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| 175 |
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sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */
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| 176 |
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sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
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| 177 |
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sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
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| 178 |
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sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
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| 179 |
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sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */
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| 180 |
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sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */
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| 181 |
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sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */
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| 182 |
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sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
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| 183 |
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sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
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| 184 |
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sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */
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| 185 |
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sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
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| 186 |
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sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
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| 187 |
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sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
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| 188 |
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sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
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| 189 |
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sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */
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| 190 |
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sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */
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| 191 |
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sfr at 0xA3 CCH0LC ; /* CACHE LOCK */
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| 192 |
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sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
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| 193 |
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sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
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| 194 |
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sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
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| 195 |
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sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
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| 196 |
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sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
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| 197 |
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sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
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| 198 |
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sfr at 0xC8 P4 ; /* PORT 4 */
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| 199 |
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sfr at 0xD8 P5 ; /* PORT 5 */
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| 200 |
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sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
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| 201 |
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sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
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| 202 |
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sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
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| 203 |
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sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
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| 204 |
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sfr at 0xE8 P6 ; /* PORT 6 */
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| 205 |
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sfr at 0xF8 P7 ; /* PORT 7 */
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| 206 |
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| 207 |
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| 208 |
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/* BIT Registers */
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| 209 |
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| 210 |
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/* P0 0x80 */
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| 211 |
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sbit at 0x80 P0_0 ;
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| 212 |
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sbit at 0x81 P0_1 ;
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| 213 |
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sbit at 0x82 P0_2 ;
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| 214 |
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sbit at 0x83 P0_3 ;
|
| 215 |
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sbit at 0x84 P0_4 ;
|
| 216 |
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sbit at 0x85 P0_5 ;
|
| 217 |
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sbit at 0x86 P0_6 ;
|
| 218 |
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sbit at 0x87 P0_7 ;
|
| 219 |
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|
| 220 |
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/* TCON 0x88 */
|
| 221 |
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sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
|
| 222 |
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sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
|
| 223 |
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sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
|
| 224 |
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sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
|
| 225 |
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sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
|
| 226 |
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sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
|
| 227 |
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sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
|
| 228 |
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sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
|
| 229 |
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|
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| 230 |
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/* CPT0CN 0x88 */
|
| 231 |
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sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
|
| 232 |
|
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sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
|
| 233 |
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sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
|
| 234 |
|
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sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
|
| 235 |
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sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
|
| 236 |
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sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
|
| 237 |
|
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sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
|
| 238 |
|
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sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
|
| 239 |
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|
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| 240 |
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/* CPT1CN 0x88 */
|
| 241 |
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sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
|
| 242 |
|
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sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
|
| 243 |
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sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
|
| 244 |
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sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
|
| 245 |
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sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
|
| 246 |
|
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sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
|
| 247 |
|
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sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
|
| 248 |
|
|
sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
|
| 249 |
|
|
|
| 250 |
|
|
/* FLSTAT 0x88 */
|
| 251 |
|
|
sbit at 0x88 FLHBUSY ; /* FLASH BUSY */
|
| 252 |
|
|
|
| 253 |
|
|
/* SCON0 0x98 */
|
| 254 |
|
|
sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
|
| 255 |
|
|
sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
|
| 256 |
|
|
sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
|
| 257 |
|
|
sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
|
| 258 |
|
|
sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */
|
| 259 |
|
|
sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */
|
| 260 |
|
|
sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */
|
| 261 |
|
|
sbit at 0x9C REN ; /* UART 0 RX ENABLE */
|
| 262 |
|
|
sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
|
| 263 |
|
|
sbit at 0x9E SM10 ; /* UART 0 MODE 1 */
|
| 264 |
|
|
sbit at 0x9F SM00 ; /* UART 0 MODE 0 */
|
| 265 |
|
|
|
| 266 |
|
|
/* SCON1 0x98 */
|
| 267 |
|
|
sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
|
| 268 |
|
|
sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
|
| 269 |
|
|
sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */
|
| 270 |
|
|
sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */
|
| 271 |
|
|
sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */
|
| 272 |
|
|
sbit at 0x9D MCE1 ; /* UART 1 MCE */
|
| 273 |
|
|
sbit at 0x9F S1MODE ; /* UART 1 MODE */
|
| 274 |
|
|
|
| 275 |
|
|
/* IE 0xA8 */
|
| 276 |
|
|
sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
|
| 277 |
|
|
sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
|
| 278 |
|
|
sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
|
| 279 |
|
|
sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
|
| 280 |
|
|
sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
|
| 281 |
|
|
sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
|
| 282 |
|
|
sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
|
| 283 |
|
|
sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
|
| 284 |
|
|
|
| 285 |
|
|
/* IP 0xB8 */
|
| 286 |
|
|
sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
|
| 287 |
|
|
sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
|
| 288 |
|
|
sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
|
| 289 |
|
|
sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
|
| 290 |
|
|
sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
|
| 291 |
|
|
sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
|
| 292 |
|
|
|
| 293 |
|
|
/* SMB0CN 0xC0 */
|
| 294 |
|
|
sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
|
| 295 |
|
|
sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
|
| 296 |
|
|
sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
|
| 297 |
|
|
sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
|
| 298 |
|
|
sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
|
| 299 |
|
|
sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
|
| 300 |
|
|
sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
|
| 301 |
|
|
sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
|
| 302 |
|
|
|
| 303 |
|
|
/* TMR2CN 0xC8 */
|
| 304 |
|
|
sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
|
| 305 |
|
|
sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
|
| 306 |
|
|
sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
|
| 307 |
|
|
sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
|
| 308 |
|
|
sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
|
| 309 |
|
|
sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
|
| 310 |
|
|
|
| 311 |
|
|
/* TMR3CN 0xC8 */
|
| 312 |
|
|
sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
|
| 313 |
|
|
sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
|
| 314 |
|
|
sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
|
| 315 |
|
|
sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
|
| 316 |
|
|
sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
|
| 317 |
|
|
sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
|
| 318 |
|
|
|
| 319 |
|
|
/* TMR4CN 0xC8 */
|
| 320 |
|
|
sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
|
| 321 |
|
|
sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
|
| 322 |
|
|
sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
|
| 323 |
|
|
sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
|
| 324 |
|
|
sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
|
| 325 |
|
|
sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
|
| 326 |
|
|
|
| 327 |
|
|
/* P4 0xC8 */
|
| 328 |
|
|
sbit at 0xC8 P4_0 ;
|
| 329 |
|
|
sbit at 0xC9 P4_1 ;
|
| 330 |
|
|
sbit at 0xCA P4_2 ;
|
| 331 |
|
|
sbit at 0xCB P4_3 ;
|
| 332 |
|
|
sbit at 0xCC P4_4 ;
|
| 333 |
|
|
sbit at 0xCD P4_5 ;
|
| 334 |
|
|
sbit at 0xCE P4_6 ;
|
| 335 |
|
|
sbit at 0xCF P4_7 ;
|
| 336 |
|
|
|
| 337 |
|
|
/* PSW 0xD0 */
|
| 338 |
|
|
sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
|
| 339 |
|
|
sbit at 0xD1 F1 ; /* USER FLAG 1 */
|
| 340 |
|
|
sbit at 0xD2 OV ; /* OVERFLOW FLAG */
|
| 341 |
|
|
sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
|
| 342 |
|
|
sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
|
| 343 |
|
|
sbit at 0xD5 F0 ; /* USER FLAG 0 */
|
| 344 |
|
|
sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
|
| 345 |
|
|
sbit at 0xD7 CY ; /* CARRY FLAG */
|
| 346 |
|
|
|
| 347 |
|
|
/* PCA0CN D8H */
|
| 348 |
|
|
sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
|
| 349 |
|
|
sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
|
| 350 |
|
|
sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
|
| 351 |
|
|
sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
|
| 352 |
|
|
sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
|
| 353 |
|
|
sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
|
| 354 |
|
|
sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
|
| 355 |
|
|
sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
|
| 356 |
|
|
|
| 357 |
|
|
/* P5 0xD8 */
|
| 358 |
|
|
sbit at 0xD8 P5_0 ;
|
| 359 |
|
|
sbit at 0xD9 P5_1 ;
|
| 360 |
|
|
sbit at 0xDA P5_2 ;
|
| 361 |
|
|
sbit at 0xDB P5_3 ;
|
| 362 |
|
|
sbit at 0xDC P5_4 ;
|
| 363 |
|
|
sbit at 0xDD P5_5 ;
|
| 364 |
|
|
sbit at 0xDE P5_6 ;
|
| 365 |
|
|
sbit at 0xDF P5_7 ;
|
| 366 |
|
|
|
| 367 |
|
|
/* ADC0CN E8H */
|
| 368 |
|
|
sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
|
| 369 |
|
|
sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
|
| 370 |
|
|
sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
|
| 371 |
|
|
sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
|
| 372 |
|
|
sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
|
| 373 |
|
|
sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
|
| 374 |
|
|
sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
|
| 375 |
|
|
sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
|
| 376 |
|
|
|
| 377 |
|
|
/* ADC2CN E8H */
|
| 378 |
|
|
sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
|
| 379 |
|
|
sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
|
| 380 |
|
|
sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
|
| 381 |
|
|
sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
|
| 382 |
|
|
sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
|
| 383 |
|
|
sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
|
| 384 |
|
|
sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
|
| 385 |
|
|
sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */
|
| 386 |
|
|
|
| 387 |
|
|
/* P6 0xE8 */
|
| 388 |
|
|
sbit at 0xE8 P6_0 ;
|
| 389 |
|
|
sbit at 0xE9 P6_1 ;
|
| 390 |
|
|
sbit at 0xEA P6_2 ;
|
| 391 |
|
|
sbit at 0xEB P6_3 ;
|
| 392 |
|
|
sbit at 0xEC P6_4 ;
|
| 393 |
|
|
sbit at 0xED P6_5 ;
|
| 394 |
|
|
sbit at 0xEE P6_6 ;
|
| 395 |
|
|
sbit at 0xEF P6_7 ;
|
| 396 |
|
|
|
| 397 |
|
|
/* SPI0CN F8H */
|
| 398 |
|
|
sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
|
| 399 |
|
|
sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
|
| 400 |
|
|
sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
|
| 401 |
|
|
sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
|
| 402 |
|
|
sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
|
| 403 |
|
|
sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
|
| 404 |
|
|
sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
|
| 405 |
|
|
sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
|
| 406 |
|
|
|
| 407 |
|
|
/* P7 0xF8 */
|
| 408 |
|
|
sbit at 0xF8 P7_0 ;
|
| 409 |
|
|
sbit at 0xF9 P7_1 ;
|
| 410 |
|
|
sbit at 0xFA P7_2 ;
|
| 411 |
|
|
sbit at 0xFB P7_3 ;
|
| 412 |
|
|
sbit at 0xFC P7_4 ;
|
| 413 |
|
|
sbit at 0xFD P7_5 ;
|
| 414 |
|
|
sbit at 0xFE P7_6 ;
|
| 415 |
|
|
sbit at 0xFF P7_7 ;
|
| 416 |
|
|
|
| 417 |
|
|
|
| 418 |
|
|
/* Predefined SFR Bit Masks */
|
| 419 |
|
|
|
| 420 |
|
|
#define IDLE 0x01 /* PCON */
|
| 421 |
|
|
#define STOP 0x02 /* PCON */
|
| 422 |
|
|
#define ECCF 0x01 /* PCA0CPMn */
|
| 423 |
|
|
#define PWM 0x02 /* PCA0CPMn */
|
| 424 |
|
|
#define TOG 0x04 /* PCA0CPMn */
|
| 425 |
|
|
#define MAT 0x08 /* PCA0CPMn */
|
| 426 |
|
|
#define CAPN 0x10 /* PCA0CPMn */
|
| 427 |
|
|
#define CAPP 0x20 /* PCA0CPMn */
|
| 428 |
|
|
#define ECOM 0x40 /* PCA0CPMn */
|
| 429 |
|
|
#define PWM16 0x80 /* PCA0CPMn */
|
| 430 |
|
|
#define PORSF 0x02 /* RSTSRC */
|
| 431 |
|
|
#define SWRSF 0x10 /* RSTSRC */
|
| 432 |
|
|
|
| 433 |
|
|
|
| 434 |
|
|
/* SFR PAGE DEFINITIONS */
|
| 435 |
|
|
|
| 436 |
|
|
#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
|
| 437 |
|
|
#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
|
| 438 |
|
|
#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
|
| 439 |
|
|
#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
|
| 440 |
|
|
#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
|
| 441 |
|
|
#define UART0_PAGE 0x00 /* UART 0 */
|
| 442 |
|
|
#define UART1_PAGE 0x01 /* UART 1 */
|
| 443 |
|
|
#define SPI0_PAGE 0x00 /* SPI 0 */
|
| 444 |
|
|
#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
|
| 445 |
|
|
#define ADC0_PAGE 0x00 /* ADC 0 */
|
| 446 |
|
|
#define ADC2_PAGE 0x02 /* ADC 2 */
|
| 447 |
|
|
#define SMB0_PAGE 0x00 /* SMBUS 0 */
|
| 448 |
|
|
#define TMR2_PAGE 0x00 /* TIMER 2 */
|
| 449 |
|
|
#define TMR3_PAGE 0x01 /* TIMER 3 */
|
| 450 |
|
|
#define TMR4_PAGE 0x02 /* TIMER 4 */
|
| 451 |
|
|
#define DAC0_PAGE 0x00 /* DAC 0 */
|
| 452 |
|
|
#define DAC1_PAGE 0x01 /* DAC 1 */
|
| 453 |
|
|
#define PCA0_PAGE 0x00 /* PCA 0 */
|
| 454 |
|
|
#define PLL0_PAGE 0x0F /* PLL 0 */
|
| 455 |
|
|
|
| 456 |
|
|
#endif
|
