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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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jeremybenn |
/****************************************************************
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KPIT Cummins Infosystems Ltd, Pune, India. - 19-June-2003.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*****************************************************************/
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void start(void); /* Startup code (in start.asm) */
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/*
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* Manual context switch trap function.
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*/
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void vPortYield( void );
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/*
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* The RTOS tick ISR.
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*/
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void vTickISR( void );
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/*
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* Serial port ISR functions.
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*/
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void vCOM_1_Rx_ISR( void );
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void vCOM_1_Tx_ISR( void );
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void vCOM_1_Error_ISR( void );
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typedef void (*fp) (void);
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#define VECT_SECT __attribute__ ((section (".vects")))
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const fp HardwareVectors[] VECT_SECT = {
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start, /* vector 0 */
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(fp)(0), /* vector 1 */
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(fp)(0), /* vector 2 */
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(fp)(0), /* vector 3 */
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(fp)(0), /* vector 4 */
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(fp)(0), /* vector 5 */
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(fp)(0), /* vector 6 */
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(fp)(0), /* vector 7 */
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vPortYield, /* vector 8 */
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(fp)(0), /* vector 9 */
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(fp)(0), /* vector 10 */
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(fp)(0), /* vector 11 */
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(fp)(0), /* vector 12 */
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(fp)(0), /* vector 13 */
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(fp)(0), /* vector 14 */
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(fp)(0), /* vector 15 */
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(fp)(0), /* vector 16 */
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(fp)(0), /* vector 17 */
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(fp)(0), /* vector 18 */
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(fp)(0), /* vector 19 */
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(fp)(0), /* vector 20 */
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(fp)(0), /* vector 21 */
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(fp)(0), /* vector 22 */
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(fp)(0), /* vector 23 */
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(fp)(0), /* vector 24 */
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(fp)(0), /* vector 25 */
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(fp)(0), /* vector 26 */
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(fp)(0), /* vector 27 */
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(fp)(0), /* vector 28 */
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(fp)(0), /* vector 29 */
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(fp)(0), /* vector 30 */
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(fp)(0), /* vector 31 */
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(fp)(0), /* vector 32 */
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(fp)(0), /* vector 33 */
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(fp)(0), /* vector 34 */
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(fp)(0), /* vector 35 */
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(fp)(0), /* vector 36 */
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(fp)(0), /* vector 37 */
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(fp)(0), /* vector 38 */
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(fp)(0), /* vector 39 */
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vTickISR, /* vector 40 */
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(fp)(0), /* vector 41 */
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(fp)(0), /* vector 42 */
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(fp)(0), /* vector 43 */
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(fp)(0), /* vector 44 */
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(fp)(0), /* vector 45 */
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(fp)(0), /* vector 46 */
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(fp)(0), /* vector 47 */
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(fp)(0), /* vector 48 */
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(fp)(0), /* vector 49 */
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(fp)(0), /* vector 50 */
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(fp)(0), /* vector 51 */
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(fp)(0), /* vector 52 */
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(fp)(0), /* vector 53 */
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(fp)(0), /* vector 54 */
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(fp)(0), /* vector 55 */
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(fp)(0), /* vector 56 */
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(fp)(0), /* vector 57 */
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(fp)(0), /* vector 58 */
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(fp)(0), /* vector 59 */
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(fp)(0), /* vector 60 */
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(fp)(0), /* vector 61 */
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(fp)(0), /* vector 62 */
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(fp)(0), /* vector 63 */
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(fp)(0), /* vector 64 */
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(fp)(0), /* vector 65 */
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(fp)(0), /* vector 66 */
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(fp)(0), /* vector 67 */
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(fp)(0), /* vector 68 */
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(fp)(0), /* vector 69 */
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(fp)(0), /* vector 70 */
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(fp)(0), /* vector 71 */
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(fp)(0), /* vector 72 */
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(fp)(0), /* vector 73 */
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(fp)(0), /* vector 74 */
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(fp)(0), /* vector 75 */
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(fp)(0), /* vector 76 */
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(fp)(0), /* vector 77 */
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(fp)(0), /* vector 78 */
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(fp)(0), /* vector 79 */
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(fp)(0), /* vector 80 */
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(fp)(0), /* vector 81 */
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(fp)(0), /* vector 82 */
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(fp)(0), /* vector 83 */
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vCOM_1_Error_ISR, /* vector 84 */
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vCOM_1_Rx_ISR, /* vector 85 */
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vCOM_1_Tx_ISR, /* vector 86 */
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(fp)(0), /* vector 87 */
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(fp)(0), /* vector 88 */
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(fp)(0), /* vector 89 */
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(fp)(0), /* vector 90 */
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(fp)(0), /* vector 91 */
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(fp)(0), /* vector 92 */
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(fp)(0), /* vector 93 */
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(fp)(0), /* vector 94 */
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(fp)(0), /* vector 95 */
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(fp)(0), /* vector 96 */
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(fp)(0), /* vector 97 */
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(fp)(0), /* vector 98 */
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(fp)(0), /* vector 99 */
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(fp)(0), /* vector 100 */
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(fp)(0), /* vector 101 */
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(fp)(0), /* vector 102 */
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(fp)(0) /* vector 103 */
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};
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