OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [HCS12_CodeWarrior_banked/] [CODE/] [Cpu.C] - Blame information for rev 861

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 588 jeremybenn
/** ###################################################################
2
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
3
**     Filename  : Cpu.C
4
**     Project   : RTOSDemo
5
**     Processor : MC9S12DP256BCPV
6
**     Beantype  : MC9S12DP256_112
7
**     Version   : Bean 01.148, Driver 01.09, CPU db: 2.87.283
8
**     Compiler  : Metrowerks HC12 C Compiler
9
**     Date/Time : 18/06/2005, 16:21
10
**     Abstract  :
11
**         This bean "MC9S12DP256_112" implements properties, methods,
12
**         and events of the CPU.
13
**     Settings  :
14
**
15
**     Contents  :
16
**         EnableInt  - void Cpu_EnableInt(void);
17
**         DisableInt - void Cpu_DisableInt(void);
18
**
19
**     (c) Copyright UNIS, spol. s r.o. 1997-2002
20
**     UNIS, spol. s r.o.
21
**     Jundrovska 33
22
**     624 00 Brno
23
**     Czech Republic
24
**     http      : www.processorexpert.com
25
**     mail      : info@processorexpert.com
26
** ###################################################################*/
27
 
28
/* MODULE Cpu. */
29
 
30
#include "TickTimer.h"
31
#include "Byte1.h"
32
#include "COM0.h"
33
#include "PE_Types.h"
34
#include "PE_Error.h"
35
#include "PE_Const.h"
36
#include "IO_Map.h"
37
#include "PE_Timer.h"
38
#include "Events.h"
39
#include "Cpu.h"
40
 
41
#define CGM_DELAY  3071UL
42
 
43
 
44
/* Global variables */
45
volatile byte CCR_reg;                 /* Current CCR reegister */
46
byte CpuMode = HIGH_SPEED;             /* Current speed mode */
47
 
48
 
49
/*
50
** ===================================================================
51
**     Method      :  Cpu_Interrupt (bean MC9S12DP256_112)
52
**
53
**     Description :
54
**         This method is internal. It is used by Processor Expert
55
**         only.
56
** ===================================================================
57
*/
58
#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
59
 
60
__interrupt void Cpu_Interrupt(void)
61
{
62
}
63
 
64
#pragma CODE_SEG DEFAULT               /* Change code section to DEFAULT. */
65
 
66
/*
67
** ===================================================================
68
**     Method      :  Cpu_DisableInt (bean MC9S12DP256_112)
69
**
70
**     Description :
71
**         Disable maskable interrupts
72
**     Parameters  : None
73
**     Returns     : Nothing
74
** ===================================================================
75
*/
76
/*
77
void Cpu_DisableInt(void)
78
 
79
**      This method is implemented as macro in the header module. **
80
*/
81
 
82
/*
83
** ===================================================================
84
**     Method      :  Cpu_EnableInt (bean MC9S12DP256_112)
85
**
86
**     Description :
87
**         Enable maskable interrupts
88
**     Parameters  : None
89
**     Returns     : Nothing
90
** ===================================================================
91
*/
92
/*
93
void Cpu_EnableInt(void)
94
 
95
**      This method is implemented as macro in the header module. **
96
*/
97
 
98
/*
99
** ===================================================================
100
**     Method      :  _EntryPoint (bean MC9S12DP256_112)
101
**
102
**     Description :
103
**         This method is internal. It is used by Processor Expert
104
**         only.
105
** ===================================================================
106
*/
107
extern void _Startup(void);            /* Forward declaration of external startup function declared in file Start12.c */
108
#define INITRG_ADR  0x0011             /* Register map position register */
109
#pragma NO_FRAME
110
#pragma NO_EXIT
111
void _EntryPoint(void)
112
{
113
  /*** ### MC9S12DP256_112 "Cpu" init code ... ***/
114
  /*** PE initialization code after reset ***/
115
  /* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */
116
  *(byte*)INITRG_ADR = 0;              /* Set the register map position */
117
  asm nop;                             /* nop instruction */
118
  INITRM=1;                            /* Set the RAM map position */
119
  INITEE=1;                            /* Set the EEPROM map position */
120
  /* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */
121
  MISC=1;
122
  /* System clock initialization */
123
  CLKSEL=0;
124
  CLKSEL_PLLSEL = 0;                   /* Select clock source from XTAL */
125
  PLLCTL_PLLON = 0;                    /* Disable the PLL */
126
  SYNR = 24;                           /* Set the multiplier register */
127
  REFDV = 15;                          /* Set the divider register */
128
  PLLCTL = 192;
129
  PLLCTL_PLLON = 1;                    /* Enable the PLL */
130
  while(!CRGFLG_LOCK);                 /* Wait */
131
  CLKSEL_PLLSEL = 1;                   /* Select clock source from PLL */
132
  /*** End of PE initialization code after reset ***/
133
 
134
  __asm   jmp _Startup;                /* Jump to C startup code */
135
}
136
 
137
/*
138
** ===================================================================
139
**     Method      :  PE_low_level_init (bean MC9S12DP256_112)
140
**
141
**     Description :
142
**         This method is internal. It is used by Processor Expert
143
**         only.
144
** ===================================================================
145
*/
146
void PE_low_level_init(void)
147
{
148
  /* Common initialization of the CPU registers */
149
/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */
150
  output( TSCR1, input( TSCR1 ) & ~192 | 32 );
151
/* TCTL2: OM0=0,OL0=0 */
152
  output( TCTL2, input( TCTL2 ) & ~3 );
153
/* TCTL1: OM7=0,OL7=0 */
154
  output( TCTL1, input( TCTL1 ) & ~192 );
155
/* TIE: C0I=0 */
156
  output( TIE, input( TIE ) & ~1 );
157
/* TTOV: TOV0=0 */
158
  output( TTOV, input( TTOV ) & ~1 );
159
/* TSCR2: TOI=0,TCRE=1 */
160
  output( TSCR2, input( TSCR2 ) & ~128 | 8 );
161
/* TIOS: IOS7=1,IOS0=1 */
162
  output( TIOS, input( TIOS ) | 129 );
163
/* PWMCTL: PSWAI=0,PFRZ=0 */
164
  output( PWMCTL, input( PWMCTL ) & ~12 );
165
/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */
166
  output( PWMSDN, 0 );
167
/* ICSYS: SH37=0,SH26=0,SH15=0,SH04=0,TFMOD=0,PACMX=0,BUFEN=0,LATQ=0 */
168
  output( ICSYS, 0 );
169
/* MCCTL: MODMC=1 */
170
  output( MCCTL, input( MCCTL ) | 64 );
171
  /* ### MC9S12DP256_112 "Cpu" init code ... */
172
  /* ### TimerInt "TickTimer" init code ... */
173
  TickTimer_Init();
174
  /* ### ByteIO "Byte1" init code ... */
175
  PORTB = 255;                         /* Prepare value for output */
176
  DDRB = 255;                          /* Set direction to output */
177
  /* ### Asynchro serial "COM0" init code ... */
178
  DDRS &= ~1;
179
  PTS |= 2;
180
  DDRS |= 2;
181
  COM0_Init();
182
 /* Common peripheral initialization - ENABLE */
183
/* TSCR1: TEN=1 */
184
  output( TSCR1, input( TSCR1 ) | 128 );
185
  INTCR_IRQEN = 0;                     /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */
186
  __DI();                              /* Disable interrupts */
187
}
188
 
189
/* END Cpu. */
190
 
191
/*
192
** ###################################################################
193
**
194
**     This file was created by UNIS Processor Expert 03.33 for
195
**     the Motorola HCS12 series of microcontrollers.
196
**
197
** ###################################################################
198
*/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.