OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [HCS12_CodeWarrior_banked/] [CODE/] [Cpu.H] - Blame information for rev 773

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 588 jeremybenn
/** ###################################################################
2
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
3
**     Filename  : Cpu.H
4
**     Project   : RTOSDemo
5
**     Processor : MC9S12DP256BCPV
6
**     Beantype  : MC9S12DP256_112
7
**     Version   : Bean 01.148, Driver 01.09, CPU db: 2.87.283
8
**     Compiler  : Metrowerks HC12 C Compiler
9
**     Date/Time : 14/06/2005, 16:34
10
**     Abstract  :
11
**         This bean "MC9S12DP256_112" implements properties, methods,
12
**         and events of the CPU.
13
**     Settings  :
14
**
15
**     Contents  :
16
**         EnableInt  - void Cpu_EnableInt(void);
17
**         DisableInt - void Cpu_DisableInt(void);
18
**
19
**     (c) Copyright UNIS, spol. s r.o. 1997-2002
20
**     UNIS, spol. s r.o.
21
**     Jundrovska 33
22
**     624 00 Brno
23
**     Czech Republic
24
**     http      : www.processorexpert.com
25
**     mail      : info@processorexpert.com
26
** ###################################################################*/
27
 
28
#ifndef __Cpu
29
#define __Cpu
30
 
31
/* Active configuration define symbol */
32
#define PEcfg_112pin 1
33
 
34
/*Include shared modules, which are used for whole project*/
35
#include "PE_Types.h"
36
#include "PE_Error.h"
37
#include "PE_Const.h"
38
#include "IO_Map.h"
39
#include "PE_Timer.h"
40
 
41
/* MODULE Cpu. */
42
 
43
 
44
/* Global variables */
45
extern volatile byte CCR_reg;          /* Current CCR reegister */
46
extern byte CpuMode;                   /* Current speed mode */
47
 
48
 
49
 
50
 
51
#define   Cpu_DisableInt()  __DI()     /* Disable interrupts */
52
/*
53
** ===================================================================
54
**     Method      :  Cpu_DisableInt (bean MC9S12DP256_112)
55
**
56
**     Description :
57
**         Disable maskable interrupts
58
**     Parameters  : None
59
**     Returns     : Nothing
60
** ===================================================================
61
*/
62
 
63
#define   Cpu_EnableInt()  __EI()      /* Enable interrupts */
64
/*
65
** ===================================================================
66
**     Method      :  Cpu_EnableInt (bean MC9S12DP256_112)
67
**
68
**     Description :
69
**         Enable maskable interrupts
70
**     Parameters  : None
71
**     Returns     : Nothing
72
** ===================================================================
73
*/
74
 
75
#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
76
 
77
__interrupt void Cpu_Interrupt(void);
78
/*
79
** ===================================================================
80
**     Method      :  Cpu_Interrupt (bean MC9S12DP256_112)
81
**
82
**     Description :
83
**         This method is internal. It is used by Processor Expert
84
**         only.
85
** ===================================================================
86
*/
87
 
88
#pragma CODE_SEG DEFAULT               /* Change code section to DEFAULT. */
89
 
90
void PE_low_level_init(void);
91
/*
92
** ===================================================================
93
**     Method      :  PE_low_level_init (bean MC9S12DP256_112)
94
**
95
**     Description :
96
**         This method is internal. It is used by Processor Expert
97
**         only.
98
** ===================================================================
99
*/
100
 
101
/* END Cpu. */
102
 
103
#endif /* ifndef __Cpu */
104
/*
105
** ###################################################################
106
**
107
**     This file was created by UNIS Processor Expert 03.33 for
108
**     the Motorola HCS12 series of microcontrollers.
109
**
110
** ###################################################################
111
*/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.