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jeremybenn |
/** ###################################################################
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** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
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** Filename : IO_Map.H
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** Project : RTOSDemo
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** Processor : MC9S12DP256BCPV
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** Beantype : IO_Map
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** Version : Driver 01.01
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** Compiler : Metrowerks HC12 C Compiler
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** Date/Time : 13/06/2005, 20:14
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** Abstract :
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** This bean "IO_Map" implements an IO devices mapping.
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** Settings :
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**
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** Contents :
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** No public methods
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**
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** (c) Copyright UNIS, spol. s r.o. 1997-2002
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** UNIS, spol. s r.o.
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** Jundrovska 33
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** 624 00 Brno
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** Czech Republic
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** http : www.processorexpert.com
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** mail : info@processorexpert.com
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** ###################################################################*/
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/* Linker pragmas */
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#pragma LINK_INFO DERIVATIVE "MC9S12DP256B"
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#pragma LINK_INFO OSCFREQUENCY "16000000"
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#define REG_BASE 0x0000 /* Base address for the I/O register block */
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/* Based on CPU DB MC9S12DP256_112, version 2.87.278 (RegistersPrg V1.027) */
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#ifndef _MC9S12DP256_112_H
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#define _MC9S12DP256_112_H
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#include "PE_Types.h"
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#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */
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/*********************************************/
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/* */
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/* PE I/O map format */
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/* */
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/*********************************************/
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/*** PORTAB - Port AB Register; 0x00000000 ***/
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typedef union {
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word Word;
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/* Overlapped registers: */
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struct {
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/*** PORTA - Port A Register; 0x00000000 ***/
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union {
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byte Byte;
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struct {
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byte BIT0 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */
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byte BIT1 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */
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byte BIT2 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */
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byte BIT3 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */
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byte BIT4 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */
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byte BIT5 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */
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byte BIT6 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */
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byte BIT7 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */
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} Bits;
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struct {
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byte grpBIT :8;
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} MergedBits;
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} PORTASTR;
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#define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte
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#define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0
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#define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1
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#define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2
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#define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3
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#define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4
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#define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5
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#define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6
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#define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7
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#define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT
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/*** PORTB - Port B Register; 0x00000001 ***/
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union {
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byte Byte;
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struct {
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byte BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */
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byte BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */
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byte BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */
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byte BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */
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byte BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */
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byte BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */
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byte BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */
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byte BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */
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} Bits;
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struct {
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byte grpBIT :8;
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} MergedBits;
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} PORTBSTR;
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#define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte
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#define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0
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#define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1
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#define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2
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#define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3
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#define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4
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#define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5
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#define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6
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#define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7
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#define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT
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} Overlap_STR;
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struct {
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word BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */
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word BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */
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word BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */
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word BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */
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word BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */
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word BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */
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word BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */
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word BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */
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word BIT8 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */
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word BIT9 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */
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word BIT10 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */
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word BIT11 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */
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word BIT12 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */
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word BIT13 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */
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word BIT14 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */
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word BIT15 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */
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} Bits;
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struct {
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word grpBIT :16;
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} MergedBits;
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} PORTABSTR;
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extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000);
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#define PORTAB _PORTAB.Word
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#define PORTAB_BIT0 _PORTAB.Bits.BIT0
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#define PORTAB_BIT1 _PORTAB.Bits.BIT1
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#define PORTAB_BIT2 _PORTAB.Bits.BIT2
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#define PORTAB_BIT3 _PORTAB.Bits.BIT3
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#define PORTAB_BIT4 _PORTAB.Bits.BIT4
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#define PORTAB_BIT5 _PORTAB.Bits.BIT5
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#define PORTAB_BIT6 _PORTAB.Bits.BIT6
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#define PORTAB_BIT7 _PORTAB.Bits.BIT7
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#define PORTAB_BIT8 _PORTAB.Bits.BIT8
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#define PORTAB_BIT9 _PORTAB.Bits.BIT9
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#define PORTAB_BIT10 _PORTAB.Bits.BIT10
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#define PORTAB_BIT11 _PORTAB.Bits.BIT11
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#define PORTAB_BIT12 _PORTAB.Bits.BIT12
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#define PORTAB_BIT13 _PORTAB.Bits.BIT13
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#define PORTAB_BIT14 _PORTAB.Bits.BIT14
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#define PORTAB_BIT15 _PORTAB.Bits.BIT15
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#define PORTAB_BIT _PORTAB.MergedBits.grpBIT
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/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/
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typedef union {
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word Word;
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/* Overlapped registers: */
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struct {
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/*** DDRA - Port A Data Direction Register; 0x00000002 ***/
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union {
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byte Byte;
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struct {
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byte BIT0 :1; /* Data Direction Port A Bit 0 */
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byte BIT1 :1; /* Data Direction Port A Bit 1 */
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byte BIT2 :1; /* Data Direction Port A Bit 2 */
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byte BIT3 :1; /* Data Direction Port A Bit 3 */
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byte BIT4 :1; /* Data Direction Port A Bit 4 */
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byte BIT5 :1; /* Data Direction Port A Bit 5 */
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byte BIT6 :1; /* Data Direction Port A Bit 6 */
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byte BIT7 :1; /* Data Direction Port A Bit 7 */
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} Bits;
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struct {
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byte grpBIT :8;
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} MergedBits;
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} DDRASTR;
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#define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte
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#define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0
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#define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1
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#define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2
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#define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3
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#define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4
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#define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5
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#define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6
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#define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7
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#define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT
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/*** DDRB - Port B Data Direction Register; 0x00000003 ***/
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union {
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byte Byte;
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struct {
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byte BIT0 :1; /* Data Direction Port B Bit 0 */
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byte BIT1 :1; /* Data Direction Port B Bit 1 */
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byte BIT2 :1; /* Data Direction Port B Bit 2 */
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byte BIT3 :1; /* Data Direction Port B Bit 3 */
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byte BIT4 :1; /* Data Direction Port B Bit 4 */
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byte BIT5 :1; /* Data Direction Port B Bit 5 */
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byte BIT6 :1; /* Data Direction Port B Bit 6 */
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byte BIT7 :1; /* Data Direction Port B Bit 7 */
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} Bits;
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struct {
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byte grpBIT :8;
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} MergedBits;
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} DDRBSTR;
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#define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte
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#define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0
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#define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1
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#define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2
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#define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3
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#define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4
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#define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5
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#define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6
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#define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7
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#define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT
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} Overlap_STR;
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struct {
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word BIT0 :1; /* Data Direction Port B Bit 0 */
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word BIT1 :1; /* Data Direction Port B Bit 1 */
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word BIT2 :1; /* Data Direction Port B Bit 2 */
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word BIT3 :1; /* Data Direction Port B Bit 3 */
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word BIT4 :1; /* Data Direction Port B Bit 4 */
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word BIT5 :1; /* Data Direction Port B Bit 5 */
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word BIT6 :1; /* Data Direction Port B Bit 6 */
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word BIT7 :1; /* Data Direction Port B Bit 7 */
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word BIT8 :1; /* Data Direction Port A Bit 8 */
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word BIT9 :1; /* Data Direction Port A Bit 9 */
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word BIT10 :1; /* Data Direction Port A Bit 10 */
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word BIT11 :1; /* Data Direction Port A Bit 11 */
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word BIT12 :1; /* Data Direction Port A Bit 12 */
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word BIT13 :1; /* Data Direction Port A Bit 13 */
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word BIT14 :1; /* Data Direction Port A Bit 14 */
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word BIT15 :1; /* Data Direction Port A Bit 15 */
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| 233 |
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} Bits;
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struct {
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| 235 |
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word grpBIT :16;
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| 236 |
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} MergedBits;
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| 237 |
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} DDRABSTR;
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| 238 |
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extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);
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#define DDRAB _DDRAB.Word
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#define DDRAB_BIT0 _DDRAB.Bits.BIT0
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#define DDRAB_BIT1 _DDRAB.Bits.BIT1
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#define DDRAB_BIT2 _DDRAB.Bits.BIT2
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#define DDRAB_BIT3 _DDRAB.Bits.BIT3
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#define DDRAB_BIT4 _DDRAB.Bits.BIT4
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#define DDRAB_BIT5 _DDRAB.Bits.BIT5
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#define DDRAB_BIT6 _DDRAB.Bits.BIT6
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| 247 |
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#define DDRAB_BIT7 _DDRAB.Bits.BIT7
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| 248 |
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#define DDRAB_BIT8 _DDRAB.Bits.BIT8
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| 249 |
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#define DDRAB_BIT9 _DDRAB.Bits.BIT9
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#define DDRAB_BIT10 _DDRAB.Bits.BIT10
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#define DDRAB_BIT11 _DDRAB.Bits.BIT11
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#define DDRAB_BIT12 _DDRAB.Bits.BIT12
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| 253 |
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#define DDRAB_BIT13 _DDRAB.Bits.BIT13
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| 254 |
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#define DDRAB_BIT14 _DDRAB.Bits.BIT14
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#define DDRAB_BIT15 _DDRAB.Bits.BIT15
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#define DDRAB_BIT _DDRAB.MergedBits.grpBIT
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| 258 |
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| 259 |
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/*** TCNT - Timer Count Register; 0x00000044 ***/
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| 260 |
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typedef union {
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| 261 |
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word Word;
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| 262 |
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/* Overlapped registers: */
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| 263 |
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struct {
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| 264 |
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/*** TCNTHi - Timer Count Register High; 0x00000044 ***/
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| 265 |
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union {
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| 266 |
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byte Byte;
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| 267 |
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struct {
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| 268 |
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byte BIT15 :1; /* Timer Count Register Bit 15 */
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| 269 |
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byte BIT14 :1; /* Timer Count Register Bit 14 */
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| 270 |
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byte BIT13 :1; /* Timer Count Register Bit 13 */
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| 271 |
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byte BIT12 :1; /* Timer Count Register Bit 12 */
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| 272 |
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byte BIT11 :1; /* Timer Count Register Bit 11 */
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| 273 |
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byte BIT10 :1; /* Timer Count Register Bit 10 */
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| 274 |
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byte BIT9 :1; /* Timer Count Register Bit 9 */
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| 275 |
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byte BIT8 :1; /* Timer Count Register Bit 8 */
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| 276 |
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} Bits;
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| 277 |
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} TCNTHiSTR;
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| 278 |
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#define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte
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| 279 |
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#define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15
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| 280 |
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#define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14
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| 281 |
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#define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13
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| 282 |
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#define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12
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| 283 |
|
|
#define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11
|
| 284 |
|
|
#define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10
|
| 285 |
|
|
#define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9
|
| 286 |
|
|
#define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8
|
| 287 |
|
|
|
| 288 |
|
|
/*** TCNTLo - Timer Count Register Low; 0x00000045 ***/
|
| 289 |
|
|
union {
|
| 290 |
|
|
byte Byte;
|
| 291 |
|
|
struct {
|
| 292 |
|
|
byte BIT0 :1; /* Timer Count Register Bit 0 */
|
| 293 |
|
|
byte BIT1 :1; /* Timer Count Register Bit 1 */
|
| 294 |
|
|
byte BIT2 :1; /* Timer Count Register Bit 2 */
|
| 295 |
|
|
byte BIT3 :1; /* Timer Count Register Bit 3 */
|
| 296 |
|
|
byte BIT4 :1; /* Timer Count Bit Register 4 */
|
| 297 |
|
|
byte BIT5 :1; /* Timer Count Bit Register 5 */
|
| 298 |
|
|
byte BIT6 :1; /* Timer Count Bit Register 6 */
|
| 299 |
|
|
byte BIT7 :1; /* Timer Count Bit Register 7 */
|
| 300 |
|
|
} Bits;
|
| 301 |
|
|
struct {
|
| 302 |
|
|
byte grpBIT :8;
|
| 303 |
|
|
} MergedBits;
|
| 304 |
|
|
} TCNTLoSTR;
|
| 305 |
|
|
#define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte
|
| 306 |
|
|
#define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0
|
| 307 |
|
|
#define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1
|
| 308 |
|
|
#define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2
|
| 309 |
|
|
#define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3
|
| 310 |
|
|
#define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4
|
| 311 |
|
|
#define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5
|
| 312 |
|
|
#define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6
|
| 313 |
|
|
#define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7
|
| 314 |
|
|
#define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT
|
| 315 |
|
|
|
| 316 |
|
|
} Overlap_STR;
|
| 317 |
|
|
|
| 318 |
|
|
struct {
|
| 319 |
|
|
word grpBIT :16;
|
| 320 |
|
|
} MergedBits;
|
| 321 |
|
|
} TCNTSTR;
|
| 322 |
|
|
extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044);
|
| 323 |
|
|
#define TCNT _TCNT.Word
|
| 324 |
|
|
#define TCNT_BIT _TCNT.MergedBits.grpBIT
|
| 325 |
|
|
|
| 326 |
|
|
|
| 327 |
|
|
/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/
|
| 328 |
|
|
typedef union {
|
| 329 |
|
|
word Word;
|
| 330 |
|
|
/* Overlapped registers: */
|
| 331 |
|
|
struct {
|
| 332 |
|
|
/*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/
|
| 333 |
|
|
union {
|
| 334 |
|
|
byte Byte;
|
| 335 |
|
|
struct {
|
| 336 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */
|
| 337 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */
|
| 338 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */
|
| 339 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */
|
| 340 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */
|
| 341 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */
|
| 342 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */
|
| 343 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */
|
| 344 |
|
|
} Bits;
|
| 345 |
|
|
struct {
|
| 346 |
|
|
byte grpBIT_8 :8;
|
| 347 |
|
|
} MergedBits;
|
| 348 |
|
|
} TC0HiSTR;
|
| 349 |
|
|
#define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte
|
| 350 |
|
|
#define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8
|
| 351 |
|
|
#define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9
|
| 352 |
|
|
#define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10
|
| 353 |
|
|
#define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11
|
| 354 |
|
|
#define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12
|
| 355 |
|
|
#define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13
|
| 356 |
|
|
#define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14
|
| 357 |
|
|
#define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15
|
| 358 |
|
|
#define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8
|
| 359 |
|
|
#define TC0Hi_BIT TC0Hi_BIT_8
|
| 360 |
|
|
|
| 361 |
|
|
/*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/
|
| 362 |
|
|
union {
|
| 363 |
|
|
byte Byte;
|
| 364 |
|
|
struct {
|
| 365 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */
|
| 366 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */
|
| 367 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */
|
| 368 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */
|
| 369 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */
|
| 370 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */
|
| 371 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */
|
| 372 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */
|
| 373 |
|
|
} Bits;
|
| 374 |
|
|
struct {
|
| 375 |
|
|
byte grpBIT :8;
|
| 376 |
|
|
} MergedBits;
|
| 377 |
|
|
} TC0LoSTR;
|
| 378 |
|
|
#define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte
|
| 379 |
|
|
#define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0
|
| 380 |
|
|
#define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1
|
| 381 |
|
|
#define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2
|
| 382 |
|
|
#define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3
|
| 383 |
|
|
#define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4
|
| 384 |
|
|
#define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5
|
| 385 |
|
|
#define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6
|
| 386 |
|
|
#define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7
|
| 387 |
|
|
#define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT
|
| 388 |
|
|
|
| 389 |
|
|
} Overlap_STR;
|
| 390 |
|
|
|
| 391 |
|
|
struct {
|
| 392 |
|
|
word grpBIT :16;
|
| 393 |
|
|
} MergedBits;
|
| 394 |
|
|
} TC0STR;
|
| 395 |
|
|
extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050);
|
| 396 |
|
|
#define TC0 _TC0.Word
|
| 397 |
|
|
#define TC0_BIT _TC0.MergedBits.grpBIT
|
| 398 |
|
|
|
| 399 |
|
|
|
| 400 |
|
|
/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/
|
| 401 |
|
|
typedef union {
|
| 402 |
|
|
word Word;
|
| 403 |
|
|
/* Overlapped registers: */
|
| 404 |
|
|
struct {
|
| 405 |
|
|
/*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/
|
| 406 |
|
|
union {
|
| 407 |
|
|
byte Byte;
|
| 408 |
|
|
struct {
|
| 409 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */
|
| 410 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */
|
| 411 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */
|
| 412 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */
|
| 413 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */
|
| 414 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */
|
| 415 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */
|
| 416 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */
|
| 417 |
|
|
} Bits;
|
| 418 |
|
|
struct {
|
| 419 |
|
|
byte grpBIT_8 :8;
|
| 420 |
|
|
} MergedBits;
|
| 421 |
|
|
} TC1HiSTR;
|
| 422 |
|
|
#define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte
|
| 423 |
|
|
#define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8
|
| 424 |
|
|
#define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9
|
| 425 |
|
|
#define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10
|
| 426 |
|
|
#define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11
|
| 427 |
|
|
#define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12
|
| 428 |
|
|
#define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13
|
| 429 |
|
|
#define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14
|
| 430 |
|
|
#define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15
|
| 431 |
|
|
#define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8
|
| 432 |
|
|
#define TC1Hi_BIT TC1Hi_BIT_8
|
| 433 |
|
|
|
| 434 |
|
|
/*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/
|
| 435 |
|
|
union {
|
| 436 |
|
|
byte Byte;
|
| 437 |
|
|
struct {
|
| 438 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */
|
| 439 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */
|
| 440 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */
|
| 441 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */
|
| 442 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */
|
| 443 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */
|
| 444 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */
|
| 445 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */
|
| 446 |
|
|
} Bits;
|
| 447 |
|
|
struct {
|
| 448 |
|
|
byte grpBIT :8;
|
| 449 |
|
|
} MergedBits;
|
| 450 |
|
|
} TC1LoSTR;
|
| 451 |
|
|
#define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte
|
| 452 |
|
|
#define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0
|
| 453 |
|
|
#define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1
|
| 454 |
|
|
#define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2
|
| 455 |
|
|
#define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3
|
| 456 |
|
|
#define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4
|
| 457 |
|
|
#define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5
|
| 458 |
|
|
#define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6
|
| 459 |
|
|
#define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7
|
| 460 |
|
|
#define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT
|
| 461 |
|
|
|
| 462 |
|
|
} Overlap_STR;
|
| 463 |
|
|
|
| 464 |
|
|
struct {
|
| 465 |
|
|
word grpBIT :16;
|
| 466 |
|
|
} MergedBits;
|
| 467 |
|
|
} TC1STR;
|
| 468 |
|
|
extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052);
|
| 469 |
|
|
#define TC1 _TC1.Word
|
| 470 |
|
|
#define TC1_BIT _TC1.MergedBits.grpBIT
|
| 471 |
|
|
|
| 472 |
|
|
|
| 473 |
|
|
/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/
|
| 474 |
|
|
typedef union {
|
| 475 |
|
|
word Word;
|
| 476 |
|
|
/* Overlapped registers: */
|
| 477 |
|
|
struct {
|
| 478 |
|
|
/*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/
|
| 479 |
|
|
union {
|
| 480 |
|
|
byte Byte;
|
| 481 |
|
|
struct {
|
| 482 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */
|
| 483 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */
|
| 484 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */
|
| 485 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */
|
| 486 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */
|
| 487 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */
|
| 488 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */
|
| 489 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */
|
| 490 |
|
|
} Bits;
|
| 491 |
|
|
struct {
|
| 492 |
|
|
byte grpBIT_8 :8;
|
| 493 |
|
|
} MergedBits;
|
| 494 |
|
|
} TC2HiSTR;
|
| 495 |
|
|
#define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte
|
| 496 |
|
|
#define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8
|
| 497 |
|
|
#define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9
|
| 498 |
|
|
#define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10
|
| 499 |
|
|
#define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11
|
| 500 |
|
|
#define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12
|
| 501 |
|
|
#define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13
|
| 502 |
|
|
#define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14
|
| 503 |
|
|
#define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15
|
| 504 |
|
|
#define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8
|
| 505 |
|
|
#define TC2Hi_BIT TC2Hi_BIT_8
|
| 506 |
|
|
|
| 507 |
|
|
/*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/
|
| 508 |
|
|
union {
|
| 509 |
|
|
byte Byte;
|
| 510 |
|
|
struct {
|
| 511 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */
|
| 512 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */
|
| 513 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */
|
| 514 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */
|
| 515 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */
|
| 516 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */
|
| 517 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */
|
| 518 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */
|
| 519 |
|
|
} Bits;
|
| 520 |
|
|
struct {
|
| 521 |
|
|
byte grpBIT :8;
|
| 522 |
|
|
} MergedBits;
|
| 523 |
|
|
} TC2LoSTR;
|
| 524 |
|
|
#define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte
|
| 525 |
|
|
#define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0
|
| 526 |
|
|
#define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1
|
| 527 |
|
|
#define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2
|
| 528 |
|
|
#define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3
|
| 529 |
|
|
#define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4
|
| 530 |
|
|
#define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5
|
| 531 |
|
|
#define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6
|
| 532 |
|
|
#define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7
|
| 533 |
|
|
#define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT
|
| 534 |
|
|
|
| 535 |
|
|
} Overlap_STR;
|
| 536 |
|
|
|
| 537 |
|
|
struct {
|
| 538 |
|
|
word grpBIT :16;
|
| 539 |
|
|
} MergedBits;
|
| 540 |
|
|
} TC2STR;
|
| 541 |
|
|
extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054);
|
| 542 |
|
|
#define TC2 _TC2.Word
|
| 543 |
|
|
#define TC2_BIT _TC2.MergedBits.grpBIT
|
| 544 |
|
|
|
| 545 |
|
|
|
| 546 |
|
|
/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/
|
| 547 |
|
|
typedef union {
|
| 548 |
|
|
word Word;
|
| 549 |
|
|
/* Overlapped registers: */
|
| 550 |
|
|
struct {
|
| 551 |
|
|
/*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/
|
| 552 |
|
|
union {
|
| 553 |
|
|
byte Byte;
|
| 554 |
|
|
struct {
|
| 555 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */
|
| 556 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */
|
| 557 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */
|
| 558 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */
|
| 559 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */
|
| 560 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */
|
| 561 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */
|
| 562 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */
|
| 563 |
|
|
} Bits;
|
| 564 |
|
|
struct {
|
| 565 |
|
|
byte grpBIT_8 :8;
|
| 566 |
|
|
} MergedBits;
|
| 567 |
|
|
} TC3HiSTR;
|
| 568 |
|
|
#define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte
|
| 569 |
|
|
#define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8
|
| 570 |
|
|
#define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9
|
| 571 |
|
|
#define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10
|
| 572 |
|
|
#define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11
|
| 573 |
|
|
#define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12
|
| 574 |
|
|
#define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13
|
| 575 |
|
|
#define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14
|
| 576 |
|
|
#define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15
|
| 577 |
|
|
#define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8
|
| 578 |
|
|
#define TC3Hi_BIT TC3Hi_BIT_8
|
| 579 |
|
|
|
| 580 |
|
|
/*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/
|
| 581 |
|
|
union {
|
| 582 |
|
|
byte Byte;
|
| 583 |
|
|
struct {
|
| 584 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */
|
| 585 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */
|
| 586 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */
|
| 587 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */
|
| 588 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */
|
| 589 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */
|
| 590 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */
|
| 591 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */
|
| 592 |
|
|
} Bits;
|
| 593 |
|
|
struct {
|
| 594 |
|
|
byte grpBIT :8;
|
| 595 |
|
|
} MergedBits;
|
| 596 |
|
|
} TC3LoSTR;
|
| 597 |
|
|
#define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte
|
| 598 |
|
|
#define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0
|
| 599 |
|
|
#define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1
|
| 600 |
|
|
#define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2
|
| 601 |
|
|
#define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3
|
| 602 |
|
|
#define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4
|
| 603 |
|
|
#define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5
|
| 604 |
|
|
#define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6
|
| 605 |
|
|
#define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7
|
| 606 |
|
|
#define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT
|
| 607 |
|
|
|
| 608 |
|
|
} Overlap_STR;
|
| 609 |
|
|
|
| 610 |
|
|
struct {
|
| 611 |
|
|
word grpBIT :16;
|
| 612 |
|
|
} MergedBits;
|
| 613 |
|
|
} TC3STR;
|
| 614 |
|
|
extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056);
|
| 615 |
|
|
#define TC3 _TC3.Word
|
| 616 |
|
|
#define TC3_BIT _TC3.MergedBits.grpBIT
|
| 617 |
|
|
|
| 618 |
|
|
|
| 619 |
|
|
/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/
|
| 620 |
|
|
typedef union {
|
| 621 |
|
|
word Word;
|
| 622 |
|
|
/* Overlapped registers: */
|
| 623 |
|
|
struct {
|
| 624 |
|
|
/*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/
|
| 625 |
|
|
union {
|
| 626 |
|
|
byte Byte;
|
| 627 |
|
|
struct {
|
| 628 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */
|
| 629 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */
|
| 630 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */
|
| 631 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */
|
| 632 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */
|
| 633 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */
|
| 634 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */
|
| 635 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */
|
| 636 |
|
|
} Bits;
|
| 637 |
|
|
struct {
|
| 638 |
|
|
byte grpBIT_8 :8;
|
| 639 |
|
|
} MergedBits;
|
| 640 |
|
|
} TC4HiSTR;
|
| 641 |
|
|
#define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte
|
| 642 |
|
|
#define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8
|
| 643 |
|
|
#define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9
|
| 644 |
|
|
#define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10
|
| 645 |
|
|
#define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11
|
| 646 |
|
|
#define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12
|
| 647 |
|
|
#define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13
|
| 648 |
|
|
#define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14
|
| 649 |
|
|
#define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15
|
| 650 |
|
|
#define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8
|
| 651 |
|
|
#define TC4Hi_BIT TC4Hi_BIT_8
|
| 652 |
|
|
|
| 653 |
|
|
/*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/
|
| 654 |
|
|
union {
|
| 655 |
|
|
byte Byte;
|
| 656 |
|
|
struct {
|
| 657 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */
|
| 658 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */
|
| 659 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */
|
| 660 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */
|
| 661 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */
|
| 662 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */
|
| 663 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */
|
| 664 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */
|
| 665 |
|
|
} Bits;
|
| 666 |
|
|
struct {
|
| 667 |
|
|
byte grpBIT :8;
|
| 668 |
|
|
} MergedBits;
|
| 669 |
|
|
} TC4LoSTR;
|
| 670 |
|
|
#define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte
|
| 671 |
|
|
#define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0
|
| 672 |
|
|
#define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1
|
| 673 |
|
|
#define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2
|
| 674 |
|
|
#define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3
|
| 675 |
|
|
#define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4
|
| 676 |
|
|
#define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5
|
| 677 |
|
|
#define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6
|
| 678 |
|
|
#define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7
|
| 679 |
|
|
#define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT
|
| 680 |
|
|
|
| 681 |
|
|
} Overlap_STR;
|
| 682 |
|
|
|
| 683 |
|
|
struct {
|
| 684 |
|
|
word grpBIT :16;
|
| 685 |
|
|
} MergedBits;
|
| 686 |
|
|
} TC4STR;
|
| 687 |
|
|
extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058);
|
| 688 |
|
|
#define TC4 _TC4.Word
|
| 689 |
|
|
#define TC4_BIT _TC4.MergedBits.grpBIT
|
| 690 |
|
|
|
| 691 |
|
|
|
| 692 |
|
|
/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/
|
| 693 |
|
|
typedef union {
|
| 694 |
|
|
word Word;
|
| 695 |
|
|
/* Overlapped registers: */
|
| 696 |
|
|
struct {
|
| 697 |
|
|
/*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/
|
| 698 |
|
|
union {
|
| 699 |
|
|
byte Byte;
|
| 700 |
|
|
struct {
|
| 701 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */
|
| 702 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */
|
| 703 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */
|
| 704 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */
|
| 705 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */
|
| 706 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */
|
| 707 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */
|
| 708 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */
|
| 709 |
|
|
} Bits;
|
| 710 |
|
|
struct {
|
| 711 |
|
|
byte grpBIT_8 :8;
|
| 712 |
|
|
} MergedBits;
|
| 713 |
|
|
} TC5HiSTR;
|
| 714 |
|
|
#define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte
|
| 715 |
|
|
#define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8
|
| 716 |
|
|
#define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9
|
| 717 |
|
|
#define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10
|
| 718 |
|
|
#define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11
|
| 719 |
|
|
#define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12
|
| 720 |
|
|
#define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13
|
| 721 |
|
|
#define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14
|
| 722 |
|
|
#define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15
|
| 723 |
|
|
#define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8
|
| 724 |
|
|
#define TC5Hi_BIT TC5Hi_BIT_8
|
| 725 |
|
|
|
| 726 |
|
|
/*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/
|
| 727 |
|
|
union {
|
| 728 |
|
|
byte Byte;
|
| 729 |
|
|
struct {
|
| 730 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */
|
| 731 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */
|
| 732 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */
|
| 733 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */
|
| 734 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */
|
| 735 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */
|
| 736 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */
|
| 737 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */
|
| 738 |
|
|
} Bits;
|
| 739 |
|
|
struct {
|
| 740 |
|
|
byte grpBIT :8;
|
| 741 |
|
|
} MergedBits;
|
| 742 |
|
|
} TC5LoSTR;
|
| 743 |
|
|
#define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte
|
| 744 |
|
|
#define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0
|
| 745 |
|
|
#define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1
|
| 746 |
|
|
#define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2
|
| 747 |
|
|
#define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3
|
| 748 |
|
|
#define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4
|
| 749 |
|
|
#define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5
|
| 750 |
|
|
#define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6
|
| 751 |
|
|
#define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7
|
| 752 |
|
|
#define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT
|
| 753 |
|
|
|
| 754 |
|
|
} Overlap_STR;
|
| 755 |
|
|
|
| 756 |
|
|
struct {
|
| 757 |
|
|
word grpBIT :16;
|
| 758 |
|
|
} MergedBits;
|
| 759 |
|
|
} TC5STR;
|
| 760 |
|
|
extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A);
|
| 761 |
|
|
#define TC5 _TC5.Word
|
| 762 |
|
|
#define TC5_BIT _TC5.MergedBits.grpBIT
|
| 763 |
|
|
|
| 764 |
|
|
|
| 765 |
|
|
/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/
|
| 766 |
|
|
typedef union {
|
| 767 |
|
|
word Word;
|
| 768 |
|
|
/* Overlapped registers: */
|
| 769 |
|
|
struct {
|
| 770 |
|
|
/*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/
|
| 771 |
|
|
union {
|
| 772 |
|
|
byte Byte;
|
| 773 |
|
|
struct {
|
| 774 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */
|
| 775 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */
|
| 776 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */
|
| 777 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */
|
| 778 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */
|
| 779 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */
|
| 780 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */
|
| 781 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */
|
| 782 |
|
|
} Bits;
|
| 783 |
|
|
struct {
|
| 784 |
|
|
byte grpBIT_8 :8;
|
| 785 |
|
|
} MergedBits;
|
| 786 |
|
|
} TC6HiSTR;
|
| 787 |
|
|
#define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte
|
| 788 |
|
|
#define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8
|
| 789 |
|
|
#define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9
|
| 790 |
|
|
#define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10
|
| 791 |
|
|
#define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11
|
| 792 |
|
|
#define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12
|
| 793 |
|
|
#define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13
|
| 794 |
|
|
#define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14
|
| 795 |
|
|
#define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15
|
| 796 |
|
|
#define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8
|
| 797 |
|
|
#define TC6Hi_BIT TC6Hi_BIT_8
|
| 798 |
|
|
|
| 799 |
|
|
/*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/
|
| 800 |
|
|
union {
|
| 801 |
|
|
byte Byte;
|
| 802 |
|
|
struct {
|
| 803 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */
|
| 804 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */
|
| 805 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */
|
| 806 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */
|
| 807 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */
|
| 808 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */
|
| 809 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */
|
| 810 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */
|
| 811 |
|
|
} Bits;
|
| 812 |
|
|
struct {
|
| 813 |
|
|
byte grpBIT :8;
|
| 814 |
|
|
} MergedBits;
|
| 815 |
|
|
} TC6LoSTR;
|
| 816 |
|
|
#define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte
|
| 817 |
|
|
#define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0
|
| 818 |
|
|
#define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1
|
| 819 |
|
|
#define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2
|
| 820 |
|
|
#define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3
|
| 821 |
|
|
#define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4
|
| 822 |
|
|
#define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5
|
| 823 |
|
|
#define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6
|
| 824 |
|
|
#define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7
|
| 825 |
|
|
#define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT
|
| 826 |
|
|
|
| 827 |
|
|
} Overlap_STR;
|
| 828 |
|
|
|
| 829 |
|
|
struct {
|
| 830 |
|
|
word grpBIT :16;
|
| 831 |
|
|
} MergedBits;
|
| 832 |
|
|
} TC6STR;
|
| 833 |
|
|
extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C);
|
| 834 |
|
|
#define TC6 _TC6.Word
|
| 835 |
|
|
#define TC6_BIT _TC6.MergedBits.grpBIT
|
| 836 |
|
|
|
| 837 |
|
|
|
| 838 |
|
|
/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/
|
| 839 |
|
|
typedef union {
|
| 840 |
|
|
word Word;
|
| 841 |
|
|
/* Overlapped registers: */
|
| 842 |
|
|
struct {
|
| 843 |
|
|
/*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/
|
| 844 |
|
|
union {
|
| 845 |
|
|
byte Byte;
|
| 846 |
|
|
struct {
|
| 847 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */
|
| 848 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */
|
| 849 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */
|
| 850 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */
|
| 851 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */
|
| 852 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */
|
| 853 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */
|
| 854 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */
|
| 855 |
|
|
} Bits;
|
| 856 |
|
|
struct {
|
| 857 |
|
|
byte grpBIT_8 :8;
|
| 858 |
|
|
} MergedBits;
|
| 859 |
|
|
} TC7HiSTR;
|
| 860 |
|
|
#define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte
|
| 861 |
|
|
#define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8
|
| 862 |
|
|
#define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9
|
| 863 |
|
|
#define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10
|
| 864 |
|
|
#define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11
|
| 865 |
|
|
#define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12
|
| 866 |
|
|
#define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13
|
| 867 |
|
|
#define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14
|
| 868 |
|
|
#define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15
|
| 869 |
|
|
#define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8
|
| 870 |
|
|
#define TC7Hi_BIT TC7Hi_BIT_8
|
| 871 |
|
|
|
| 872 |
|
|
/*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/
|
| 873 |
|
|
union {
|
| 874 |
|
|
byte Byte;
|
| 875 |
|
|
struct {
|
| 876 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */
|
| 877 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */
|
| 878 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */
|
| 879 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */
|
| 880 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */
|
| 881 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */
|
| 882 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */
|
| 883 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */
|
| 884 |
|
|
} Bits;
|
| 885 |
|
|
struct {
|
| 886 |
|
|
byte grpBIT :8;
|
| 887 |
|
|
} MergedBits;
|
| 888 |
|
|
} TC7LoSTR;
|
| 889 |
|
|
#define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte
|
| 890 |
|
|
#define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0
|
| 891 |
|
|
#define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1
|
| 892 |
|
|
#define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2
|
| 893 |
|
|
#define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3
|
| 894 |
|
|
#define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4
|
| 895 |
|
|
#define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5
|
| 896 |
|
|
#define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6
|
| 897 |
|
|
#define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7
|
| 898 |
|
|
#define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT
|
| 899 |
|
|
|
| 900 |
|
|
} Overlap_STR;
|
| 901 |
|
|
|
| 902 |
|
|
struct {
|
| 903 |
|
|
word grpBIT :16;
|
| 904 |
|
|
} MergedBits;
|
| 905 |
|
|
} TC7STR;
|
| 906 |
|
|
extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E);
|
| 907 |
|
|
#define TC7 _TC7.Word
|
| 908 |
|
|
#define TC7_BIT _TC7.MergedBits.grpBIT
|
| 909 |
|
|
|
| 910 |
|
|
|
| 911 |
|
|
/*** PACN32 - Pulse Accumulators Count 32 Register; 0x00000062 ***/
|
| 912 |
|
|
typedef union {
|
| 913 |
|
|
word Word;
|
| 914 |
|
|
/* Overlapped registers: */
|
| 915 |
|
|
struct {
|
| 916 |
|
|
/*** PACN3 - Pulse Accumulators Count 3 Register; 0x00000062 ***/
|
| 917 |
|
|
union {
|
| 918 |
|
|
byte Byte;
|
| 919 |
|
|
struct {
|
| 920 |
|
|
byte grpBIT :8;
|
| 921 |
|
|
} MergedBits;
|
| 922 |
|
|
} PACN3STR;
|
| 923 |
|
|
#define PACN3 _PACN32.Overlap_STR.PACN3STR.Byte
|
| 924 |
|
|
#define PACN3_BIT _PACN32.Overlap_STR.PACN3STR.MergedBits.grpBIT
|
| 925 |
|
|
|
| 926 |
|
|
/*** PACN2 - Pulse Accumulators Count 2 Register; 0x00000063 ***/
|
| 927 |
|
|
union {
|
| 928 |
|
|
byte Byte;
|
| 929 |
|
|
struct {
|
| 930 |
|
|
byte grpBIT :8;
|
| 931 |
|
|
} MergedBits;
|
| 932 |
|
|
} PACN2STR;
|
| 933 |
|
|
#define PACN2 _PACN32.Overlap_STR.PACN2STR.Byte
|
| 934 |
|
|
#define PACN2_BIT _PACN32.Overlap_STR.PACN2STR.MergedBits.grpBIT
|
| 935 |
|
|
|
| 936 |
|
|
} Overlap_STR;
|
| 937 |
|
|
|
| 938 |
|
|
struct {
|
| 939 |
|
|
word grpBIT :16;
|
| 940 |
|
|
} MergedBits;
|
| 941 |
|
|
} PACN32STR;
|
| 942 |
|
|
extern volatile PACN32STR _PACN32 @(REG_BASE + 0x00000062);
|
| 943 |
|
|
#define PACN32 _PACN32.Word
|
| 944 |
|
|
#define PACN32_BIT _PACN32.MergedBits.grpBIT
|
| 945 |
|
|
|
| 946 |
|
|
|
| 947 |
|
|
/*** PACN10 - Pulse Accumulators Count 10 Register; 0x00000064 ***/
|
| 948 |
|
|
typedef union {
|
| 949 |
|
|
word Word;
|
| 950 |
|
|
/* Overlapped registers: */
|
| 951 |
|
|
struct {
|
| 952 |
|
|
/*** PACN1 - Pulse Accumulators Count 1 Register; 0x00000064 ***/
|
| 953 |
|
|
union {
|
| 954 |
|
|
byte Byte;
|
| 955 |
|
|
struct {
|
| 956 |
|
|
byte grpBIT :8;
|
| 957 |
|
|
} MergedBits;
|
| 958 |
|
|
} PACN1STR;
|
| 959 |
|
|
#define PACN1 _PACN10.Overlap_STR.PACN1STR.Byte
|
| 960 |
|
|
#define PACN1_BIT _PACN10.Overlap_STR.PACN1STR.MergedBits.grpBIT
|
| 961 |
|
|
|
| 962 |
|
|
/*** PACN0 - Pulse Accumulators Count 0 Register; 0x00000065 ***/
|
| 963 |
|
|
union {
|
| 964 |
|
|
byte Byte;
|
| 965 |
|
|
struct {
|
| 966 |
|
|
byte grpBIT :8;
|
| 967 |
|
|
} MergedBits;
|
| 968 |
|
|
} PACN0STR;
|
| 969 |
|
|
#define PACN0 _PACN10.Overlap_STR.PACN0STR.Byte
|
| 970 |
|
|
#define PACN0_BIT _PACN10.Overlap_STR.PACN0STR.MergedBits.grpBIT
|
| 971 |
|
|
|
| 972 |
|
|
} Overlap_STR;
|
| 973 |
|
|
|
| 974 |
|
|
struct {
|
| 975 |
|
|
word grpBIT :16;
|
| 976 |
|
|
} MergedBits;
|
| 977 |
|
|
} PACN10STR;
|
| 978 |
|
|
extern volatile PACN10STR _PACN10 @(REG_BASE + 0x00000064);
|
| 979 |
|
|
#define PACN10 _PACN10.Word
|
| 980 |
|
|
#define PACN10_BIT _PACN10.MergedBits.grpBIT
|
| 981 |
|
|
|
| 982 |
|
|
|
| 983 |
|
|
/*** PA32H - 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 ***/
|
| 984 |
|
|
typedef union {
|
| 985 |
|
|
word Word;
|
| 986 |
|
|
/* Overlapped registers: */
|
| 987 |
|
|
struct {
|
| 988 |
|
|
/*** PA3H - 8-Bit Pulse Accumulators Holding 3 Register; 0x00000072 ***/
|
| 989 |
|
|
union {
|
| 990 |
|
|
byte Byte;
|
| 991 |
|
|
struct {
|
| 992 |
|
|
byte BIT0 :1; /* Pulse Accumulator Bit 0 */
|
| 993 |
|
|
byte BIT1 :1; /* Pulse Accumulator Bit 1 */
|
| 994 |
|
|
byte BIT2 :1; /* Pulse Accumulator Bit 2 */
|
| 995 |
|
|
byte BIT3 :1; /* Pulse Accumulator Bit 3 */
|
| 996 |
|
|
byte BIT4 :1; /* Pulse Accumulator Bit 4 */
|
| 997 |
|
|
byte BIT5 :1; /* Pulse Accumulator Bit 5 */
|
| 998 |
|
|
byte BIT6 :1; /* Pulse Accumulator Bit 6 */
|
| 999 |
|
|
byte BIT7 :1; /* Pulse Accumulator Bit 7 */
|
| 1000 |
|
|
} Bits;
|
| 1001 |
|
|
struct {
|
| 1002 |
|
|
byte grpBIT :8;
|
| 1003 |
|
|
} MergedBits;
|
| 1004 |
|
|
} PA3HSTR;
|
| 1005 |
|
|
#define PA3H _PA32H.Overlap_STR.PA3HSTR.Byte
|
| 1006 |
|
|
#define PA3H_BIT0 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT0
|
| 1007 |
|
|
#define PA3H_BIT1 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT1
|
| 1008 |
|
|
#define PA3H_BIT2 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT2
|
| 1009 |
|
|
#define PA3H_BIT3 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT3
|
| 1010 |
|
|
#define PA3H_BIT4 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT4
|
| 1011 |
|
|
#define PA3H_BIT5 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT5
|
| 1012 |
|
|
#define PA3H_BIT6 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT6
|
| 1013 |
|
|
#define PA3H_BIT7 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT7
|
| 1014 |
|
|
#define PA3H_BIT _PA32H.Overlap_STR.PA3HSTR.MergedBits.grpBIT
|
| 1015 |
|
|
|
| 1016 |
|
|
/*** PA2H - 8-Bit Pulse Accumulators Holding 2 Register; 0x00000073 ***/
|
| 1017 |
|
|
union {
|
| 1018 |
|
|
byte Byte;
|
| 1019 |
|
|
struct {
|
| 1020 |
|
|
byte BIT0 :1; /* Pulse Accumulator Bit 0 */
|
| 1021 |
|
|
byte BIT1 :1; /* Pulse Accumulator Bit 1 */
|
| 1022 |
|
|
byte BIT2 :1; /* Pulse Accumulator Bit 2 */
|
| 1023 |
|
|
byte BIT3 :1; /* Pulse Accumulator Bit 3 */
|
| 1024 |
|
|
byte BIT4 :1; /* Pulse Accumulator Bit 4 */
|
| 1025 |
|
|
byte BIT5 :1; /* Pulse Accumulator Bit 5 */
|
| 1026 |
|
|
byte BIT6 :1; /* Pulse Accumulator Bit 6 */
|
| 1027 |
|
|
byte BIT7 :1; /* Pulse Accumulator Bit 7 */
|
| 1028 |
|
|
} Bits;
|
| 1029 |
|
|
struct {
|
| 1030 |
|
|
byte grpBIT :8;
|
| 1031 |
|
|
} MergedBits;
|
| 1032 |
|
|
} PA2HSTR;
|
| 1033 |
|
|
#define PA2H _PA32H.Overlap_STR.PA2HSTR.Byte
|
| 1034 |
|
|
#define PA2H_BIT0 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT0
|
| 1035 |
|
|
#define PA2H_BIT1 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT1
|
| 1036 |
|
|
#define PA2H_BIT2 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT2
|
| 1037 |
|
|
#define PA2H_BIT3 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT3
|
| 1038 |
|
|
#define PA2H_BIT4 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT4
|
| 1039 |
|
|
#define PA2H_BIT5 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT5
|
| 1040 |
|
|
#define PA2H_BIT6 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT6
|
| 1041 |
|
|
#define PA2H_BIT7 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT7
|
| 1042 |
|
|
#define PA2H_BIT _PA32H.Overlap_STR.PA2HSTR.MergedBits.grpBIT
|
| 1043 |
|
|
|
| 1044 |
|
|
} Overlap_STR;
|
| 1045 |
|
|
|
| 1046 |
|
|
struct {
|
| 1047 |
|
|
word BIT0 :1; /* Pulse Accumulator Bit 0 */
|
| 1048 |
|
|
word BIT1 :1; /* Pulse Accumulator Bit 1 */
|
| 1049 |
|
|
word BIT2 :1; /* Pulse Accumulator Bit 2 */
|
| 1050 |
|
|
word BIT3 :1; /* Pulse Accumulator Bit 3 */
|
| 1051 |
|
|
word BIT4 :1; /* Pulse Accumulator Bit 4 */
|
| 1052 |
|
|
word BIT5 :1; /* Pulse Accumulator Bit 5 */
|
| 1053 |
|
|
word BIT6 :1; /* Pulse Accumulator Bit 6 */
|
| 1054 |
|
|
word BIT7 :1; /* Pulse Accumulator Bit 7 */
|
| 1055 |
|
|
word BIT8 :1; /* Pulse Accumulator Bit 8 */
|
| 1056 |
|
|
word BIT9 :1; /* Pulse Accumulator Bit 9 */
|
| 1057 |
|
|
word BIT10 :1; /* Pulse Accumulator Bit 10 */
|
| 1058 |
|
|
word BIT11 :1; /* Pulse Accumulator Bit 11 */
|
| 1059 |
|
|
word BIT12 :1; /* Pulse Accumulator Bit 12 */
|
| 1060 |
|
|
word BIT13 :1; /* Pulse Accumulator Bit 13 */
|
| 1061 |
|
|
word BIT14 :1; /* Pulse Accumulator Bit 14 */
|
| 1062 |
|
|
word BIT15 :1; /* Pulse Accumulator Bit 15 */
|
| 1063 |
|
|
} Bits;
|
| 1064 |
|
|
struct {
|
| 1065 |
|
|
word grpBIT :16;
|
| 1066 |
|
|
} MergedBits;
|
| 1067 |
|
|
} PA32HSTR;
|
| 1068 |
|
|
extern volatile PA32HSTR _PA32H @(REG_BASE + 0x00000072);
|
| 1069 |
|
|
#define PA32H _PA32H.Word
|
| 1070 |
|
|
#define PA32H_BIT0 _PA32H.Bits.BIT0
|
| 1071 |
|
|
#define PA32H_BIT1 _PA32H.Bits.BIT1
|
| 1072 |
|
|
#define PA32H_BIT2 _PA32H.Bits.BIT2
|
| 1073 |
|
|
#define PA32H_BIT3 _PA32H.Bits.BIT3
|
| 1074 |
|
|
#define PA32H_BIT4 _PA32H.Bits.BIT4
|
| 1075 |
|
|
#define PA32H_BIT5 _PA32H.Bits.BIT5
|
| 1076 |
|
|
#define PA32H_BIT6 _PA32H.Bits.BIT6
|
| 1077 |
|
|
#define PA32H_BIT7 _PA32H.Bits.BIT7
|
| 1078 |
|
|
#define PA32H_BIT8 _PA32H.Bits.BIT8
|
| 1079 |
|
|
#define PA32H_BIT9 _PA32H.Bits.BIT9
|
| 1080 |
|
|
#define PA32H_BIT10 _PA32H.Bits.BIT10
|
| 1081 |
|
|
#define PA32H_BIT11 _PA32H.Bits.BIT11
|
| 1082 |
|
|
#define PA32H_BIT12 _PA32H.Bits.BIT12
|
| 1083 |
|
|
#define PA32H_BIT13 _PA32H.Bits.BIT13
|
| 1084 |
|
|
#define PA32H_BIT14 _PA32H.Bits.BIT14
|
| 1085 |
|
|
#define PA32H_BIT15 _PA32H.Bits.BIT15
|
| 1086 |
|
|
#define PA32H_BIT _PA32H.MergedBits.grpBIT
|
| 1087 |
|
|
|
| 1088 |
|
|
|
| 1089 |
|
|
/*** PA10H - 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 ***/
|
| 1090 |
|
|
typedef union {
|
| 1091 |
|
|
word Word;
|
| 1092 |
|
|
/* Overlapped registers: */
|
| 1093 |
|
|
struct {
|
| 1094 |
|
|
/*** PA1H - 8-Bit Pulse Accumulators Holding 1 Register; 0x00000074 ***/
|
| 1095 |
|
|
union {
|
| 1096 |
|
|
byte Byte;
|
| 1097 |
|
|
struct {
|
| 1098 |
|
|
byte BIT0 :1; /* Pulse Accumulator Bit 0 */
|
| 1099 |
|
|
byte BIT1 :1; /* Pulse Accumulator Bit 1 */
|
| 1100 |
|
|
byte BIT2 :1; /* Pulse Accumulator Bit 2 */
|
| 1101 |
|
|
byte BIT3 :1; /* Pulse Accumulator Bit 3 */
|
| 1102 |
|
|
byte BIT4 :1; /* Pulse Accumulator Bit 4 */
|
| 1103 |
|
|
byte BIT5 :1; /* Pulse Accumulator Bit 5 */
|
| 1104 |
|
|
byte BIT6 :1; /* Pulse Accumulator Bit 6 */
|
| 1105 |
|
|
byte BIT7 :1; /* Pulse Accumulator Bit 7 */
|
| 1106 |
|
|
} Bits;
|
| 1107 |
|
|
struct {
|
| 1108 |
|
|
byte grpBIT :8;
|
| 1109 |
|
|
} MergedBits;
|
| 1110 |
|
|
} PA1HSTR;
|
| 1111 |
|
|
#define PA1H _PA10H.Overlap_STR.PA1HSTR.Byte
|
| 1112 |
|
|
#define PA1H_BIT0 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT0
|
| 1113 |
|
|
#define PA1H_BIT1 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT1
|
| 1114 |
|
|
#define PA1H_BIT2 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT2
|
| 1115 |
|
|
#define PA1H_BIT3 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT3
|
| 1116 |
|
|
#define PA1H_BIT4 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT4
|
| 1117 |
|
|
#define PA1H_BIT5 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT5
|
| 1118 |
|
|
#define PA1H_BIT6 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT6
|
| 1119 |
|
|
#define PA1H_BIT7 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT7
|
| 1120 |
|
|
#define PA1H_BIT _PA10H.Overlap_STR.PA1HSTR.MergedBits.grpBIT
|
| 1121 |
|
|
|
| 1122 |
|
|
/*** PA0H - 8-Bit Pulse Accumulators Holding 0 Register; 0x00000075 ***/
|
| 1123 |
|
|
union {
|
| 1124 |
|
|
byte Byte;
|
| 1125 |
|
|
struct {
|
| 1126 |
|
|
byte BIT0 :1; /* Pulse Accumulator Bit 0 */
|
| 1127 |
|
|
byte BIT1 :1; /* Pulse Accumulator Bit 1 */
|
| 1128 |
|
|
byte BIT2 :1; /* Pulse Accumulator Bit 2 */
|
| 1129 |
|
|
byte BIT3 :1; /* Pulse Accumulator Bit 3 */
|
| 1130 |
|
|
byte BIT4 :1; /* Pulse Accumulator Bit 4 */
|
| 1131 |
|
|
byte BIT5 :1; /* Pulse Accumulator Bit 5 */
|
| 1132 |
|
|
byte BIT6 :1; /* Pulse Accumulator Bit 6 */
|
| 1133 |
|
|
byte BIT7 :1; /* Pulse Accumulator Bit 7 */
|
| 1134 |
|
|
} Bits;
|
| 1135 |
|
|
struct {
|
| 1136 |
|
|
byte grpBIT :8;
|
| 1137 |
|
|
} MergedBits;
|
| 1138 |
|
|
} PA0HSTR;
|
| 1139 |
|
|
#define PA0H _PA10H.Overlap_STR.PA0HSTR.Byte
|
| 1140 |
|
|
#define PA0H_BIT0 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT0
|
| 1141 |
|
|
#define PA0H_BIT1 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT1
|
| 1142 |
|
|
#define PA0H_BIT2 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT2
|
| 1143 |
|
|
#define PA0H_BIT3 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT3
|
| 1144 |
|
|
#define PA0H_BIT4 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT4
|
| 1145 |
|
|
#define PA0H_BIT5 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT5
|
| 1146 |
|
|
#define PA0H_BIT6 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT6
|
| 1147 |
|
|
#define PA0H_BIT7 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT7
|
| 1148 |
|
|
#define PA0H_BIT _PA10H.Overlap_STR.PA0HSTR.MergedBits.grpBIT
|
| 1149 |
|
|
|
| 1150 |
|
|
} Overlap_STR;
|
| 1151 |
|
|
|
| 1152 |
|
|
struct {
|
| 1153 |
|
|
word BIT0 :1; /* Pulse Accumulator Bit 0 */
|
| 1154 |
|
|
word BIT1 :1; /* Pulse Accumulator Bit 1 */
|
| 1155 |
|
|
word BIT2 :1; /* Pulse Accumulator Bit 2 */
|
| 1156 |
|
|
word BIT3 :1; /* Pulse Accumulator Bit 3 */
|
| 1157 |
|
|
word BIT4 :1; /* Pulse Accumulator Bit 4 */
|
| 1158 |
|
|
word BIT5 :1; /* Pulse Accumulator Bit 5 */
|
| 1159 |
|
|
word BIT6 :1; /* Pulse Accumulator Bit 6 */
|
| 1160 |
|
|
word BIT7 :1; /* Pulse Accumulator Bit 7 */
|
| 1161 |
|
|
word BIT8 :1; /* Pulse Accumulator Bit 8 */
|
| 1162 |
|
|
word BIT9 :1; /* Pulse Accumulator Bit 9 */
|
| 1163 |
|
|
word BIT10 :1; /* Pulse Accumulator Bit 10 */
|
| 1164 |
|
|
word BIT11 :1; /* Pulse Accumulator Bit 11 */
|
| 1165 |
|
|
word BIT12 :1; /* Pulse Accumulator Bit 12 */
|
| 1166 |
|
|
word BIT13 :1; /* Pulse Accumulator Bit 13 */
|
| 1167 |
|
|
word BIT14 :1; /* Pulse Accumulator Bit 14 */
|
| 1168 |
|
|
word BIT15 :1; /* Pulse Accumulator Bit 15 */
|
| 1169 |
|
|
} Bits;
|
| 1170 |
|
|
struct {
|
| 1171 |
|
|
word grpBIT :16;
|
| 1172 |
|
|
} MergedBits;
|
| 1173 |
|
|
} PA10HSTR;
|
| 1174 |
|
|
extern volatile PA10HSTR _PA10H @(REG_BASE + 0x00000074);
|
| 1175 |
|
|
#define PA10H _PA10H.Word
|
| 1176 |
|
|
#define PA10H_BIT0 _PA10H.Bits.BIT0
|
| 1177 |
|
|
#define PA10H_BIT1 _PA10H.Bits.BIT1
|
| 1178 |
|
|
#define PA10H_BIT2 _PA10H.Bits.BIT2
|
| 1179 |
|
|
#define PA10H_BIT3 _PA10H.Bits.BIT3
|
| 1180 |
|
|
#define PA10H_BIT4 _PA10H.Bits.BIT4
|
| 1181 |
|
|
#define PA10H_BIT5 _PA10H.Bits.BIT5
|
| 1182 |
|
|
#define PA10H_BIT6 _PA10H.Bits.BIT6
|
| 1183 |
|
|
#define PA10H_BIT7 _PA10H.Bits.BIT7
|
| 1184 |
|
|
#define PA10H_BIT8 _PA10H.Bits.BIT8
|
| 1185 |
|
|
#define PA10H_BIT9 _PA10H.Bits.BIT9
|
| 1186 |
|
|
#define PA10H_BIT10 _PA10H.Bits.BIT10
|
| 1187 |
|
|
#define PA10H_BIT11 _PA10H.Bits.BIT11
|
| 1188 |
|
|
#define PA10H_BIT12 _PA10H.Bits.BIT12
|
| 1189 |
|
|
#define PA10H_BIT13 _PA10H.Bits.BIT13
|
| 1190 |
|
|
#define PA10H_BIT14 _PA10H.Bits.BIT14
|
| 1191 |
|
|
#define PA10H_BIT15 _PA10H.Bits.BIT15
|
| 1192 |
|
|
#define PA10H_BIT _PA10H.MergedBits.grpBIT
|
| 1193 |
|
|
|
| 1194 |
|
|
|
| 1195 |
|
|
/*** MCCNT - Modulus Down-Counter Count Register; 0x00000076 ***/
|
| 1196 |
|
|
typedef union {
|
| 1197 |
|
|
word Word;
|
| 1198 |
|
|
/* Overlapped registers: */
|
| 1199 |
|
|
struct {
|
| 1200 |
|
|
/*** MCCNThi - Modulus Down-Counter Count Register High; 0x00000076 ***/
|
| 1201 |
|
|
union {
|
| 1202 |
|
|
byte Byte;
|
| 1203 |
|
|
struct {
|
| 1204 |
|
|
byte BIT8 :1; /* Modulus Down-Counter Bit 8 */
|
| 1205 |
|
|
byte BIT9 :1; /* Modulus Down-Counter Bit 9 */
|
| 1206 |
|
|
byte BIT10 :1; /* Modulus Down-Counter Bit 10 */
|
| 1207 |
|
|
byte BIT11 :1; /* Modulus Down-Counter Bit 11 */
|
| 1208 |
|
|
byte BIT12 :1; /* Modulus Down-Counter Bit 12 */
|
| 1209 |
|
|
byte BIT13 :1; /* Modulus Down-Counter Bit 13 */
|
| 1210 |
|
|
byte BIT14 :1; /* Modulus Down-Counter Bit 14 */
|
| 1211 |
|
|
byte BIT15 :1; /* Modulus Down-Counter Bit 15 */
|
| 1212 |
|
|
} Bits;
|
| 1213 |
|
|
struct {
|
| 1214 |
|
|
byte grpBIT_8 :8;
|
| 1215 |
|
|
} MergedBits;
|
| 1216 |
|
|
} MCCNThiSTR;
|
| 1217 |
|
|
#define MCCNThi _MCCNT.Overlap_STR.MCCNThiSTR.Byte
|
| 1218 |
|
|
#define MCCNThi_BIT8 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT8
|
| 1219 |
|
|
#define MCCNThi_BIT9 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT9
|
| 1220 |
|
|
#define MCCNThi_BIT10 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT10
|
| 1221 |
|
|
#define MCCNThi_BIT11 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT11
|
| 1222 |
|
|
#define MCCNThi_BIT12 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT12
|
| 1223 |
|
|
#define MCCNThi_BIT13 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT13
|
| 1224 |
|
|
#define MCCNThi_BIT14 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT14
|
| 1225 |
|
|
#define MCCNThi_BIT15 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT15
|
| 1226 |
|
|
#define MCCNThi_BIT_8 _MCCNT.Overlap_STR.MCCNThiSTR.MergedBits.grpBIT_8
|
| 1227 |
|
|
#define MCCNThi_BIT MCCNThi_BIT_8
|
| 1228 |
|
|
|
| 1229 |
|
|
/*** MCCNTlo - Modulus Down-Counter Count Register Low; 0x00000077 ***/
|
| 1230 |
|
|
union {
|
| 1231 |
|
|
byte Byte;
|
| 1232 |
|
|
struct {
|
| 1233 |
|
|
byte BIT0 :1; /* Modulus Down-Counter Bit 0 */
|
| 1234 |
|
|
byte BIT1 :1; /* Modulus Down-Counter Bit 1 */
|
| 1235 |
|
|
byte BIT2 :1; /* Modulus Down-Counter Bit 2 */
|
| 1236 |
|
|
byte BIT3 :1; /* Modulus Down-Counter Bit 3 */
|
| 1237 |
|
|
byte BIT4 :1; /* Modulus Down-Counter Bit 4 */
|
| 1238 |
|
|
byte BIT5 :1; /* Modulus Down-Counter Bit 5 */
|
| 1239 |
|
|
byte BIT6 :1; /* Modulus Down-Counter Bit 6 */
|
| 1240 |
|
|
byte BIT7 :1; /* Modulus Down-Counter Bit 7 */
|
| 1241 |
|
|
} Bits;
|
| 1242 |
|
|
struct {
|
| 1243 |
|
|
byte grpBIT :8;
|
| 1244 |
|
|
} MergedBits;
|
| 1245 |
|
|
} MCCNTloSTR;
|
| 1246 |
|
|
#define MCCNTlo _MCCNT.Overlap_STR.MCCNTloSTR.Byte
|
| 1247 |
|
|
#define MCCNTlo_BIT0 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT0
|
| 1248 |
|
|
#define MCCNTlo_BIT1 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT1
|
| 1249 |
|
|
#define MCCNTlo_BIT2 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT2
|
| 1250 |
|
|
#define MCCNTlo_BIT3 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT3
|
| 1251 |
|
|
#define MCCNTlo_BIT4 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT4
|
| 1252 |
|
|
#define MCCNTlo_BIT5 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT5
|
| 1253 |
|
|
#define MCCNTlo_BIT6 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT6
|
| 1254 |
|
|
#define MCCNTlo_BIT7 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT7
|
| 1255 |
|
|
#define MCCNTlo_BIT _MCCNT.Overlap_STR.MCCNTloSTR.MergedBits.grpBIT
|
| 1256 |
|
|
|
| 1257 |
|
|
} Overlap_STR;
|
| 1258 |
|
|
|
| 1259 |
|
|
struct {
|
| 1260 |
|
|
word grpBIT :16;
|
| 1261 |
|
|
} MergedBits;
|
| 1262 |
|
|
} MCCNTSTR;
|
| 1263 |
|
|
extern volatile MCCNTSTR _MCCNT @(REG_BASE + 0x00000076);
|
| 1264 |
|
|
#define MCCNT _MCCNT.Word
|
| 1265 |
|
|
#define MCCNT_BIT _MCCNT.MergedBits.grpBIT
|
| 1266 |
|
|
|
| 1267 |
|
|
|
| 1268 |
|
|
/*** TC0H - Timer Input Capture Holding Registers 0; 0x00000078 ***/
|
| 1269 |
|
|
typedef union {
|
| 1270 |
|
|
word Word;
|
| 1271 |
|
|
/* Overlapped registers: */
|
| 1272 |
|
|
struct {
|
| 1273 |
|
|
/*** TC0Hhi - Timer Input Capture Holding Registers 0 High; 0x00000078 ***/
|
| 1274 |
|
|
union {
|
| 1275 |
|
|
byte Byte;
|
| 1276 |
|
|
struct {
|
| 1277 |
|
|
byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */
|
| 1278 |
|
|
byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */
|
| 1279 |
|
|
byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */
|
| 1280 |
|
|
byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */
|
| 1281 |
|
|
byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */
|
| 1282 |
|
|
byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */
|
| 1283 |
|
|
byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */
|
| 1284 |
|
|
byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */
|
| 1285 |
|
|
} Bits;
|
| 1286 |
|
|
struct {
|
| 1287 |
|
|
byte grpBIT_8 :8;
|
| 1288 |
|
|
} MergedBits;
|
| 1289 |
|
|
} TC0HhiSTR;
|
| 1290 |
|
|
#define TC0Hhi _TC0H.Overlap_STR.TC0HhiSTR.Byte
|
| 1291 |
|
|
#define TC0Hhi_BIT8 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT8
|
| 1292 |
|
|
#define TC0Hhi_BIT9 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT9
|
| 1293 |
|
|
#define TC0Hhi_BIT10 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT10
|
| 1294 |
|
|
#define TC0Hhi_BIT11 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT11
|
| 1295 |
|
|
#define TC0Hhi_BIT12 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT12
|
| 1296 |
|
|
#define TC0Hhi_BIT13 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT13
|
| 1297 |
|
|
#define TC0Hhi_BIT14 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT14
|
| 1298 |
|
|
#define TC0Hhi_BIT15 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT15
|
| 1299 |
|
|
#define TC0Hhi_BIT_8 _TC0H.Overlap_STR.TC0HhiSTR.MergedBits.grpBIT_8
|
| 1300 |
|
|
#define TC0Hhi_BIT TC0Hhi_BIT_8
|
| 1301 |
|
|
|
| 1302 |
|
|
/*** TC0Hlo - Timer Input Capture Holding Registers 0 Low; 0x00000079 ***/
|
| 1303 |
|
|
union {
|
| 1304 |
|
|
byte Byte;
|
| 1305 |
|
|
struct {
|
| 1306 |
|
|
byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */
|
| 1307 |
|
|
byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */
|
| 1308 |
|
|
byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */
|
| 1309 |
|
|
byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */
|
| 1310 |
|
|
byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */
|
| 1311 |
|
|
byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */
|
| 1312 |
|
|
byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */
|
| 1313 |
|
|
byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */
|
| 1314 |
|
|
} Bits;
|
| 1315 |
|
|
struct {
|
| 1316 |
|
|
byte grpBIT :8;
|
| 1317 |
|
|
} MergedBits;
|
| 1318 |
|
|
} TC0HloSTR;
|
| 1319 |
|
|
#define TC0Hlo _TC0H.Overlap_STR.TC0HloSTR.Byte
|
| 1320 |
|
|
#define TC0Hlo_BIT0 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT0
|
| 1321 |
|
|
#define TC0Hlo_BIT1 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT1
|
| 1322 |
|
|
#define TC0Hlo_BIT2 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT2
|
| 1323 |
|
|
#define TC0Hlo_BIT3 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT3
|
| 1324 |
|
|
#define TC0Hlo_BIT4 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT4
|
| 1325 |
|
|
#define TC0Hlo_BIT5 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT5
|
| 1326 |
|
|
#define TC0Hlo_BIT6 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT6
|
| 1327 |
|
|
#define TC0Hlo_BIT7 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT7
|
| 1328 |
|
|
#define TC0Hlo_BIT _TC0H.Overlap_STR.TC0HloSTR.MergedBits.grpBIT
|
| 1329 |
|
|
|
| 1330 |
|
|
} Overlap_STR;
|
| 1331 |
|
|
|
| 1332 |
|
|
struct {
|
| 1333 |
|
|
word BIT0 :1; /* Timer Input Capture Holding Bit 0 */
|
| 1334 |
|
|
word BIT1 :1; /* Timer Input Capture Holding Bit 1 */
|
| 1335 |
|
|
word BIT2 :1; /* Timer Input Capture Holding Bit 2 */
|
| 1336 |
|
|
word BIT3 :1; /* Timer Input Capture Holding Bit 3 */
|
| 1337 |
|
|
word BIT4 :1; /* Timer Input Capture Holding Bit 4 */
|
| 1338 |
|
|
word BIT5 :1; /* Timer Input Capture Holding Bit 5 */
|
| 1339 |
|
|
word BIT6 :1; /* Timer Input Capture Holding Bit 6 */
|
| 1340 |
|
|
word BIT7 :1; /* Timer Input Capture Holding Bit 7 */
|
| 1341 |
|
|
word BIT8 :1; /* Timer Input Capture Holding Bit 8 */
|
| 1342 |
|
|
word BIT9 :1; /* Timer Input Capture Holding Bit 9 */
|
| 1343 |
|
|
word BIT10 :1; /* Timer Input Capture Holding Bit 10 */
|
| 1344 |
|
|
word BIT11 :1; /* Timer Input Capture Holding Bit 11 */
|
| 1345 |
|
|
word BIT12 :1; /* Timer Input Capture Holding Bit 12 */
|
| 1346 |
|
|
word BIT13 :1; /* Timer Input Capture Holding Bit 13 */
|
| 1347 |
|
|
word BIT14 :1; /* Timer Input Capture Holding Bit 14 */
|
| 1348 |
|
|
word BIT15 :1; /* Timer Input Capture Holding Bit 15 */
|
| 1349 |
|
|
} Bits;
|
| 1350 |
|
|
struct {
|
| 1351 |
|
|
word grpBIT :16;
|
| 1352 |
|
|
} MergedBits;
|
| 1353 |
|
|
} TC0HSTR;
|
| 1354 |
|
|
extern volatile TC0HSTR _TC0H @(REG_BASE + 0x00000078);
|
| 1355 |
|
|
#define TC0H _TC0H.Word
|
| 1356 |
|
|
#define TC0H_BIT0 _TC0H.Bits.BIT0
|
| 1357 |
|
|
#define TC0H_BIT1 _TC0H.Bits.BIT1
|
| 1358 |
|
|
#define TC0H_BIT2 _TC0H.Bits.BIT2
|
| 1359 |
|
|
#define TC0H_BIT3 _TC0H.Bits.BIT3
|
| 1360 |
|
|
#define TC0H_BIT4 _TC0H.Bits.BIT4
|
| 1361 |
|
|
#define TC0H_BIT5 _TC0H.Bits.BIT5
|
| 1362 |
|
|
#define TC0H_BIT6 _TC0H.Bits.BIT6
|
| 1363 |
|
|
#define TC0H_BIT7 _TC0H.Bits.BIT7
|
| 1364 |
|
|
#define TC0H_BIT8 _TC0H.Bits.BIT8
|
| 1365 |
|
|
#define TC0H_BIT9 _TC0H.Bits.BIT9
|
| 1366 |
|
|
#define TC0H_BIT10 _TC0H.Bits.BIT10
|
| 1367 |
|
|
#define TC0H_BIT11 _TC0H.Bits.BIT11
|
| 1368 |
|
|
#define TC0H_BIT12 _TC0H.Bits.BIT12
|
| 1369 |
|
|
#define TC0H_BIT13 _TC0H.Bits.BIT13
|
| 1370 |
|
|
#define TC0H_BIT14 _TC0H.Bits.BIT14
|
| 1371 |
|
|
#define TC0H_BIT15 _TC0H.Bits.BIT15
|
| 1372 |
|
|
#define TC0H_BIT _TC0H.MergedBits.grpBIT
|
| 1373 |
|
|
|
| 1374 |
|
|
|
| 1375 |
|
|
/*** TC1H - Timer Input Capture Holding Registers 1; 0x0000007A ***/
|
| 1376 |
|
|
typedef union {
|
| 1377 |
|
|
word Word;
|
| 1378 |
|
|
/* Overlapped registers: */
|
| 1379 |
|
|
struct {
|
| 1380 |
|
|
/*** TC1Hhi - Timer Input Capture Holding Registers 1 High; 0x0000007A ***/
|
| 1381 |
|
|
union {
|
| 1382 |
|
|
byte Byte;
|
| 1383 |
|
|
struct {
|
| 1384 |
|
|
byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */
|
| 1385 |
|
|
byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */
|
| 1386 |
|
|
byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */
|
| 1387 |
|
|
byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */
|
| 1388 |
|
|
byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */
|
| 1389 |
|
|
byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */
|
| 1390 |
|
|
byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */
|
| 1391 |
|
|
byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */
|
| 1392 |
|
|
} Bits;
|
| 1393 |
|
|
struct {
|
| 1394 |
|
|
byte grpBIT_8 :8;
|
| 1395 |
|
|
} MergedBits;
|
| 1396 |
|
|
} TC1HhiSTR;
|
| 1397 |
|
|
#define TC1Hhi _TC1H.Overlap_STR.TC1HhiSTR.Byte
|
| 1398 |
|
|
#define TC1Hhi_BIT8 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT8
|
| 1399 |
|
|
#define TC1Hhi_BIT9 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT9
|
| 1400 |
|
|
#define TC1Hhi_BIT10 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT10
|
| 1401 |
|
|
#define TC1Hhi_BIT11 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT11
|
| 1402 |
|
|
#define TC1Hhi_BIT12 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT12
|
| 1403 |
|
|
#define TC1Hhi_BIT13 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT13
|
| 1404 |
|
|
#define TC1Hhi_BIT14 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT14
|
| 1405 |
|
|
#define TC1Hhi_BIT15 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT15
|
| 1406 |
|
|
#define TC1Hhi_BIT_8 _TC1H.Overlap_STR.TC1HhiSTR.MergedBits.grpBIT_8
|
| 1407 |
|
|
#define TC1Hhi_BIT TC1Hhi_BIT_8
|
| 1408 |
|
|
|
| 1409 |
|
|
/*** TC1Hlo - Timer Input Capture Holding Registers 1 Low; 0x0000007B ***/
|
| 1410 |
|
|
union {
|
| 1411 |
|
|
byte Byte;
|
| 1412 |
|
|
struct {
|
| 1413 |
|
|
byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */
|
| 1414 |
|
|
byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */
|
| 1415 |
|
|
byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */
|
| 1416 |
|
|
byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */
|
| 1417 |
|
|
byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */
|
| 1418 |
|
|
byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */
|
| 1419 |
|
|
byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */
|
| 1420 |
|
|
byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */
|
| 1421 |
|
|
} Bits;
|
| 1422 |
|
|
struct {
|
| 1423 |
|
|
byte grpBIT :8;
|
| 1424 |
|
|
} MergedBits;
|
| 1425 |
|
|
} TC1HloSTR;
|
| 1426 |
|
|
#define TC1Hlo _TC1H.Overlap_STR.TC1HloSTR.Byte
|
| 1427 |
|
|
#define TC1Hlo_BIT0 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT0
|
| 1428 |
|
|
#define TC1Hlo_BIT1 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT1
|
| 1429 |
|
|
#define TC1Hlo_BIT2 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT2
|
| 1430 |
|
|
#define TC1Hlo_BIT3 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT3
|
| 1431 |
|
|
#define TC1Hlo_BIT4 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT4
|
| 1432 |
|
|
#define TC1Hlo_BIT5 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT5
|
| 1433 |
|
|
#define TC1Hlo_BIT6 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT6
|
| 1434 |
|
|
#define TC1Hlo_BIT7 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT7
|
| 1435 |
|
|
#define TC1Hlo_BIT _TC1H.Overlap_STR.TC1HloSTR.MergedBits.grpBIT
|
| 1436 |
|
|
|
| 1437 |
|
|
} Overlap_STR;
|
| 1438 |
|
|
|
| 1439 |
|
|
struct {
|
| 1440 |
|
|
word BIT0 :1; /* Timer Input Capture Holding Bit 0 */
|
| 1441 |
|
|
word BIT1 :1; /* Timer Input Capture Holding Bit 1 */
|
| 1442 |
|
|
word BIT2 :1; /* Timer Input Capture Holding Bit 2 */
|
| 1443 |
|
|
word BIT3 :1; /* Timer Input Capture Holding Bit 3 */
|
| 1444 |
|
|
word BIT4 :1; /* Timer Input Capture Holding Bit 4 */
|
| 1445 |
|
|
word BIT5 :1; /* Timer Input Capture Holding Bit 5 */
|
| 1446 |
|
|
word BIT6 :1; /* Timer Input Capture Holding Bit 6 */
|
| 1447 |
|
|
word BIT7 :1; /* Timer Input Capture Holding Bit 7 */
|
| 1448 |
|
|
word BIT8 :1; /* Timer Input Capture Holding Bit 8 */
|
| 1449 |
|
|
word BIT9 :1; /* Timer Input Capture Holding Bit 9 */
|
| 1450 |
|
|
word BIT10 :1; /* Timer Input Capture Holding Bit 10 */
|
| 1451 |
|
|
word BIT11 :1; /* Timer Input Capture Holding Bit 11 */
|
| 1452 |
|
|
word BIT12 :1; /* Timer Input Capture Holding Bit 12 */
|
| 1453 |
|
|
word BIT13 :1; /* Timer Input Capture Holding Bit 13 */
|
| 1454 |
|
|
word BIT14 :1; /* Timer Input Capture Holding Bit 14 */
|
| 1455 |
|
|
word BIT15 :1; /* Timer Input Capture Holding Bit 15 */
|
| 1456 |
|
|
} Bits;
|
| 1457 |
|
|
struct {
|
| 1458 |
|
|
word grpBIT :16;
|
| 1459 |
|
|
} MergedBits;
|
| 1460 |
|
|
} TC1HSTR;
|
| 1461 |
|
|
extern volatile TC1HSTR _TC1H @(REG_BASE + 0x0000007A);
|
| 1462 |
|
|
#define TC1H _TC1H.Word
|
| 1463 |
|
|
#define TC1H_BIT0 _TC1H.Bits.BIT0
|
| 1464 |
|
|
#define TC1H_BIT1 _TC1H.Bits.BIT1
|
| 1465 |
|
|
#define TC1H_BIT2 _TC1H.Bits.BIT2
|
| 1466 |
|
|
#define TC1H_BIT3 _TC1H.Bits.BIT3
|
| 1467 |
|
|
#define TC1H_BIT4 _TC1H.Bits.BIT4
|
| 1468 |
|
|
#define TC1H_BIT5 _TC1H.Bits.BIT5
|
| 1469 |
|
|
#define TC1H_BIT6 _TC1H.Bits.BIT6
|
| 1470 |
|
|
#define TC1H_BIT7 _TC1H.Bits.BIT7
|
| 1471 |
|
|
#define TC1H_BIT8 _TC1H.Bits.BIT8
|
| 1472 |
|
|
#define TC1H_BIT9 _TC1H.Bits.BIT9
|
| 1473 |
|
|
#define TC1H_BIT10 _TC1H.Bits.BIT10
|
| 1474 |
|
|
#define TC1H_BIT11 _TC1H.Bits.BIT11
|
| 1475 |
|
|
#define TC1H_BIT12 _TC1H.Bits.BIT12
|
| 1476 |
|
|
#define TC1H_BIT13 _TC1H.Bits.BIT13
|
| 1477 |
|
|
#define TC1H_BIT14 _TC1H.Bits.BIT14
|
| 1478 |
|
|
#define TC1H_BIT15 _TC1H.Bits.BIT15
|
| 1479 |
|
|
#define TC1H_BIT _TC1H.MergedBits.grpBIT
|
| 1480 |
|
|
|
| 1481 |
|
|
|
| 1482 |
|
|
/*** TC2H - Timer Input Capture Holding Registers 2; 0x0000007C ***/
|
| 1483 |
|
|
typedef union {
|
| 1484 |
|
|
word Word;
|
| 1485 |
|
|
/* Overlapped registers: */
|
| 1486 |
|
|
struct {
|
| 1487 |
|
|
/*** TC2Hhi - Timer Input Capture Holding Registers 2 High; 0x0000007C ***/
|
| 1488 |
|
|
union {
|
| 1489 |
|
|
byte Byte;
|
| 1490 |
|
|
struct {
|
| 1491 |
|
|
byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */
|
| 1492 |
|
|
byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */
|
| 1493 |
|
|
byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */
|
| 1494 |
|
|
byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */
|
| 1495 |
|
|
byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */
|
| 1496 |
|
|
byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */
|
| 1497 |
|
|
byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */
|
| 1498 |
|
|
byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */
|
| 1499 |
|
|
} Bits;
|
| 1500 |
|
|
struct {
|
| 1501 |
|
|
byte grpBIT_8 :8;
|
| 1502 |
|
|
} MergedBits;
|
| 1503 |
|
|
} TC2HhiSTR;
|
| 1504 |
|
|
#define TC2Hhi _TC2H.Overlap_STR.TC2HhiSTR.Byte
|
| 1505 |
|
|
#define TC2Hhi_BIT8 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT8
|
| 1506 |
|
|
#define TC2Hhi_BIT9 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT9
|
| 1507 |
|
|
#define TC2Hhi_BIT10 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT10
|
| 1508 |
|
|
#define TC2Hhi_BIT11 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT11
|
| 1509 |
|
|
#define TC2Hhi_BIT12 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT12
|
| 1510 |
|
|
#define TC2Hhi_BIT13 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT13
|
| 1511 |
|
|
#define TC2Hhi_BIT14 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT14
|
| 1512 |
|
|
#define TC2Hhi_BIT15 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT15
|
| 1513 |
|
|
#define TC2Hhi_BIT_8 _TC2H.Overlap_STR.TC2HhiSTR.MergedBits.grpBIT_8
|
| 1514 |
|
|
#define TC2Hhi_BIT TC2Hhi_BIT_8
|
| 1515 |
|
|
|
| 1516 |
|
|
/*** TC2Hlo - Timer Input Capture Holding Registers 2 Low; 0x0000007D ***/
|
| 1517 |
|
|
union {
|
| 1518 |
|
|
byte Byte;
|
| 1519 |
|
|
struct {
|
| 1520 |
|
|
byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */
|
| 1521 |
|
|
byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */
|
| 1522 |
|
|
byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */
|
| 1523 |
|
|
byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */
|
| 1524 |
|
|
byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */
|
| 1525 |
|
|
byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */
|
| 1526 |
|
|
byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */
|
| 1527 |
|
|
byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */
|
| 1528 |
|
|
} Bits;
|
| 1529 |
|
|
struct {
|
| 1530 |
|
|
byte grpBIT :8;
|
| 1531 |
|
|
} MergedBits;
|
| 1532 |
|
|
} TC2HloSTR;
|
| 1533 |
|
|
#define TC2Hlo _TC2H.Overlap_STR.TC2HloSTR.Byte
|
| 1534 |
|
|
#define TC2Hlo_BIT0 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT0
|
| 1535 |
|
|
#define TC2Hlo_BIT1 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT1
|
| 1536 |
|
|
#define TC2Hlo_BIT2 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT2
|
| 1537 |
|
|
#define TC2Hlo_BIT3 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT3
|
| 1538 |
|
|
#define TC2Hlo_BIT4 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT4
|
| 1539 |
|
|
#define TC2Hlo_BIT5 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT5
|
| 1540 |
|
|
#define TC2Hlo_BIT6 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT6
|
| 1541 |
|
|
#define TC2Hlo_BIT7 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT7
|
| 1542 |
|
|
#define TC2Hlo_BIT _TC2H.Overlap_STR.TC2HloSTR.MergedBits.grpBIT
|
| 1543 |
|
|
|
| 1544 |
|
|
} Overlap_STR;
|
| 1545 |
|
|
|
| 1546 |
|
|
struct {
|
| 1547 |
|
|
word BIT0 :1; /* Timer Input Capture Holding Bit 0 */
|
| 1548 |
|
|
word BIT1 :1; /* Timer Input Capture Holding Bit 1 */
|
| 1549 |
|
|
word BIT2 :1; /* Timer Input Capture Holding Bit 2 */
|
| 1550 |
|
|
word BIT3 :1; /* Timer Input Capture Holding Bit 3 */
|
| 1551 |
|
|
word BIT4 :1; /* Timer Input Capture Holding Bit 4 */
|
| 1552 |
|
|
word BIT5 :1; /* Timer Input Capture Holding Bit 5 */
|
| 1553 |
|
|
word BIT6 :1; /* Timer Input Capture Holding Bit 6 */
|
| 1554 |
|
|
word BIT7 :1; /* Timer Input Capture Holding Bit 7 */
|
| 1555 |
|
|
word BIT8 :1; /* Timer Input Capture Holding Bit 8 */
|
| 1556 |
|
|
word BIT9 :1; /* Timer Input Capture Holding Bit 9 */
|
| 1557 |
|
|
word BIT10 :1; /* Timer Input Capture Holding Bit 10 */
|
| 1558 |
|
|
word BIT11 :1; /* Timer Input Capture Holding Bit 11 */
|
| 1559 |
|
|
word BIT12 :1; /* Timer Input Capture Holding Bit 12 */
|
| 1560 |
|
|
word BIT13 :1; /* Timer Input Capture Holding Bit 13 */
|
| 1561 |
|
|
word BIT14 :1; /* Timer Input Capture Holding Bit 14 */
|
| 1562 |
|
|
word BIT15 :1; /* Timer Input Capture Holding Bit 15 */
|
| 1563 |
|
|
} Bits;
|
| 1564 |
|
|
struct {
|
| 1565 |
|
|
word grpBIT :16;
|
| 1566 |
|
|
} MergedBits;
|
| 1567 |
|
|
} TC2HSTR;
|
| 1568 |
|
|
extern volatile TC2HSTR _TC2H @(REG_BASE + 0x0000007C);
|
| 1569 |
|
|
#define TC2H _TC2H.Word
|
| 1570 |
|
|
#define TC2H_BIT0 _TC2H.Bits.BIT0
|
| 1571 |
|
|
#define TC2H_BIT1 _TC2H.Bits.BIT1
|
| 1572 |
|
|
#define TC2H_BIT2 _TC2H.Bits.BIT2
|
| 1573 |
|
|
#define TC2H_BIT3 _TC2H.Bits.BIT3
|
| 1574 |
|
|
#define TC2H_BIT4 _TC2H.Bits.BIT4
|
| 1575 |
|
|
#define TC2H_BIT5 _TC2H.Bits.BIT5
|
| 1576 |
|
|
#define TC2H_BIT6 _TC2H.Bits.BIT6
|
| 1577 |
|
|
#define TC2H_BIT7 _TC2H.Bits.BIT7
|
| 1578 |
|
|
#define TC2H_BIT8 _TC2H.Bits.BIT8
|
| 1579 |
|
|
#define TC2H_BIT9 _TC2H.Bits.BIT9
|
| 1580 |
|
|
#define TC2H_BIT10 _TC2H.Bits.BIT10
|
| 1581 |
|
|
#define TC2H_BIT11 _TC2H.Bits.BIT11
|
| 1582 |
|
|
#define TC2H_BIT12 _TC2H.Bits.BIT12
|
| 1583 |
|
|
#define TC2H_BIT13 _TC2H.Bits.BIT13
|
| 1584 |
|
|
#define TC2H_BIT14 _TC2H.Bits.BIT14
|
| 1585 |
|
|
#define TC2H_BIT15 _TC2H.Bits.BIT15
|
| 1586 |
|
|
#define TC2H_BIT _TC2H.MergedBits.grpBIT
|
| 1587 |
|
|
|
| 1588 |
|
|
|
| 1589 |
|
|
/*** TC3H - Timer Input Capture Holding Registers 3; 0x0000007E ***/
|
| 1590 |
|
|
typedef union {
|
| 1591 |
|
|
word Word;
|
| 1592 |
|
|
/* Overlapped registers: */
|
| 1593 |
|
|
struct {
|
| 1594 |
|
|
/*** TC3Hhi - Timer Input Capture Holding Registers 3 High; 0x0000007E ***/
|
| 1595 |
|
|
union {
|
| 1596 |
|
|
byte Byte;
|
| 1597 |
|
|
struct {
|
| 1598 |
|
|
byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */
|
| 1599 |
|
|
byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */
|
| 1600 |
|
|
byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */
|
| 1601 |
|
|
byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */
|
| 1602 |
|
|
byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */
|
| 1603 |
|
|
byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */
|
| 1604 |
|
|
byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */
|
| 1605 |
|
|
byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */
|
| 1606 |
|
|
} Bits;
|
| 1607 |
|
|
struct {
|
| 1608 |
|
|
byte grpBIT_8 :8;
|
| 1609 |
|
|
} MergedBits;
|
| 1610 |
|
|
} TC3HhiSTR;
|
| 1611 |
|
|
#define TC3Hhi _TC3H.Overlap_STR.TC3HhiSTR.Byte
|
| 1612 |
|
|
#define TC3Hhi_BIT8 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT8
|
| 1613 |
|
|
#define TC3Hhi_BIT9 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT9
|
| 1614 |
|
|
#define TC3Hhi_BIT10 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT10
|
| 1615 |
|
|
#define TC3Hhi_BIT11 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT11
|
| 1616 |
|
|
#define TC3Hhi_BIT12 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT12
|
| 1617 |
|
|
#define TC3Hhi_BIT13 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT13
|
| 1618 |
|
|
#define TC3Hhi_BIT14 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT14
|
| 1619 |
|
|
#define TC3Hhi_BIT15 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT15
|
| 1620 |
|
|
#define TC3Hhi_BIT_8 _TC3H.Overlap_STR.TC3HhiSTR.MergedBits.grpBIT_8
|
| 1621 |
|
|
#define TC3Hhi_BIT TC3Hhi_BIT_8
|
| 1622 |
|
|
|
| 1623 |
|
|
/*** TC3Hlo - Timer Input Capture Holding Registers 3 Low; 0x0000007F ***/
|
| 1624 |
|
|
union {
|
| 1625 |
|
|
byte Byte;
|
| 1626 |
|
|
struct {
|
| 1627 |
|
|
byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */
|
| 1628 |
|
|
byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */
|
| 1629 |
|
|
byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */
|
| 1630 |
|
|
byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */
|
| 1631 |
|
|
byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */
|
| 1632 |
|
|
byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */
|
| 1633 |
|
|
byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */
|
| 1634 |
|
|
byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */
|
| 1635 |
|
|
} Bits;
|
| 1636 |
|
|
struct {
|
| 1637 |
|
|
byte grpBIT :8;
|
| 1638 |
|
|
} MergedBits;
|
| 1639 |
|
|
} TC3HloSTR;
|
| 1640 |
|
|
#define TC3Hlo _TC3H.Overlap_STR.TC3HloSTR.Byte
|
| 1641 |
|
|
#define TC3Hlo_BIT0 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT0
|
| 1642 |
|
|
#define TC3Hlo_BIT1 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT1
|
| 1643 |
|
|
#define TC3Hlo_BIT2 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT2
|
| 1644 |
|
|
#define TC3Hlo_BIT3 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT3
|
| 1645 |
|
|
#define TC3Hlo_BIT4 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT4
|
| 1646 |
|
|
#define TC3Hlo_BIT5 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT5
|
| 1647 |
|
|
#define TC3Hlo_BIT6 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT6
|
| 1648 |
|
|
#define TC3Hlo_BIT7 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT7
|
| 1649 |
|
|
#define TC3Hlo_BIT _TC3H.Overlap_STR.TC3HloSTR.MergedBits.grpBIT
|
| 1650 |
|
|
|
| 1651 |
|
|
} Overlap_STR;
|
| 1652 |
|
|
|
| 1653 |
|
|
struct {
|
| 1654 |
|
|
word BIT0 :1; /* Timer Input Capture Holding Bit 0 */
|
| 1655 |
|
|
word BIT1 :1; /* Timer Input Capture Holding Bit 1 */
|
| 1656 |
|
|
word BIT2 :1; /* Timer Input Capture Holding Bit 2 */
|
| 1657 |
|
|
word BIT3 :1; /* Timer Input Capture Holding Bit 3 */
|
| 1658 |
|
|
word BIT4 :1; /* Timer Input Capture Holding Bit 4 */
|
| 1659 |
|
|
word BIT5 :1; /* Timer Input Capture Holding Bit 5 */
|
| 1660 |
|
|
word BIT6 :1; /* Timer Input Capture Holding Bit 6 */
|
| 1661 |
|
|
word BIT7 :1; /* Timer Input Capture Holding Bit 7 */
|
| 1662 |
|
|
word BIT8 :1; /* Timer Input Capture Holding Bit 8 */
|
| 1663 |
|
|
word BIT9 :1; /* Timer Input Capture Holding Bit 9 */
|
| 1664 |
|
|
word BIT10 :1; /* Timer Input Capture Holding Bit 10 */
|
| 1665 |
|
|
word BIT11 :1; /* Timer Input Capture Holding Bit 11 */
|
| 1666 |
|
|
word BIT12 :1; /* Timer Input Capture Holding Bit 12 */
|
| 1667 |
|
|
word BIT13 :1; /* Timer Input Capture Holding Bit 13 */
|
| 1668 |
|
|
word BIT14 :1; /* Timer Input Capture Holding Bit 14 */
|
| 1669 |
|
|
word BIT15 :1; /* Timer Input Capture Holding Bit 15 */
|
| 1670 |
|
|
} Bits;
|
| 1671 |
|
|
struct {
|
| 1672 |
|
|
word grpBIT :16;
|
| 1673 |
|
|
} MergedBits;
|
| 1674 |
|
|
} TC3HSTR;
|
| 1675 |
|
|
extern volatile TC3HSTR _TC3H @(REG_BASE + 0x0000007E);
|
| 1676 |
|
|
#define TC3H _TC3H.Word
|
| 1677 |
|
|
#define TC3H_BIT0 _TC3H.Bits.BIT0
|
| 1678 |
|
|
#define TC3H_BIT1 _TC3H.Bits.BIT1
|
| 1679 |
|
|
#define TC3H_BIT2 _TC3H.Bits.BIT2
|
| 1680 |
|
|
#define TC3H_BIT3 _TC3H.Bits.BIT3
|
| 1681 |
|
|
#define TC3H_BIT4 _TC3H.Bits.BIT4
|
| 1682 |
|
|
#define TC3H_BIT5 _TC3H.Bits.BIT5
|
| 1683 |
|
|
#define TC3H_BIT6 _TC3H.Bits.BIT6
|
| 1684 |
|
|
#define TC3H_BIT7 _TC3H.Bits.BIT7
|
| 1685 |
|
|
#define TC3H_BIT8 _TC3H.Bits.BIT8
|
| 1686 |
|
|
#define TC3H_BIT9 _TC3H.Bits.BIT9
|
| 1687 |
|
|
#define TC3H_BIT10 _TC3H.Bits.BIT10
|
| 1688 |
|
|
#define TC3H_BIT11 _TC3H.Bits.BIT11
|
| 1689 |
|
|
#define TC3H_BIT12 _TC3H.Bits.BIT12
|
| 1690 |
|
|
#define TC3H_BIT13 _TC3H.Bits.BIT13
|
| 1691 |
|
|
#define TC3H_BIT14 _TC3H.Bits.BIT14
|
| 1692 |
|
|
#define TC3H_BIT15 _TC3H.Bits.BIT15
|
| 1693 |
|
|
#define TC3H_BIT _TC3H.MergedBits.grpBIT
|
| 1694 |
|
|
|
| 1695 |
|
|
|
| 1696 |
|
|
/*** ATD0CTL23 - ATD 0 Control Register 23; 0x00000082 ***/
|
| 1697 |
|
|
typedef union {
|
| 1698 |
|
|
word Word;
|
| 1699 |
|
|
/* Overlapped registers: */
|
| 1700 |
|
|
struct {
|
| 1701 |
|
|
/*** ATD0CTL2 - ATD 0 Control Register 2; 0x00000082 ***/
|
| 1702 |
|
|
union {
|
| 1703 |
|
|
byte Byte;
|
| 1704 |
|
|
struct {
|
| 1705 |
|
|
byte ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */
|
| 1706 |
|
|
byte ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */
|
| 1707 |
|
|
byte ETRIGE :1; /* External Trigger Mode enable */
|
| 1708 |
|
|
byte ETRIGP :1; /* External Trigger Polarity */
|
| 1709 |
|
|
byte ETRIGLE :1; /* External Trigger Level/Edge control */
|
| 1710 |
|
|
byte AWAI :1; /* ATD 0 Wait Mode */
|
| 1711 |
|
|
byte AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */
|
| 1712 |
|
|
byte ADPU :1; /* ATD 0 Disable / Power Down */
|
| 1713 |
|
|
} Bits;
|
| 1714 |
|
|
} ATD0CTL2STR;
|
| 1715 |
|
|
#define ATD0CTL2 _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Byte
|
| 1716 |
|
|
#define ATD0CTL2_ASCIF _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIF
|
| 1717 |
|
|
#define ATD0CTL2_ASCIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIE
|
| 1718 |
|
|
#define ATD0CTL2_ETRIGE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGE
|
| 1719 |
|
|
#define ATD0CTL2_ETRIGP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGP
|
| 1720 |
|
|
#define ATD0CTL2_ETRIGLE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGLE
|
| 1721 |
|
|
#define ATD0CTL2_AWAI _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AWAI
|
| 1722 |
|
|
#define ATD0CTL2_AFFC _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AFFC
|
| 1723 |
|
|
#define ATD0CTL2_ADPU _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ADPU
|
| 1724 |
|
|
|
| 1725 |
|
|
/*** ATD0CTL3 - ATD 0 Control Register 3; 0x00000083 ***/
|
| 1726 |
|
|
union {
|
| 1727 |
|
|
byte Byte;
|
| 1728 |
|
|
struct {
|
| 1729 |
|
|
byte FRZ0 :1; /* Background Debug Freeze Enable */
|
| 1730 |
|
|
byte FRZ1 :1; /* Background Debug Freeze Enable */
|
| 1731 |
|
|
byte FIFO :1; /* Result Register FIFO Mode */
|
| 1732 |
|
|
byte S1C :1; /* Conversion Sequence Length 1 */
|
| 1733 |
|
|
byte S2C :1; /* Conversion Sequence Length 2 */
|
| 1734 |
|
|
byte S4C :1; /* Conversion Sequence Length 4 */
|
| 1735 |
|
|
byte S8C :1; /* Conversion Sequence Length 8 */
|
| 1736 |
|
|
byte :1;
|
| 1737 |
|
|
} Bits;
|
| 1738 |
|
|
struct {
|
| 1739 |
|
|
byte grpFRZ :2;
|
| 1740 |
|
|
byte :1;
|
| 1741 |
|
|
byte :1;
|
| 1742 |
|
|
byte :1;
|
| 1743 |
|
|
byte :1;
|
| 1744 |
|
|
byte :1;
|
| 1745 |
|
|
byte :1;
|
| 1746 |
|
|
} MergedBits;
|
| 1747 |
|
|
} ATD0CTL3STR;
|
| 1748 |
|
|
#define ATD0CTL3 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Byte
|
| 1749 |
|
|
#define ATD0CTL3_FRZ0 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ0
|
| 1750 |
|
|
#define ATD0CTL3_FRZ1 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ1
|
| 1751 |
|
|
#define ATD0CTL3_FIFO _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FIFO
|
| 1752 |
|
|
#define ATD0CTL3_S1C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S1C
|
| 1753 |
|
|
#define ATD0CTL3_S2C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S2C
|
| 1754 |
|
|
#define ATD0CTL3_S4C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S4C
|
| 1755 |
|
|
#define ATD0CTL3_S8C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S8C
|
| 1756 |
|
|
#define ATD0CTL3_FRZ _ATD0CTL23.Overlap_STR.ATD0CTL3STR.MergedBits.grpFRZ
|
| 1757 |
|
|
|
| 1758 |
|
|
} Overlap_STR;
|
| 1759 |
|
|
|
| 1760 |
|
|
struct {
|
| 1761 |
|
|
word FRZ0 :1; /* Background Debug Freeze Enable */
|
| 1762 |
|
|
word FRZ1 :1; /* Background Debug Freeze Enable */
|
| 1763 |
|
|
word FIFO :1; /* Result Register FIFO Mode */
|
| 1764 |
|
|
word S1C :1; /* Conversion Sequence Length 1 */
|
| 1765 |
|
|
word S2C :1; /* Conversion Sequence Length 2 */
|
| 1766 |
|
|
word S4C :1; /* Conversion Sequence Length 4 */
|
| 1767 |
|
|
word S8C :1; /* Conversion Sequence Length 8 */
|
| 1768 |
|
|
word :1;
|
| 1769 |
|
|
word ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */
|
| 1770 |
|
|
word ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */
|
| 1771 |
|
|
word ETRIGE :1; /* External Trigger Mode enable */
|
| 1772 |
|
|
word ETRIGP :1; /* External Trigger Polarity */
|
| 1773 |
|
|
word ETRIGLE :1; /* External Trigger Level/Edge control */
|
| 1774 |
|
|
word AWAI :1; /* ATD 0 Wait Mode */
|
| 1775 |
|
|
word AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */
|
| 1776 |
|
|
word ADPU :1; /* ATD 0 Disable / Power Down */
|
| 1777 |
|
|
} Bits;
|
| 1778 |
|
|
struct {
|
| 1779 |
|
|
word grpFRZ :2;
|
| 1780 |
|
|
word :1;
|
| 1781 |
|
|
word :1;
|
| 1782 |
|
|
word :1;
|
| 1783 |
|
|
word :1;
|
| 1784 |
|
|
word :1;
|
| 1785 |
|
|
word :1;
|
| 1786 |
|
|
word :1;
|
| 1787 |
|
|
word :1;
|
| 1788 |
|
|
word :1;
|
| 1789 |
|
|
word :1;
|
| 1790 |
|
|
word :1;
|
| 1791 |
|
|
word :1;
|
| 1792 |
|
|
word :1;
|
| 1793 |
|
|
word :1;
|
| 1794 |
|
|
} MergedBits;
|
| 1795 |
|
|
} ATD0CTL23STR;
|
| 1796 |
|
|
extern volatile ATD0CTL23STR _ATD0CTL23 @(REG_BASE + 0x00000082);
|
| 1797 |
|
|
#define ATD0CTL23 _ATD0CTL23.Word
|
| 1798 |
|
|
#define ATD0CTL23_FRZ0 _ATD0CTL23.Bits.FRZ0
|
| 1799 |
|
|
#define ATD0CTL23_FRZ1 _ATD0CTL23.Bits.FRZ1
|
| 1800 |
|
|
#define ATD0CTL23_FIFO _ATD0CTL23.Bits.FIFO
|
| 1801 |
|
|
#define ATD0CTL23_S1C _ATD0CTL23.Bits.S1C
|
| 1802 |
|
|
#define ATD0CTL23_S2C _ATD0CTL23.Bits.S2C
|
| 1803 |
|
|
#define ATD0CTL23_S4C _ATD0CTL23.Bits.S4C
|
| 1804 |
|
|
#define ATD0CTL23_S8C _ATD0CTL23.Bits.S8C
|
| 1805 |
|
|
#define ATD0CTL23_ASCIF _ATD0CTL23.Bits.ASCIF
|
| 1806 |
|
|
#define ATD0CTL23_ASCIE _ATD0CTL23.Bits.ASCIE
|
| 1807 |
|
|
#define ATD0CTL23_ETRIGE _ATD0CTL23.Bits.ETRIGE
|
| 1808 |
|
|
#define ATD0CTL23_ETRIGP _ATD0CTL23.Bits.ETRIGP
|
| 1809 |
|
|
#define ATD0CTL23_ETRIGLE _ATD0CTL23.Bits.ETRIGLE
|
| 1810 |
|
|
#define ATD0CTL23_AWAI _ATD0CTL23.Bits.AWAI
|
| 1811 |
|
|
#define ATD0CTL23_AFFC _ATD0CTL23.Bits.AFFC
|
| 1812 |
|
|
#define ATD0CTL23_ADPU _ATD0CTL23.Bits.ADPU
|
| 1813 |
|
|
#define ATD0CTL23_FRZ _ATD0CTL23.MergedBits.grpFRZ
|
| 1814 |
|
|
|
| 1815 |
|
|
|
| 1816 |
|
|
/*** ATD0CTL45 - ATD 0 Control Register 45; 0x00000084 ***/
|
| 1817 |
|
|
typedef union {
|
| 1818 |
|
|
word Word;
|
| 1819 |
|
|
/* Overlapped registers: */
|
| 1820 |
|
|
struct {
|
| 1821 |
|
|
/*** ATD0CTL4 - ATD 0 Control Register 4; 0x00000084 ***/
|
| 1822 |
|
|
union {
|
| 1823 |
|
|
byte Byte;
|
| 1824 |
|
|
struct {
|
| 1825 |
|
|
byte PRS0 :1; /* ATD 0 Clock Prescaler 0 */
|
| 1826 |
|
|
byte PRS1 :1; /* ATD 0 Clock Prescaler 1 */
|
| 1827 |
|
|
byte PRS2 :1; /* ATD 0 Clock Prescaler 2 */
|
| 1828 |
|
|
byte PRS3 :1; /* ATD 0 Clock Prescaler 3 */
|
| 1829 |
|
|
byte PRS4 :1; /* ATD 0 Clock Prescaler 4 */
|
| 1830 |
|
|
byte SMP0 :1; /* Sample Time Select 0 */
|
| 1831 |
|
|
byte SMP1 :1; /* Sample Time Select 1 */
|
| 1832 |
|
|
byte SRES8 :1; /* ATD 0 Resolution Select */
|
| 1833 |
|
|
} Bits;
|
| 1834 |
|
|
struct {
|
| 1835 |
|
|
byte grpPRS :5;
|
| 1836 |
|
|
byte grpSMP :2;
|
| 1837 |
|
|
byte grpSRES_8 :1;
|
| 1838 |
|
|
} MergedBits;
|
| 1839 |
|
|
} ATD0CTL4STR;
|
| 1840 |
|
|
#define ATD0CTL4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Byte
|
| 1841 |
|
|
#define ATD0CTL4_PRS0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS0
|
| 1842 |
|
|
#define ATD0CTL4_PRS1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS1
|
| 1843 |
|
|
#define ATD0CTL4_PRS2 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS2
|
| 1844 |
|
|
#define ATD0CTL4_PRS3 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS3
|
| 1845 |
|
|
#define ATD0CTL4_PRS4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS4
|
| 1846 |
|
|
#define ATD0CTL4_SMP0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP0
|
| 1847 |
|
|
#define ATD0CTL4_SMP1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP1
|
| 1848 |
|
|
#define ATD0CTL4_SRES8 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SRES8
|
| 1849 |
|
|
#define ATD0CTL4_PRS _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpPRS
|
| 1850 |
|
|
#define ATD0CTL4_SMP _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpSMP
|
| 1851 |
|
|
|
| 1852 |
|
|
/*** ATD0CTL5 - ATD 0 Control Register 5; 0x00000085 ***/
|
| 1853 |
|
|
union {
|
| 1854 |
|
|
byte Byte;
|
| 1855 |
|
|
struct {
|
| 1856 |
|
|
byte CA :1; /* Analog Input Channel Select Code A */
|
| 1857 |
|
|
byte CB :1; /* Analog Input Channel Select Code B */
|
| 1858 |
|
|
byte CC :1; /* Analog Input Channel Select Code C */
|
| 1859 |
|
|
byte :1;
|
| 1860 |
|
|
byte MULT :1; /* Multi-Channel Sample Mode */
|
| 1861 |
|
|
byte SCAN :1; /* Continuous Conversion Sequence Mode */
|
| 1862 |
|
|
byte DSGN :1; /* Signed/Unsigned Result Data Mode */
|
| 1863 |
|
|
byte DJM :1; /* Result Register Data Justification Mode */
|
| 1864 |
|
|
} Bits;
|
| 1865 |
|
|
} ATD0CTL5STR;
|
| 1866 |
|
|
#define ATD0CTL5 _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Byte
|
| 1867 |
|
|
#define ATD0CTL5_CA _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CA
|
| 1868 |
|
|
#define ATD0CTL5_CB _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CB
|
| 1869 |
|
|
#define ATD0CTL5_CC _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CC
|
| 1870 |
|
|
#define ATD0CTL5_MULT _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.MULT
|
| 1871 |
|
|
#define ATD0CTL5_SCAN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.SCAN
|
| 1872 |
|
|
#define ATD0CTL5_DSGN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DSGN
|
| 1873 |
|
|
#define ATD0CTL5_DJM _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DJM
|
| 1874 |
|
|
|
| 1875 |
|
|
} Overlap_STR;
|
| 1876 |
|
|
|
| 1877 |
|
|
struct {
|
| 1878 |
|
|
word CA :1; /* Analog Input Channel Select Code A */
|
| 1879 |
|
|
word CB :1; /* Analog Input Channel Select Code B */
|
| 1880 |
|
|
word CC :1; /* Analog Input Channel Select Code C */
|
| 1881 |
|
|
word :1;
|
| 1882 |
|
|
word MULT :1; /* Multi-Channel Sample Mode */
|
| 1883 |
|
|
word SCAN :1; /* Continuous Conversion Sequence Mode */
|
| 1884 |
|
|
word DSGN :1; /* Signed/Unsigned Result Data Mode */
|
| 1885 |
|
|
word DJM :1; /* Result Register Data Justification Mode */
|
| 1886 |
|
|
word PRS0 :1; /* ATD 0 Clock Prescaler 0 */
|
| 1887 |
|
|
word PRS1 :1; /* ATD 0 Clock Prescaler 1 */
|
| 1888 |
|
|
word PRS2 :1; /* ATD 0 Clock Prescaler 2 */
|
| 1889 |
|
|
word PRS3 :1; /* ATD 0 Clock Prescaler 3 */
|
| 1890 |
|
|
word PRS4 :1; /* ATD 0 Clock Prescaler 4 */
|
| 1891 |
|
|
word SMP0 :1; /* Sample Time Select 0 */
|
| 1892 |
|
|
word SMP1 :1; /* Sample Time Select 1 */
|
| 1893 |
|
|
word SRES8 :1; /* ATD 0 Resolution Select */
|
| 1894 |
|
|
} Bits;
|
| 1895 |
|
|
struct {
|
| 1896 |
|
|
word :1;
|
| 1897 |
|
|
word :1;
|
| 1898 |
|
|
word :1;
|
| 1899 |
|
|
word :1;
|
| 1900 |
|
|
word :1;
|
| 1901 |
|
|
word :1;
|
| 1902 |
|
|
word :1;
|
| 1903 |
|
|
word :1;
|
| 1904 |
|
|
word grpPRS :5;
|
| 1905 |
|
|
word grpSMP :2;
|
| 1906 |
|
|
word grpSRES_8 :1;
|
| 1907 |
|
|
} MergedBits;
|
| 1908 |
|
|
} ATD0CTL45STR;
|
| 1909 |
|
|
extern volatile ATD0CTL45STR _ATD0CTL45 @(REG_BASE + 0x00000084);
|
| 1910 |
|
|
#define ATD0CTL45 _ATD0CTL45.Word
|
| 1911 |
|
|
#define ATD0CTL45_CA _ATD0CTL45.Bits.CA
|
| 1912 |
|
|
#define ATD0CTL45_CB _ATD0CTL45.Bits.CB
|
| 1913 |
|
|
#define ATD0CTL45_CC _ATD0CTL45.Bits.CC
|
| 1914 |
|
|
#define ATD0CTL45_MULT _ATD0CTL45.Bits.MULT
|
| 1915 |
|
|
#define ATD0CTL45_SCAN _ATD0CTL45.Bits.SCAN
|
| 1916 |
|
|
#define ATD0CTL45_DSGN _ATD0CTL45.Bits.DSGN
|
| 1917 |
|
|
#define ATD0CTL45_DJM _ATD0CTL45.Bits.DJM
|
| 1918 |
|
|
#define ATD0CTL45_PRS0 _ATD0CTL45.Bits.PRS0
|
| 1919 |
|
|
#define ATD0CTL45_PRS1 _ATD0CTL45.Bits.PRS1
|
| 1920 |
|
|
#define ATD0CTL45_PRS2 _ATD0CTL45.Bits.PRS2
|
| 1921 |
|
|
#define ATD0CTL45_PRS3 _ATD0CTL45.Bits.PRS3
|
| 1922 |
|
|
#define ATD0CTL45_PRS4 _ATD0CTL45.Bits.PRS4
|
| 1923 |
|
|
#define ATD0CTL45_SMP0 _ATD0CTL45.Bits.SMP0
|
| 1924 |
|
|
#define ATD0CTL45_SMP1 _ATD0CTL45.Bits.SMP1
|
| 1925 |
|
|
#define ATD0CTL45_SRES8 _ATD0CTL45.Bits.SRES8
|
| 1926 |
|
|
#define ATD0CTL45_PRS _ATD0CTL45.MergedBits.grpPRS
|
| 1927 |
|
|
#define ATD0CTL45_SMP _ATD0CTL45.MergedBits.grpSMP
|
| 1928 |
|
|
|
| 1929 |
|
|
|
| 1930 |
|
|
/*** ATD0DR0 - ATD 0 Conversion Result Register 0; 0x00000090 ***/
|
| 1931 |
|
|
typedef union {
|
| 1932 |
|
|
word Word;
|
| 1933 |
|
|
/* Overlapped registers: */
|
| 1934 |
|
|
struct {
|
| 1935 |
|
|
/*** ATD0DR0H - ATD 0 Conversion Result Register 0 High; 0x00000090 ***/
|
| 1936 |
|
|
union {
|
| 1937 |
|
|
byte Byte;
|
| 1938 |
|
|
struct {
|
| 1939 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 1940 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 1941 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 1942 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 1943 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 1944 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 1945 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 1946 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 1947 |
|
|
} Bits;
|
| 1948 |
|
|
struct {
|
| 1949 |
|
|
byte grpBIT_8 :8;
|
| 1950 |
|
|
} MergedBits;
|
| 1951 |
|
|
} ATD0DR0HSTR;
|
| 1952 |
|
|
#define ATD0DR0H _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Byte
|
| 1953 |
|
|
#define ATD0DR0H_BIT8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT8
|
| 1954 |
|
|
#define ATD0DR0H_BIT9 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT9
|
| 1955 |
|
|
#define ATD0DR0H_BIT10 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT10
|
| 1956 |
|
|
#define ATD0DR0H_BIT11 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT11
|
| 1957 |
|
|
#define ATD0DR0H_BIT12 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT12
|
| 1958 |
|
|
#define ATD0DR0H_BIT13 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT13
|
| 1959 |
|
|
#define ATD0DR0H_BIT14 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT14
|
| 1960 |
|
|
#define ATD0DR0H_BIT15 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT15
|
| 1961 |
|
|
#define ATD0DR0H_BIT_8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.MergedBits.grpBIT_8
|
| 1962 |
|
|
#define ATD0DR0H_BIT ATD0DR0H_BIT_8
|
| 1963 |
|
|
|
| 1964 |
|
|
/*** ATD0DR0L - ATD 0 Conversion Result Register 0 Low; 0x00000091 ***/
|
| 1965 |
|
|
union {
|
| 1966 |
|
|
byte Byte;
|
| 1967 |
|
|
struct {
|
| 1968 |
|
|
byte :1;
|
| 1969 |
|
|
byte :1;
|
| 1970 |
|
|
byte :1;
|
| 1971 |
|
|
byte :1;
|
| 1972 |
|
|
byte :1;
|
| 1973 |
|
|
byte :1;
|
| 1974 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 1975 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 1976 |
|
|
} Bits;
|
| 1977 |
|
|
struct {
|
| 1978 |
|
|
byte :1;
|
| 1979 |
|
|
byte :1;
|
| 1980 |
|
|
byte :1;
|
| 1981 |
|
|
byte :1;
|
| 1982 |
|
|
byte :1;
|
| 1983 |
|
|
byte :1;
|
| 1984 |
|
|
byte grpBIT_6 :2;
|
| 1985 |
|
|
} MergedBits;
|
| 1986 |
|
|
} ATD0DR0LSTR;
|
| 1987 |
|
|
#define ATD0DR0L _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Byte
|
| 1988 |
|
|
#define ATD0DR0L_BIT6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT6
|
| 1989 |
|
|
#define ATD0DR0L_BIT7 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT7
|
| 1990 |
|
|
#define ATD0DR0L_BIT_6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.MergedBits.grpBIT_6
|
| 1991 |
|
|
#define ATD0DR0L_BIT ATD0DR0L_BIT_6
|
| 1992 |
|
|
|
| 1993 |
|
|
} Overlap_STR;
|
| 1994 |
|
|
|
| 1995 |
|
|
struct {
|
| 1996 |
|
|
word :1;
|
| 1997 |
|
|
word :1;
|
| 1998 |
|
|
word :1;
|
| 1999 |
|
|
word :1;
|
| 2000 |
|
|
word :1;
|
| 2001 |
|
|
word :1;
|
| 2002 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 2003 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 2004 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 2005 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 2006 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 2007 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 2008 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 2009 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 2010 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 2011 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 2012 |
|
|
} Bits;
|
| 2013 |
|
|
struct {
|
| 2014 |
|
|
word :1;
|
| 2015 |
|
|
word :1;
|
| 2016 |
|
|
word :1;
|
| 2017 |
|
|
word :1;
|
| 2018 |
|
|
word :1;
|
| 2019 |
|
|
word :1;
|
| 2020 |
|
|
word grpBIT_6 :10;
|
| 2021 |
|
|
} MergedBits;
|
| 2022 |
|
|
} ATD0DR0STR;
|
| 2023 |
|
|
extern volatile ATD0DR0STR _ATD0DR0 @(REG_BASE + 0x00000090);
|
| 2024 |
|
|
#define ATD0DR0 _ATD0DR0.Word
|
| 2025 |
|
|
#define ATD0DR0_BIT6 _ATD0DR0.Bits.BIT6
|
| 2026 |
|
|
#define ATD0DR0_BIT7 _ATD0DR0.Bits.BIT7
|
| 2027 |
|
|
#define ATD0DR0_BIT8 _ATD0DR0.Bits.BIT8
|
| 2028 |
|
|
#define ATD0DR0_BIT9 _ATD0DR0.Bits.BIT9
|
| 2029 |
|
|
#define ATD0DR0_BIT10 _ATD0DR0.Bits.BIT10
|
| 2030 |
|
|
#define ATD0DR0_BIT11 _ATD0DR0.Bits.BIT11
|
| 2031 |
|
|
#define ATD0DR0_BIT12 _ATD0DR0.Bits.BIT12
|
| 2032 |
|
|
#define ATD0DR0_BIT13 _ATD0DR0.Bits.BIT13
|
| 2033 |
|
|
#define ATD0DR0_BIT14 _ATD0DR0.Bits.BIT14
|
| 2034 |
|
|
#define ATD0DR0_BIT15 _ATD0DR0.Bits.BIT15
|
| 2035 |
|
|
#define ATD0DR0_BIT_6 _ATD0DR0.MergedBits.grpBIT_6
|
| 2036 |
|
|
#define ATD0DR0_BIT ATD0DR0_BIT_6
|
| 2037 |
|
|
|
| 2038 |
|
|
|
| 2039 |
|
|
/*** ATD0DR1 - ATD 0 Conversion Result Register 1; 0x00000092 ***/
|
| 2040 |
|
|
typedef union {
|
| 2041 |
|
|
word Word;
|
| 2042 |
|
|
/* Overlapped registers: */
|
| 2043 |
|
|
struct {
|
| 2044 |
|
|
/*** ATD0DR1H - ATD 0 Conversion Result Register 1 High; 0x00000092 ***/
|
| 2045 |
|
|
union {
|
| 2046 |
|
|
byte Byte;
|
| 2047 |
|
|
struct {
|
| 2048 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 2049 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 2050 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 2051 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 2052 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 2053 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 2054 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 2055 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 2056 |
|
|
} Bits;
|
| 2057 |
|
|
struct {
|
| 2058 |
|
|
byte grpBIT_8 :8;
|
| 2059 |
|
|
} MergedBits;
|
| 2060 |
|
|
} ATD0DR1HSTR;
|
| 2061 |
|
|
#define ATD0DR1H _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Byte
|
| 2062 |
|
|
#define ATD0DR1H_BIT8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT8
|
| 2063 |
|
|
#define ATD0DR1H_BIT9 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT9
|
| 2064 |
|
|
#define ATD0DR1H_BIT10 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT10
|
| 2065 |
|
|
#define ATD0DR1H_BIT11 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT11
|
| 2066 |
|
|
#define ATD0DR1H_BIT12 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT12
|
| 2067 |
|
|
#define ATD0DR1H_BIT13 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT13
|
| 2068 |
|
|
#define ATD0DR1H_BIT14 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT14
|
| 2069 |
|
|
#define ATD0DR1H_BIT15 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT15
|
| 2070 |
|
|
#define ATD0DR1H_BIT_8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.MergedBits.grpBIT_8
|
| 2071 |
|
|
#define ATD0DR1H_BIT ATD0DR1H_BIT_8
|
| 2072 |
|
|
|
| 2073 |
|
|
/*** ATD0DR1L - ATD 0 Conversion Result Register 1 Low; 0x00000093 ***/
|
| 2074 |
|
|
union {
|
| 2075 |
|
|
byte Byte;
|
| 2076 |
|
|
struct {
|
| 2077 |
|
|
byte :1;
|
| 2078 |
|
|
byte :1;
|
| 2079 |
|
|
byte :1;
|
| 2080 |
|
|
byte :1;
|
| 2081 |
|
|
byte :1;
|
| 2082 |
|
|
byte :1;
|
| 2083 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 2084 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 2085 |
|
|
} Bits;
|
| 2086 |
|
|
struct {
|
| 2087 |
|
|
byte :1;
|
| 2088 |
|
|
byte :1;
|
| 2089 |
|
|
byte :1;
|
| 2090 |
|
|
byte :1;
|
| 2091 |
|
|
byte :1;
|
| 2092 |
|
|
byte :1;
|
| 2093 |
|
|
byte grpBIT_6 :2;
|
| 2094 |
|
|
} MergedBits;
|
| 2095 |
|
|
} ATD0DR1LSTR;
|
| 2096 |
|
|
#define ATD0DR1L _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Byte
|
| 2097 |
|
|
#define ATD0DR1L_BIT6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT6
|
| 2098 |
|
|
#define ATD0DR1L_BIT7 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT7
|
| 2099 |
|
|
#define ATD0DR1L_BIT_6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.MergedBits.grpBIT_6
|
| 2100 |
|
|
#define ATD0DR1L_BIT ATD0DR1L_BIT_6
|
| 2101 |
|
|
|
| 2102 |
|
|
} Overlap_STR;
|
| 2103 |
|
|
|
| 2104 |
|
|
struct {
|
| 2105 |
|
|
word :1;
|
| 2106 |
|
|
word :1;
|
| 2107 |
|
|
word :1;
|
| 2108 |
|
|
word :1;
|
| 2109 |
|
|
word :1;
|
| 2110 |
|
|
word :1;
|
| 2111 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 2112 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 2113 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 2114 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 2115 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 2116 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 2117 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 2118 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 2119 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 2120 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 2121 |
|
|
} Bits;
|
| 2122 |
|
|
struct {
|
| 2123 |
|
|
word :1;
|
| 2124 |
|
|
word :1;
|
| 2125 |
|
|
word :1;
|
| 2126 |
|
|
word :1;
|
| 2127 |
|
|
word :1;
|
| 2128 |
|
|
word :1;
|
| 2129 |
|
|
word grpBIT_6 :10;
|
| 2130 |
|
|
} MergedBits;
|
| 2131 |
|
|
} ATD0DR1STR;
|
| 2132 |
|
|
extern volatile ATD0DR1STR _ATD0DR1 @(REG_BASE + 0x00000092);
|
| 2133 |
|
|
#define ATD0DR1 _ATD0DR1.Word
|
| 2134 |
|
|
#define ATD0DR1_BIT6 _ATD0DR1.Bits.BIT6
|
| 2135 |
|
|
#define ATD0DR1_BIT7 _ATD0DR1.Bits.BIT7
|
| 2136 |
|
|
#define ATD0DR1_BIT8 _ATD0DR1.Bits.BIT8
|
| 2137 |
|
|
#define ATD0DR1_BIT9 _ATD0DR1.Bits.BIT9
|
| 2138 |
|
|
#define ATD0DR1_BIT10 _ATD0DR1.Bits.BIT10
|
| 2139 |
|
|
#define ATD0DR1_BIT11 _ATD0DR1.Bits.BIT11
|
| 2140 |
|
|
#define ATD0DR1_BIT12 _ATD0DR1.Bits.BIT12
|
| 2141 |
|
|
#define ATD0DR1_BIT13 _ATD0DR1.Bits.BIT13
|
| 2142 |
|
|
#define ATD0DR1_BIT14 _ATD0DR1.Bits.BIT14
|
| 2143 |
|
|
#define ATD0DR1_BIT15 _ATD0DR1.Bits.BIT15
|
| 2144 |
|
|
#define ATD0DR1_BIT_6 _ATD0DR1.MergedBits.grpBIT_6
|
| 2145 |
|
|
#define ATD0DR1_BIT ATD0DR1_BIT_6
|
| 2146 |
|
|
|
| 2147 |
|
|
|
| 2148 |
|
|
/*** ATD0DR2 - ATD 0 Conversion Result Register 2; 0x00000094 ***/
|
| 2149 |
|
|
typedef union {
|
| 2150 |
|
|
word Word;
|
| 2151 |
|
|
/* Overlapped registers: */
|
| 2152 |
|
|
struct {
|
| 2153 |
|
|
/*** ATD0DR2H - ATD 0 Conversion Result Register 2 High; 0x00000094 ***/
|
| 2154 |
|
|
union {
|
| 2155 |
|
|
byte Byte;
|
| 2156 |
|
|
struct {
|
| 2157 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 2158 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 2159 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 2160 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 2161 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 2162 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 2163 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 2164 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 2165 |
|
|
} Bits;
|
| 2166 |
|
|
struct {
|
| 2167 |
|
|
byte grpBIT_8 :8;
|
| 2168 |
|
|
} MergedBits;
|
| 2169 |
|
|
} ATD0DR2HSTR;
|
| 2170 |
|
|
#define ATD0DR2H _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Byte
|
| 2171 |
|
|
#define ATD0DR2H_BIT8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT8
|
| 2172 |
|
|
#define ATD0DR2H_BIT9 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT9
|
| 2173 |
|
|
#define ATD0DR2H_BIT10 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT10
|
| 2174 |
|
|
#define ATD0DR2H_BIT11 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT11
|
| 2175 |
|
|
#define ATD0DR2H_BIT12 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT12
|
| 2176 |
|
|
#define ATD0DR2H_BIT13 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT13
|
| 2177 |
|
|
#define ATD0DR2H_BIT14 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT14
|
| 2178 |
|
|
#define ATD0DR2H_BIT15 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT15
|
| 2179 |
|
|
#define ATD0DR2H_BIT_8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.MergedBits.grpBIT_8
|
| 2180 |
|
|
#define ATD0DR2H_BIT ATD0DR2H_BIT_8
|
| 2181 |
|
|
|
| 2182 |
|
|
/*** ATD0DR2L - ATD 0 Conversion Result Register 2 Low; 0x00000095 ***/
|
| 2183 |
|
|
union {
|
| 2184 |
|
|
byte Byte;
|
| 2185 |
|
|
struct {
|
| 2186 |
|
|
byte :1;
|
| 2187 |
|
|
byte :1;
|
| 2188 |
|
|
byte :1;
|
| 2189 |
|
|
byte :1;
|
| 2190 |
|
|
byte :1;
|
| 2191 |
|
|
byte :1;
|
| 2192 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 2193 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 2194 |
|
|
} Bits;
|
| 2195 |
|
|
struct {
|
| 2196 |
|
|
byte :1;
|
| 2197 |
|
|
byte :1;
|
| 2198 |
|
|
byte :1;
|
| 2199 |
|
|
byte :1;
|
| 2200 |
|
|
byte :1;
|
| 2201 |
|
|
byte :1;
|
| 2202 |
|
|
byte grpBIT_6 :2;
|
| 2203 |
|
|
} MergedBits;
|
| 2204 |
|
|
} ATD0DR2LSTR;
|
| 2205 |
|
|
#define ATD0DR2L _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Byte
|
| 2206 |
|
|
#define ATD0DR2L_BIT6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT6
|
| 2207 |
|
|
#define ATD0DR2L_BIT7 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT7
|
| 2208 |
|
|
#define ATD0DR2L_BIT_6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.MergedBits.grpBIT_6
|
| 2209 |
|
|
#define ATD0DR2L_BIT ATD0DR2L_BIT_6
|
| 2210 |
|
|
|
| 2211 |
|
|
} Overlap_STR;
|
| 2212 |
|
|
|
| 2213 |
|
|
struct {
|
| 2214 |
|
|
word :1;
|
| 2215 |
|
|
word :1;
|
| 2216 |
|
|
word :1;
|
| 2217 |
|
|
word :1;
|
| 2218 |
|
|
word :1;
|
| 2219 |
|
|
word :1;
|
| 2220 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 2221 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 2222 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 2223 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 2224 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 2225 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 2226 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 2227 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 2228 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 2229 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 2230 |
|
|
} Bits;
|
| 2231 |
|
|
struct {
|
| 2232 |
|
|
word :1;
|
| 2233 |
|
|
word :1;
|
| 2234 |
|
|
word :1;
|
| 2235 |
|
|
word :1;
|
| 2236 |
|
|
word :1;
|
| 2237 |
|
|
word :1;
|
| 2238 |
|
|
word grpBIT_6 :10;
|
| 2239 |
|
|
} MergedBits;
|
| 2240 |
|
|
} ATD0DR2STR;
|
| 2241 |
|
|
extern volatile ATD0DR2STR _ATD0DR2 @(REG_BASE + 0x00000094);
|
| 2242 |
|
|
#define ATD0DR2 _ATD0DR2.Word
|
| 2243 |
|
|
#define ATD0DR2_BIT6 _ATD0DR2.Bits.BIT6
|
| 2244 |
|
|
#define ATD0DR2_BIT7 _ATD0DR2.Bits.BIT7
|
| 2245 |
|
|
#define ATD0DR2_BIT8 _ATD0DR2.Bits.BIT8
|
| 2246 |
|
|
#define ATD0DR2_BIT9 _ATD0DR2.Bits.BIT9
|
| 2247 |
|
|
#define ATD0DR2_BIT10 _ATD0DR2.Bits.BIT10
|
| 2248 |
|
|
#define ATD0DR2_BIT11 _ATD0DR2.Bits.BIT11
|
| 2249 |
|
|
#define ATD0DR2_BIT12 _ATD0DR2.Bits.BIT12
|
| 2250 |
|
|
#define ATD0DR2_BIT13 _ATD0DR2.Bits.BIT13
|
| 2251 |
|
|
#define ATD0DR2_BIT14 _ATD0DR2.Bits.BIT14
|
| 2252 |
|
|
#define ATD0DR2_BIT15 _ATD0DR2.Bits.BIT15
|
| 2253 |
|
|
#define ATD0DR2_BIT_6 _ATD0DR2.MergedBits.grpBIT_6
|
| 2254 |
|
|
#define ATD0DR2_BIT ATD0DR2_BIT_6
|
| 2255 |
|
|
|
| 2256 |
|
|
|
| 2257 |
|
|
/*** ATD0DR3 - ATD 0 Conversion Result Register 3; 0x00000096 ***/
|
| 2258 |
|
|
typedef union {
|
| 2259 |
|
|
word Word;
|
| 2260 |
|
|
/* Overlapped registers: */
|
| 2261 |
|
|
struct {
|
| 2262 |
|
|
/*** ATD0DR3H - ATD 0 Conversion Result Register 3 High; 0x00000096 ***/
|
| 2263 |
|
|
union {
|
| 2264 |
|
|
byte Byte;
|
| 2265 |
|
|
struct {
|
| 2266 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 2267 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 2268 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 2269 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 2270 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 2271 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 2272 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 2273 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 2274 |
|
|
} Bits;
|
| 2275 |
|
|
struct {
|
| 2276 |
|
|
byte grpBIT_8 :8;
|
| 2277 |
|
|
} MergedBits;
|
| 2278 |
|
|
} ATD0DR3HSTR;
|
| 2279 |
|
|
#define ATD0DR3H _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Byte
|
| 2280 |
|
|
#define ATD0DR3H_BIT8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT8
|
| 2281 |
|
|
#define ATD0DR3H_BIT9 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT9
|
| 2282 |
|
|
#define ATD0DR3H_BIT10 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT10
|
| 2283 |
|
|
#define ATD0DR3H_BIT11 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT11
|
| 2284 |
|
|
#define ATD0DR3H_BIT12 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT12
|
| 2285 |
|
|
#define ATD0DR3H_BIT13 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT13
|
| 2286 |
|
|
#define ATD0DR3H_BIT14 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT14
|
| 2287 |
|
|
#define ATD0DR3H_BIT15 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT15
|
| 2288 |
|
|
#define ATD0DR3H_BIT_8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.MergedBits.grpBIT_8
|
| 2289 |
|
|
#define ATD0DR3H_BIT ATD0DR3H_BIT_8
|
| 2290 |
|
|
|
| 2291 |
|
|
/*** ATD0DR3L - ATD 0 Conversion Result Register 3 Low; 0x00000097 ***/
|
| 2292 |
|
|
union {
|
| 2293 |
|
|
byte Byte;
|
| 2294 |
|
|
struct {
|
| 2295 |
|
|
byte :1;
|
| 2296 |
|
|
byte :1;
|
| 2297 |
|
|
byte :1;
|
| 2298 |
|
|
byte :1;
|
| 2299 |
|
|
byte :1;
|
| 2300 |
|
|
byte :1;
|
| 2301 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 2302 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 2303 |
|
|
} Bits;
|
| 2304 |
|
|
struct {
|
| 2305 |
|
|
byte :1;
|
| 2306 |
|
|
byte :1;
|
| 2307 |
|
|
byte :1;
|
| 2308 |
|
|
byte :1;
|
| 2309 |
|
|
byte :1;
|
| 2310 |
|
|
byte :1;
|
| 2311 |
|
|
byte grpBIT_6 :2;
|
| 2312 |
|
|
} MergedBits;
|
| 2313 |
|
|
} ATD0DR3LSTR;
|
| 2314 |
|
|
#define ATD0DR3L _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Byte
|
| 2315 |
|
|
#define ATD0DR3L_BIT6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT6
|
| 2316 |
|
|
#define ATD0DR3L_BIT7 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT7
|
| 2317 |
|
|
#define ATD0DR3L_BIT_6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.MergedBits.grpBIT_6
|
| 2318 |
|
|
#define ATD0DR3L_BIT ATD0DR3L_BIT_6
|
| 2319 |
|
|
|
| 2320 |
|
|
} Overlap_STR;
|
| 2321 |
|
|
|
| 2322 |
|
|
struct {
|
| 2323 |
|
|
word :1;
|
| 2324 |
|
|
word :1;
|
| 2325 |
|
|
word :1;
|
| 2326 |
|
|
word :1;
|
| 2327 |
|
|
word :1;
|
| 2328 |
|
|
word :1;
|
| 2329 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 2330 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 2331 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 2332 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 2333 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 2334 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 2335 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 2336 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 2337 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 2338 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 2339 |
|
|
} Bits;
|
| 2340 |
|
|
struct {
|
| 2341 |
|
|
word :1;
|
| 2342 |
|
|
word :1;
|
| 2343 |
|
|
word :1;
|
| 2344 |
|
|
word :1;
|
| 2345 |
|
|
word :1;
|
| 2346 |
|
|
word :1;
|
| 2347 |
|
|
word grpBIT_6 :10;
|
| 2348 |
|
|
} MergedBits;
|
| 2349 |
|
|
} ATD0DR3STR;
|
| 2350 |
|
|
extern volatile ATD0DR3STR _ATD0DR3 @(REG_BASE + 0x00000096);
|
| 2351 |
|
|
#define ATD0DR3 _ATD0DR3.Word
|
| 2352 |
|
|
#define ATD0DR3_BIT6 _ATD0DR3.Bits.BIT6
|
| 2353 |
|
|
#define ATD0DR3_BIT7 _ATD0DR3.Bits.BIT7
|
| 2354 |
|
|
#define ATD0DR3_BIT8 _ATD0DR3.Bits.BIT8
|
| 2355 |
|
|
#define ATD0DR3_BIT9 _ATD0DR3.Bits.BIT9
|
| 2356 |
|
|
#define ATD0DR3_BIT10 _ATD0DR3.Bits.BIT10
|
| 2357 |
|
|
#define ATD0DR3_BIT11 _ATD0DR3.Bits.BIT11
|
| 2358 |
|
|
#define ATD0DR3_BIT12 _ATD0DR3.Bits.BIT12
|
| 2359 |
|
|
#define ATD0DR3_BIT13 _ATD0DR3.Bits.BIT13
|
| 2360 |
|
|
#define ATD0DR3_BIT14 _ATD0DR3.Bits.BIT14
|
| 2361 |
|
|
#define ATD0DR3_BIT15 _ATD0DR3.Bits.BIT15
|
| 2362 |
|
|
#define ATD0DR3_BIT_6 _ATD0DR3.MergedBits.grpBIT_6
|
| 2363 |
|
|
#define ATD0DR3_BIT ATD0DR3_BIT_6
|
| 2364 |
|
|
|
| 2365 |
|
|
|
| 2366 |
|
|
/*** ATD0DR4 - ATD 0 Conversion Result Register 4; 0x00000098 ***/
|
| 2367 |
|
|
typedef union {
|
| 2368 |
|
|
word Word;
|
| 2369 |
|
|
/* Overlapped registers: */
|
| 2370 |
|
|
struct {
|
| 2371 |
|
|
/*** ATD0DR4H - ATD 0 Conversion Result Register 4 High; 0x00000098 ***/
|
| 2372 |
|
|
union {
|
| 2373 |
|
|
byte Byte;
|
| 2374 |
|
|
struct {
|
| 2375 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 2376 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 2377 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 2378 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 2379 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 2380 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 2381 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 2382 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 2383 |
|
|
} Bits;
|
| 2384 |
|
|
struct {
|
| 2385 |
|
|
byte grpBIT_8 :8;
|
| 2386 |
|
|
} MergedBits;
|
| 2387 |
|
|
} ATD0DR4HSTR;
|
| 2388 |
|
|
#define ATD0DR4H _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Byte
|
| 2389 |
|
|
#define ATD0DR4H_BIT8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT8
|
| 2390 |
|
|
#define ATD0DR4H_BIT9 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT9
|
| 2391 |
|
|
#define ATD0DR4H_BIT10 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT10
|
| 2392 |
|
|
#define ATD0DR4H_BIT11 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT11
|
| 2393 |
|
|
#define ATD0DR4H_BIT12 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT12
|
| 2394 |
|
|
#define ATD0DR4H_BIT13 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT13
|
| 2395 |
|
|
#define ATD0DR4H_BIT14 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT14
|
| 2396 |
|
|
#define ATD0DR4H_BIT15 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT15
|
| 2397 |
|
|
#define ATD0DR4H_BIT_8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.MergedBits.grpBIT_8
|
| 2398 |
|
|
#define ATD0DR4H_BIT ATD0DR4H_BIT_8
|
| 2399 |
|
|
|
| 2400 |
|
|
/*** ATD0DR4L - ATD 0 Conversion Result Register 4 Low; 0x00000099 ***/
|
| 2401 |
|
|
union {
|
| 2402 |
|
|
byte Byte;
|
| 2403 |
|
|
struct {
|
| 2404 |
|
|
byte :1;
|
| 2405 |
|
|
byte :1;
|
| 2406 |
|
|
byte :1;
|
| 2407 |
|
|
byte :1;
|
| 2408 |
|
|
byte :1;
|
| 2409 |
|
|
byte :1;
|
| 2410 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 2411 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 2412 |
|
|
} Bits;
|
| 2413 |
|
|
struct {
|
| 2414 |
|
|
byte :1;
|
| 2415 |
|
|
byte :1;
|
| 2416 |
|
|
byte :1;
|
| 2417 |
|
|
byte :1;
|
| 2418 |
|
|
byte :1;
|
| 2419 |
|
|
byte :1;
|
| 2420 |
|
|
byte grpBIT_6 :2;
|
| 2421 |
|
|
} MergedBits;
|
| 2422 |
|
|
} ATD0DR4LSTR;
|
| 2423 |
|
|
#define ATD0DR4L _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Byte
|
| 2424 |
|
|
#define ATD0DR4L_BIT6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT6
|
| 2425 |
|
|
#define ATD0DR4L_BIT7 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT7
|
| 2426 |
|
|
#define ATD0DR4L_BIT_6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.MergedBits.grpBIT_6
|
| 2427 |
|
|
#define ATD0DR4L_BIT ATD0DR4L_BIT_6
|
| 2428 |
|
|
|
| 2429 |
|
|
} Overlap_STR;
|
| 2430 |
|
|
|
| 2431 |
|
|
struct {
|
| 2432 |
|
|
word :1;
|
| 2433 |
|
|
word :1;
|
| 2434 |
|
|
word :1;
|
| 2435 |
|
|
word :1;
|
| 2436 |
|
|
word :1;
|
| 2437 |
|
|
word :1;
|
| 2438 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 2439 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 2440 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 2441 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 2442 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 2443 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 2444 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 2445 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 2446 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 2447 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 2448 |
|
|
} Bits;
|
| 2449 |
|
|
struct {
|
| 2450 |
|
|
word :1;
|
| 2451 |
|
|
word :1;
|
| 2452 |
|
|
word :1;
|
| 2453 |
|
|
word :1;
|
| 2454 |
|
|
word :1;
|
| 2455 |
|
|
word :1;
|
| 2456 |
|
|
word grpBIT_6 :10;
|
| 2457 |
|
|
} MergedBits;
|
| 2458 |
|
|
} ATD0DR4STR;
|
| 2459 |
|
|
extern volatile ATD0DR4STR _ATD0DR4 @(REG_BASE + 0x00000098);
|
| 2460 |
|
|
#define ATD0DR4 _ATD0DR4.Word
|
| 2461 |
|
|
#define ATD0DR4_BIT6 _ATD0DR4.Bits.BIT6
|
| 2462 |
|
|
#define ATD0DR4_BIT7 _ATD0DR4.Bits.BIT7
|
| 2463 |
|
|
#define ATD0DR4_BIT8 _ATD0DR4.Bits.BIT8
|
| 2464 |
|
|
#define ATD0DR4_BIT9 _ATD0DR4.Bits.BIT9
|
| 2465 |
|
|
#define ATD0DR4_BIT10 _ATD0DR4.Bits.BIT10
|
| 2466 |
|
|
#define ATD0DR4_BIT11 _ATD0DR4.Bits.BIT11
|
| 2467 |
|
|
#define ATD0DR4_BIT12 _ATD0DR4.Bits.BIT12
|
| 2468 |
|
|
#define ATD0DR4_BIT13 _ATD0DR4.Bits.BIT13
|
| 2469 |
|
|
#define ATD0DR4_BIT14 _ATD0DR4.Bits.BIT14
|
| 2470 |
|
|
#define ATD0DR4_BIT15 _ATD0DR4.Bits.BIT15
|
| 2471 |
|
|
#define ATD0DR4_BIT_6 _ATD0DR4.MergedBits.grpBIT_6
|
| 2472 |
|
|
#define ATD0DR4_BIT ATD0DR4_BIT_6
|
| 2473 |
|
|
|
| 2474 |
|
|
|
| 2475 |
|
|
/*** ATD0DR5 - ATD 0 Conversion Result Register 5; 0x0000009A ***/
|
| 2476 |
|
|
typedef union {
|
| 2477 |
|
|
word Word;
|
| 2478 |
|
|
/* Overlapped registers: */
|
| 2479 |
|
|
struct {
|
| 2480 |
|
|
/*** ATD0DR5H - ATD 0 Conversion Result Register 5 High; 0x0000009A ***/
|
| 2481 |
|
|
union {
|
| 2482 |
|
|
byte Byte;
|
| 2483 |
|
|
struct {
|
| 2484 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 2485 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 2486 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 2487 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 2488 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 2489 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 2490 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 2491 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 2492 |
|
|
} Bits;
|
| 2493 |
|
|
struct {
|
| 2494 |
|
|
byte grpBIT_8 :8;
|
| 2495 |
|
|
} MergedBits;
|
| 2496 |
|
|
} ATD0DR5HSTR;
|
| 2497 |
|
|
#define ATD0DR5H _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Byte
|
| 2498 |
|
|
#define ATD0DR5H_BIT8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT8
|
| 2499 |
|
|
#define ATD0DR5H_BIT9 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT9
|
| 2500 |
|
|
#define ATD0DR5H_BIT10 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT10
|
| 2501 |
|
|
#define ATD0DR5H_BIT11 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT11
|
| 2502 |
|
|
#define ATD0DR5H_BIT12 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT12
|
| 2503 |
|
|
#define ATD0DR5H_BIT13 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT13
|
| 2504 |
|
|
#define ATD0DR5H_BIT14 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT14
|
| 2505 |
|
|
#define ATD0DR5H_BIT15 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT15
|
| 2506 |
|
|
#define ATD0DR5H_BIT_8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.MergedBits.grpBIT_8
|
| 2507 |
|
|
#define ATD0DR5H_BIT ATD0DR5H_BIT_8
|
| 2508 |
|
|
|
| 2509 |
|
|
/*** ATD0DR5L - ATD 0 Conversion Result Register 5 Low; 0x0000009B ***/
|
| 2510 |
|
|
union {
|
| 2511 |
|
|
byte Byte;
|
| 2512 |
|
|
struct {
|
| 2513 |
|
|
byte :1;
|
| 2514 |
|
|
byte :1;
|
| 2515 |
|
|
byte :1;
|
| 2516 |
|
|
byte :1;
|
| 2517 |
|
|
byte :1;
|
| 2518 |
|
|
byte :1;
|
| 2519 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 2520 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 2521 |
|
|
} Bits;
|
| 2522 |
|
|
struct {
|
| 2523 |
|
|
byte :1;
|
| 2524 |
|
|
byte :1;
|
| 2525 |
|
|
byte :1;
|
| 2526 |
|
|
byte :1;
|
| 2527 |
|
|
byte :1;
|
| 2528 |
|
|
byte :1;
|
| 2529 |
|
|
byte grpBIT_6 :2;
|
| 2530 |
|
|
} MergedBits;
|
| 2531 |
|
|
} ATD0DR5LSTR;
|
| 2532 |
|
|
#define ATD0DR5L _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Byte
|
| 2533 |
|
|
#define ATD0DR5L_BIT6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT6
|
| 2534 |
|
|
#define ATD0DR5L_BIT7 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT7
|
| 2535 |
|
|
#define ATD0DR5L_BIT_6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.MergedBits.grpBIT_6
|
| 2536 |
|
|
#define ATD0DR5L_BIT ATD0DR5L_BIT_6
|
| 2537 |
|
|
|
| 2538 |
|
|
} Overlap_STR;
|
| 2539 |
|
|
|
| 2540 |
|
|
struct {
|
| 2541 |
|
|
word :1;
|
| 2542 |
|
|
word :1;
|
| 2543 |
|
|
word :1;
|
| 2544 |
|
|
word :1;
|
| 2545 |
|
|
word :1;
|
| 2546 |
|
|
word :1;
|
| 2547 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 2548 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 2549 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 2550 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 2551 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 2552 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 2553 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 2554 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 2555 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 2556 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 2557 |
|
|
} Bits;
|
| 2558 |
|
|
struct {
|
| 2559 |
|
|
word :1;
|
| 2560 |
|
|
word :1;
|
| 2561 |
|
|
word :1;
|
| 2562 |
|
|
word :1;
|
| 2563 |
|
|
word :1;
|
| 2564 |
|
|
word :1;
|
| 2565 |
|
|
word grpBIT_6 :10;
|
| 2566 |
|
|
} MergedBits;
|
| 2567 |
|
|
} ATD0DR5STR;
|
| 2568 |
|
|
extern volatile ATD0DR5STR _ATD0DR5 @(REG_BASE + 0x0000009A);
|
| 2569 |
|
|
#define ATD0DR5 _ATD0DR5.Word
|
| 2570 |
|
|
#define ATD0DR5_BIT6 _ATD0DR5.Bits.BIT6
|
| 2571 |
|
|
#define ATD0DR5_BIT7 _ATD0DR5.Bits.BIT7
|
| 2572 |
|
|
#define ATD0DR5_BIT8 _ATD0DR5.Bits.BIT8
|
| 2573 |
|
|
#define ATD0DR5_BIT9 _ATD0DR5.Bits.BIT9
|
| 2574 |
|
|
#define ATD0DR5_BIT10 _ATD0DR5.Bits.BIT10
|
| 2575 |
|
|
#define ATD0DR5_BIT11 _ATD0DR5.Bits.BIT11
|
| 2576 |
|
|
#define ATD0DR5_BIT12 _ATD0DR5.Bits.BIT12
|
| 2577 |
|
|
#define ATD0DR5_BIT13 _ATD0DR5.Bits.BIT13
|
| 2578 |
|
|
#define ATD0DR5_BIT14 _ATD0DR5.Bits.BIT14
|
| 2579 |
|
|
#define ATD0DR5_BIT15 _ATD0DR5.Bits.BIT15
|
| 2580 |
|
|
#define ATD0DR5_BIT_6 _ATD0DR5.MergedBits.grpBIT_6
|
| 2581 |
|
|
#define ATD0DR5_BIT ATD0DR5_BIT_6
|
| 2582 |
|
|
|
| 2583 |
|
|
|
| 2584 |
|
|
/*** ATD0DR6 - ATD 0 Conversion Result Register 6; 0x0000009C ***/
|
| 2585 |
|
|
typedef union {
|
| 2586 |
|
|
word Word;
|
| 2587 |
|
|
/* Overlapped registers: */
|
| 2588 |
|
|
struct {
|
| 2589 |
|
|
/*** ATD0DR6H - ATD 0 Conversion Result Register 6 High; 0x0000009C ***/
|
| 2590 |
|
|
union {
|
| 2591 |
|
|
byte Byte;
|
| 2592 |
|
|
struct {
|
| 2593 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 2594 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 2595 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 2596 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 2597 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 2598 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 2599 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 2600 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 2601 |
|
|
} Bits;
|
| 2602 |
|
|
struct {
|
| 2603 |
|
|
byte grpBIT_8 :8;
|
| 2604 |
|
|
} MergedBits;
|
| 2605 |
|
|
} ATD0DR6HSTR;
|
| 2606 |
|
|
#define ATD0DR6H _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Byte
|
| 2607 |
|
|
#define ATD0DR6H_BIT8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT8
|
| 2608 |
|
|
#define ATD0DR6H_BIT9 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT9
|
| 2609 |
|
|
#define ATD0DR6H_BIT10 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT10
|
| 2610 |
|
|
#define ATD0DR6H_BIT11 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT11
|
| 2611 |
|
|
#define ATD0DR6H_BIT12 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT12
|
| 2612 |
|
|
#define ATD0DR6H_BIT13 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT13
|
| 2613 |
|
|
#define ATD0DR6H_BIT14 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT14
|
| 2614 |
|
|
#define ATD0DR6H_BIT15 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT15
|
| 2615 |
|
|
#define ATD0DR6H_BIT_8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.MergedBits.grpBIT_8
|
| 2616 |
|
|
#define ATD0DR6H_BIT ATD0DR6H_BIT_8
|
| 2617 |
|
|
|
| 2618 |
|
|
/*** ATD0DR6L - ATD 0 Conversion Result Register 6 Low; 0x0000009D ***/
|
| 2619 |
|
|
union {
|
| 2620 |
|
|
byte Byte;
|
| 2621 |
|
|
struct {
|
| 2622 |
|
|
byte :1;
|
| 2623 |
|
|
byte :1;
|
| 2624 |
|
|
byte :1;
|
| 2625 |
|
|
byte :1;
|
| 2626 |
|
|
byte :1;
|
| 2627 |
|
|
byte :1;
|
| 2628 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 2629 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 2630 |
|
|
} Bits;
|
| 2631 |
|
|
struct {
|
| 2632 |
|
|
byte :1;
|
| 2633 |
|
|
byte :1;
|
| 2634 |
|
|
byte :1;
|
| 2635 |
|
|
byte :1;
|
| 2636 |
|
|
byte :1;
|
| 2637 |
|
|
byte :1;
|
| 2638 |
|
|
byte grpBIT_6 :2;
|
| 2639 |
|
|
} MergedBits;
|
| 2640 |
|
|
} ATD0DR6LSTR;
|
| 2641 |
|
|
#define ATD0DR6L _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Byte
|
| 2642 |
|
|
#define ATD0DR6L_BIT6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT6
|
| 2643 |
|
|
#define ATD0DR6L_BIT7 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT7
|
| 2644 |
|
|
#define ATD0DR6L_BIT_6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.MergedBits.grpBIT_6
|
| 2645 |
|
|
#define ATD0DR6L_BIT ATD0DR6L_BIT_6
|
| 2646 |
|
|
|
| 2647 |
|
|
} Overlap_STR;
|
| 2648 |
|
|
|
| 2649 |
|
|
struct {
|
| 2650 |
|
|
word :1;
|
| 2651 |
|
|
word :1;
|
| 2652 |
|
|
word :1;
|
| 2653 |
|
|
word :1;
|
| 2654 |
|
|
word :1;
|
| 2655 |
|
|
word :1;
|
| 2656 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 2657 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 2658 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 2659 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 2660 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 2661 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 2662 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 2663 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 2664 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 2665 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 2666 |
|
|
} Bits;
|
| 2667 |
|
|
struct {
|
| 2668 |
|
|
word :1;
|
| 2669 |
|
|
word :1;
|
| 2670 |
|
|
word :1;
|
| 2671 |
|
|
word :1;
|
| 2672 |
|
|
word :1;
|
| 2673 |
|
|
word :1;
|
| 2674 |
|
|
word grpBIT_6 :10;
|
| 2675 |
|
|
} MergedBits;
|
| 2676 |
|
|
} ATD0DR6STR;
|
| 2677 |
|
|
extern volatile ATD0DR6STR _ATD0DR6 @(REG_BASE + 0x0000009C);
|
| 2678 |
|
|
#define ATD0DR6 _ATD0DR6.Word
|
| 2679 |
|
|
#define ATD0DR6_BIT6 _ATD0DR6.Bits.BIT6
|
| 2680 |
|
|
#define ATD0DR6_BIT7 _ATD0DR6.Bits.BIT7
|
| 2681 |
|
|
#define ATD0DR6_BIT8 _ATD0DR6.Bits.BIT8
|
| 2682 |
|
|
#define ATD0DR6_BIT9 _ATD0DR6.Bits.BIT9
|
| 2683 |
|
|
#define ATD0DR6_BIT10 _ATD0DR6.Bits.BIT10
|
| 2684 |
|
|
#define ATD0DR6_BIT11 _ATD0DR6.Bits.BIT11
|
| 2685 |
|
|
#define ATD0DR6_BIT12 _ATD0DR6.Bits.BIT12
|
| 2686 |
|
|
#define ATD0DR6_BIT13 _ATD0DR6.Bits.BIT13
|
| 2687 |
|
|
#define ATD0DR6_BIT14 _ATD0DR6.Bits.BIT14
|
| 2688 |
|
|
#define ATD0DR6_BIT15 _ATD0DR6.Bits.BIT15
|
| 2689 |
|
|
#define ATD0DR6_BIT_6 _ATD0DR6.MergedBits.grpBIT_6
|
| 2690 |
|
|
#define ATD0DR6_BIT ATD0DR6_BIT_6
|
| 2691 |
|
|
|
| 2692 |
|
|
|
| 2693 |
|
|
/*** ATD0DR7 - ATD 0 Conversion Result Register 7; 0x0000009E ***/
|
| 2694 |
|
|
typedef union {
|
| 2695 |
|
|
word Word;
|
| 2696 |
|
|
/* Overlapped registers: */
|
| 2697 |
|
|
struct {
|
| 2698 |
|
|
/*** ATD0DR7H - ATD 0 Conversion Result Register 7 High; 0x0000009E ***/
|
| 2699 |
|
|
union {
|
| 2700 |
|
|
byte Byte;
|
| 2701 |
|
|
struct {
|
| 2702 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 2703 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 2704 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 2705 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 2706 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 2707 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 2708 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 2709 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 2710 |
|
|
} Bits;
|
| 2711 |
|
|
struct {
|
| 2712 |
|
|
byte grpBIT_8 :8;
|
| 2713 |
|
|
} MergedBits;
|
| 2714 |
|
|
} ATD0DR7HSTR;
|
| 2715 |
|
|
#define ATD0DR7H _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Byte
|
| 2716 |
|
|
#define ATD0DR7H_BIT8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT8
|
| 2717 |
|
|
#define ATD0DR7H_BIT9 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT9
|
| 2718 |
|
|
#define ATD0DR7H_BIT10 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT10
|
| 2719 |
|
|
#define ATD0DR7H_BIT11 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT11
|
| 2720 |
|
|
#define ATD0DR7H_BIT12 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT12
|
| 2721 |
|
|
#define ATD0DR7H_BIT13 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT13
|
| 2722 |
|
|
#define ATD0DR7H_BIT14 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT14
|
| 2723 |
|
|
#define ATD0DR7H_BIT15 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT15
|
| 2724 |
|
|
#define ATD0DR7H_BIT_8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.MergedBits.grpBIT_8
|
| 2725 |
|
|
#define ATD0DR7H_BIT ATD0DR7H_BIT_8
|
| 2726 |
|
|
|
| 2727 |
|
|
/*** ATD0DR7L - ATD 0 Conversion Result Register 7 Low; 0x0000009F ***/
|
| 2728 |
|
|
union {
|
| 2729 |
|
|
byte Byte;
|
| 2730 |
|
|
struct {
|
| 2731 |
|
|
byte :1;
|
| 2732 |
|
|
byte :1;
|
| 2733 |
|
|
byte :1;
|
| 2734 |
|
|
byte :1;
|
| 2735 |
|
|
byte :1;
|
| 2736 |
|
|
byte :1;
|
| 2737 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 2738 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 2739 |
|
|
} Bits;
|
| 2740 |
|
|
struct {
|
| 2741 |
|
|
byte :1;
|
| 2742 |
|
|
byte :1;
|
| 2743 |
|
|
byte :1;
|
| 2744 |
|
|
byte :1;
|
| 2745 |
|
|
byte :1;
|
| 2746 |
|
|
byte :1;
|
| 2747 |
|
|
byte grpBIT_6 :2;
|
| 2748 |
|
|
} MergedBits;
|
| 2749 |
|
|
} ATD0DR7LSTR;
|
| 2750 |
|
|
#define ATD0DR7L _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Byte
|
| 2751 |
|
|
#define ATD0DR7L_BIT6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT6
|
| 2752 |
|
|
#define ATD0DR7L_BIT7 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT7
|
| 2753 |
|
|
#define ATD0DR7L_BIT_6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.MergedBits.grpBIT_6
|
| 2754 |
|
|
#define ATD0DR7L_BIT ATD0DR7L_BIT_6
|
| 2755 |
|
|
|
| 2756 |
|
|
} Overlap_STR;
|
| 2757 |
|
|
|
| 2758 |
|
|
struct {
|
| 2759 |
|
|
word :1;
|
| 2760 |
|
|
word :1;
|
| 2761 |
|
|
word :1;
|
| 2762 |
|
|
word :1;
|
| 2763 |
|
|
word :1;
|
| 2764 |
|
|
word :1;
|
| 2765 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 2766 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 2767 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 2768 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 2769 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 2770 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 2771 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 2772 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 2773 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 2774 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 2775 |
|
|
} Bits;
|
| 2776 |
|
|
struct {
|
| 2777 |
|
|
word :1;
|
| 2778 |
|
|
word :1;
|
| 2779 |
|
|
word :1;
|
| 2780 |
|
|
word :1;
|
| 2781 |
|
|
word :1;
|
| 2782 |
|
|
word :1;
|
| 2783 |
|
|
word grpBIT_6 :10;
|
| 2784 |
|
|
} MergedBits;
|
| 2785 |
|
|
} ATD0DR7STR;
|
| 2786 |
|
|
extern volatile ATD0DR7STR _ATD0DR7 @(REG_BASE + 0x0000009E);
|
| 2787 |
|
|
#define ATD0DR7 _ATD0DR7.Word
|
| 2788 |
|
|
#define ATD0DR7_BIT6 _ATD0DR7.Bits.BIT6
|
| 2789 |
|
|
#define ATD0DR7_BIT7 _ATD0DR7.Bits.BIT7
|
| 2790 |
|
|
#define ATD0DR7_BIT8 _ATD0DR7.Bits.BIT8
|
| 2791 |
|
|
#define ATD0DR7_BIT9 _ATD0DR7.Bits.BIT9
|
| 2792 |
|
|
#define ATD0DR7_BIT10 _ATD0DR7.Bits.BIT10
|
| 2793 |
|
|
#define ATD0DR7_BIT11 _ATD0DR7.Bits.BIT11
|
| 2794 |
|
|
#define ATD0DR7_BIT12 _ATD0DR7.Bits.BIT12
|
| 2795 |
|
|
#define ATD0DR7_BIT13 _ATD0DR7.Bits.BIT13
|
| 2796 |
|
|
#define ATD0DR7_BIT14 _ATD0DR7.Bits.BIT14
|
| 2797 |
|
|
#define ATD0DR7_BIT15 _ATD0DR7.Bits.BIT15
|
| 2798 |
|
|
#define ATD0DR7_BIT_6 _ATD0DR7.MergedBits.grpBIT_6
|
| 2799 |
|
|
#define ATD0DR7_BIT ATD0DR7_BIT_6
|
| 2800 |
|
|
|
| 2801 |
|
|
|
| 2802 |
|
|
/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000AC ***/
|
| 2803 |
|
|
typedef union {
|
| 2804 |
|
|
word Word;
|
| 2805 |
|
|
/* Overlapped registers: */
|
| 2806 |
|
|
struct {
|
| 2807 |
|
|
/*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000AC ***/
|
| 2808 |
|
|
union {
|
| 2809 |
|
|
byte Byte;
|
| 2810 |
|
|
struct {
|
| 2811 |
|
|
byte grpBIT :8;
|
| 2812 |
|
|
} MergedBits;
|
| 2813 |
|
|
} PWMCNT0STR;
|
| 2814 |
|
|
#define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte
|
| 2815 |
|
|
#define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT
|
| 2816 |
|
|
|
| 2817 |
|
|
/*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000AD ***/
|
| 2818 |
|
|
union {
|
| 2819 |
|
|
byte Byte;
|
| 2820 |
|
|
struct {
|
| 2821 |
|
|
byte grpBIT :8;
|
| 2822 |
|
|
} MergedBits;
|
| 2823 |
|
|
} PWMCNT1STR;
|
| 2824 |
|
|
#define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte
|
| 2825 |
|
|
#define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT
|
| 2826 |
|
|
|
| 2827 |
|
|
} Overlap_STR;
|
| 2828 |
|
|
|
| 2829 |
|
|
struct {
|
| 2830 |
|
|
word grpBIT :16;
|
| 2831 |
|
|
} MergedBits;
|
| 2832 |
|
|
} PWMCNT01STR;
|
| 2833 |
|
|
extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000AC);
|
| 2834 |
|
|
#define PWMCNT01 _PWMCNT01.Word
|
| 2835 |
|
|
#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT
|
| 2836 |
|
|
|
| 2837 |
|
|
|
| 2838 |
|
|
/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000AE ***/
|
| 2839 |
|
|
typedef union {
|
| 2840 |
|
|
word Word;
|
| 2841 |
|
|
/* Overlapped registers: */
|
| 2842 |
|
|
struct {
|
| 2843 |
|
|
/*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000AE ***/
|
| 2844 |
|
|
union {
|
| 2845 |
|
|
byte Byte;
|
| 2846 |
|
|
struct {
|
| 2847 |
|
|
byte grpBIT :8;
|
| 2848 |
|
|
} MergedBits;
|
| 2849 |
|
|
} PWMCNT2STR;
|
| 2850 |
|
|
#define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte
|
| 2851 |
|
|
#define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT
|
| 2852 |
|
|
|
| 2853 |
|
|
/*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000AF ***/
|
| 2854 |
|
|
union {
|
| 2855 |
|
|
byte Byte;
|
| 2856 |
|
|
struct {
|
| 2857 |
|
|
byte grpBIT :8;
|
| 2858 |
|
|
} MergedBits;
|
| 2859 |
|
|
} PWMCNT3STR;
|
| 2860 |
|
|
#define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte
|
| 2861 |
|
|
#define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT
|
| 2862 |
|
|
|
| 2863 |
|
|
} Overlap_STR;
|
| 2864 |
|
|
|
| 2865 |
|
|
struct {
|
| 2866 |
|
|
word grpBIT :16;
|
| 2867 |
|
|
} MergedBits;
|
| 2868 |
|
|
} PWMCNT23STR;
|
| 2869 |
|
|
extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000AE);
|
| 2870 |
|
|
#define PWMCNT23 _PWMCNT23.Word
|
| 2871 |
|
|
#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT
|
| 2872 |
|
|
|
| 2873 |
|
|
|
| 2874 |
|
|
/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000B0 ***/
|
| 2875 |
|
|
typedef union {
|
| 2876 |
|
|
word Word;
|
| 2877 |
|
|
/* Overlapped registers: */
|
| 2878 |
|
|
struct {
|
| 2879 |
|
|
/*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000B0 ***/
|
| 2880 |
|
|
union {
|
| 2881 |
|
|
byte Byte;
|
| 2882 |
|
|
struct {
|
| 2883 |
|
|
byte grpBIT :8;
|
| 2884 |
|
|
} MergedBits;
|
| 2885 |
|
|
} PWMCNT4STR;
|
| 2886 |
|
|
#define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte
|
| 2887 |
|
|
#define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT
|
| 2888 |
|
|
|
| 2889 |
|
|
/*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000B1 ***/
|
| 2890 |
|
|
union {
|
| 2891 |
|
|
byte Byte;
|
| 2892 |
|
|
struct {
|
| 2893 |
|
|
byte grpBIT :8;
|
| 2894 |
|
|
} MergedBits;
|
| 2895 |
|
|
} PWMCNT5STR;
|
| 2896 |
|
|
#define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte
|
| 2897 |
|
|
#define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT
|
| 2898 |
|
|
|
| 2899 |
|
|
} Overlap_STR;
|
| 2900 |
|
|
|
| 2901 |
|
|
struct {
|
| 2902 |
|
|
word grpBIT :16;
|
| 2903 |
|
|
} MergedBits;
|
| 2904 |
|
|
} PWMCNT45STR;
|
| 2905 |
|
|
extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000B0);
|
| 2906 |
|
|
#define PWMCNT45 _PWMCNT45.Word
|
| 2907 |
|
|
#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT
|
| 2908 |
|
|
|
| 2909 |
|
|
|
| 2910 |
|
|
/*** PWMCNT67 - PWM Channel Counter 67 Register; 0x000000B2 ***/
|
| 2911 |
|
|
typedef union {
|
| 2912 |
|
|
word Word;
|
| 2913 |
|
|
/* Overlapped registers: */
|
| 2914 |
|
|
struct {
|
| 2915 |
|
|
/*** PWMCNT6 - PWM Channel Counter 6 Register; 0x000000B2 ***/
|
| 2916 |
|
|
union {
|
| 2917 |
|
|
byte Byte;
|
| 2918 |
|
|
struct {
|
| 2919 |
|
|
byte grpBIT :8;
|
| 2920 |
|
|
} MergedBits;
|
| 2921 |
|
|
} PWMCNT6STR;
|
| 2922 |
|
|
#define PWMCNT6 _PWMCNT67.Overlap_STR.PWMCNT6STR.Byte
|
| 2923 |
|
|
#define PWMCNT6_BIT _PWMCNT67.Overlap_STR.PWMCNT6STR.MergedBits.grpBIT
|
| 2924 |
|
|
|
| 2925 |
|
|
/*** PWMCNT7 - PWM Channel Counter 7 Register; 0x000000B3 ***/
|
| 2926 |
|
|
union {
|
| 2927 |
|
|
byte Byte;
|
| 2928 |
|
|
struct {
|
| 2929 |
|
|
byte grpBIT :8;
|
| 2930 |
|
|
} MergedBits;
|
| 2931 |
|
|
} PWMCNT7STR;
|
| 2932 |
|
|
#define PWMCNT7 _PWMCNT67.Overlap_STR.PWMCNT7STR.Byte
|
| 2933 |
|
|
#define PWMCNT7_BIT _PWMCNT67.Overlap_STR.PWMCNT7STR.MergedBits.grpBIT
|
| 2934 |
|
|
|
| 2935 |
|
|
} Overlap_STR;
|
| 2936 |
|
|
|
| 2937 |
|
|
struct {
|
| 2938 |
|
|
word grpBIT :16;
|
| 2939 |
|
|
} MergedBits;
|
| 2940 |
|
|
} PWMCNT67STR;
|
| 2941 |
|
|
extern volatile PWMCNT67STR _PWMCNT67 @(REG_BASE + 0x000000B2);
|
| 2942 |
|
|
#define PWMCNT67 _PWMCNT67.Word
|
| 2943 |
|
|
#define PWMCNT67_BIT _PWMCNT67.MergedBits.grpBIT
|
| 2944 |
|
|
|
| 2945 |
|
|
|
| 2946 |
|
|
/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000B4 ***/
|
| 2947 |
|
|
typedef union {
|
| 2948 |
|
|
word Word;
|
| 2949 |
|
|
/* Overlapped registers: */
|
| 2950 |
|
|
struct {
|
| 2951 |
|
|
/*** PWMPER0 - PWM Channel Period 0 Register; 0x000000B4 ***/
|
| 2952 |
|
|
union {
|
| 2953 |
|
|
byte Byte;
|
| 2954 |
|
|
struct {
|
| 2955 |
|
|
byte grpBIT :8;
|
| 2956 |
|
|
} MergedBits;
|
| 2957 |
|
|
} PWMPER0STR;
|
| 2958 |
|
|
#define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte
|
| 2959 |
|
|
#define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT
|
| 2960 |
|
|
|
| 2961 |
|
|
/*** PWMPER1 - PWM Channel Period 1 Register; 0x000000B5 ***/
|
| 2962 |
|
|
union {
|
| 2963 |
|
|
byte Byte;
|
| 2964 |
|
|
struct {
|
| 2965 |
|
|
byte grpBIT :8;
|
| 2966 |
|
|
} MergedBits;
|
| 2967 |
|
|
} PWMPER1STR;
|
| 2968 |
|
|
#define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte
|
| 2969 |
|
|
#define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT
|
| 2970 |
|
|
|
| 2971 |
|
|
} Overlap_STR;
|
| 2972 |
|
|
|
| 2973 |
|
|
struct {
|
| 2974 |
|
|
word grpBIT :16;
|
| 2975 |
|
|
} MergedBits;
|
| 2976 |
|
|
} PWMPER01STR;
|
| 2977 |
|
|
extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000B4);
|
| 2978 |
|
|
#define PWMPER01 _PWMPER01.Word
|
| 2979 |
|
|
#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT
|
| 2980 |
|
|
|
| 2981 |
|
|
|
| 2982 |
|
|
/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000B6 ***/
|
| 2983 |
|
|
typedef union {
|
| 2984 |
|
|
word Word;
|
| 2985 |
|
|
/* Overlapped registers: */
|
| 2986 |
|
|
struct {
|
| 2987 |
|
|
/*** PWMPER2 - PWM Channel Period 2 Register; 0x000000B6 ***/
|
| 2988 |
|
|
union {
|
| 2989 |
|
|
byte Byte;
|
| 2990 |
|
|
struct {
|
| 2991 |
|
|
byte grpBIT :8;
|
| 2992 |
|
|
} MergedBits;
|
| 2993 |
|
|
} PWMPER2STR;
|
| 2994 |
|
|
#define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte
|
| 2995 |
|
|
#define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT
|
| 2996 |
|
|
|
| 2997 |
|
|
/*** PWMPER3 - PWM Channel Period 3 Register; 0x000000B7 ***/
|
| 2998 |
|
|
union {
|
| 2999 |
|
|
byte Byte;
|
| 3000 |
|
|
struct {
|
| 3001 |
|
|
byte grpBIT :8;
|
| 3002 |
|
|
} MergedBits;
|
| 3003 |
|
|
} PWMPER3STR;
|
| 3004 |
|
|
#define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte
|
| 3005 |
|
|
#define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT
|
| 3006 |
|
|
|
| 3007 |
|
|
} Overlap_STR;
|
| 3008 |
|
|
|
| 3009 |
|
|
struct {
|
| 3010 |
|
|
word grpBIT :16;
|
| 3011 |
|
|
} MergedBits;
|
| 3012 |
|
|
} PWMPER23STR;
|
| 3013 |
|
|
extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000B6);
|
| 3014 |
|
|
#define PWMPER23 _PWMPER23.Word
|
| 3015 |
|
|
#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT
|
| 3016 |
|
|
|
| 3017 |
|
|
|
| 3018 |
|
|
/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000B8 ***/
|
| 3019 |
|
|
typedef union {
|
| 3020 |
|
|
word Word;
|
| 3021 |
|
|
/* Overlapped registers: */
|
| 3022 |
|
|
struct {
|
| 3023 |
|
|
/*** PWMPER4 - PWM Channel Period 4 Register; 0x000000B8 ***/
|
| 3024 |
|
|
union {
|
| 3025 |
|
|
byte Byte;
|
| 3026 |
|
|
struct {
|
| 3027 |
|
|
byte grpBIT :8;
|
| 3028 |
|
|
} MergedBits;
|
| 3029 |
|
|
} PWMPER4STR;
|
| 3030 |
|
|
#define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte
|
| 3031 |
|
|
#define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT
|
| 3032 |
|
|
|
| 3033 |
|
|
/*** PWMPER5 - PWM Channel Period 5 Register; 0x000000B9 ***/
|
| 3034 |
|
|
union {
|
| 3035 |
|
|
byte Byte;
|
| 3036 |
|
|
struct {
|
| 3037 |
|
|
byte grpBIT :8;
|
| 3038 |
|
|
} MergedBits;
|
| 3039 |
|
|
} PWMPER5STR;
|
| 3040 |
|
|
#define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte
|
| 3041 |
|
|
#define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT
|
| 3042 |
|
|
|
| 3043 |
|
|
} Overlap_STR;
|
| 3044 |
|
|
|
| 3045 |
|
|
struct {
|
| 3046 |
|
|
word grpBIT :16;
|
| 3047 |
|
|
} MergedBits;
|
| 3048 |
|
|
} PWMPER45STR;
|
| 3049 |
|
|
extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000B8);
|
| 3050 |
|
|
#define PWMPER45 _PWMPER45.Word
|
| 3051 |
|
|
#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT
|
| 3052 |
|
|
|
| 3053 |
|
|
|
| 3054 |
|
|
/*** PWMPER67 - PWM Channel Period 67 Register; 0x000000BA ***/
|
| 3055 |
|
|
typedef union {
|
| 3056 |
|
|
word Word;
|
| 3057 |
|
|
/* Overlapped registers: */
|
| 3058 |
|
|
struct {
|
| 3059 |
|
|
/*** PWMPER6 - PWM Channel Period 6 Register; 0x000000BA ***/
|
| 3060 |
|
|
union {
|
| 3061 |
|
|
byte Byte;
|
| 3062 |
|
|
struct {
|
| 3063 |
|
|
byte grpBIT :8;
|
| 3064 |
|
|
} MergedBits;
|
| 3065 |
|
|
} PWMPER6STR;
|
| 3066 |
|
|
#define PWMPER6 _PWMPER67.Overlap_STR.PWMPER6STR.Byte
|
| 3067 |
|
|
#define PWMPER6_BIT _PWMPER67.Overlap_STR.PWMPER6STR.MergedBits.grpBIT
|
| 3068 |
|
|
|
| 3069 |
|
|
/*** PWMPER7 - PWM Channel Period 7 Register; 0x000000BB ***/
|
| 3070 |
|
|
union {
|
| 3071 |
|
|
byte Byte;
|
| 3072 |
|
|
struct {
|
| 3073 |
|
|
byte grpBIT :8;
|
| 3074 |
|
|
} MergedBits;
|
| 3075 |
|
|
} PWMPER7STR;
|
| 3076 |
|
|
#define PWMPER7 _PWMPER67.Overlap_STR.PWMPER7STR.Byte
|
| 3077 |
|
|
#define PWMPER7_BIT _PWMPER67.Overlap_STR.PWMPER7STR.MergedBits.grpBIT
|
| 3078 |
|
|
|
| 3079 |
|
|
} Overlap_STR;
|
| 3080 |
|
|
|
| 3081 |
|
|
struct {
|
| 3082 |
|
|
word grpBIT :16;
|
| 3083 |
|
|
} MergedBits;
|
| 3084 |
|
|
} PWMPER67STR;
|
| 3085 |
|
|
extern volatile PWMPER67STR _PWMPER67 @(REG_BASE + 0x000000BA);
|
| 3086 |
|
|
#define PWMPER67 _PWMPER67.Word
|
| 3087 |
|
|
#define PWMPER67_BIT _PWMPER67.MergedBits.grpBIT
|
| 3088 |
|
|
|
| 3089 |
|
|
|
| 3090 |
|
|
/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000BC ***/
|
| 3091 |
|
|
typedef union {
|
| 3092 |
|
|
word Word;
|
| 3093 |
|
|
/* Overlapped registers: */
|
| 3094 |
|
|
struct {
|
| 3095 |
|
|
/*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000BC ***/
|
| 3096 |
|
|
union {
|
| 3097 |
|
|
byte Byte;
|
| 3098 |
|
|
struct {
|
| 3099 |
|
|
byte grpBIT :8;
|
| 3100 |
|
|
} MergedBits;
|
| 3101 |
|
|
} PWMDTY0STR;
|
| 3102 |
|
|
#define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte
|
| 3103 |
|
|
#define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT
|
| 3104 |
|
|
|
| 3105 |
|
|
/*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000BD ***/
|
| 3106 |
|
|
union {
|
| 3107 |
|
|
byte Byte;
|
| 3108 |
|
|
struct {
|
| 3109 |
|
|
byte grpBIT :8;
|
| 3110 |
|
|
} MergedBits;
|
| 3111 |
|
|
} PWMDTY1STR;
|
| 3112 |
|
|
#define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte
|
| 3113 |
|
|
#define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT
|
| 3114 |
|
|
|
| 3115 |
|
|
} Overlap_STR;
|
| 3116 |
|
|
|
| 3117 |
|
|
struct {
|
| 3118 |
|
|
word grpBIT :16;
|
| 3119 |
|
|
} MergedBits;
|
| 3120 |
|
|
} PWMDTY01STR;
|
| 3121 |
|
|
extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000BC);
|
| 3122 |
|
|
#define PWMDTY01 _PWMDTY01.Word
|
| 3123 |
|
|
#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT
|
| 3124 |
|
|
|
| 3125 |
|
|
|
| 3126 |
|
|
/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000BE ***/
|
| 3127 |
|
|
typedef union {
|
| 3128 |
|
|
word Word;
|
| 3129 |
|
|
/* Overlapped registers: */
|
| 3130 |
|
|
struct {
|
| 3131 |
|
|
/*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000BE ***/
|
| 3132 |
|
|
union {
|
| 3133 |
|
|
byte Byte;
|
| 3134 |
|
|
struct {
|
| 3135 |
|
|
byte grpBIT :8;
|
| 3136 |
|
|
} MergedBits;
|
| 3137 |
|
|
} PWMDTY2STR;
|
| 3138 |
|
|
#define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte
|
| 3139 |
|
|
#define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT
|
| 3140 |
|
|
|
| 3141 |
|
|
/*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000BF ***/
|
| 3142 |
|
|
union {
|
| 3143 |
|
|
byte Byte;
|
| 3144 |
|
|
struct {
|
| 3145 |
|
|
byte grpBIT :8;
|
| 3146 |
|
|
} MergedBits;
|
| 3147 |
|
|
} PWMDTY3STR;
|
| 3148 |
|
|
#define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte
|
| 3149 |
|
|
#define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT
|
| 3150 |
|
|
|
| 3151 |
|
|
} Overlap_STR;
|
| 3152 |
|
|
|
| 3153 |
|
|
struct {
|
| 3154 |
|
|
word grpBIT :16;
|
| 3155 |
|
|
} MergedBits;
|
| 3156 |
|
|
} PWMDTY23STR;
|
| 3157 |
|
|
extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000BE);
|
| 3158 |
|
|
#define PWMDTY23 _PWMDTY23.Word
|
| 3159 |
|
|
#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT
|
| 3160 |
|
|
|
| 3161 |
|
|
|
| 3162 |
|
|
/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000C0 ***/
|
| 3163 |
|
|
typedef union {
|
| 3164 |
|
|
word Word;
|
| 3165 |
|
|
/* Overlapped registers: */
|
| 3166 |
|
|
struct {
|
| 3167 |
|
|
/*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000C0 ***/
|
| 3168 |
|
|
union {
|
| 3169 |
|
|
byte Byte;
|
| 3170 |
|
|
struct {
|
| 3171 |
|
|
byte grpBIT :8;
|
| 3172 |
|
|
} MergedBits;
|
| 3173 |
|
|
} PWMDTY4STR;
|
| 3174 |
|
|
#define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte
|
| 3175 |
|
|
#define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT
|
| 3176 |
|
|
|
| 3177 |
|
|
/*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000C1 ***/
|
| 3178 |
|
|
union {
|
| 3179 |
|
|
byte Byte;
|
| 3180 |
|
|
struct {
|
| 3181 |
|
|
byte grpBIT :8;
|
| 3182 |
|
|
} MergedBits;
|
| 3183 |
|
|
} PWMDTY5STR;
|
| 3184 |
|
|
#define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte
|
| 3185 |
|
|
#define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT
|
| 3186 |
|
|
|
| 3187 |
|
|
} Overlap_STR;
|
| 3188 |
|
|
|
| 3189 |
|
|
struct {
|
| 3190 |
|
|
word grpBIT :16;
|
| 3191 |
|
|
} MergedBits;
|
| 3192 |
|
|
} PWMDTY45STR;
|
| 3193 |
|
|
extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000C0);
|
| 3194 |
|
|
#define PWMDTY45 _PWMDTY45.Word
|
| 3195 |
|
|
#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT
|
| 3196 |
|
|
|
| 3197 |
|
|
|
| 3198 |
|
|
/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x000000C2 ***/
|
| 3199 |
|
|
typedef union {
|
| 3200 |
|
|
word Word;
|
| 3201 |
|
|
/* Overlapped registers: */
|
| 3202 |
|
|
struct {
|
| 3203 |
|
|
/*** PWMDTY6 - PWM Channel Duty 6 Register; 0x000000C2 ***/
|
| 3204 |
|
|
union {
|
| 3205 |
|
|
byte Byte;
|
| 3206 |
|
|
struct {
|
| 3207 |
|
|
byte grpBIT :8;
|
| 3208 |
|
|
} MergedBits;
|
| 3209 |
|
|
} PWMDTY6STR;
|
| 3210 |
|
|
#define PWMDTY6 _PWMDTY67.Overlap_STR.PWMDTY6STR.Byte
|
| 3211 |
|
|
#define PWMDTY6_BIT _PWMDTY67.Overlap_STR.PWMDTY6STR.MergedBits.grpBIT
|
| 3212 |
|
|
|
| 3213 |
|
|
/*** PWMDTY7 - PWM Channel Duty 7 Register; 0x000000C3 ***/
|
| 3214 |
|
|
union {
|
| 3215 |
|
|
byte Byte;
|
| 3216 |
|
|
struct {
|
| 3217 |
|
|
byte grpBIT :8;
|
| 3218 |
|
|
} MergedBits;
|
| 3219 |
|
|
} PWMDTY7STR;
|
| 3220 |
|
|
#define PWMDTY7 _PWMDTY67.Overlap_STR.PWMDTY7STR.Byte
|
| 3221 |
|
|
#define PWMDTY7_BIT _PWMDTY67.Overlap_STR.PWMDTY7STR.MergedBits.grpBIT
|
| 3222 |
|
|
|
| 3223 |
|
|
} Overlap_STR;
|
| 3224 |
|
|
|
| 3225 |
|
|
struct {
|
| 3226 |
|
|
word grpBIT :16;
|
| 3227 |
|
|
} MergedBits;
|
| 3228 |
|
|
} PWMDTY67STR;
|
| 3229 |
|
|
extern volatile PWMDTY67STR _PWMDTY67 @(REG_BASE + 0x000000C2);
|
| 3230 |
|
|
#define PWMDTY67 _PWMDTY67.Word
|
| 3231 |
|
|
#define PWMDTY67_BIT _PWMDTY67.MergedBits.grpBIT
|
| 3232 |
|
|
|
| 3233 |
|
|
|
| 3234 |
|
|
/*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***/
|
| 3235 |
|
|
typedef union {
|
| 3236 |
|
|
word Word;
|
| 3237 |
|
|
/* Overlapped registers: */
|
| 3238 |
|
|
struct {
|
| 3239 |
|
|
/*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***/
|
| 3240 |
|
|
union {
|
| 3241 |
|
|
byte Byte;
|
| 3242 |
|
|
struct {
|
| 3243 |
|
|
byte SBR8 :1; /* SCI 0 baud rate Bit 8 */
|
| 3244 |
|
|
byte SBR9 :1; /* SCI 0 baud rate Bit 9 */
|
| 3245 |
|
|
byte SBR10 :1; /* SCI 0 baud rate Bit 10 */
|
| 3246 |
|
|
byte SBR11 :1; /* SCI 0 baud rate Bit 11 */
|
| 3247 |
|
|
byte SBR12 :1; /* SCI 0 baud rate Bit 12 */
|
| 3248 |
|
|
byte :1;
|
| 3249 |
|
|
byte :1;
|
| 3250 |
|
|
byte :1;
|
| 3251 |
|
|
} Bits;
|
| 3252 |
|
|
struct {
|
| 3253 |
|
|
byte grpSBR_8 :5;
|
| 3254 |
|
|
byte :1;
|
| 3255 |
|
|
byte :1;
|
| 3256 |
|
|
byte :1;
|
| 3257 |
|
|
} MergedBits;
|
| 3258 |
|
|
} SCI0BDHSTR;
|
| 3259 |
|
|
#define SCI0BDH _SCI0BD.Overlap_STR.SCI0BDHSTR.Byte
|
| 3260 |
|
|
#define SCI0BDH_SBR8 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR8
|
| 3261 |
|
|
#define SCI0BDH_SBR9 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR9
|
| 3262 |
|
|
#define SCI0BDH_SBR10 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR10
|
| 3263 |
|
|
#define SCI0BDH_SBR11 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR11
|
| 3264 |
|
|
#define SCI0BDH_SBR12 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR12
|
| 3265 |
|
|
#define SCI0BDH_SBR_8 _SCI0BD.Overlap_STR.SCI0BDHSTR.MergedBits.grpSBR_8
|
| 3266 |
|
|
#define SCI0BDH_SBR SCI0BDH_SBR_8
|
| 3267 |
|
|
|
| 3268 |
|
|
/*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***/
|
| 3269 |
|
|
union {
|
| 3270 |
|
|
byte Byte;
|
| 3271 |
|
|
struct {
|
| 3272 |
|
|
byte SBR0 :1; /* SCI 0 baud rate Bit 0 */
|
| 3273 |
|
|
byte SBR1 :1; /* SCI 0 baud rate Bit 1 */
|
| 3274 |
|
|
byte SBR2 :1; /* SCI 0 baud rate Bit 2 */
|
| 3275 |
|
|
byte SBR3 :1; /* SCI 0 baud rate Bit 3 */
|
| 3276 |
|
|
byte SBR4 :1; /* SCI 0 baud rate Bit 4 */
|
| 3277 |
|
|
byte SBR5 :1; /* SCI 0 baud rate Bit 5 */
|
| 3278 |
|
|
byte SBR6 :1; /* SCI 0 baud rate Bit 6 */
|
| 3279 |
|
|
byte SBR7 :1; /* SCI 0 baud rate Bit 7 */
|
| 3280 |
|
|
} Bits;
|
| 3281 |
|
|
struct {
|
| 3282 |
|
|
byte grpSBR :8;
|
| 3283 |
|
|
} MergedBits;
|
| 3284 |
|
|
} SCI0BDLSTR;
|
| 3285 |
|
|
#define SCI0BDL _SCI0BD.Overlap_STR.SCI0BDLSTR.Byte
|
| 3286 |
|
|
#define SCI0BDL_SBR0 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR0
|
| 3287 |
|
|
#define SCI0BDL_SBR1 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR1
|
| 3288 |
|
|
#define SCI0BDL_SBR2 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR2
|
| 3289 |
|
|
#define SCI0BDL_SBR3 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR3
|
| 3290 |
|
|
#define SCI0BDL_SBR4 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR4
|
| 3291 |
|
|
#define SCI0BDL_SBR5 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR5
|
| 3292 |
|
|
#define SCI0BDL_SBR6 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR6
|
| 3293 |
|
|
#define SCI0BDL_SBR7 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR7
|
| 3294 |
|
|
#define SCI0BDL_SBR _SCI0BD.Overlap_STR.SCI0BDLSTR.MergedBits.grpSBR
|
| 3295 |
|
|
|
| 3296 |
|
|
} Overlap_STR;
|
| 3297 |
|
|
|
| 3298 |
|
|
struct {
|
| 3299 |
|
|
word SBR0 :1; /* SCI 0 baud rate Bit 0 */
|
| 3300 |
|
|
word SBR1 :1; /* SCI 0 baud rate Bit 1 */
|
| 3301 |
|
|
word SBR2 :1; /* SCI 0 baud rate Bit 2 */
|
| 3302 |
|
|
word SBR3 :1; /* SCI 0 baud rate Bit 3 */
|
| 3303 |
|
|
word SBR4 :1; /* SCI 0 baud rate Bit 4 */
|
| 3304 |
|
|
word SBR5 :1; /* SCI 0 baud rate Bit 5 */
|
| 3305 |
|
|
word SBR6 :1; /* SCI 0 baud rate Bit 6 */
|
| 3306 |
|
|
word SBR7 :1; /* SCI 0 baud rate Bit 7 */
|
| 3307 |
|
|
word SBR8 :1; /* SCI 0 baud rate Bit 8 */
|
| 3308 |
|
|
word SBR9 :1; /* SCI 0 baud rate Bit 9 */
|
| 3309 |
|
|
word SBR10 :1; /* SCI 0 baud rate Bit 10 */
|
| 3310 |
|
|
word SBR11 :1; /* SCI 0 baud rate Bit 11 */
|
| 3311 |
|
|
word SBR12 :1; /* SCI 0 baud rate Bit 12 */
|
| 3312 |
|
|
word :1;
|
| 3313 |
|
|
word :1;
|
| 3314 |
|
|
word :1;
|
| 3315 |
|
|
} Bits;
|
| 3316 |
|
|
struct {
|
| 3317 |
|
|
word grpSBR :13;
|
| 3318 |
|
|
word :1;
|
| 3319 |
|
|
word :1;
|
| 3320 |
|
|
word :1;
|
| 3321 |
|
|
} MergedBits;
|
| 3322 |
|
|
} SCI0BDSTR;
|
| 3323 |
|
|
extern volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8);
|
| 3324 |
|
|
#define SCI0BD _SCI0BD.Word
|
| 3325 |
|
|
#define SCI0BD_SBR0 _SCI0BD.Bits.SBR0
|
| 3326 |
|
|
#define SCI0BD_SBR1 _SCI0BD.Bits.SBR1
|
| 3327 |
|
|
#define SCI0BD_SBR2 _SCI0BD.Bits.SBR2
|
| 3328 |
|
|
#define SCI0BD_SBR3 _SCI0BD.Bits.SBR3
|
| 3329 |
|
|
#define SCI0BD_SBR4 _SCI0BD.Bits.SBR4
|
| 3330 |
|
|
#define SCI0BD_SBR5 _SCI0BD.Bits.SBR5
|
| 3331 |
|
|
#define SCI0BD_SBR6 _SCI0BD.Bits.SBR6
|
| 3332 |
|
|
#define SCI0BD_SBR7 _SCI0BD.Bits.SBR7
|
| 3333 |
|
|
#define SCI0BD_SBR8 _SCI0BD.Bits.SBR8
|
| 3334 |
|
|
#define SCI0BD_SBR9 _SCI0BD.Bits.SBR9
|
| 3335 |
|
|
#define SCI0BD_SBR10 _SCI0BD.Bits.SBR10
|
| 3336 |
|
|
#define SCI0BD_SBR11 _SCI0BD.Bits.SBR11
|
| 3337 |
|
|
#define SCI0BD_SBR12 _SCI0BD.Bits.SBR12
|
| 3338 |
|
|
#define SCI0BD_SBR _SCI0BD.MergedBits.grpSBR
|
| 3339 |
|
|
|
| 3340 |
|
|
|
| 3341 |
|
|
/*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***/
|
| 3342 |
|
|
typedef union {
|
| 3343 |
|
|
word Word;
|
| 3344 |
|
|
/* Overlapped registers: */
|
| 3345 |
|
|
struct {
|
| 3346 |
|
|
/*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***/
|
| 3347 |
|
|
union {
|
| 3348 |
|
|
byte Byte;
|
| 3349 |
|
|
struct {
|
| 3350 |
|
|
byte SBR8 :1; /* SCI 1 baud rate Bit 8 */
|
| 3351 |
|
|
byte SBR9 :1; /* SCI 1 baud rate Bit 9 */
|
| 3352 |
|
|
byte SBR10 :1; /* SCI 1 baud rate Bit 10 */
|
| 3353 |
|
|
byte SBR11 :1; /* SCI 1 baud rate Bit 11 */
|
| 3354 |
|
|
byte SBR12 :1; /* SCI 1 baud rate Bit 12 */
|
| 3355 |
|
|
byte :1;
|
| 3356 |
|
|
byte :1;
|
| 3357 |
|
|
byte :1;
|
| 3358 |
|
|
} Bits;
|
| 3359 |
|
|
struct {
|
| 3360 |
|
|
byte grpSBR_8 :5;
|
| 3361 |
|
|
byte :1;
|
| 3362 |
|
|
byte :1;
|
| 3363 |
|
|
byte :1;
|
| 3364 |
|
|
} MergedBits;
|
| 3365 |
|
|
} SCI1BDHSTR;
|
| 3366 |
|
|
#define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte
|
| 3367 |
|
|
#define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8
|
| 3368 |
|
|
#define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9
|
| 3369 |
|
|
#define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10
|
| 3370 |
|
|
#define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11
|
| 3371 |
|
|
#define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12
|
| 3372 |
|
|
#define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8
|
| 3373 |
|
|
#define SCI1BDH_SBR SCI1BDH_SBR_8
|
| 3374 |
|
|
|
| 3375 |
|
|
/*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***/
|
| 3376 |
|
|
union {
|
| 3377 |
|
|
byte Byte;
|
| 3378 |
|
|
struct {
|
| 3379 |
|
|
byte SBR0 :1; /* SCI 1 baud rate Bit 0 */
|
| 3380 |
|
|
byte SBR1 :1; /* SCI 1 baud rate Bit 1 */
|
| 3381 |
|
|
byte SBR2 :1; /* SCI 1 baud rate Bit 2 */
|
| 3382 |
|
|
byte SBR3 :1; /* SCI 1 baud rate Bit 3 */
|
| 3383 |
|
|
byte SBR4 :1; /* SCI 1 baud rate Bit 4 */
|
| 3384 |
|
|
byte SBR5 :1; /* SCI 1 baud rate Bit 5 */
|
| 3385 |
|
|
byte SBR6 :1; /* SCI 1 baud rate Bit 6 */
|
| 3386 |
|
|
byte SBR7 :1; /* SCI 1 baud rate Bit 7 */
|
| 3387 |
|
|
} Bits;
|
| 3388 |
|
|
struct {
|
| 3389 |
|
|
byte grpSBR :8;
|
| 3390 |
|
|
} MergedBits;
|
| 3391 |
|
|
} SCI1BDLSTR;
|
| 3392 |
|
|
#define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte
|
| 3393 |
|
|
#define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0
|
| 3394 |
|
|
#define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1
|
| 3395 |
|
|
#define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2
|
| 3396 |
|
|
#define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3
|
| 3397 |
|
|
#define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4
|
| 3398 |
|
|
#define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5
|
| 3399 |
|
|
#define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6
|
| 3400 |
|
|
#define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7
|
| 3401 |
|
|
#define SCI1BDL_SBR _SCI1BD.Overlap_STR.SCI1BDLSTR.MergedBits.grpSBR
|
| 3402 |
|
|
|
| 3403 |
|
|
} Overlap_STR;
|
| 3404 |
|
|
|
| 3405 |
|
|
struct {
|
| 3406 |
|
|
word SBR0 :1; /* SCI 1 baud rate Bit 0 */
|
| 3407 |
|
|
word SBR1 :1; /* SCI 1 baud rate Bit 1 */
|
| 3408 |
|
|
word SBR2 :1; /* SCI 1 baud rate Bit 2 */
|
| 3409 |
|
|
word SBR3 :1; /* SCI 1 baud rate Bit 3 */
|
| 3410 |
|
|
word SBR4 :1; /* SCI 1 baud rate Bit 4 */
|
| 3411 |
|
|
word SBR5 :1; /* SCI 1 baud rate Bit 5 */
|
| 3412 |
|
|
word SBR6 :1; /* SCI 1 baud rate Bit 6 */
|
| 3413 |
|
|
word SBR7 :1; /* SCI 1 baud rate Bit 7 */
|
| 3414 |
|
|
word SBR8 :1; /* SCI 1 baud rate Bit 8 */
|
| 3415 |
|
|
word SBR9 :1; /* SCI 1 baud rate Bit 9 */
|
| 3416 |
|
|
word SBR10 :1; /* SCI 1 baud rate Bit 10 */
|
| 3417 |
|
|
word SBR11 :1; /* SCI 1 baud rate Bit 11 */
|
| 3418 |
|
|
word SBR12 :1; /* SCI 1 baud rate Bit 12 */
|
| 3419 |
|
|
word :1;
|
| 3420 |
|
|
word :1;
|
| 3421 |
|
|
word :1;
|
| 3422 |
|
|
} Bits;
|
| 3423 |
|
|
struct {
|
| 3424 |
|
|
word grpSBR :13;
|
| 3425 |
|
|
word :1;
|
| 3426 |
|
|
word :1;
|
| 3427 |
|
|
word :1;
|
| 3428 |
|
|
} MergedBits;
|
| 3429 |
|
|
} SCI1BDSTR;
|
| 3430 |
|
|
extern volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0);
|
| 3431 |
|
|
#define SCI1BD _SCI1BD.Word
|
| 3432 |
|
|
#define SCI1BD_SBR0 _SCI1BD.Bits.SBR0
|
| 3433 |
|
|
#define SCI1BD_SBR1 _SCI1BD.Bits.SBR1
|
| 3434 |
|
|
#define SCI1BD_SBR2 _SCI1BD.Bits.SBR2
|
| 3435 |
|
|
#define SCI1BD_SBR3 _SCI1BD.Bits.SBR3
|
| 3436 |
|
|
#define SCI1BD_SBR4 _SCI1BD.Bits.SBR4
|
| 3437 |
|
|
#define SCI1BD_SBR5 _SCI1BD.Bits.SBR5
|
| 3438 |
|
|
#define SCI1BD_SBR6 _SCI1BD.Bits.SBR6
|
| 3439 |
|
|
#define SCI1BD_SBR7 _SCI1BD.Bits.SBR7
|
| 3440 |
|
|
#define SCI1BD_SBR8 _SCI1BD.Bits.SBR8
|
| 3441 |
|
|
#define SCI1BD_SBR9 _SCI1BD.Bits.SBR9
|
| 3442 |
|
|
#define SCI1BD_SBR10 _SCI1BD.Bits.SBR10
|
| 3443 |
|
|
#define SCI1BD_SBR11 _SCI1BD.Bits.SBR11
|
| 3444 |
|
|
#define SCI1BD_SBR12 _SCI1BD.Bits.SBR12
|
| 3445 |
|
|
#define SCI1BD_SBR _SCI1BD.MergedBits.grpSBR
|
| 3446 |
|
|
|
| 3447 |
|
|
|
| 3448 |
|
|
/*** ATD1CTL23 - ATD 1 Control Register 23; 0x00000122 ***/
|
| 3449 |
|
|
typedef union {
|
| 3450 |
|
|
word Word;
|
| 3451 |
|
|
/* Overlapped registers: */
|
| 3452 |
|
|
struct {
|
| 3453 |
|
|
/*** ATD1CTL2 - ATD 1 Control Register 2; 0x00000122 ***/
|
| 3454 |
|
|
union {
|
| 3455 |
|
|
byte Byte;
|
| 3456 |
|
|
struct {
|
| 3457 |
|
|
byte ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */
|
| 3458 |
|
|
byte ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */
|
| 3459 |
|
|
byte ETRIGE :1; /* External Trigger Mode enable */
|
| 3460 |
|
|
byte ETRIGP :1; /* External Trigger Polarity */
|
| 3461 |
|
|
byte ETRIGLE :1; /* External Trigger Level/Edge control */
|
| 3462 |
|
|
byte AWAI :1; /* ATD 1 Wait Mode */
|
| 3463 |
|
|
byte AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */
|
| 3464 |
|
|
byte ADPU :1; /* ATD 1 Disable / Power Down */
|
| 3465 |
|
|
} Bits;
|
| 3466 |
|
|
} ATD1CTL2STR;
|
| 3467 |
|
|
#define ATD1CTL2 _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Byte
|
| 3468 |
|
|
#define ATD1CTL2_ASCIF _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIF
|
| 3469 |
|
|
#define ATD1CTL2_ASCIE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIE
|
| 3470 |
|
|
#define ATD1CTL2_ETRIGE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGE
|
| 3471 |
|
|
#define ATD1CTL2_ETRIGP _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGP
|
| 3472 |
|
|
#define ATD1CTL2_ETRIGLE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGLE
|
| 3473 |
|
|
#define ATD1CTL2_AWAI _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AWAI
|
| 3474 |
|
|
#define ATD1CTL2_AFFC _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AFFC
|
| 3475 |
|
|
#define ATD1CTL2_ADPU _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ADPU
|
| 3476 |
|
|
|
| 3477 |
|
|
/*** ATD1CTL3 - ATD 1 Control Register 3; 0x00000123 ***/
|
| 3478 |
|
|
union {
|
| 3479 |
|
|
byte Byte;
|
| 3480 |
|
|
struct {
|
| 3481 |
|
|
byte FRZ0 :1; /* Background Debug Freeze Enable */
|
| 3482 |
|
|
byte FRZ1 :1; /* Background Debug Freeze Enable */
|
| 3483 |
|
|
byte FIFO :1; /* Result Register FIFO Mode */
|
| 3484 |
|
|
byte S1C :1; /* Conversion Sequence Length 1 */
|
| 3485 |
|
|
byte S2C :1; /* Conversion Sequence Length 2 */
|
| 3486 |
|
|
byte S4C :1; /* Conversion Sequence Length 4 */
|
| 3487 |
|
|
byte S8C :1; /* Conversion Sequence Length 8 */
|
| 3488 |
|
|
byte :1;
|
| 3489 |
|
|
} Bits;
|
| 3490 |
|
|
struct {
|
| 3491 |
|
|
byte grpFRZ :2;
|
| 3492 |
|
|
byte :1;
|
| 3493 |
|
|
byte :1;
|
| 3494 |
|
|
byte :1;
|
| 3495 |
|
|
byte :1;
|
| 3496 |
|
|
byte :1;
|
| 3497 |
|
|
byte :1;
|
| 3498 |
|
|
} MergedBits;
|
| 3499 |
|
|
} ATD1CTL3STR;
|
| 3500 |
|
|
#define ATD1CTL3 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Byte
|
| 3501 |
|
|
#define ATD1CTL3_FRZ0 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ0
|
| 3502 |
|
|
#define ATD1CTL3_FRZ1 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ1
|
| 3503 |
|
|
#define ATD1CTL3_FIFO _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FIFO
|
| 3504 |
|
|
#define ATD1CTL3_S1C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S1C
|
| 3505 |
|
|
#define ATD1CTL3_S2C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S2C
|
| 3506 |
|
|
#define ATD1CTL3_S4C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S4C
|
| 3507 |
|
|
#define ATD1CTL3_S8C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S8C
|
| 3508 |
|
|
#define ATD1CTL3_FRZ _ATD1CTL23.Overlap_STR.ATD1CTL3STR.MergedBits.grpFRZ
|
| 3509 |
|
|
|
| 3510 |
|
|
} Overlap_STR;
|
| 3511 |
|
|
|
| 3512 |
|
|
struct {
|
| 3513 |
|
|
word FRZ0 :1; /* Background Debug Freeze Enable */
|
| 3514 |
|
|
word FRZ1 :1; /* Background Debug Freeze Enable */
|
| 3515 |
|
|
word FIFO :1; /* Result Register FIFO Mode */
|
| 3516 |
|
|
word S1C :1; /* Conversion Sequence Length 1 */
|
| 3517 |
|
|
word S2C :1; /* Conversion Sequence Length 2 */
|
| 3518 |
|
|
word S4C :1; /* Conversion Sequence Length 4 */
|
| 3519 |
|
|
word S8C :1; /* Conversion Sequence Length 8 */
|
| 3520 |
|
|
word :1;
|
| 3521 |
|
|
word ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */
|
| 3522 |
|
|
word ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */
|
| 3523 |
|
|
word ETRIGE :1; /* External Trigger Mode enable */
|
| 3524 |
|
|
word ETRIGP :1; /* External Trigger Polarity */
|
| 3525 |
|
|
word ETRIGLE :1; /* External Trigger Level/Edge control */
|
| 3526 |
|
|
word AWAI :1; /* ATD 1 Wait Mode */
|
| 3527 |
|
|
word AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */
|
| 3528 |
|
|
word ADPU :1; /* ATD 1 Disable / Power Down */
|
| 3529 |
|
|
} Bits;
|
| 3530 |
|
|
struct {
|
| 3531 |
|
|
word grpFRZ :2;
|
| 3532 |
|
|
word :1;
|
| 3533 |
|
|
word :1;
|
| 3534 |
|
|
word :1;
|
| 3535 |
|
|
word :1;
|
| 3536 |
|
|
word :1;
|
| 3537 |
|
|
word :1;
|
| 3538 |
|
|
word :1;
|
| 3539 |
|
|
word :1;
|
| 3540 |
|
|
word :1;
|
| 3541 |
|
|
word :1;
|
| 3542 |
|
|
word :1;
|
| 3543 |
|
|
word :1;
|
| 3544 |
|
|
word :1;
|
| 3545 |
|
|
word :1;
|
| 3546 |
|
|
} MergedBits;
|
| 3547 |
|
|
} ATD1CTL23STR;
|
| 3548 |
|
|
extern volatile ATD1CTL23STR _ATD1CTL23 @(REG_BASE + 0x00000122);
|
| 3549 |
|
|
#define ATD1CTL23 _ATD1CTL23.Word
|
| 3550 |
|
|
#define ATD1CTL23_FRZ0 _ATD1CTL23.Bits.FRZ0
|
| 3551 |
|
|
#define ATD1CTL23_FRZ1 _ATD1CTL23.Bits.FRZ1
|
| 3552 |
|
|
#define ATD1CTL23_FIFO _ATD1CTL23.Bits.FIFO
|
| 3553 |
|
|
#define ATD1CTL23_S1C _ATD1CTL23.Bits.S1C
|
| 3554 |
|
|
#define ATD1CTL23_S2C _ATD1CTL23.Bits.S2C
|
| 3555 |
|
|
#define ATD1CTL23_S4C _ATD1CTL23.Bits.S4C
|
| 3556 |
|
|
#define ATD1CTL23_S8C _ATD1CTL23.Bits.S8C
|
| 3557 |
|
|
#define ATD1CTL23_ASCIF _ATD1CTL23.Bits.ASCIF
|
| 3558 |
|
|
#define ATD1CTL23_ASCIE _ATD1CTL23.Bits.ASCIE
|
| 3559 |
|
|
#define ATD1CTL23_ETRIGE _ATD1CTL23.Bits.ETRIGE
|
| 3560 |
|
|
#define ATD1CTL23_ETRIGP _ATD1CTL23.Bits.ETRIGP
|
| 3561 |
|
|
#define ATD1CTL23_ETRIGLE _ATD1CTL23.Bits.ETRIGLE
|
| 3562 |
|
|
#define ATD1CTL23_AWAI _ATD1CTL23.Bits.AWAI
|
| 3563 |
|
|
#define ATD1CTL23_AFFC _ATD1CTL23.Bits.AFFC
|
| 3564 |
|
|
#define ATD1CTL23_ADPU _ATD1CTL23.Bits.ADPU
|
| 3565 |
|
|
#define ATD1CTL23_FRZ _ATD1CTL23.MergedBits.grpFRZ
|
| 3566 |
|
|
|
| 3567 |
|
|
|
| 3568 |
|
|
/*** ATD1CTL45 - ATD 1 Control Register 45; 0x00000124 ***/
|
| 3569 |
|
|
typedef union {
|
| 3570 |
|
|
word Word;
|
| 3571 |
|
|
/* Overlapped registers: */
|
| 3572 |
|
|
struct {
|
| 3573 |
|
|
/*** ATD1CTL4 - ATD 1 Control Register 4; 0x00000124 ***/
|
| 3574 |
|
|
union {
|
| 3575 |
|
|
byte Byte;
|
| 3576 |
|
|
struct {
|
| 3577 |
|
|
byte PRS0 :1; /* ATD 1 Clock Prescaler 0 */
|
| 3578 |
|
|
byte PRS1 :1; /* ATD 1 Clock Prescaler 1 */
|
| 3579 |
|
|
byte PRS2 :1; /* ATD 1 Clock Prescaler 2 */
|
| 3580 |
|
|
byte PRS3 :1; /* ATD 1 Clock Prescaler 3 */
|
| 3581 |
|
|
byte PRS4 :1; /* ATD 1 Clock Prescaler 4 */
|
| 3582 |
|
|
byte SMP0 :1; /* Sample Time Select 0 */
|
| 3583 |
|
|
byte SMP1 :1; /* Sample Time Select 1 */
|
| 3584 |
|
|
byte SRES8 :1; /* ATD 1 Resolution Select */
|
| 3585 |
|
|
} Bits;
|
| 3586 |
|
|
struct {
|
| 3587 |
|
|
byte grpPRS :5;
|
| 3588 |
|
|
byte grpSMP :2;
|
| 3589 |
|
|
byte grpSRES_8 :1;
|
| 3590 |
|
|
} MergedBits;
|
| 3591 |
|
|
} ATD1CTL4STR;
|
| 3592 |
|
|
#define ATD1CTL4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Byte
|
| 3593 |
|
|
#define ATD1CTL4_PRS0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS0
|
| 3594 |
|
|
#define ATD1CTL4_PRS1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS1
|
| 3595 |
|
|
#define ATD1CTL4_PRS2 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS2
|
| 3596 |
|
|
#define ATD1CTL4_PRS3 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS3
|
| 3597 |
|
|
#define ATD1CTL4_PRS4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS4
|
| 3598 |
|
|
#define ATD1CTL4_SMP0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP0
|
| 3599 |
|
|
#define ATD1CTL4_SMP1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP1
|
| 3600 |
|
|
#define ATD1CTL4_SRES8 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SRES8
|
| 3601 |
|
|
#define ATD1CTL4_PRS _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpPRS
|
| 3602 |
|
|
#define ATD1CTL4_SMP _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpSMP
|
| 3603 |
|
|
|
| 3604 |
|
|
/*** ATD1CTL5 - ATD 1 Control Register 5; 0x00000125 ***/
|
| 3605 |
|
|
union {
|
| 3606 |
|
|
byte Byte;
|
| 3607 |
|
|
struct {
|
| 3608 |
|
|
byte CA :1; /* Analog Input Channel Select Code A */
|
| 3609 |
|
|
byte CB :1; /* Analog Input Channel Select Code B */
|
| 3610 |
|
|
byte CC :1; /* Analog Input Channel Select Code C */
|
| 3611 |
|
|
byte :1;
|
| 3612 |
|
|
byte MULT :1; /* Multi-Channel Sample Mode */
|
| 3613 |
|
|
byte SCAN :1; /* Continuous Conversion Sequence Mode */
|
| 3614 |
|
|
byte DSGN :1; /* Signed/Unsigned Result Data Mode */
|
| 3615 |
|
|
byte DJM :1; /* Result Register Data Justification Mode */
|
| 3616 |
|
|
} Bits;
|
| 3617 |
|
|
} ATD1CTL5STR;
|
| 3618 |
|
|
#define ATD1CTL5 _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Byte
|
| 3619 |
|
|
#define ATD1CTL5_CA _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CA
|
| 3620 |
|
|
#define ATD1CTL5_CB _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CB
|
| 3621 |
|
|
#define ATD1CTL5_CC _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CC
|
| 3622 |
|
|
#define ATD1CTL5_MULT _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.MULT
|
| 3623 |
|
|
#define ATD1CTL5_SCAN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.SCAN
|
| 3624 |
|
|
#define ATD1CTL5_DSGN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DSGN
|
| 3625 |
|
|
#define ATD1CTL5_DJM _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DJM
|
| 3626 |
|
|
|
| 3627 |
|
|
} Overlap_STR;
|
| 3628 |
|
|
|
| 3629 |
|
|
struct {
|
| 3630 |
|
|
word CA :1; /* Analog Input Channel Select Code A */
|
| 3631 |
|
|
word CB :1; /* Analog Input Channel Select Code B */
|
| 3632 |
|
|
word CC :1; /* Analog Input Channel Select Code C */
|
| 3633 |
|
|
word :1;
|
| 3634 |
|
|
word MULT :1; /* Multi-Channel Sample Mode */
|
| 3635 |
|
|
word SCAN :1; /* Continuous Conversion Sequence Mode */
|
| 3636 |
|
|
word DSGN :1; /* Signed/Unsigned Result Data Mode */
|
| 3637 |
|
|
word DJM :1; /* Result Register Data Justification Mode */
|
| 3638 |
|
|
word PRS0 :1; /* ATD 1 Clock Prescaler 0 */
|
| 3639 |
|
|
word PRS1 :1; /* ATD 1 Clock Prescaler 1 */
|
| 3640 |
|
|
word PRS2 :1; /* ATD 1 Clock Prescaler 2 */
|
| 3641 |
|
|
word PRS3 :1; /* ATD 1 Clock Prescaler 3 */
|
| 3642 |
|
|
word PRS4 :1; /* ATD 1 Clock Prescaler 4 */
|
| 3643 |
|
|
word SMP0 :1; /* Sample Time Select 0 */
|
| 3644 |
|
|
word SMP1 :1; /* Sample Time Select 1 */
|
| 3645 |
|
|
word SRES8 :1; /* ATD 1 Resolution Select */
|
| 3646 |
|
|
} Bits;
|
| 3647 |
|
|
struct {
|
| 3648 |
|
|
word :1;
|
| 3649 |
|
|
word :1;
|
| 3650 |
|
|
word :1;
|
| 3651 |
|
|
word :1;
|
| 3652 |
|
|
word :1;
|
| 3653 |
|
|
word :1;
|
| 3654 |
|
|
word :1;
|
| 3655 |
|
|
word :1;
|
| 3656 |
|
|
word grpPRS :5;
|
| 3657 |
|
|
word grpSMP :2;
|
| 3658 |
|
|
word grpSRES_8 :1;
|
| 3659 |
|
|
} MergedBits;
|
| 3660 |
|
|
} ATD1CTL45STR;
|
| 3661 |
|
|
extern volatile ATD1CTL45STR _ATD1CTL45 @(REG_BASE + 0x00000124);
|
| 3662 |
|
|
#define ATD1CTL45 _ATD1CTL45.Word
|
| 3663 |
|
|
#define ATD1CTL45_CA _ATD1CTL45.Bits.CA
|
| 3664 |
|
|
#define ATD1CTL45_CB _ATD1CTL45.Bits.CB
|
| 3665 |
|
|
#define ATD1CTL45_CC _ATD1CTL45.Bits.CC
|
| 3666 |
|
|
#define ATD1CTL45_MULT _ATD1CTL45.Bits.MULT
|
| 3667 |
|
|
#define ATD1CTL45_SCAN _ATD1CTL45.Bits.SCAN
|
| 3668 |
|
|
#define ATD1CTL45_DSGN _ATD1CTL45.Bits.DSGN
|
| 3669 |
|
|
#define ATD1CTL45_DJM _ATD1CTL45.Bits.DJM
|
| 3670 |
|
|
#define ATD1CTL45_PRS0 _ATD1CTL45.Bits.PRS0
|
| 3671 |
|
|
#define ATD1CTL45_PRS1 _ATD1CTL45.Bits.PRS1
|
| 3672 |
|
|
#define ATD1CTL45_PRS2 _ATD1CTL45.Bits.PRS2
|
| 3673 |
|
|
#define ATD1CTL45_PRS3 _ATD1CTL45.Bits.PRS3
|
| 3674 |
|
|
#define ATD1CTL45_PRS4 _ATD1CTL45.Bits.PRS4
|
| 3675 |
|
|
#define ATD1CTL45_SMP0 _ATD1CTL45.Bits.SMP0
|
| 3676 |
|
|
#define ATD1CTL45_SMP1 _ATD1CTL45.Bits.SMP1
|
| 3677 |
|
|
#define ATD1CTL45_SRES8 _ATD1CTL45.Bits.SRES8
|
| 3678 |
|
|
#define ATD1CTL45_PRS _ATD1CTL45.MergedBits.grpPRS
|
| 3679 |
|
|
#define ATD1CTL45_SMP _ATD1CTL45.MergedBits.grpSMP
|
| 3680 |
|
|
|
| 3681 |
|
|
|
| 3682 |
|
|
/*** ATD1DR0 - ATD 1 Conversion Result Register 0; 0x00000130 ***/
|
| 3683 |
|
|
typedef union {
|
| 3684 |
|
|
word Word;
|
| 3685 |
|
|
/* Overlapped registers: */
|
| 3686 |
|
|
struct {
|
| 3687 |
|
|
/*** ATD1DR0H - ATD 1 Conversion Result Register 0 High; 0x00000130 ***/
|
| 3688 |
|
|
union {
|
| 3689 |
|
|
byte Byte;
|
| 3690 |
|
|
struct {
|
| 3691 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 3692 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 3693 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 3694 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 3695 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 3696 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 3697 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 3698 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 3699 |
|
|
} Bits;
|
| 3700 |
|
|
struct {
|
| 3701 |
|
|
byte grpBIT_8 :8;
|
| 3702 |
|
|
} MergedBits;
|
| 3703 |
|
|
} ATD1DR0HSTR;
|
| 3704 |
|
|
#define ATD1DR0H _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Byte
|
| 3705 |
|
|
#define ATD1DR0H_BIT8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT8
|
| 3706 |
|
|
#define ATD1DR0H_BIT9 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT9
|
| 3707 |
|
|
#define ATD1DR0H_BIT10 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT10
|
| 3708 |
|
|
#define ATD1DR0H_BIT11 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT11
|
| 3709 |
|
|
#define ATD1DR0H_BIT12 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT12
|
| 3710 |
|
|
#define ATD1DR0H_BIT13 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT13
|
| 3711 |
|
|
#define ATD1DR0H_BIT14 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT14
|
| 3712 |
|
|
#define ATD1DR0H_BIT15 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT15
|
| 3713 |
|
|
#define ATD1DR0H_BIT_8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.MergedBits.grpBIT_8
|
| 3714 |
|
|
#define ATD1DR0H_BIT ATD1DR0H_BIT_8
|
| 3715 |
|
|
|
| 3716 |
|
|
/*** ATD1DR0L - ATD 1 Conversion Result Register 0 Low; 0x00000131 ***/
|
| 3717 |
|
|
union {
|
| 3718 |
|
|
byte Byte;
|
| 3719 |
|
|
struct {
|
| 3720 |
|
|
byte :1;
|
| 3721 |
|
|
byte :1;
|
| 3722 |
|
|
byte :1;
|
| 3723 |
|
|
byte :1;
|
| 3724 |
|
|
byte :1;
|
| 3725 |
|
|
byte :1;
|
| 3726 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 3727 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 3728 |
|
|
} Bits;
|
| 3729 |
|
|
struct {
|
| 3730 |
|
|
byte :1;
|
| 3731 |
|
|
byte :1;
|
| 3732 |
|
|
byte :1;
|
| 3733 |
|
|
byte :1;
|
| 3734 |
|
|
byte :1;
|
| 3735 |
|
|
byte :1;
|
| 3736 |
|
|
byte grpBIT_6 :2;
|
| 3737 |
|
|
} MergedBits;
|
| 3738 |
|
|
} ATD1DR0LSTR;
|
| 3739 |
|
|
#define ATD1DR0L _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Byte
|
| 3740 |
|
|
#define ATD1DR0L_BIT6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT6
|
| 3741 |
|
|
#define ATD1DR0L_BIT7 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT7
|
| 3742 |
|
|
#define ATD1DR0L_BIT_6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.MergedBits.grpBIT_6
|
| 3743 |
|
|
#define ATD1DR0L_BIT ATD1DR0L_BIT_6
|
| 3744 |
|
|
|
| 3745 |
|
|
} Overlap_STR;
|
| 3746 |
|
|
|
| 3747 |
|
|
struct {
|
| 3748 |
|
|
word :1;
|
| 3749 |
|
|
word :1;
|
| 3750 |
|
|
word :1;
|
| 3751 |
|
|
word :1;
|
| 3752 |
|
|
word :1;
|
| 3753 |
|
|
word :1;
|
| 3754 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 3755 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 3756 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 3757 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 3758 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 3759 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 3760 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 3761 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 3762 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 3763 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 3764 |
|
|
} Bits;
|
| 3765 |
|
|
struct {
|
| 3766 |
|
|
word :1;
|
| 3767 |
|
|
word :1;
|
| 3768 |
|
|
word :1;
|
| 3769 |
|
|
word :1;
|
| 3770 |
|
|
word :1;
|
| 3771 |
|
|
word :1;
|
| 3772 |
|
|
word grpBIT_6 :10;
|
| 3773 |
|
|
} MergedBits;
|
| 3774 |
|
|
} ATD1DR0STR;
|
| 3775 |
|
|
extern volatile ATD1DR0STR _ATD1DR0 @(REG_BASE + 0x00000130);
|
| 3776 |
|
|
#define ATD1DR0 _ATD1DR0.Word
|
| 3777 |
|
|
#define ATD1DR0_BIT6 _ATD1DR0.Bits.BIT6
|
| 3778 |
|
|
#define ATD1DR0_BIT7 _ATD1DR0.Bits.BIT7
|
| 3779 |
|
|
#define ATD1DR0_BIT8 _ATD1DR0.Bits.BIT8
|
| 3780 |
|
|
#define ATD1DR0_BIT9 _ATD1DR0.Bits.BIT9
|
| 3781 |
|
|
#define ATD1DR0_BIT10 _ATD1DR0.Bits.BIT10
|
| 3782 |
|
|
#define ATD1DR0_BIT11 _ATD1DR0.Bits.BIT11
|
| 3783 |
|
|
#define ATD1DR0_BIT12 _ATD1DR0.Bits.BIT12
|
| 3784 |
|
|
#define ATD1DR0_BIT13 _ATD1DR0.Bits.BIT13
|
| 3785 |
|
|
#define ATD1DR0_BIT14 _ATD1DR0.Bits.BIT14
|
| 3786 |
|
|
#define ATD1DR0_BIT15 _ATD1DR0.Bits.BIT15
|
| 3787 |
|
|
#define ATD1DR0_BIT_6 _ATD1DR0.MergedBits.grpBIT_6
|
| 3788 |
|
|
#define ATD1DR0_BIT ATD1DR0_BIT_6
|
| 3789 |
|
|
|
| 3790 |
|
|
|
| 3791 |
|
|
/*** ATD1DR1 - ATD 1 Conversion Result Register 1; 0x00000132 ***/
|
| 3792 |
|
|
typedef union {
|
| 3793 |
|
|
word Word;
|
| 3794 |
|
|
/* Overlapped registers: */
|
| 3795 |
|
|
struct {
|
| 3796 |
|
|
/*** ATD1DR1H - ATD 1 Conversion Result Register 1 High; 0x00000132 ***/
|
| 3797 |
|
|
union {
|
| 3798 |
|
|
byte Byte;
|
| 3799 |
|
|
struct {
|
| 3800 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 3801 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 3802 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 3803 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 3804 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 3805 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 3806 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 3807 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 3808 |
|
|
} Bits;
|
| 3809 |
|
|
struct {
|
| 3810 |
|
|
byte grpBIT_8 :8;
|
| 3811 |
|
|
} MergedBits;
|
| 3812 |
|
|
} ATD1DR1HSTR;
|
| 3813 |
|
|
#define ATD1DR1H _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Byte
|
| 3814 |
|
|
#define ATD1DR1H_BIT8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT8
|
| 3815 |
|
|
#define ATD1DR1H_BIT9 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT9
|
| 3816 |
|
|
#define ATD1DR1H_BIT10 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT10
|
| 3817 |
|
|
#define ATD1DR1H_BIT11 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT11
|
| 3818 |
|
|
#define ATD1DR1H_BIT12 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT12
|
| 3819 |
|
|
#define ATD1DR1H_BIT13 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT13
|
| 3820 |
|
|
#define ATD1DR1H_BIT14 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT14
|
| 3821 |
|
|
#define ATD1DR1H_BIT15 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT15
|
| 3822 |
|
|
#define ATD1DR1H_BIT_8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.MergedBits.grpBIT_8
|
| 3823 |
|
|
#define ATD1DR1H_BIT ATD1DR1H_BIT_8
|
| 3824 |
|
|
|
| 3825 |
|
|
/*** ATD1DR1L - ATD 1 Conversion Result Register 1 Low; 0x00000133 ***/
|
| 3826 |
|
|
union {
|
| 3827 |
|
|
byte Byte;
|
| 3828 |
|
|
struct {
|
| 3829 |
|
|
byte :1;
|
| 3830 |
|
|
byte :1;
|
| 3831 |
|
|
byte :1;
|
| 3832 |
|
|
byte :1;
|
| 3833 |
|
|
byte :1;
|
| 3834 |
|
|
byte :1;
|
| 3835 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 3836 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 3837 |
|
|
} Bits;
|
| 3838 |
|
|
struct {
|
| 3839 |
|
|
byte :1;
|
| 3840 |
|
|
byte :1;
|
| 3841 |
|
|
byte :1;
|
| 3842 |
|
|
byte :1;
|
| 3843 |
|
|
byte :1;
|
| 3844 |
|
|
byte :1;
|
| 3845 |
|
|
byte grpBIT_6 :2;
|
| 3846 |
|
|
} MergedBits;
|
| 3847 |
|
|
} ATD1DR1LSTR;
|
| 3848 |
|
|
#define ATD1DR1L _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Byte
|
| 3849 |
|
|
#define ATD1DR1L_BIT6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT6
|
| 3850 |
|
|
#define ATD1DR1L_BIT7 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT7
|
| 3851 |
|
|
#define ATD1DR1L_BIT_6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.MergedBits.grpBIT_6
|
| 3852 |
|
|
#define ATD1DR1L_BIT ATD1DR1L_BIT_6
|
| 3853 |
|
|
|
| 3854 |
|
|
} Overlap_STR;
|
| 3855 |
|
|
|
| 3856 |
|
|
struct {
|
| 3857 |
|
|
word :1;
|
| 3858 |
|
|
word :1;
|
| 3859 |
|
|
word :1;
|
| 3860 |
|
|
word :1;
|
| 3861 |
|
|
word :1;
|
| 3862 |
|
|
word :1;
|
| 3863 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 3864 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 3865 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 3866 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 3867 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 3868 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 3869 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 3870 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 3871 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 3872 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 3873 |
|
|
} Bits;
|
| 3874 |
|
|
struct {
|
| 3875 |
|
|
word :1;
|
| 3876 |
|
|
word :1;
|
| 3877 |
|
|
word :1;
|
| 3878 |
|
|
word :1;
|
| 3879 |
|
|
word :1;
|
| 3880 |
|
|
word :1;
|
| 3881 |
|
|
word grpBIT_6 :10;
|
| 3882 |
|
|
} MergedBits;
|
| 3883 |
|
|
} ATD1DR1STR;
|
| 3884 |
|
|
extern volatile ATD1DR1STR _ATD1DR1 @(REG_BASE + 0x00000132);
|
| 3885 |
|
|
#define ATD1DR1 _ATD1DR1.Word
|
| 3886 |
|
|
#define ATD1DR1_BIT6 _ATD1DR1.Bits.BIT6
|
| 3887 |
|
|
#define ATD1DR1_BIT7 _ATD1DR1.Bits.BIT7
|
| 3888 |
|
|
#define ATD1DR1_BIT8 _ATD1DR1.Bits.BIT8
|
| 3889 |
|
|
#define ATD1DR1_BIT9 _ATD1DR1.Bits.BIT9
|
| 3890 |
|
|
#define ATD1DR1_BIT10 _ATD1DR1.Bits.BIT10
|
| 3891 |
|
|
#define ATD1DR1_BIT11 _ATD1DR1.Bits.BIT11
|
| 3892 |
|
|
#define ATD1DR1_BIT12 _ATD1DR1.Bits.BIT12
|
| 3893 |
|
|
#define ATD1DR1_BIT13 _ATD1DR1.Bits.BIT13
|
| 3894 |
|
|
#define ATD1DR1_BIT14 _ATD1DR1.Bits.BIT14
|
| 3895 |
|
|
#define ATD1DR1_BIT15 _ATD1DR1.Bits.BIT15
|
| 3896 |
|
|
#define ATD1DR1_BIT_6 _ATD1DR1.MergedBits.grpBIT_6
|
| 3897 |
|
|
#define ATD1DR1_BIT ATD1DR1_BIT_6
|
| 3898 |
|
|
|
| 3899 |
|
|
|
| 3900 |
|
|
/*** ATD1DR2 - ATD 1 Conversion Result Register 2; 0x00000134 ***/
|
| 3901 |
|
|
typedef union {
|
| 3902 |
|
|
word Word;
|
| 3903 |
|
|
/* Overlapped registers: */
|
| 3904 |
|
|
struct {
|
| 3905 |
|
|
/*** ATD1DR2H - ATD 1 Conversion Result Register 2 High; 0x00000134 ***/
|
| 3906 |
|
|
union {
|
| 3907 |
|
|
byte Byte;
|
| 3908 |
|
|
struct {
|
| 3909 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 3910 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 3911 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 3912 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 3913 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 3914 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 3915 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 3916 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 3917 |
|
|
} Bits;
|
| 3918 |
|
|
struct {
|
| 3919 |
|
|
byte grpBIT_8 :8;
|
| 3920 |
|
|
} MergedBits;
|
| 3921 |
|
|
} ATD1DR2HSTR;
|
| 3922 |
|
|
#define ATD1DR2H _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Byte
|
| 3923 |
|
|
#define ATD1DR2H_BIT8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT8
|
| 3924 |
|
|
#define ATD1DR2H_BIT9 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT9
|
| 3925 |
|
|
#define ATD1DR2H_BIT10 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT10
|
| 3926 |
|
|
#define ATD1DR2H_BIT11 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT11
|
| 3927 |
|
|
#define ATD1DR2H_BIT12 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT12
|
| 3928 |
|
|
#define ATD1DR2H_BIT13 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT13
|
| 3929 |
|
|
#define ATD1DR2H_BIT14 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT14
|
| 3930 |
|
|
#define ATD1DR2H_BIT15 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT15
|
| 3931 |
|
|
#define ATD1DR2H_BIT_8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.MergedBits.grpBIT_8
|
| 3932 |
|
|
#define ATD1DR2H_BIT ATD1DR2H_BIT_8
|
| 3933 |
|
|
|
| 3934 |
|
|
/*** ATD1DR2L - ATD 1 Conversion Result Register 2 Low; 0x00000135 ***/
|
| 3935 |
|
|
union {
|
| 3936 |
|
|
byte Byte;
|
| 3937 |
|
|
struct {
|
| 3938 |
|
|
byte :1;
|
| 3939 |
|
|
byte :1;
|
| 3940 |
|
|
byte :1;
|
| 3941 |
|
|
byte :1;
|
| 3942 |
|
|
byte :1;
|
| 3943 |
|
|
byte :1;
|
| 3944 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 3945 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 3946 |
|
|
} Bits;
|
| 3947 |
|
|
struct {
|
| 3948 |
|
|
byte :1;
|
| 3949 |
|
|
byte :1;
|
| 3950 |
|
|
byte :1;
|
| 3951 |
|
|
byte :1;
|
| 3952 |
|
|
byte :1;
|
| 3953 |
|
|
byte :1;
|
| 3954 |
|
|
byte grpBIT_6 :2;
|
| 3955 |
|
|
} MergedBits;
|
| 3956 |
|
|
} ATD1DR2LSTR;
|
| 3957 |
|
|
#define ATD1DR2L _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Byte
|
| 3958 |
|
|
#define ATD1DR2L_BIT6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT6
|
| 3959 |
|
|
#define ATD1DR2L_BIT7 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT7
|
| 3960 |
|
|
#define ATD1DR2L_BIT_6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.MergedBits.grpBIT_6
|
| 3961 |
|
|
#define ATD1DR2L_BIT ATD1DR2L_BIT_6
|
| 3962 |
|
|
|
| 3963 |
|
|
} Overlap_STR;
|
| 3964 |
|
|
|
| 3965 |
|
|
struct {
|
| 3966 |
|
|
word :1;
|
| 3967 |
|
|
word :1;
|
| 3968 |
|
|
word :1;
|
| 3969 |
|
|
word :1;
|
| 3970 |
|
|
word :1;
|
| 3971 |
|
|
word :1;
|
| 3972 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 3973 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 3974 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 3975 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 3976 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 3977 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 3978 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 3979 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 3980 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 3981 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 3982 |
|
|
} Bits;
|
| 3983 |
|
|
struct {
|
| 3984 |
|
|
word :1;
|
| 3985 |
|
|
word :1;
|
| 3986 |
|
|
word :1;
|
| 3987 |
|
|
word :1;
|
| 3988 |
|
|
word :1;
|
| 3989 |
|
|
word :1;
|
| 3990 |
|
|
word grpBIT_6 :10;
|
| 3991 |
|
|
} MergedBits;
|
| 3992 |
|
|
} ATD1DR2STR;
|
| 3993 |
|
|
extern volatile ATD1DR2STR _ATD1DR2 @(REG_BASE + 0x00000134);
|
| 3994 |
|
|
#define ATD1DR2 _ATD1DR2.Word
|
| 3995 |
|
|
#define ATD1DR2_BIT6 _ATD1DR2.Bits.BIT6
|
| 3996 |
|
|
#define ATD1DR2_BIT7 _ATD1DR2.Bits.BIT7
|
| 3997 |
|
|
#define ATD1DR2_BIT8 _ATD1DR2.Bits.BIT8
|
| 3998 |
|
|
#define ATD1DR2_BIT9 _ATD1DR2.Bits.BIT9
|
| 3999 |
|
|
#define ATD1DR2_BIT10 _ATD1DR2.Bits.BIT10
|
| 4000 |
|
|
#define ATD1DR2_BIT11 _ATD1DR2.Bits.BIT11
|
| 4001 |
|
|
#define ATD1DR2_BIT12 _ATD1DR2.Bits.BIT12
|
| 4002 |
|
|
#define ATD1DR2_BIT13 _ATD1DR2.Bits.BIT13
|
| 4003 |
|
|
#define ATD1DR2_BIT14 _ATD1DR2.Bits.BIT14
|
| 4004 |
|
|
#define ATD1DR2_BIT15 _ATD1DR2.Bits.BIT15
|
| 4005 |
|
|
#define ATD1DR2_BIT_6 _ATD1DR2.MergedBits.grpBIT_6
|
| 4006 |
|
|
#define ATD1DR2_BIT ATD1DR2_BIT_6
|
| 4007 |
|
|
|
| 4008 |
|
|
|
| 4009 |
|
|
/*** ATD1DR3 - ATD 1 Conversion Result Register 3; 0x00000136 ***/
|
| 4010 |
|
|
typedef union {
|
| 4011 |
|
|
word Word;
|
| 4012 |
|
|
/* Overlapped registers: */
|
| 4013 |
|
|
struct {
|
| 4014 |
|
|
/*** ATD1DR3H - ATD 1 Conversion Result Register 3 High; 0x00000136 ***/
|
| 4015 |
|
|
union {
|
| 4016 |
|
|
byte Byte;
|
| 4017 |
|
|
struct {
|
| 4018 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 4019 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 4020 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 4021 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 4022 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 4023 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 4024 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 4025 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 4026 |
|
|
} Bits;
|
| 4027 |
|
|
struct {
|
| 4028 |
|
|
byte grpBIT_8 :8;
|
| 4029 |
|
|
} MergedBits;
|
| 4030 |
|
|
} ATD1DR3HSTR;
|
| 4031 |
|
|
#define ATD1DR3H _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Byte
|
| 4032 |
|
|
#define ATD1DR3H_BIT8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT8
|
| 4033 |
|
|
#define ATD1DR3H_BIT9 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT9
|
| 4034 |
|
|
#define ATD1DR3H_BIT10 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT10
|
| 4035 |
|
|
#define ATD1DR3H_BIT11 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT11
|
| 4036 |
|
|
#define ATD1DR3H_BIT12 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT12
|
| 4037 |
|
|
#define ATD1DR3H_BIT13 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT13
|
| 4038 |
|
|
#define ATD1DR3H_BIT14 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT14
|
| 4039 |
|
|
#define ATD1DR3H_BIT15 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT15
|
| 4040 |
|
|
#define ATD1DR3H_BIT_8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.MergedBits.grpBIT_8
|
| 4041 |
|
|
#define ATD1DR3H_BIT ATD1DR3H_BIT_8
|
| 4042 |
|
|
|
| 4043 |
|
|
/*** ATD1DR3L - ATD 1 Conversion Result Register 3 Low; 0x00000137 ***/
|
| 4044 |
|
|
union {
|
| 4045 |
|
|
byte Byte;
|
| 4046 |
|
|
struct {
|
| 4047 |
|
|
byte :1;
|
| 4048 |
|
|
byte :1;
|
| 4049 |
|
|
byte :1;
|
| 4050 |
|
|
byte :1;
|
| 4051 |
|
|
byte :1;
|
| 4052 |
|
|
byte :1;
|
| 4053 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 4054 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 4055 |
|
|
} Bits;
|
| 4056 |
|
|
struct {
|
| 4057 |
|
|
byte :1;
|
| 4058 |
|
|
byte :1;
|
| 4059 |
|
|
byte :1;
|
| 4060 |
|
|
byte :1;
|
| 4061 |
|
|
byte :1;
|
| 4062 |
|
|
byte :1;
|
| 4063 |
|
|
byte grpBIT_6 :2;
|
| 4064 |
|
|
} MergedBits;
|
| 4065 |
|
|
} ATD1DR3LSTR;
|
| 4066 |
|
|
#define ATD1DR3L _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Byte
|
| 4067 |
|
|
#define ATD1DR3L_BIT6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT6
|
| 4068 |
|
|
#define ATD1DR3L_BIT7 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT7
|
| 4069 |
|
|
#define ATD1DR3L_BIT_6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.MergedBits.grpBIT_6
|
| 4070 |
|
|
#define ATD1DR3L_BIT ATD1DR3L_BIT_6
|
| 4071 |
|
|
|
| 4072 |
|
|
} Overlap_STR;
|
| 4073 |
|
|
|
| 4074 |
|
|
struct {
|
| 4075 |
|
|
word :1;
|
| 4076 |
|
|
word :1;
|
| 4077 |
|
|
word :1;
|
| 4078 |
|
|
word :1;
|
| 4079 |
|
|
word :1;
|
| 4080 |
|
|
word :1;
|
| 4081 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 4082 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 4083 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 4084 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 4085 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 4086 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 4087 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 4088 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 4089 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 4090 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 4091 |
|
|
} Bits;
|
| 4092 |
|
|
struct {
|
| 4093 |
|
|
word :1;
|
| 4094 |
|
|
word :1;
|
| 4095 |
|
|
word :1;
|
| 4096 |
|
|
word :1;
|
| 4097 |
|
|
word :1;
|
| 4098 |
|
|
word :1;
|
| 4099 |
|
|
word grpBIT_6 :10;
|
| 4100 |
|
|
} MergedBits;
|
| 4101 |
|
|
} ATD1DR3STR;
|
| 4102 |
|
|
extern volatile ATD1DR3STR _ATD1DR3 @(REG_BASE + 0x00000136);
|
| 4103 |
|
|
#define ATD1DR3 _ATD1DR3.Word
|
| 4104 |
|
|
#define ATD1DR3_BIT6 _ATD1DR3.Bits.BIT6
|
| 4105 |
|
|
#define ATD1DR3_BIT7 _ATD1DR3.Bits.BIT7
|
| 4106 |
|
|
#define ATD1DR3_BIT8 _ATD1DR3.Bits.BIT8
|
| 4107 |
|
|
#define ATD1DR3_BIT9 _ATD1DR3.Bits.BIT9
|
| 4108 |
|
|
#define ATD1DR3_BIT10 _ATD1DR3.Bits.BIT10
|
| 4109 |
|
|
#define ATD1DR3_BIT11 _ATD1DR3.Bits.BIT11
|
| 4110 |
|
|
#define ATD1DR3_BIT12 _ATD1DR3.Bits.BIT12
|
| 4111 |
|
|
#define ATD1DR3_BIT13 _ATD1DR3.Bits.BIT13
|
| 4112 |
|
|
#define ATD1DR3_BIT14 _ATD1DR3.Bits.BIT14
|
| 4113 |
|
|
#define ATD1DR3_BIT15 _ATD1DR3.Bits.BIT15
|
| 4114 |
|
|
#define ATD1DR3_BIT_6 _ATD1DR3.MergedBits.grpBIT_6
|
| 4115 |
|
|
#define ATD1DR3_BIT ATD1DR3_BIT_6
|
| 4116 |
|
|
|
| 4117 |
|
|
|
| 4118 |
|
|
/*** ATD1DR4 - ATD 1 Conversion Result Register 4; 0x00000138 ***/
|
| 4119 |
|
|
typedef union {
|
| 4120 |
|
|
word Word;
|
| 4121 |
|
|
/* Overlapped registers: */
|
| 4122 |
|
|
struct {
|
| 4123 |
|
|
/*** ATD1DR4H - ATD 1 Conversion Result Register 4 High; 0x00000138 ***/
|
| 4124 |
|
|
union {
|
| 4125 |
|
|
byte Byte;
|
| 4126 |
|
|
struct {
|
| 4127 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 4128 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 4129 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 4130 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 4131 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 4132 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 4133 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 4134 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 4135 |
|
|
} Bits;
|
| 4136 |
|
|
struct {
|
| 4137 |
|
|
byte grpBIT_8 :8;
|
| 4138 |
|
|
} MergedBits;
|
| 4139 |
|
|
} ATD1DR4HSTR;
|
| 4140 |
|
|
#define ATD1DR4H _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Byte
|
| 4141 |
|
|
#define ATD1DR4H_BIT8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT8
|
| 4142 |
|
|
#define ATD1DR4H_BIT9 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT9
|
| 4143 |
|
|
#define ATD1DR4H_BIT10 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT10
|
| 4144 |
|
|
#define ATD1DR4H_BIT11 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT11
|
| 4145 |
|
|
#define ATD1DR4H_BIT12 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT12
|
| 4146 |
|
|
#define ATD1DR4H_BIT13 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT13
|
| 4147 |
|
|
#define ATD1DR4H_BIT14 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT14
|
| 4148 |
|
|
#define ATD1DR4H_BIT15 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT15
|
| 4149 |
|
|
#define ATD1DR4H_BIT_8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.MergedBits.grpBIT_8
|
| 4150 |
|
|
#define ATD1DR4H_BIT ATD1DR4H_BIT_8
|
| 4151 |
|
|
|
| 4152 |
|
|
/*** ATD1DR4L - ATD 1 Conversion Result Register 4 Low; 0x00000139 ***/
|
| 4153 |
|
|
union {
|
| 4154 |
|
|
byte Byte;
|
| 4155 |
|
|
struct {
|
| 4156 |
|
|
byte :1;
|
| 4157 |
|
|
byte :1;
|
| 4158 |
|
|
byte :1;
|
| 4159 |
|
|
byte :1;
|
| 4160 |
|
|
byte :1;
|
| 4161 |
|
|
byte :1;
|
| 4162 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 4163 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 4164 |
|
|
} Bits;
|
| 4165 |
|
|
struct {
|
| 4166 |
|
|
byte :1;
|
| 4167 |
|
|
byte :1;
|
| 4168 |
|
|
byte :1;
|
| 4169 |
|
|
byte :1;
|
| 4170 |
|
|
byte :1;
|
| 4171 |
|
|
byte :1;
|
| 4172 |
|
|
byte grpBIT_6 :2;
|
| 4173 |
|
|
} MergedBits;
|
| 4174 |
|
|
} ATD1DR4LSTR;
|
| 4175 |
|
|
#define ATD1DR4L _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Byte
|
| 4176 |
|
|
#define ATD1DR4L_BIT6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT6
|
| 4177 |
|
|
#define ATD1DR4L_BIT7 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT7
|
| 4178 |
|
|
#define ATD1DR4L_BIT_6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.MergedBits.grpBIT_6
|
| 4179 |
|
|
#define ATD1DR4L_BIT ATD1DR4L_BIT_6
|
| 4180 |
|
|
|
| 4181 |
|
|
} Overlap_STR;
|
| 4182 |
|
|
|
| 4183 |
|
|
struct {
|
| 4184 |
|
|
word :1;
|
| 4185 |
|
|
word :1;
|
| 4186 |
|
|
word :1;
|
| 4187 |
|
|
word :1;
|
| 4188 |
|
|
word :1;
|
| 4189 |
|
|
word :1;
|
| 4190 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 4191 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 4192 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 4193 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 4194 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 4195 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 4196 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 4197 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 4198 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 4199 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 4200 |
|
|
} Bits;
|
| 4201 |
|
|
struct {
|
| 4202 |
|
|
word :1;
|
| 4203 |
|
|
word :1;
|
| 4204 |
|
|
word :1;
|
| 4205 |
|
|
word :1;
|
| 4206 |
|
|
word :1;
|
| 4207 |
|
|
word :1;
|
| 4208 |
|
|
word grpBIT_6 :10;
|
| 4209 |
|
|
} MergedBits;
|
| 4210 |
|
|
} ATD1DR4STR;
|
| 4211 |
|
|
extern volatile ATD1DR4STR _ATD1DR4 @(REG_BASE + 0x00000138);
|
| 4212 |
|
|
#define ATD1DR4 _ATD1DR4.Word
|
| 4213 |
|
|
#define ATD1DR4_BIT6 _ATD1DR4.Bits.BIT6
|
| 4214 |
|
|
#define ATD1DR4_BIT7 _ATD1DR4.Bits.BIT7
|
| 4215 |
|
|
#define ATD1DR4_BIT8 _ATD1DR4.Bits.BIT8
|
| 4216 |
|
|
#define ATD1DR4_BIT9 _ATD1DR4.Bits.BIT9
|
| 4217 |
|
|
#define ATD1DR4_BIT10 _ATD1DR4.Bits.BIT10
|
| 4218 |
|
|
#define ATD1DR4_BIT11 _ATD1DR4.Bits.BIT11
|
| 4219 |
|
|
#define ATD1DR4_BIT12 _ATD1DR4.Bits.BIT12
|
| 4220 |
|
|
#define ATD1DR4_BIT13 _ATD1DR4.Bits.BIT13
|
| 4221 |
|
|
#define ATD1DR4_BIT14 _ATD1DR4.Bits.BIT14
|
| 4222 |
|
|
#define ATD1DR4_BIT15 _ATD1DR4.Bits.BIT15
|
| 4223 |
|
|
#define ATD1DR4_BIT_6 _ATD1DR4.MergedBits.grpBIT_6
|
| 4224 |
|
|
#define ATD1DR4_BIT ATD1DR4_BIT_6
|
| 4225 |
|
|
|
| 4226 |
|
|
|
| 4227 |
|
|
/*** ATD1DR5 - ATD 1 Conversion Result Register 5; 0x0000013A ***/
|
| 4228 |
|
|
typedef union {
|
| 4229 |
|
|
word Word;
|
| 4230 |
|
|
/* Overlapped registers: */
|
| 4231 |
|
|
struct {
|
| 4232 |
|
|
/*** ATD1DR5H - ATD 1 Conversion Result Register 5 High; 0x0000013A ***/
|
| 4233 |
|
|
union {
|
| 4234 |
|
|
byte Byte;
|
| 4235 |
|
|
struct {
|
| 4236 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 4237 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 4238 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 4239 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 4240 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 4241 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 4242 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 4243 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 4244 |
|
|
} Bits;
|
| 4245 |
|
|
struct {
|
| 4246 |
|
|
byte grpBIT_8 :8;
|
| 4247 |
|
|
} MergedBits;
|
| 4248 |
|
|
} ATD1DR5HSTR;
|
| 4249 |
|
|
#define ATD1DR5H _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Byte
|
| 4250 |
|
|
#define ATD1DR5H_BIT8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT8
|
| 4251 |
|
|
#define ATD1DR5H_BIT9 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT9
|
| 4252 |
|
|
#define ATD1DR5H_BIT10 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT10
|
| 4253 |
|
|
#define ATD1DR5H_BIT11 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT11
|
| 4254 |
|
|
#define ATD1DR5H_BIT12 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT12
|
| 4255 |
|
|
#define ATD1DR5H_BIT13 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT13
|
| 4256 |
|
|
#define ATD1DR5H_BIT14 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT14
|
| 4257 |
|
|
#define ATD1DR5H_BIT15 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT15
|
| 4258 |
|
|
#define ATD1DR5H_BIT_8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.MergedBits.grpBIT_8
|
| 4259 |
|
|
#define ATD1DR5H_BIT ATD1DR5H_BIT_8
|
| 4260 |
|
|
|
| 4261 |
|
|
/*** ATD1DR5L - ATD 1 Conversion Result Register 5 Low; 0x0000013B ***/
|
| 4262 |
|
|
union {
|
| 4263 |
|
|
byte Byte;
|
| 4264 |
|
|
struct {
|
| 4265 |
|
|
byte :1;
|
| 4266 |
|
|
byte :1;
|
| 4267 |
|
|
byte :1;
|
| 4268 |
|
|
byte :1;
|
| 4269 |
|
|
byte :1;
|
| 4270 |
|
|
byte :1;
|
| 4271 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 4272 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 4273 |
|
|
} Bits;
|
| 4274 |
|
|
struct {
|
| 4275 |
|
|
byte :1;
|
| 4276 |
|
|
byte :1;
|
| 4277 |
|
|
byte :1;
|
| 4278 |
|
|
byte :1;
|
| 4279 |
|
|
byte :1;
|
| 4280 |
|
|
byte :1;
|
| 4281 |
|
|
byte grpBIT_6 :2;
|
| 4282 |
|
|
} MergedBits;
|
| 4283 |
|
|
} ATD1DR5LSTR;
|
| 4284 |
|
|
#define ATD1DR5L _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Byte
|
| 4285 |
|
|
#define ATD1DR5L_BIT6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT6
|
| 4286 |
|
|
#define ATD1DR5L_BIT7 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT7
|
| 4287 |
|
|
#define ATD1DR5L_BIT_6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.MergedBits.grpBIT_6
|
| 4288 |
|
|
#define ATD1DR5L_BIT ATD1DR5L_BIT_6
|
| 4289 |
|
|
|
| 4290 |
|
|
} Overlap_STR;
|
| 4291 |
|
|
|
| 4292 |
|
|
struct {
|
| 4293 |
|
|
word :1;
|
| 4294 |
|
|
word :1;
|
| 4295 |
|
|
word :1;
|
| 4296 |
|
|
word :1;
|
| 4297 |
|
|
word :1;
|
| 4298 |
|
|
word :1;
|
| 4299 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 4300 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 4301 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 4302 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 4303 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 4304 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 4305 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 4306 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 4307 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 4308 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 4309 |
|
|
} Bits;
|
| 4310 |
|
|
struct {
|
| 4311 |
|
|
word :1;
|
| 4312 |
|
|
word :1;
|
| 4313 |
|
|
word :1;
|
| 4314 |
|
|
word :1;
|
| 4315 |
|
|
word :1;
|
| 4316 |
|
|
word :1;
|
| 4317 |
|
|
word grpBIT_6 :10;
|
| 4318 |
|
|
} MergedBits;
|
| 4319 |
|
|
} ATD1DR5STR;
|
| 4320 |
|
|
extern volatile ATD1DR5STR _ATD1DR5 @(REG_BASE + 0x0000013A);
|
| 4321 |
|
|
#define ATD1DR5 _ATD1DR5.Word
|
| 4322 |
|
|
#define ATD1DR5_BIT6 _ATD1DR5.Bits.BIT6
|
| 4323 |
|
|
#define ATD1DR5_BIT7 _ATD1DR5.Bits.BIT7
|
| 4324 |
|
|
#define ATD1DR5_BIT8 _ATD1DR5.Bits.BIT8
|
| 4325 |
|
|
#define ATD1DR5_BIT9 _ATD1DR5.Bits.BIT9
|
| 4326 |
|
|
#define ATD1DR5_BIT10 _ATD1DR5.Bits.BIT10
|
| 4327 |
|
|
#define ATD1DR5_BIT11 _ATD1DR5.Bits.BIT11
|
| 4328 |
|
|
#define ATD1DR5_BIT12 _ATD1DR5.Bits.BIT12
|
| 4329 |
|
|
#define ATD1DR5_BIT13 _ATD1DR5.Bits.BIT13
|
| 4330 |
|
|
#define ATD1DR5_BIT14 _ATD1DR5.Bits.BIT14
|
| 4331 |
|
|
#define ATD1DR5_BIT15 _ATD1DR5.Bits.BIT15
|
| 4332 |
|
|
#define ATD1DR5_BIT_6 _ATD1DR5.MergedBits.grpBIT_6
|
| 4333 |
|
|
#define ATD1DR5_BIT ATD1DR5_BIT_6
|
| 4334 |
|
|
|
| 4335 |
|
|
|
| 4336 |
|
|
/*** ATD1DR6 - ATD 1 Conversion Result Register 6; 0x0000013C ***/
|
| 4337 |
|
|
typedef union {
|
| 4338 |
|
|
word Word;
|
| 4339 |
|
|
/* Overlapped registers: */
|
| 4340 |
|
|
struct {
|
| 4341 |
|
|
/*** ATD1DR6H - ATD 1 Conversion Result Register 6 High; 0x0000013C ***/
|
| 4342 |
|
|
union {
|
| 4343 |
|
|
byte Byte;
|
| 4344 |
|
|
struct {
|
| 4345 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 4346 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 4347 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 4348 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 4349 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 4350 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 4351 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 4352 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 4353 |
|
|
} Bits;
|
| 4354 |
|
|
struct {
|
| 4355 |
|
|
byte grpBIT_8 :8;
|
| 4356 |
|
|
} MergedBits;
|
| 4357 |
|
|
} ATD1DR6HSTR;
|
| 4358 |
|
|
#define ATD1DR6H _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Byte
|
| 4359 |
|
|
#define ATD1DR6H_BIT8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT8
|
| 4360 |
|
|
#define ATD1DR6H_BIT9 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT9
|
| 4361 |
|
|
#define ATD1DR6H_BIT10 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT10
|
| 4362 |
|
|
#define ATD1DR6H_BIT11 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT11
|
| 4363 |
|
|
#define ATD1DR6H_BIT12 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT12
|
| 4364 |
|
|
#define ATD1DR6H_BIT13 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT13
|
| 4365 |
|
|
#define ATD1DR6H_BIT14 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT14
|
| 4366 |
|
|
#define ATD1DR6H_BIT15 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT15
|
| 4367 |
|
|
#define ATD1DR6H_BIT_8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.MergedBits.grpBIT_8
|
| 4368 |
|
|
#define ATD1DR6H_BIT ATD1DR6H_BIT_8
|
| 4369 |
|
|
|
| 4370 |
|
|
/*** ATD1DR6L - ATD 1 Conversion Result Register 6 Low; 0x0000013D ***/
|
| 4371 |
|
|
union {
|
| 4372 |
|
|
byte Byte;
|
| 4373 |
|
|
struct {
|
| 4374 |
|
|
byte :1;
|
| 4375 |
|
|
byte :1;
|
| 4376 |
|
|
byte :1;
|
| 4377 |
|
|
byte :1;
|
| 4378 |
|
|
byte :1;
|
| 4379 |
|
|
byte :1;
|
| 4380 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 4381 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 4382 |
|
|
} Bits;
|
| 4383 |
|
|
struct {
|
| 4384 |
|
|
byte :1;
|
| 4385 |
|
|
byte :1;
|
| 4386 |
|
|
byte :1;
|
| 4387 |
|
|
byte :1;
|
| 4388 |
|
|
byte :1;
|
| 4389 |
|
|
byte :1;
|
| 4390 |
|
|
byte grpBIT_6 :2;
|
| 4391 |
|
|
} MergedBits;
|
| 4392 |
|
|
} ATD1DR6LSTR;
|
| 4393 |
|
|
#define ATD1DR6L _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Byte
|
| 4394 |
|
|
#define ATD1DR6L_BIT6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT6
|
| 4395 |
|
|
#define ATD1DR6L_BIT7 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT7
|
| 4396 |
|
|
#define ATD1DR6L_BIT_6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.MergedBits.grpBIT_6
|
| 4397 |
|
|
#define ATD1DR6L_BIT ATD1DR6L_BIT_6
|
| 4398 |
|
|
|
| 4399 |
|
|
} Overlap_STR;
|
| 4400 |
|
|
|
| 4401 |
|
|
struct {
|
| 4402 |
|
|
word :1;
|
| 4403 |
|
|
word :1;
|
| 4404 |
|
|
word :1;
|
| 4405 |
|
|
word :1;
|
| 4406 |
|
|
word :1;
|
| 4407 |
|
|
word :1;
|
| 4408 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 4409 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 4410 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 4411 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 4412 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 4413 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 4414 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 4415 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 4416 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 4417 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 4418 |
|
|
} Bits;
|
| 4419 |
|
|
struct {
|
| 4420 |
|
|
word :1;
|
| 4421 |
|
|
word :1;
|
| 4422 |
|
|
word :1;
|
| 4423 |
|
|
word :1;
|
| 4424 |
|
|
word :1;
|
| 4425 |
|
|
word :1;
|
| 4426 |
|
|
word grpBIT_6 :10;
|
| 4427 |
|
|
} MergedBits;
|
| 4428 |
|
|
} ATD1DR6STR;
|
| 4429 |
|
|
extern volatile ATD1DR6STR _ATD1DR6 @(REG_BASE + 0x0000013C);
|
| 4430 |
|
|
#define ATD1DR6 _ATD1DR6.Word
|
| 4431 |
|
|
#define ATD1DR6_BIT6 _ATD1DR6.Bits.BIT6
|
| 4432 |
|
|
#define ATD1DR6_BIT7 _ATD1DR6.Bits.BIT7
|
| 4433 |
|
|
#define ATD1DR6_BIT8 _ATD1DR6.Bits.BIT8
|
| 4434 |
|
|
#define ATD1DR6_BIT9 _ATD1DR6.Bits.BIT9
|
| 4435 |
|
|
#define ATD1DR6_BIT10 _ATD1DR6.Bits.BIT10
|
| 4436 |
|
|
#define ATD1DR6_BIT11 _ATD1DR6.Bits.BIT11
|
| 4437 |
|
|
#define ATD1DR6_BIT12 _ATD1DR6.Bits.BIT12
|
| 4438 |
|
|
#define ATD1DR6_BIT13 _ATD1DR6.Bits.BIT13
|
| 4439 |
|
|
#define ATD1DR6_BIT14 _ATD1DR6.Bits.BIT14
|
| 4440 |
|
|
#define ATD1DR6_BIT15 _ATD1DR6.Bits.BIT15
|
| 4441 |
|
|
#define ATD1DR6_BIT_6 _ATD1DR6.MergedBits.grpBIT_6
|
| 4442 |
|
|
#define ATD1DR6_BIT ATD1DR6_BIT_6
|
| 4443 |
|
|
|
| 4444 |
|
|
|
| 4445 |
|
|
/*** ATD1DR7 - ATD 1 Conversion Result Register 7; 0x0000013E ***/
|
| 4446 |
|
|
typedef union {
|
| 4447 |
|
|
word Word;
|
| 4448 |
|
|
/* Overlapped registers: */
|
| 4449 |
|
|
struct {
|
| 4450 |
|
|
/*** ATD1DR7H - ATD 1 Conversion Result Register 7 High; 0x0000013E ***/
|
| 4451 |
|
|
union {
|
| 4452 |
|
|
byte Byte;
|
| 4453 |
|
|
struct {
|
| 4454 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 4455 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 4456 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 4457 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 4458 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 4459 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 4460 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 4461 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 4462 |
|
|
} Bits;
|
| 4463 |
|
|
struct {
|
| 4464 |
|
|
byte grpBIT_8 :8;
|
| 4465 |
|
|
} MergedBits;
|
| 4466 |
|
|
} ATD1DR7HSTR;
|
| 4467 |
|
|
#define ATD1DR7H _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Byte
|
| 4468 |
|
|
#define ATD1DR7H_BIT8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT8
|
| 4469 |
|
|
#define ATD1DR7H_BIT9 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT9
|
| 4470 |
|
|
#define ATD1DR7H_BIT10 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT10
|
| 4471 |
|
|
#define ATD1DR7H_BIT11 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT11
|
| 4472 |
|
|
#define ATD1DR7H_BIT12 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT12
|
| 4473 |
|
|
#define ATD1DR7H_BIT13 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT13
|
| 4474 |
|
|
#define ATD1DR7H_BIT14 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT14
|
| 4475 |
|
|
#define ATD1DR7H_BIT15 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT15
|
| 4476 |
|
|
#define ATD1DR7H_BIT_8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.MergedBits.grpBIT_8
|
| 4477 |
|
|
#define ATD1DR7H_BIT ATD1DR7H_BIT_8
|
| 4478 |
|
|
|
| 4479 |
|
|
/*** ATD1DR7L - ATD 1 Conversion Result Register 7 Low; 0x0000013F ***/
|
| 4480 |
|
|
union {
|
| 4481 |
|
|
byte Byte;
|
| 4482 |
|
|
struct {
|
| 4483 |
|
|
byte :1;
|
| 4484 |
|
|
byte :1;
|
| 4485 |
|
|
byte :1;
|
| 4486 |
|
|
byte :1;
|
| 4487 |
|
|
byte :1;
|
| 4488 |
|
|
byte :1;
|
| 4489 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 4490 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 4491 |
|
|
} Bits;
|
| 4492 |
|
|
struct {
|
| 4493 |
|
|
byte :1;
|
| 4494 |
|
|
byte :1;
|
| 4495 |
|
|
byte :1;
|
| 4496 |
|
|
byte :1;
|
| 4497 |
|
|
byte :1;
|
| 4498 |
|
|
byte :1;
|
| 4499 |
|
|
byte grpBIT_6 :2;
|
| 4500 |
|
|
} MergedBits;
|
| 4501 |
|
|
} ATD1DR7LSTR;
|
| 4502 |
|
|
#define ATD1DR7L _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Byte
|
| 4503 |
|
|
#define ATD1DR7L_BIT6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT6
|
| 4504 |
|
|
#define ATD1DR7L_BIT7 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT7
|
| 4505 |
|
|
#define ATD1DR7L_BIT_6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.MergedBits.grpBIT_6
|
| 4506 |
|
|
#define ATD1DR7L_BIT ATD1DR7L_BIT_6
|
| 4507 |
|
|
|
| 4508 |
|
|
} Overlap_STR;
|
| 4509 |
|
|
|
| 4510 |
|
|
struct {
|
| 4511 |
|
|
word :1;
|
| 4512 |
|
|
word :1;
|
| 4513 |
|
|
word :1;
|
| 4514 |
|
|
word :1;
|
| 4515 |
|
|
word :1;
|
| 4516 |
|
|
word :1;
|
| 4517 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 4518 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 4519 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 4520 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 4521 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 4522 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 4523 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 4524 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 4525 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 4526 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 4527 |
|
|
} Bits;
|
| 4528 |
|
|
struct {
|
| 4529 |
|
|
word :1;
|
| 4530 |
|
|
word :1;
|
| 4531 |
|
|
word :1;
|
| 4532 |
|
|
word :1;
|
| 4533 |
|
|
word :1;
|
| 4534 |
|
|
word :1;
|
| 4535 |
|
|
word grpBIT_6 :10;
|
| 4536 |
|
|
} MergedBits;
|
| 4537 |
|
|
} ATD1DR7STR;
|
| 4538 |
|
|
extern volatile ATD1DR7STR _ATD1DR7 @(REG_BASE + 0x0000013E);
|
| 4539 |
|
|
#define ATD1DR7 _ATD1DR7.Word
|
| 4540 |
|
|
#define ATD1DR7_BIT6 _ATD1DR7.Bits.BIT6
|
| 4541 |
|
|
#define ATD1DR7_BIT7 _ATD1DR7.Bits.BIT7
|
| 4542 |
|
|
#define ATD1DR7_BIT8 _ATD1DR7.Bits.BIT8
|
| 4543 |
|
|
#define ATD1DR7_BIT9 _ATD1DR7.Bits.BIT9
|
| 4544 |
|
|
#define ATD1DR7_BIT10 _ATD1DR7.Bits.BIT10
|
| 4545 |
|
|
#define ATD1DR7_BIT11 _ATD1DR7.Bits.BIT11
|
| 4546 |
|
|
#define ATD1DR7_BIT12 _ATD1DR7.Bits.BIT12
|
| 4547 |
|
|
#define ATD1DR7_BIT13 _ATD1DR7.Bits.BIT13
|
| 4548 |
|
|
#define ATD1DR7_BIT14 _ATD1DR7.Bits.BIT14
|
| 4549 |
|
|
#define ATD1DR7_BIT15 _ATD1DR7.Bits.BIT15
|
| 4550 |
|
|
#define ATD1DR7_BIT_6 _ATD1DR7.MergedBits.grpBIT_6
|
| 4551 |
|
|
#define ATD1DR7_BIT ATD1DR7_BIT_6
|
| 4552 |
|
|
|
| 4553 |
|
|
|
| 4554 |
|
|
/*** PORTE - Port E Register; 0x00000008 ***/
|
| 4555 |
|
|
typedef union {
|
| 4556 |
|
|
byte Byte;
|
| 4557 |
|
|
struct {
|
| 4558 |
|
|
byte BIT0 :1; /* Port E Bit 0, XIRQ */
|
| 4559 |
|
|
byte BIT1 :1; /* Port E Bit 1, IRQ */
|
| 4560 |
|
|
byte BIT2 :1; /* Port E Bit 2, R/W */
|
| 4561 |
|
|
byte BIT3 :1; /* Port E Bit 3, LSTRB, TAGLO */
|
| 4562 |
|
|
byte BIT4 :1; /* Port E Bit 4, ECLK */
|
| 4563 |
|
|
byte BIT5 :1; /* Port E Bit 5, MODA, IPIPE0, RCRTO */
|
| 4564 |
|
|
byte BIT6 :1; /* Port E Bit 6, MODB, IPIPE1, SCGTO */
|
| 4565 |
|
|
byte BIT7 :1; /* Port E Bit 7, XCLKS, NOACC */
|
| 4566 |
|
|
} Bits;
|
| 4567 |
|
|
struct {
|
| 4568 |
|
|
byte grpBIT :8;
|
| 4569 |
|
|
} MergedBits;
|
| 4570 |
|
|
} PORTESTR;
|
| 4571 |
|
|
extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);
|
| 4572 |
|
|
#define PORTE _PORTE.Byte
|
| 4573 |
|
|
#define PORTE_BIT0 _PORTE.Bits.BIT0
|
| 4574 |
|
|
#define PORTE_BIT1 _PORTE.Bits.BIT1
|
| 4575 |
|
|
#define PORTE_BIT2 _PORTE.Bits.BIT2
|
| 4576 |
|
|
#define PORTE_BIT3 _PORTE.Bits.BIT3
|
| 4577 |
|
|
#define PORTE_BIT4 _PORTE.Bits.BIT4
|
| 4578 |
|
|
#define PORTE_BIT5 _PORTE.Bits.BIT5
|
| 4579 |
|
|
#define PORTE_BIT6 _PORTE.Bits.BIT6
|
| 4580 |
|
|
#define PORTE_BIT7 _PORTE.Bits.BIT7
|
| 4581 |
|
|
#define PORTE_BIT _PORTE.MergedBits.grpBIT
|
| 4582 |
|
|
|
| 4583 |
|
|
|
| 4584 |
|
|
/*** DDRE - Port E Data Direction Register; 0x00000009 ***/
|
| 4585 |
|
|
typedef union {
|
| 4586 |
|
|
byte Byte;
|
| 4587 |
|
|
struct {
|
| 4588 |
|
|
byte BIT0 :1; /* Data Direction Port A Bit 0 */
|
| 4589 |
|
|
byte BIT1 :1; /* Data Direction Port A Bit 1 */
|
| 4590 |
|
|
byte BIT2 :1; /* Data Direction Port A Bit 2 */
|
| 4591 |
|
|
byte BIT3 :1; /* Data Direction Port A Bit 3 */
|
| 4592 |
|
|
byte BIT4 :1; /* Data Direction Port A Bit 4 */
|
| 4593 |
|
|
byte BIT5 :1; /* Data Direction Port A Bit 5 */
|
| 4594 |
|
|
byte BIT6 :1; /* Data Direction Port A Bit 6 */
|
| 4595 |
|
|
byte BIT7 :1; /* Data Direction Port A Bit 7 */
|
| 4596 |
|
|
} Bits;
|
| 4597 |
|
|
struct {
|
| 4598 |
|
|
byte grpBIT :8;
|
| 4599 |
|
|
} MergedBits;
|
| 4600 |
|
|
} DDRESTR;
|
| 4601 |
|
|
extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);
|
| 4602 |
|
|
#define DDRE _DDRE.Byte
|
| 4603 |
|
|
#define DDRE_BIT0 _DDRE.Bits.BIT0
|
| 4604 |
|
|
#define DDRE_BIT1 _DDRE.Bits.BIT1
|
| 4605 |
|
|
#define DDRE_BIT2 _DDRE.Bits.BIT2
|
| 4606 |
|
|
#define DDRE_BIT3 _DDRE.Bits.BIT3
|
| 4607 |
|
|
#define DDRE_BIT4 _DDRE.Bits.BIT4
|
| 4608 |
|
|
#define DDRE_BIT5 _DDRE.Bits.BIT5
|
| 4609 |
|
|
#define DDRE_BIT6 _DDRE.Bits.BIT6
|
| 4610 |
|
|
#define DDRE_BIT7 _DDRE.Bits.BIT7
|
| 4611 |
|
|
#define DDRE_BIT _DDRE.MergedBits.grpBIT
|
| 4612 |
|
|
|
| 4613 |
|
|
|
| 4614 |
|
|
/*** PEAR - Port E Assignment Register; 0x0000000A ***/
|
| 4615 |
|
|
typedef union {
|
| 4616 |
|
|
byte Byte;
|
| 4617 |
|
|
struct {
|
| 4618 |
|
|
byte :1;
|
| 4619 |
|
|
byte :1;
|
| 4620 |
|
|
byte RDWE :1; /* Read / Write Enable */
|
| 4621 |
|
|
byte LSTRE :1; /* Low Strobe (LSTRB) Enable */
|
| 4622 |
|
|
byte NECLK :1; /* No External E Clock */
|
| 4623 |
|
|
byte PIPOE :1; /* Pipe Status Signal Output Enable */
|
| 4624 |
|
|
byte :1;
|
| 4625 |
|
|
byte NOACCE :1; /* CPU No Access Output Enable */
|
| 4626 |
|
|
} Bits;
|
| 4627 |
|
|
} PEARSTR;
|
| 4628 |
|
|
extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);
|
| 4629 |
|
|
#define PEAR _PEAR.Byte
|
| 4630 |
|
|
#define PEAR_RDWE _PEAR.Bits.RDWE
|
| 4631 |
|
|
#define PEAR_LSTRE _PEAR.Bits.LSTRE
|
| 4632 |
|
|
#define PEAR_NECLK _PEAR.Bits.NECLK
|
| 4633 |
|
|
#define PEAR_PIPOE _PEAR.Bits.PIPOE
|
| 4634 |
|
|
#define PEAR_NOACCE _PEAR.Bits.NOACCE
|
| 4635 |
|
|
|
| 4636 |
|
|
|
| 4637 |
|
|
/*** MODE - Mode Register; 0x0000000B ***/
|
| 4638 |
|
|
typedef union {
|
| 4639 |
|
|
byte Byte;
|
| 4640 |
|
|
struct {
|
| 4641 |
|
|
byte EME :1; /* Emulate Port E */
|
| 4642 |
|
|
byte EMK :1; /* Emulate Port K */
|
| 4643 |
|
|
byte :1;
|
| 4644 |
|
|
byte IVIS :1; /* Internal Visibility */
|
| 4645 |
|
|
byte :1;
|
| 4646 |
|
|
byte MODA :1; /* Mode Select Bit A */
|
| 4647 |
|
|
byte MODB :1; /* Mode Select Bit B */
|
| 4648 |
|
|
byte MODC :1; /* Mode Select Bit C */
|
| 4649 |
|
|
} Bits;
|
| 4650 |
|
|
} MODESTR;
|
| 4651 |
|
|
extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B);
|
| 4652 |
|
|
#define MODE _MODE.Byte
|
| 4653 |
|
|
#define MODE_EME _MODE.Bits.EME
|
| 4654 |
|
|
#define MODE_EMK _MODE.Bits.EMK
|
| 4655 |
|
|
#define MODE_IVIS _MODE.Bits.IVIS
|
| 4656 |
|
|
#define MODE_MODA _MODE.Bits.MODA
|
| 4657 |
|
|
#define MODE_MODB _MODE.Bits.MODB
|
| 4658 |
|
|
#define MODE_MODC _MODE.Bits.MODC
|
| 4659 |
|
|
|
| 4660 |
|
|
|
| 4661 |
|
|
/*** PUCR - Pull-Up Control Register; 0x0000000C ***/
|
| 4662 |
|
|
typedef union {
|
| 4663 |
|
|
byte Byte;
|
| 4664 |
|
|
struct {
|
| 4665 |
|
|
byte PUPAE :1; /* Pull-Up Port A Enable */
|
| 4666 |
|
|
byte PUPBE :1; /* Pull-Up Port B Enable */
|
| 4667 |
|
|
byte :1;
|
| 4668 |
|
|
byte :1;
|
| 4669 |
|
|
byte PUPEE :1; /* Pull-Up Port E Enable */
|
| 4670 |
|
|
byte :1;
|
| 4671 |
|
|
byte :1;
|
| 4672 |
|
|
byte PUPKE :1; /* Pull-Up Port K Enable */
|
| 4673 |
|
|
} Bits;
|
| 4674 |
|
|
} PUCRSTR;
|
| 4675 |
|
|
extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C);
|
| 4676 |
|
|
#define PUCR _PUCR.Byte
|
| 4677 |
|
|
#define PUCR_PUPAE _PUCR.Bits.PUPAE
|
| 4678 |
|
|
#define PUCR_PUPBE _PUCR.Bits.PUPBE
|
| 4679 |
|
|
#define PUCR_PUPEE _PUCR.Bits.PUPEE
|
| 4680 |
|
|
#define PUCR_PUPKE _PUCR.Bits.PUPKE
|
| 4681 |
|
|
|
| 4682 |
|
|
|
| 4683 |
|
|
/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/
|
| 4684 |
|
|
typedef union {
|
| 4685 |
|
|
byte Byte;
|
| 4686 |
|
|
struct {
|
| 4687 |
|
|
byte RDPA :1; /* Reduced Drive of Port A */
|
| 4688 |
|
|
byte RDPB :1; /* Reduced Drive of Port B */
|
| 4689 |
|
|
byte :1;
|
| 4690 |
|
|
byte :1;
|
| 4691 |
|
|
byte RDPE :1; /* Reduced Drive of Port E */
|
| 4692 |
|
|
byte :1;
|
| 4693 |
|
|
byte :1;
|
| 4694 |
|
|
byte RDPK :1; /* Reduced Drive of Port K */
|
| 4695 |
|
|
} Bits;
|
| 4696 |
|
|
} RDRIVSTR;
|
| 4697 |
|
|
extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);
|
| 4698 |
|
|
#define RDRIV _RDRIV.Byte
|
| 4699 |
|
|
#define RDRIV_RDPA _RDRIV.Bits.RDPA
|
| 4700 |
|
|
#define RDRIV_RDPB _RDRIV.Bits.RDPB
|
| 4701 |
|
|
#define RDRIV_RDPE _RDRIV.Bits.RDPE
|
| 4702 |
|
|
#define RDRIV_RDPK _RDRIV.Bits.RDPK
|
| 4703 |
|
|
|
| 4704 |
|
|
|
| 4705 |
|
|
/*** EBICTL - External Bus Interface Control; 0x0000000E ***/
|
| 4706 |
|
|
typedef union {
|
| 4707 |
|
|
byte Byte;
|
| 4708 |
|
|
struct {
|
| 4709 |
|
|
byte ESTR :1; /* E Stretches */
|
| 4710 |
|
|
byte :1;
|
| 4711 |
|
|
byte :1;
|
| 4712 |
|
|
byte :1;
|
| 4713 |
|
|
byte :1;
|
| 4714 |
|
|
byte :1;
|
| 4715 |
|
|
byte :1;
|
| 4716 |
|
|
byte :1;
|
| 4717 |
|
|
} Bits;
|
| 4718 |
|
|
} EBICTLSTR;
|
| 4719 |
|
|
extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);
|
| 4720 |
|
|
#define EBICTL _EBICTL.Byte
|
| 4721 |
|
|
#define EBICTL_ESTR _EBICTL.Bits.ESTR
|
| 4722 |
|
|
|
| 4723 |
|
|
|
| 4724 |
|
|
/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/
|
| 4725 |
|
|
typedef union {
|
| 4726 |
|
|
byte Byte;
|
| 4727 |
|
|
struct {
|
| 4728 |
|
|
byte RAMHAL :1; /* Internal RAM map alignment */
|
| 4729 |
|
|
byte :1;
|
| 4730 |
|
|
byte :1;
|
| 4731 |
|
|
byte RAM11 :1; /* Internal RAM map position Bit 11 */
|
| 4732 |
|
|
byte RAM12 :1; /* Internal RAM map position Bit 12 */
|
| 4733 |
|
|
byte RAM13 :1; /* Internal RAM map position Bit 13 */
|
| 4734 |
|
|
byte RAM14 :1; /* Internal RAM map position Bit 14 */
|
| 4735 |
|
|
byte RAM15 :1; /* Internal RAM map position Bit 15 */
|
| 4736 |
|
|
} Bits;
|
| 4737 |
|
|
struct {
|
| 4738 |
|
|
byte :1;
|
| 4739 |
|
|
byte :1;
|
| 4740 |
|
|
byte :1;
|
| 4741 |
|
|
byte grpRAM_11 :5;
|
| 4742 |
|
|
} MergedBits;
|
| 4743 |
|
|
} INITRMSTR;
|
| 4744 |
|
|
extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);
|
| 4745 |
|
|
#define INITRM _INITRM.Byte
|
| 4746 |
|
|
#define INITRM_RAMHAL _INITRM.Bits.RAMHAL
|
| 4747 |
|
|
#define INITRM_RAM11 _INITRM.Bits.RAM11
|
| 4748 |
|
|
#define INITRM_RAM12 _INITRM.Bits.RAM12
|
| 4749 |
|
|
#define INITRM_RAM13 _INITRM.Bits.RAM13
|
| 4750 |
|
|
#define INITRM_RAM14 _INITRM.Bits.RAM14
|
| 4751 |
|
|
#define INITRM_RAM15 _INITRM.Bits.RAM15
|
| 4752 |
|
|
#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11
|
| 4753 |
|
|
#define INITRM_RAM INITRM_RAM_11
|
| 4754 |
|
|
|
| 4755 |
|
|
|
| 4756 |
|
|
/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/
|
| 4757 |
|
|
typedef union {
|
| 4758 |
|
|
byte Byte;
|
| 4759 |
|
|
struct {
|
| 4760 |
|
|
byte :1;
|
| 4761 |
|
|
byte :1;
|
| 4762 |
|
|
byte :1;
|
| 4763 |
|
|
byte REG11 :1; /* Internal register map position REG11 */
|
| 4764 |
|
|
byte REG12 :1; /* Internal register map position REG12 */
|
| 4765 |
|
|
byte REG13 :1; /* Internal register map position REG13 */
|
| 4766 |
|
|
byte REG14 :1; /* Internal register map position REG14 */
|
| 4767 |
|
|
byte :1;
|
| 4768 |
|
|
} Bits;
|
| 4769 |
|
|
struct {
|
| 4770 |
|
|
byte :1;
|
| 4771 |
|
|
byte :1;
|
| 4772 |
|
|
byte :1;
|
| 4773 |
|
|
byte grpREG_11 :4;
|
| 4774 |
|
|
byte :1;
|
| 4775 |
|
|
} MergedBits;
|
| 4776 |
|
|
} INITRGSTR;
|
| 4777 |
|
|
extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);
|
| 4778 |
|
|
#define INITRG _INITRG.Byte
|
| 4779 |
|
|
#define INITRG_REG11 _INITRG.Bits.REG11
|
| 4780 |
|
|
#define INITRG_REG12 _INITRG.Bits.REG12
|
| 4781 |
|
|
#define INITRG_REG13 _INITRG.Bits.REG13
|
| 4782 |
|
|
#define INITRG_REG14 _INITRG.Bits.REG14
|
| 4783 |
|
|
#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11
|
| 4784 |
|
|
#define INITRG_REG INITRG_REG_11
|
| 4785 |
|
|
|
| 4786 |
|
|
|
| 4787 |
|
|
/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/
|
| 4788 |
|
|
typedef union {
|
| 4789 |
|
|
byte Byte;
|
| 4790 |
|
|
struct {
|
| 4791 |
|
|
byte EEON :1; /* Internal EEPROM On */
|
| 4792 |
|
|
byte :1;
|
| 4793 |
|
|
byte :1;
|
| 4794 |
|
|
byte :1;
|
| 4795 |
|
|
byte EE12 :1; /* Internal EEPROM map position Bit 12 */
|
| 4796 |
|
|
byte EE13 :1; /* Internal EEPROM map position Bit 13 */
|
| 4797 |
|
|
byte EE14 :1; /* Internal EEPROM map position Bit 14 */
|
| 4798 |
|
|
byte EE15 :1; /* Internal EEPROM map position Bit 15 */
|
| 4799 |
|
|
} Bits;
|
| 4800 |
|
|
struct {
|
| 4801 |
|
|
byte :1;
|
| 4802 |
|
|
byte :1;
|
| 4803 |
|
|
byte :1;
|
| 4804 |
|
|
byte :1;
|
| 4805 |
|
|
byte grpEE_12 :4;
|
| 4806 |
|
|
} MergedBits;
|
| 4807 |
|
|
} INITEESTR;
|
| 4808 |
|
|
extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);
|
| 4809 |
|
|
#define INITEE _INITEE.Byte
|
| 4810 |
|
|
#define INITEE_EEON _INITEE.Bits.EEON
|
| 4811 |
|
|
#define INITEE_EE12 _INITEE.Bits.EE12
|
| 4812 |
|
|
#define INITEE_EE13 _INITEE.Bits.EE13
|
| 4813 |
|
|
#define INITEE_EE14 _INITEE.Bits.EE14
|
| 4814 |
|
|
#define INITEE_EE15 _INITEE.Bits.EE15
|
| 4815 |
|
|
#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12
|
| 4816 |
|
|
#define INITEE_EE INITEE_EE_12
|
| 4817 |
|
|
|
| 4818 |
|
|
|
| 4819 |
|
|
/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/
|
| 4820 |
|
|
typedef union {
|
| 4821 |
|
|
byte Byte;
|
| 4822 |
|
|
struct {
|
| 4823 |
|
|
byte ROMON :1; /* Enable Flash EEPROM */
|
| 4824 |
|
|
byte ROMHM :1; /* Flash EEPROM only in second half of memory map */
|
| 4825 |
|
|
byte EXSTR0 :1; /* External Access Stretch Bit 0 */
|
| 4826 |
|
|
byte EXSTR1 :1; /* External Access Stretch Bit 1 */
|
| 4827 |
|
|
byte :1;
|
| 4828 |
|
|
byte :1;
|
| 4829 |
|
|
byte :1;
|
| 4830 |
|
|
byte :1;
|
| 4831 |
|
|
} Bits;
|
| 4832 |
|
|
struct {
|
| 4833 |
|
|
byte :1;
|
| 4834 |
|
|
byte :1;
|
| 4835 |
|
|
byte grpEXSTR :2;
|
| 4836 |
|
|
byte :1;
|
| 4837 |
|
|
byte :1;
|
| 4838 |
|
|
byte :1;
|
| 4839 |
|
|
byte :1;
|
| 4840 |
|
|
} MergedBits;
|
| 4841 |
|
|
} MISCSTR;
|
| 4842 |
|
|
extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013);
|
| 4843 |
|
|
#define MISC _MISC.Byte
|
| 4844 |
|
|
#define MISC_ROMON _MISC.Bits.ROMON
|
| 4845 |
|
|
#define MISC_ROMHM _MISC.Bits.ROMHM
|
| 4846 |
|
|
#define MISC_EXSTR0 _MISC.Bits.EXSTR0
|
| 4847 |
|
|
#define MISC_EXSTR1 _MISC.Bits.EXSTR1
|
| 4848 |
|
|
#define MISC_EXSTR _MISC.MergedBits.grpEXSTR
|
| 4849 |
|
|
|
| 4850 |
|
|
|
| 4851 |
|
|
/*** MTST0 - MTST0; 0x00000014 ***/
|
| 4852 |
|
|
typedef union {
|
| 4853 |
|
|
byte Byte;
|
| 4854 |
|
|
struct {
|
| 4855 |
|
|
byte BIT0 :1; /* MTST0 Bit 0 */
|
| 4856 |
|
|
byte BIT1 :1; /* MTST0 Bit 1 */
|
| 4857 |
|
|
byte BIT2 :1; /* MTST0 Bit 2 */
|
| 4858 |
|
|
byte BIT3 :1; /* MTST0 Bit 3 */
|
| 4859 |
|
|
byte BIT4 :1; /* MTST0 Bit 4 */
|
| 4860 |
|
|
byte BIT5 :1; /* MTST0 Bit 5 */
|
| 4861 |
|
|
byte BIT6 :1; /* MTST0 Bit 6 */
|
| 4862 |
|
|
byte BIT7 :1; /* MTST0 Bit 7 */
|
| 4863 |
|
|
} Bits;
|
| 4864 |
|
|
struct {
|
| 4865 |
|
|
byte grpBIT :8;
|
| 4866 |
|
|
} MergedBits;
|
| 4867 |
|
|
} MTST0STR;
|
| 4868 |
|
|
extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014);
|
| 4869 |
|
|
#define MTST0 _MTST0.Byte
|
| 4870 |
|
|
#define MTST0_BIT0 _MTST0.Bits.BIT0
|
| 4871 |
|
|
#define MTST0_BIT1 _MTST0.Bits.BIT1
|
| 4872 |
|
|
#define MTST0_BIT2 _MTST0.Bits.BIT2
|
| 4873 |
|
|
#define MTST0_BIT3 _MTST0.Bits.BIT3
|
| 4874 |
|
|
#define MTST0_BIT4 _MTST0.Bits.BIT4
|
| 4875 |
|
|
#define MTST0_BIT5 _MTST0.Bits.BIT5
|
| 4876 |
|
|
#define MTST0_BIT6 _MTST0.Bits.BIT6
|
| 4877 |
|
|
#define MTST0_BIT7 _MTST0.Bits.BIT7
|
| 4878 |
|
|
#define MTST0_BIT _MTST0.MergedBits.grpBIT
|
| 4879 |
|
|
|
| 4880 |
|
|
|
| 4881 |
|
|
/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/
|
| 4882 |
|
|
typedef union {
|
| 4883 |
|
|
byte Byte;
|
| 4884 |
|
|
struct {
|
| 4885 |
|
|
byte ADR0 :1; /* Test register select Bit 0 */
|
| 4886 |
|
|
byte ADR1 :1; /* Test register select Bit 1 */
|
| 4887 |
|
|
byte ADR2 :1; /* Test register select Bit 2 */
|
| 4888 |
|
|
byte ADR3 :1; /* Test register select Bit 3 */
|
| 4889 |
|
|
byte WRTINT :1; /* Write to the Interrupt Test Registers */
|
| 4890 |
|
|
byte :1;
|
| 4891 |
|
|
byte :1;
|
| 4892 |
|
|
byte :1;
|
| 4893 |
|
|
} Bits;
|
| 4894 |
|
|
struct {
|
| 4895 |
|
|
byte grpADR :4;
|
| 4896 |
|
|
byte :1;
|
| 4897 |
|
|
byte :1;
|
| 4898 |
|
|
byte :1;
|
| 4899 |
|
|
byte :1;
|
| 4900 |
|
|
} MergedBits;
|
| 4901 |
|
|
} ITCRSTR;
|
| 4902 |
|
|
extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);
|
| 4903 |
|
|
#define ITCR _ITCR.Byte
|
| 4904 |
|
|
#define ITCR_ADR0 _ITCR.Bits.ADR0
|
| 4905 |
|
|
#define ITCR_ADR1 _ITCR.Bits.ADR1
|
| 4906 |
|
|
#define ITCR_ADR2 _ITCR.Bits.ADR2
|
| 4907 |
|
|
#define ITCR_ADR3 _ITCR.Bits.ADR3
|
| 4908 |
|
|
#define ITCR_WRTINT _ITCR.Bits.WRTINT
|
| 4909 |
|
|
#define ITCR_ADR _ITCR.MergedBits.grpADR
|
| 4910 |
|
|
|
| 4911 |
|
|
|
| 4912 |
|
|
/*** ITEST - Interrupt Test Register; 0x00000016 ***/
|
| 4913 |
|
|
typedef union {
|
| 4914 |
|
|
byte Byte;
|
| 4915 |
|
|
struct {
|
| 4916 |
|
|
byte INT0 :1; /* Interrupt Test Register Bit 0 */
|
| 4917 |
|
|
byte INT2 :1; /* Interrupt Test Register Bit 1 */
|
| 4918 |
|
|
byte INT4 :1; /* Interrupt Test Register Bit 2 */
|
| 4919 |
|
|
byte INT6 :1; /* Interrupt Test Register Bit 3 */
|
| 4920 |
|
|
byte INT8 :1; /* Interrupt Test Register Bit 4 */
|
| 4921 |
|
|
byte INTA :1; /* Interrupt Test Register Bit 5 */
|
| 4922 |
|
|
byte INTC :1; /* Interrupt Test Register Bit 6 */
|
| 4923 |
|
|
byte INTE :1; /* Interrupt Test Register Bit 7 */
|
| 4924 |
|
|
} Bits;
|
| 4925 |
|
|
} ITESTSTR;
|
| 4926 |
|
|
extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);
|
| 4927 |
|
|
#define ITEST _ITEST.Byte
|
| 4928 |
|
|
#define ITEST_INT0 _ITEST.Bits.INT0
|
| 4929 |
|
|
#define ITEST_INT2 _ITEST.Bits.INT2
|
| 4930 |
|
|
#define ITEST_INT4 _ITEST.Bits.INT4
|
| 4931 |
|
|
#define ITEST_INT6 _ITEST.Bits.INT6
|
| 4932 |
|
|
#define ITEST_INT8 _ITEST.Bits.INT8
|
| 4933 |
|
|
#define ITEST_INTA _ITEST.Bits.INTA
|
| 4934 |
|
|
#define ITEST_INTC _ITEST.Bits.INTC
|
| 4935 |
|
|
#define ITEST_INTE _ITEST.Bits.INTE
|
| 4936 |
|
|
|
| 4937 |
|
|
|
| 4938 |
|
|
/*** MTST1 - MTST1; 0x00000017 ***/
|
| 4939 |
|
|
typedef union {
|
| 4940 |
|
|
byte Byte;
|
| 4941 |
|
|
struct {
|
| 4942 |
|
|
byte BIT0 :1; /* MTST1 Bit 0 */
|
| 4943 |
|
|
byte BIT1 :1; /* MTST1 Bit 1 */
|
| 4944 |
|
|
byte BIT2 :1; /* MTST1 Bit 2 */
|
| 4945 |
|
|
byte BIT3 :1; /* MTST1 Bit 3 */
|
| 4946 |
|
|
byte BIT4 :1; /* MTST1 Bit 4 */
|
| 4947 |
|
|
byte BIT5 :1; /* MTST1 Bit 5 */
|
| 4948 |
|
|
byte BIT6 :1; /* MTST1 Bit 6 */
|
| 4949 |
|
|
byte BIT7 :1; /* MTST1 Bit 7 */
|
| 4950 |
|
|
} Bits;
|
| 4951 |
|
|
struct {
|
| 4952 |
|
|
byte grpBIT :8;
|
| 4953 |
|
|
} MergedBits;
|
| 4954 |
|
|
} MTST1STR;
|
| 4955 |
|
|
extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017);
|
| 4956 |
|
|
#define MTST1 _MTST1.Byte
|
| 4957 |
|
|
#define MTST1_BIT0 _MTST1.Bits.BIT0
|
| 4958 |
|
|
#define MTST1_BIT1 _MTST1.Bits.BIT1
|
| 4959 |
|
|
#define MTST1_BIT2 _MTST1.Bits.BIT2
|
| 4960 |
|
|
#define MTST1_BIT3 _MTST1.Bits.BIT3
|
| 4961 |
|
|
#define MTST1_BIT4 _MTST1.Bits.BIT4
|
| 4962 |
|
|
#define MTST1_BIT5 _MTST1.Bits.BIT5
|
| 4963 |
|
|
#define MTST1_BIT6 _MTST1.Bits.BIT6
|
| 4964 |
|
|
#define MTST1_BIT7 _MTST1.Bits.BIT7
|
| 4965 |
|
|
#define MTST1_BIT _MTST1.MergedBits.grpBIT
|
| 4966 |
|
|
|
| 4967 |
|
|
|
| 4968 |
|
|
/*** PARTIDH - Part ID Register High; 0x0000001A ***/
|
| 4969 |
|
|
typedef union {
|
| 4970 |
|
|
byte Byte;
|
| 4971 |
|
|
struct {
|
| 4972 |
|
|
byte ID15 :1; /* Part ID Register Bit 15 */
|
| 4973 |
|
|
byte ID14 :1; /* Part ID Register Bit 14 */
|
| 4974 |
|
|
byte ID13 :1; /* Part ID Register Bit 13 */
|
| 4975 |
|
|
byte ID12 :1; /* Part ID Register Bit 12 */
|
| 4976 |
|
|
byte ID11 :1; /* Part ID Register Bit 11 */
|
| 4977 |
|
|
byte ID10 :1; /* Part ID Register Bit 10 */
|
| 4978 |
|
|
byte ID9 :1; /* Part ID Register Bit 9 */
|
| 4979 |
|
|
byte ID8 :1; /* Part ID Register Bit 8 */
|
| 4980 |
|
|
} Bits;
|
| 4981 |
|
|
} PARTIDHSTR;
|
| 4982 |
|
|
extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A);
|
| 4983 |
|
|
#define PARTIDH _PARTIDH.Byte
|
| 4984 |
|
|
#define PARTIDH_ID15 _PARTIDH.Bits.ID15
|
| 4985 |
|
|
#define PARTIDH_ID14 _PARTIDH.Bits.ID14
|
| 4986 |
|
|
#define PARTIDH_ID13 _PARTIDH.Bits.ID13
|
| 4987 |
|
|
#define PARTIDH_ID12 _PARTIDH.Bits.ID12
|
| 4988 |
|
|
#define PARTIDH_ID11 _PARTIDH.Bits.ID11
|
| 4989 |
|
|
#define PARTIDH_ID10 _PARTIDH.Bits.ID10
|
| 4990 |
|
|
#define PARTIDH_ID9 _PARTIDH.Bits.ID9
|
| 4991 |
|
|
#define PARTIDH_ID8 _PARTIDH.Bits.ID8
|
| 4992 |
|
|
|
| 4993 |
|
|
|
| 4994 |
|
|
/*** PARTIDL - Part ID Register Low; 0x0000001B ***/
|
| 4995 |
|
|
typedef union {
|
| 4996 |
|
|
byte Byte;
|
| 4997 |
|
|
struct {
|
| 4998 |
|
|
byte ID0 :1; /* Part ID Register Bit 0 */
|
| 4999 |
|
|
byte ID1 :1; /* Part ID Register Bit 1 */
|
| 5000 |
|
|
byte ID2 :1; /* Part ID Register Bit 2 */
|
| 5001 |
|
|
byte ID3 :1; /* Part ID Register Bit 3 */
|
| 5002 |
|
|
byte ID4 :1; /* Part ID Register Bit 4 */
|
| 5003 |
|
|
byte ID5 :1; /* Part ID Register Bit 5 */
|
| 5004 |
|
|
byte ID6 :1; /* Part ID Register Bit 6 */
|
| 5005 |
|
|
byte ID7 :1; /* Part ID Register Bit 7 */
|
| 5006 |
|
|
} Bits;
|
| 5007 |
|
|
struct {
|
| 5008 |
|
|
byte grpID :8;
|
| 5009 |
|
|
} MergedBits;
|
| 5010 |
|
|
} PARTIDLSTR;
|
| 5011 |
|
|
extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B);
|
| 5012 |
|
|
#define PARTIDL _PARTIDL.Byte
|
| 5013 |
|
|
#define PARTIDL_ID0 _PARTIDL.Bits.ID0
|
| 5014 |
|
|
#define PARTIDL_ID1 _PARTIDL.Bits.ID1
|
| 5015 |
|
|
#define PARTIDL_ID2 _PARTIDL.Bits.ID2
|
| 5016 |
|
|
#define PARTIDL_ID3 _PARTIDL.Bits.ID3
|
| 5017 |
|
|
#define PARTIDL_ID4 _PARTIDL.Bits.ID4
|
| 5018 |
|
|
#define PARTIDL_ID5 _PARTIDL.Bits.ID5
|
| 5019 |
|
|
#define PARTIDL_ID6 _PARTIDL.Bits.ID6
|
| 5020 |
|
|
#define PARTIDL_ID7 _PARTIDL.Bits.ID7
|
| 5021 |
|
|
#define PARTIDL_ID _PARTIDL.MergedBits.grpID
|
| 5022 |
|
|
|
| 5023 |
|
|
|
| 5024 |
|
|
/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/
|
| 5025 |
|
|
typedef union {
|
| 5026 |
|
|
byte Byte;
|
| 5027 |
|
|
struct {
|
| 5028 |
|
|
byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */
|
| 5029 |
|
|
byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */
|
| 5030 |
|
|
byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */
|
| 5031 |
|
|
byte :1;
|
| 5032 |
|
|
byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */
|
| 5033 |
|
|
byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */
|
| 5034 |
|
|
byte :1;
|
| 5035 |
|
|
byte reg_sw0 :1; /* Allocated System Register Space */
|
| 5036 |
|
|
} Bits;
|
| 5037 |
|
|
struct {
|
| 5038 |
|
|
byte grpram_sw :3;
|
| 5039 |
|
|
byte :1;
|
| 5040 |
|
|
byte grpeep_sw :2;
|
| 5041 |
|
|
byte :1;
|
| 5042 |
|
|
byte grpreg_sw :1;
|
| 5043 |
|
|
} MergedBits;
|
| 5044 |
|
|
} MEMSIZ0STR;
|
| 5045 |
|
|
extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);
|
| 5046 |
|
|
#define MEMSIZ0 _MEMSIZ0.Byte
|
| 5047 |
|
|
#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0
|
| 5048 |
|
|
#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1
|
| 5049 |
|
|
#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2
|
| 5050 |
|
|
#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0
|
| 5051 |
|
|
#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1
|
| 5052 |
|
|
#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0
|
| 5053 |
|
|
#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw
|
| 5054 |
|
|
#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw
|
| 5055 |
|
|
|
| 5056 |
|
|
|
| 5057 |
|
|
/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/
|
| 5058 |
|
|
typedef union {
|
| 5059 |
|
|
byte Byte;
|
| 5060 |
|
|
struct {
|
| 5061 |
|
|
byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */
|
| 5062 |
|
|
byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */
|
| 5063 |
|
|
byte :1;
|
| 5064 |
|
|
byte :1;
|
| 5065 |
|
|
byte :1;
|
| 5066 |
|
|
byte :1;
|
| 5067 |
|
|
byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */
|
| 5068 |
|
|
byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */
|
| 5069 |
|
|
} Bits;
|
| 5070 |
|
|
struct {
|
| 5071 |
|
|
byte grppag_sw :2;
|
| 5072 |
|
|
byte :1;
|
| 5073 |
|
|
byte :1;
|
| 5074 |
|
|
byte :1;
|
| 5075 |
|
|
byte :1;
|
| 5076 |
|
|
byte grprom_sw :2;
|
| 5077 |
|
|
} MergedBits;
|
| 5078 |
|
|
} MEMSIZ1STR;
|
| 5079 |
|
|
extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);
|
| 5080 |
|
|
#define MEMSIZ1 _MEMSIZ1.Byte
|
| 5081 |
|
|
#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0
|
| 5082 |
|
|
#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1
|
| 5083 |
|
|
#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0
|
| 5084 |
|
|
#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1
|
| 5085 |
|
|
#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw
|
| 5086 |
|
|
#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw
|
| 5087 |
|
|
|
| 5088 |
|
|
|
| 5089 |
|
|
/*** INTCR - Interrupt Control Register; 0x0000001E ***/
|
| 5090 |
|
|
typedef union {
|
| 5091 |
|
|
byte Byte;
|
| 5092 |
|
|
struct {
|
| 5093 |
|
|
byte :1;
|
| 5094 |
|
|
byte :1;
|
| 5095 |
|
|
byte :1;
|
| 5096 |
|
|
byte :1;
|
| 5097 |
|
|
byte :1;
|
| 5098 |
|
|
byte :1;
|
| 5099 |
|
|
byte IRQEN :1; /* External IRQ Enable */
|
| 5100 |
|
|
byte IRQE :1; /* IRQ Select Edge Sensitive Only */
|
| 5101 |
|
|
} Bits;
|
| 5102 |
|
|
} INTCRSTR;
|
| 5103 |
|
|
extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);
|
| 5104 |
|
|
#define INTCR _INTCR.Byte
|
| 5105 |
|
|
#define INTCR_IRQEN _INTCR.Bits.IRQEN
|
| 5106 |
|
|
#define INTCR_IRQE _INTCR.Bits.IRQE
|
| 5107 |
|
|
|
| 5108 |
|
|
|
| 5109 |
|
|
/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/
|
| 5110 |
|
|
typedef union {
|
| 5111 |
|
|
byte Byte;
|
| 5112 |
|
|
struct {
|
| 5113 |
|
|
byte :1;
|
| 5114 |
|
|
byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */
|
| 5115 |
|
|
byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */
|
| 5116 |
|
|
byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */
|
| 5117 |
|
|
byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */
|
| 5118 |
|
|
byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */
|
| 5119 |
|
|
byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */
|
| 5120 |
|
|
byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */
|
| 5121 |
|
|
} Bits;
|
| 5122 |
|
|
struct {
|
| 5123 |
|
|
byte :1;
|
| 5124 |
|
|
byte grpPSEL_1 :7;
|
| 5125 |
|
|
} MergedBits;
|
| 5126 |
|
|
} HPRIOSTR;
|
| 5127 |
|
|
extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);
|
| 5128 |
|
|
#define HPRIO _HPRIO.Byte
|
| 5129 |
|
|
#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1
|
| 5130 |
|
|
#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2
|
| 5131 |
|
|
#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3
|
| 5132 |
|
|
#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4
|
| 5133 |
|
|
#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5
|
| 5134 |
|
|
#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6
|
| 5135 |
|
|
#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7
|
| 5136 |
|
|
#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1
|
| 5137 |
|
|
#define HPRIO_PSEL HPRIO_PSEL_1
|
| 5138 |
|
|
|
| 5139 |
|
|
|
| 5140 |
|
|
/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/
|
| 5141 |
|
|
typedef union {
|
| 5142 |
|
|
byte Byte;
|
| 5143 |
|
|
struct {
|
| 5144 |
|
|
byte :1;
|
| 5145 |
|
|
byte :1;
|
| 5146 |
|
|
byte :1;
|
| 5147 |
|
|
byte :1;
|
| 5148 |
|
|
byte BKTAG :1; /* Breakpoint on Tag */
|
| 5149 |
|
|
byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */
|
| 5150 |
|
|
byte BKFULL :1; /* Full Breakpoint Mode Enable */
|
| 5151 |
|
|
byte BKEN :1; /* Breakpoint Enable */
|
| 5152 |
|
|
} Bits;
|
| 5153 |
|
|
} BKPCT0STR;
|
| 5154 |
|
|
extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);
|
| 5155 |
|
|
#define BKPCT0 _BKPCT0.Byte
|
| 5156 |
|
|
#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG
|
| 5157 |
|
|
#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM
|
| 5158 |
|
|
#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL
|
| 5159 |
|
|
#define BKPCT0_BKEN _BKPCT0.Bits.BKEN
|
| 5160 |
|
|
|
| 5161 |
|
|
|
| 5162 |
|
|
/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/
|
| 5163 |
|
|
typedef union {
|
| 5164 |
|
|
byte Byte;
|
| 5165 |
|
|
struct {
|
| 5166 |
|
|
byte BK1RW :1; /* R/W Compare Value 1 */
|
| 5167 |
|
|
byte BK1RWE :1; /* R/W Compare Enable 1 */
|
| 5168 |
|
|
byte BK0RW :1; /* R/W Compare Value 0 */
|
| 5169 |
|
|
byte BK0RWE :1; /* R/W Compare Enable 0 */
|
| 5170 |
|
|
byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */
|
| 5171 |
|
|
byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */
|
| 5172 |
|
|
byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */
|
| 5173 |
|
|
byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */
|
| 5174 |
|
|
} Bits;
|
| 5175 |
|
|
} BKPCT1STR;
|
| 5176 |
|
|
extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);
|
| 5177 |
|
|
#define BKPCT1 _BKPCT1.Byte
|
| 5178 |
|
|
#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW
|
| 5179 |
|
|
#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE
|
| 5180 |
|
|
#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW
|
| 5181 |
|
|
#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE
|
| 5182 |
|
|
#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL
|
| 5183 |
|
|
#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH
|
| 5184 |
|
|
#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL
|
| 5185 |
|
|
#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH
|
| 5186 |
|
|
|
| 5187 |
|
|
|
| 5188 |
|
|
/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/
|
| 5189 |
|
|
typedef union {
|
| 5190 |
|
|
byte Byte;
|
| 5191 |
|
|
struct {
|
| 5192 |
|
|
byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */
|
| 5193 |
|
|
byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */
|
| 5194 |
|
|
byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */
|
| 5195 |
|
|
byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */
|
| 5196 |
|
|
byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */
|
| 5197 |
|
|
byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */
|
| 5198 |
|
|
byte :1;
|
| 5199 |
|
|
byte :1;
|
| 5200 |
|
|
} Bits;
|
| 5201 |
|
|
struct {
|
| 5202 |
|
|
byte grpBK0V :6;
|
| 5203 |
|
|
byte :1;
|
| 5204 |
|
|
byte :1;
|
| 5205 |
|
|
} MergedBits;
|
| 5206 |
|
|
} BKP0XSTR;
|
| 5207 |
|
|
extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);
|
| 5208 |
|
|
#define BKP0X _BKP0X.Byte
|
| 5209 |
|
|
#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0
|
| 5210 |
|
|
#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1
|
| 5211 |
|
|
#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2
|
| 5212 |
|
|
#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3
|
| 5213 |
|
|
#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4
|
| 5214 |
|
|
#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5
|
| 5215 |
|
|
#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V
|
| 5216 |
|
|
|
| 5217 |
|
|
|
| 5218 |
|
|
/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/
|
| 5219 |
|
|
typedef union {
|
| 5220 |
|
|
byte Byte;
|
| 5221 |
|
|
struct {
|
| 5222 |
|
|
byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */
|
| 5223 |
|
|
byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */
|
| 5224 |
|
|
byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */
|
| 5225 |
|
|
byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */
|
| 5226 |
|
|
byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */
|
| 5227 |
|
|
byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */
|
| 5228 |
|
|
byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */
|
| 5229 |
|
|
byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */
|
| 5230 |
|
|
} Bits;
|
| 5231 |
|
|
struct {
|
| 5232 |
|
|
byte grpBIT_8 :8;
|
| 5233 |
|
|
} MergedBits;
|
| 5234 |
|
|
} BKP0HSTR;
|
| 5235 |
|
|
extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B);
|
| 5236 |
|
|
#define BKP0H _BKP0H.Byte
|
| 5237 |
|
|
#define BKP0H_BIT8 _BKP0H.Bits.BIT8
|
| 5238 |
|
|
#define BKP0H_BIT9 _BKP0H.Bits.BIT9
|
| 5239 |
|
|
#define BKP0H_BIT10 _BKP0H.Bits.BIT10
|
| 5240 |
|
|
#define BKP0H_BIT11 _BKP0H.Bits.BIT11
|
| 5241 |
|
|
#define BKP0H_BIT12 _BKP0H.Bits.BIT12
|
| 5242 |
|
|
#define BKP0H_BIT13 _BKP0H.Bits.BIT13
|
| 5243 |
|
|
#define BKP0H_BIT14 _BKP0H.Bits.BIT14
|
| 5244 |
|
|
#define BKP0H_BIT15 _BKP0H.Bits.BIT15
|
| 5245 |
|
|
#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8
|
| 5246 |
|
|
#define BKP0H_BIT BKP0H_BIT_8
|
| 5247 |
|
|
|
| 5248 |
|
|
|
| 5249 |
|
|
/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/
|
| 5250 |
|
|
typedef union {
|
| 5251 |
|
|
byte Byte;
|
| 5252 |
|
|
struct {
|
| 5253 |
|
|
byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */
|
| 5254 |
|
|
byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */
|
| 5255 |
|
|
byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */
|
| 5256 |
|
|
byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */
|
| 5257 |
|
|
byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */
|
| 5258 |
|
|
byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */
|
| 5259 |
|
|
byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */
|
| 5260 |
|
|
byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */
|
| 5261 |
|
|
} Bits;
|
| 5262 |
|
|
struct {
|
| 5263 |
|
|
byte grpBIT :8;
|
| 5264 |
|
|
} MergedBits;
|
| 5265 |
|
|
} BKP0LSTR;
|
| 5266 |
|
|
extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C);
|
| 5267 |
|
|
#define BKP0L _BKP0L.Byte
|
| 5268 |
|
|
#define BKP0L_BIT0 _BKP0L.Bits.BIT0
|
| 5269 |
|
|
#define BKP0L_BIT1 _BKP0L.Bits.BIT1
|
| 5270 |
|
|
#define BKP0L_BIT2 _BKP0L.Bits.BIT2
|
| 5271 |
|
|
#define BKP0L_BIT3 _BKP0L.Bits.BIT3
|
| 5272 |
|
|
#define BKP0L_BIT4 _BKP0L.Bits.BIT4
|
| 5273 |
|
|
#define BKP0L_BIT5 _BKP0L.Bits.BIT5
|
| 5274 |
|
|
#define BKP0L_BIT6 _BKP0L.Bits.BIT6
|
| 5275 |
|
|
#define BKP0L_BIT7 _BKP0L.Bits.BIT7
|
| 5276 |
|
|
#define BKP0L_BIT _BKP0L.MergedBits.grpBIT
|
| 5277 |
|
|
|
| 5278 |
|
|
|
| 5279 |
|
|
/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/
|
| 5280 |
|
|
typedef union {
|
| 5281 |
|
|
byte Byte;
|
| 5282 |
|
|
struct {
|
| 5283 |
|
|
byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */
|
| 5284 |
|
|
byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */
|
| 5285 |
|
|
byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */
|
| 5286 |
|
|
byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */
|
| 5287 |
|
|
byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */
|
| 5288 |
|
|
byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */
|
| 5289 |
|
|
byte :1;
|
| 5290 |
|
|
byte :1;
|
| 5291 |
|
|
} Bits;
|
| 5292 |
|
|
struct {
|
| 5293 |
|
|
byte grpBK1V :6;
|
| 5294 |
|
|
byte :1;
|
| 5295 |
|
|
byte :1;
|
| 5296 |
|
|
} MergedBits;
|
| 5297 |
|
|
} BKP1XSTR;
|
| 5298 |
|
|
extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D);
|
| 5299 |
|
|
#define BKP1X _BKP1X.Byte
|
| 5300 |
|
|
#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0
|
| 5301 |
|
|
#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1
|
| 5302 |
|
|
#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2
|
| 5303 |
|
|
#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3
|
| 5304 |
|
|
#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4
|
| 5305 |
|
|
#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5
|
| 5306 |
|
|
#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V
|
| 5307 |
|
|
|
| 5308 |
|
|
|
| 5309 |
|
|
/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/
|
| 5310 |
|
|
typedef union {
|
| 5311 |
|
|
byte Byte;
|
| 5312 |
|
|
struct {
|
| 5313 |
|
|
byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */
|
| 5314 |
|
|
byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */
|
| 5315 |
|
|
byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */
|
| 5316 |
|
|
byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */
|
| 5317 |
|
|
byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */
|
| 5318 |
|
|
byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */
|
| 5319 |
|
|
byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */
|
| 5320 |
|
|
byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */
|
| 5321 |
|
|
} Bits;
|
| 5322 |
|
|
struct {
|
| 5323 |
|
|
byte grpBIT_8 :8;
|
| 5324 |
|
|
} MergedBits;
|
| 5325 |
|
|
} BKP1HSTR;
|
| 5326 |
|
|
extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E);
|
| 5327 |
|
|
#define BKP1H _BKP1H.Byte
|
| 5328 |
|
|
#define BKP1H_BIT8 _BKP1H.Bits.BIT8
|
| 5329 |
|
|
#define BKP1H_BIT9 _BKP1H.Bits.BIT9
|
| 5330 |
|
|
#define BKP1H_BIT10 _BKP1H.Bits.BIT10
|
| 5331 |
|
|
#define BKP1H_BIT11 _BKP1H.Bits.BIT11
|
| 5332 |
|
|
#define BKP1H_BIT12 _BKP1H.Bits.BIT12
|
| 5333 |
|
|
#define BKP1H_BIT13 _BKP1H.Bits.BIT13
|
| 5334 |
|
|
#define BKP1H_BIT14 _BKP1H.Bits.BIT14
|
| 5335 |
|
|
#define BKP1H_BIT15 _BKP1H.Bits.BIT15
|
| 5336 |
|
|
#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8
|
| 5337 |
|
|
#define BKP1H_BIT BKP1H_BIT_8
|
| 5338 |
|
|
|
| 5339 |
|
|
|
| 5340 |
|
|
/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/
|
| 5341 |
|
|
typedef union {
|
| 5342 |
|
|
byte Byte;
|
| 5343 |
|
|
struct {
|
| 5344 |
|
|
byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */
|
| 5345 |
|
|
byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */
|
| 5346 |
|
|
byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */
|
| 5347 |
|
|
byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */
|
| 5348 |
|
|
byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */
|
| 5349 |
|
|
byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */
|
| 5350 |
|
|
byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */
|
| 5351 |
|
|
byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */
|
| 5352 |
|
|
} Bits;
|
| 5353 |
|
|
struct {
|
| 5354 |
|
|
byte grpBIT :8;
|
| 5355 |
|
|
} MergedBits;
|
| 5356 |
|
|
} BKP1LSTR;
|
| 5357 |
|
|
extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F);
|
| 5358 |
|
|
#define BKP1L _BKP1L.Byte
|
| 5359 |
|
|
#define BKP1L_BIT0 _BKP1L.Bits.BIT0
|
| 5360 |
|
|
#define BKP1L_BIT1 _BKP1L.Bits.BIT1
|
| 5361 |
|
|
#define BKP1L_BIT2 _BKP1L.Bits.BIT2
|
| 5362 |
|
|
#define BKP1L_BIT3 _BKP1L.Bits.BIT3
|
| 5363 |
|
|
#define BKP1L_BIT4 _BKP1L.Bits.BIT4
|
| 5364 |
|
|
#define BKP1L_BIT5 _BKP1L.Bits.BIT5
|
| 5365 |
|
|
#define BKP1L_BIT6 _BKP1L.Bits.BIT6
|
| 5366 |
|
|
#define BKP1L_BIT7 _BKP1L.Bits.BIT7
|
| 5367 |
|
|
#define BKP1L_BIT _BKP1L.MergedBits.grpBIT
|
| 5368 |
|
|
|
| 5369 |
|
|
|
| 5370 |
|
|
/*** PPAGE - Page Index Register; 0x00000030 ***/
|
| 5371 |
|
|
typedef union {
|
| 5372 |
|
|
byte Byte;
|
| 5373 |
|
|
struct {
|
| 5374 |
|
|
byte PIX0 :1; /* Page Index Register Bit 0 */
|
| 5375 |
|
|
byte PIX1 :1; /* Page Index Register Bit 1 */
|
| 5376 |
|
|
byte PIX2 :1; /* Page Index Register Bit 2 */
|
| 5377 |
|
|
byte PIX3 :1; /* Page Index Register Bit 3 */
|
| 5378 |
|
|
byte PIX4 :1; /* Page Index Register Bit 4 */
|
| 5379 |
|
|
byte PIX5 :1; /* Page Index Register Bit 5 */
|
| 5380 |
|
|
byte :1;
|
| 5381 |
|
|
byte :1;
|
| 5382 |
|
|
} Bits;
|
| 5383 |
|
|
struct {
|
| 5384 |
|
|
byte grpPIX :6;
|
| 5385 |
|
|
byte :1;
|
| 5386 |
|
|
byte :1;
|
| 5387 |
|
|
} MergedBits;
|
| 5388 |
|
|
} PPAGESTR;
|
| 5389 |
|
|
extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030);
|
| 5390 |
|
|
#define PPAGE _PPAGE.Byte
|
| 5391 |
|
|
#define PPAGE_PIX0 _PPAGE.Bits.PIX0
|
| 5392 |
|
|
#define PPAGE_PIX1 _PPAGE.Bits.PIX1
|
| 5393 |
|
|
#define PPAGE_PIX2 _PPAGE.Bits.PIX2
|
| 5394 |
|
|
#define PPAGE_PIX3 _PPAGE.Bits.PIX3
|
| 5395 |
|
|
#define PPAGE_PIX4 _PPAGE.Bits.PIX4
|
| 5396 |
|
|
#define PPAGE_PIX5 _PPAGE.Bits.PIX5
|
| 5397 |
|
|
#define PPAGE_PIX _PPAGE.MergedBits.grpPIX
|
| 5398 |
|
|
|
| 5399 |
|
|
|
| 5400 |
|
|
/*** PORTK - Port K Data Register; 0x00000032 ***/
|
| 5401 |
|
|
typedef union {
|
| 5402 |
|
|
byte Byte;
|
| 5403 |
|
|
struct {
|
| 5404 |
|
|
byte BIT0 :1; /* Port K Bit 0 */
|
| 5405 |
|
|
byte BIT1 :1; /* Port K Bit 1 */
|
| 5406 |
|
|
byte BIT2 :1; /* Port K Bit 2 */
|
| 5407 |
|
|
byte BIT3 :1; /* Port K Bit 3 */
|
| 5408 |
|
|
byte BIT4 :1; /* Port K Bit 4 */
|
| 5409 |
|
|
byte BIT5 :1; /* Port K Bit 5 */
|
| 5410 |
|
|
byte :1;
|
| 5411 |
|
|
byte BIT7 :1; /* Port K Bit 7 */
|
| 5412 |
|
|
} Bits;
|
| 5413 |
|
|
struct {
|
| 5414 |
|
|
byte grpBIT :6;
|
| 5415 |
|
|
byte :1;
|
| 5416 |
|
|
byte grpBIT_7 :1;
|
| 5417 |
|
|
} MergedBits;
|
| 5418 |
|
|
} PORTKSTR;
|
| 5419 |
|
|
extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);
|
| 5420 |
|
|
#define PORTK _PORTK.Byte
|
| 5421 |
|
|
#define PORTK_BIT0 _PORTK.Bits.BIT0
|
| 5422 |
|
|
#define PORTK_BIT1 _PORTK.Bits.BIT1
|
| 5423 |
|
|
#define PORTK_BIT2 _PORTK.Bits.BIT2
|
| 5424 |
|
|
#define PORTK_BIT3 _PORTK.Bits.BIT3
|
| 5425 |
|
|
#define PORTK_BIT4 _PORTK.Bits.BIT4
|
| 5426 |
|
|
#define PORTK_BIT5 _PORTK.Bits.BIT5
|
| 5427 |
|
|
#define PORTK_BIT7 _PORTK.Bits.BIT7
|
| 5428 |
|
|
#define PORTK_BIT _PORTK.MergedBits.grpBIT
|
| 5429 |
|
|
|
| 5430 |
|
|
|
| 5431 |
|
|
/*** DDRK - Port K Data Direction Register; 0x00000033 ***/
|
| 5432 |
|
|
typedef union {
|
| 5433 |
|
|
byte Byte;
|
| 5434 |
|
|
struct {
|
| 5435 |
|
|
byte DDK0 :1; /* Port K Data Direction Bit 0 */
|
| 5436 |
|
|
byte DDK1 :1; /* Port K Data Direction Bit 1 */
|
| 5437 |
|
|
byte DDK2 :1; /* Port K Data Direction Bit 2 */
|
| 5438 |
|
|
byte DDK3 :1; /* Port K Data Direction Bit 3 */
|
| 5439 |
|
|
byte DDK4 :1; /* Port K Data Direction Bit 4 */
|
| 5440 |
|
|
byte DDK5 :1; /* Port K Data Direction Bit 5 */
|
| 5441 |
|
|
byte :1;
|
| 5442 |
|
|
byte DDK7 :1; /* Port K Data Direction Bit 7 */
|
| 5443 |
|
|
} Bits;
|
| 5444 |
|
|
struct {
|
| 5445 |
|
|
byte grpDDK :6;
|
| 5446 |
|
|
byte :1;
|
| 5447 |
|
|
byte grpDDK_7 :1;
|
| 5448 |
|
|
} MergedBits;
|
| 5449 |
|
|
} DDRKSTR;
|
| 5450 |
|
|
extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);
|
| 5451 |
|
|
#define DDRK _DDRK.Byte
|
| 5452 |
|
|
#define DDRK_DDK0 _DDRK.Bits.DDK0
|
| 5453 |
|
|
#define DDRK_DDK1 _DDRK.Bits.DDK1
|
| 5454 |
|
|
#define DDRK_DDK2 _DDRK.Bits.DDK2
|
| 5455 |
|
|
#define DDRK_DDK3 _DDRK.Bits.DDK3
|
| 5456 |
|
|
#define DDRK_DDK4 _DDRK.Bits.DDK4
|
| 5457 |
|
|
#define DDRK_DDK5 _DDRK.Bits.DDK5
|
| 5458 |
|
|
#define DDRK_DDK7 _DDRK.Bits.DDK7
|
| 5459 |
|
|
#define DDRK_DDK _DDRK.MergedBits.grpDDK
|
| 5460 |
|
|
|
| 5461 |
|
|
|
| 5462 |
|
|
/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/
|
| 5463 |
|
|
typedef union {
|
| 5464 |
|
|
byte Byte;
|
| 5465 |
|
|
struct {
|
| 5466 |
|
|
byte SYN0 :1; /* CRG Synthesizer Bit 0 */
|
| 5467 |
|
|
byte SYN1 :1; /* CRG Synthesizer Bit 1 */
|
| 5468 |
|
|
byte SYN2 :1; /* CRG Synthesizer Bit 2 */
|
| 5469 |
|
|
byte SYN3 :1; /* CRG Synthesizer Bit 3 */
|
| 5470 |
|
|
byte SYN4 :1; /* CRG Synthesizer Bit 4 */
|
| 5471 |
|
|
byte SYN5 :1; /* CRG Synthesizer Bit 5 */
|
| 5472 |
|
|
byte :1;
|
| 5473 |
|
|
byte :1;
|
| 5474 |
|
|
} Bits;
|
| 5475 |
|
|
struct {
|
| 5476 |
|
|
byte grpSYN :6;
|
| 5477 |
|
|
byte :1;
|
| 5478 |
|
|
byte :1;
|
| 5479 |
|
|
} MergedBits;
|
| 5480 |
|
|
} SYNRSTR;
|
| 5481 |
|
|
extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);
|
| 5482 |
|
|
#define SYNR _SYNR.Byte
|
| 5483 |
|
|
#define SYNR_SYN0 _SYNR.Bits.SYN0
|
| 5484 |
|
|
#define SYNR_SYN1 _SYNR.Bits.SYN1
|
| 5485 |
|
|
#define SYNR_SYN2 _SYNR.Bits.SYN2
|
| 5486 |
|
|
#define SYNR_SYN3 _SYNR.Bits.SYN3
|
| 5487 |
|
|
#define SYNR_SYN4 _SYNR.Bits.SYN4
|
| 5488 |
|
|
#define SYNR_SYN5 _SYNR.Bits.SYN5
|
| 5489 |
|
|
#define SYNR_SYN _SYNR.MergedBits.grpSYN
|
| 5490 |
|
|
|
| 5491 |
|
|
|
| 5492 |
|
|
/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/
|
| 5493 |
|
|
typedef union {
|
| 5494 |
|
|
byte Byte;
|
| 5495 |
|
|
struct {
|
| 5496 |
|
|
byte REFDV0 :1; /* CRG Reference Divider Bit 0 */
|
| 5497 |
|
|
byte REFDV1 :1; /* CRG Reference Divider Bit 1 */
|
| 5498 |
|
|
byte REFDV2 :1; /* CRG Reference Divider Bit 2 */
|
| 5499 |
|
|
byte REFDV3 :1; /* CRG Reference Divider Bit 3 */
|
| 5500 |
|
|
byte :1;
|
| 5501 |
|
|
byte :1;
|
| 5502 |
|
|
byte :1;
|
| 5503 |
|
|
byte :1;
|
| 5504 |
|
|
} Bits;
|
| 5505 |
|
|
struct {
|
| 5506 |
|
|
byte grpREFDV :4;
|
| 5507 |
|
|
byte :1;
|
| 5508 |
|
|
byte :1;
|
| 5509 |
|
|
byte :1;
|
| 5510 |
|
|
byte :1;
|
| 5511 |
|
|
} MergedBits;
|
| 5512 |
|
|
} REFDVSTR;
|
| 5513 |
|
|
extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);
|
| 5514 |
|
|
#define REFDV _REFDV.Byte
|
| 5515 |
|
|
#define REFDV_REFDV0 _REFDV.Bits.REFDV0
|
| 5516 |
|
|
#define REFDV_REFDV1 _REFDV.Bits.REFDV1
|
| 5517 |
|
|
#define REFDV_REFDV2 _REFDV.Bits.REFDV2
|
| 5518 |
|
|
#define REFDV_REFDV3 _REFDV.Bits.REFDV3
|
| 5519 |
|
|
#define REFDV_REFDV _REFDV.MergedBits.grpREFDV
|
| 5520 |
|
|
|
| 5521 |
|
|
|
| 5522 |
|
|
/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/
|
| 5523 |
|
|
typedef union {
|
| 5524 |
|
|
byte Byte;
|
| 5525 |
|
|
struct {
|
| 5526 |
|
|
byte TOUT0 :1; /* CRG Test Flags Bit 0 */
|
| 5527 |
|
|
byte TOUT1 :1; /* CRG Test Flags Bit 1 */
|
| 5528 |
|
|
byte TOUT2 :1; /* CRG Test Flags Bit 2 */
|
| 5529 |
|
|
byte TOUT3 :1; /* CRG Test Flags Bit 3 */
|
| 5530 |
|
|
byte TOUT4 :1; /* CRG Test Flags Bit 4 */
|
| 5531 |
|
|
byte TOUT5 :1; /* CRG Test Flags Bit 5 */
|
| 5532 |
|
|
byte TOUT6 :1; /* CRG Test Flags Bit 6 */
|
| 5533 |
|
|
byte TOUT7 :1; /* CRG Test Flags Bit 7 */
|
| 5534 |
|
|
} Bits;
|
| 5535 |
|
|
struct {
|
| 5536 |
|
|
byte grpTOUT :8;
|
| 5537 |
|
|
} MergedBits;
|
| 5538 |
|
|
} CTFLGSTR;
|
| 5539 |
|
|
extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036);
|
| 5540 |
|
|
#define CTFLG _CTFLG.Byte
|
| 5541 |
|
|
#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0
|
| 5542 |
|
|
#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1
|
| 5543 |
|
|
#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2
|
| 5544 |
|
|
#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3
|
| 5545 |
|
|
#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4
|
| 5546 |
|
|
#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5
|
| 5547 |
|
|
#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6
|
| 5548 |
|
|
#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7
|
| 5549 |
|
|
#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT
|
| 5550 |
|
|
|
| 5551 |
|
|
|
| 5552 |
|
|
/*** CRGFLG - CRG Flags Register; 0x00000037 ***/
|
| 5553 |
|
|
typedef union {
|
| 5554 |
|
|
byte Byte;
|
| 5555 |
|
|
struct {
|
| 5556 |
|
|
byte SCM :1; /* Self-clock mode Status */
|
| 5557 |
|
|
byte SCMIF :1; /* Self-clock mode Interrupt Flag */
|
| 5558 |
|
|
byte TRACK :1; /* Track Status */
|
| 5559 |
|
|
byte LOCK :1; /* Lock Status */
|
| 5560 |
|
|
byte LOCKIF :1; /* PLL Lock Interrupt Flag */
|
| 5561 |
|
|
byte :1;
|
| 5562 |
|
|
byte PORF :1; /* Power on Reset Flag */
|
| 5563 |
|
|
byte RTIF :1; /* Real Time Interrupt Flag */
|
| 5564 |
|
|
} Bits;
|
| 5565 |
|
|
} CRGFLGSTR;
|
| 5566 |
|
|
extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);
|
| 5567 |
|
|
#define CRGFLG _CRGFLG.Byte
|
| 5568 |
|
|
#define CRGFLG_SCM _CRGFLG.Bits.SCM
|
| 5569 |
|
|
#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF
|
| 5570 |
|
|
#define CRGFLG_TRACK _CRGFLG.Bits.TRACK
|
| 5571 |
|
|
#define CRGFLG_LOCK _CRGFLG.Bits.LOCK
|
| 5572 |
|
|
#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF
|
| 5573 |
|
|
#define CRGFLG_PORF _CRGFLG.Bits.PORF
|
| 5574 |
|
|
#define CRGFLG_RTIF _CRGFLG.Bits.RTIF
|
| 5575 |
|
|
|
| 5576 |
|
|
|
| 5577 |
|
|
/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/
|
| 5578 |
|
|
typedef union {
|
| 5579 |
|
|
byte Byte;
|
| 5580 |
|
|
struct {
|
| 5581 |
|
|
byte :1;
|
| 5582 |
|
|
byte SCMIE :1; /* Self-clock mode Interrupt Enable */
|
| 5583 |
|
|
byte :1;
|
| 5584 |
|
|
byte :1;
|
| 5585 |
|
|
byte LOCKIE :1; /* Lock Interrupt Enable */
|
| 5586 |
|
|
byte :1;
|
| 5587 |
|
|
byte :1;
|
| 5588 |
|
|
byte RTIE :1; /* Real Time Interrupt Enable */
|
| 5589 |
|
|
} Bits;
|
| 5590 |
|
|
} CRGINTSTR;
|
| 5591 |
|
|
extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038);
|
| 5592 |
|
|
#define CRGINT _CRGINT.Byte
|
| 5593 |
|
|
#define CRGINT_SCMIE _CRGINT.Bits.SCMIE
|
| 5594 |
|
|
#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE
|
| 5595 |
|
|
#define CRGINT_RTIE _CRGINT.Bits.RTIE
|
| 5596 |
|
|
|
| 5597 |
|
|
|
| 5598 |
|
|
/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/
|
| 5599 |
|
|
typedef union {
|
| 5600 |
|
|
byte Byte;
|
| 5601 |
|
|
struct {
|
| 5602 |
|
|
byte COPWAI :1; /* COP stops in WAIT mode */
|
| 5603 |
|
|
byte RTIWAI :1; /* RTI stops in WAIT mode */
|
| 5604 |
|
|
byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */
|
| 5605 |
|
|
byte PLLWAI :1; /* PLL stops in WAIT mode */
|
| 5606 |
|
|
byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */
|
| 5607 |
|
|
byte SYSWAI :1; /* System clocks stop in WAIT mode */
|
| 5608 |
|
|
byte PSTP :1; /* Pseudo Stop */
|
| 5609 |
|
|
byte PLLSEL :1; /* PLL selected for system clock */
|
| 5610 |
|
|
} Bits;
|
| 5611 |
|
|
} CLKSELSTR;
|
| 5612 |
|
|
extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039);
|
| 5613 |
|
|
#define CLKSEL _CLKSEL.Byte
|
| 5614 |
|
|
#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI
|
| 5615 |
|
|
#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI
|
| 5616 |
|
|
#define CLKSEL_CWAI _CLKSEL.Bits.CWAI
|
| 5617 |
|
|
#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI
|
| 5618 |
|
|
#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI
|
| 5619 |
|
|
#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI
|
| 5620 |
|
|
#define CLKSEL_PSTP _CLKSEL.Bits.PSTP
|
| 5621 |
|
|
#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL
|
| 5622 |
|
|
|
| 5623 |
|
|
|
| 5624 |
|
|
/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/
|
| 5625 |
|
|
typedef union {
|
| 5626 |
|
|
byte Byte;
|
| 5627 |
|
|
struct {
|
| 5628 |
|
|
byte SCME :1; /* Self-clock mode enable */
|
| 5629 |
|
|
byte :1;
|
| 5630 |
|
|
byte :1;
|
| 5631 |
|
|
byte :1;
|
| 5632 |
|
|
byte ACQ :1; /* Acquisition */
|
| 5633 |
|
|
byte AUTO :1; /* Automatic Bandwidth Control */
|
| 5634 |
|
|
byte PLLON :1; /* Phase Lock Loop On */
|
| 5635 |
|
|
byte CME :1; /* Crystal Monitor Enable */
|
| 5636 |
|
|
} Bits;
|
| 5637 |
|
|
} PLLCTLSTR;
|
| 5638 |
|
|
extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A);
|
| 5639 |
|
|
#define PLLCTL _PLLCTL.Byte
|
| 5640 |
|
|
#define PLLCTL_SCME _PLLCTL.Bits.SCME
|
| 5641 |
|
|
#define PLLCTL_ACQ _PLLCTL.Bits.ACQ
|
| 5642 |
|
|
#define PLLCTL_AUTO _PLLCTL.Bits.AUTO
|
| 5643 |
|
|
#define PLLCTL_PLLON _PLLCTL.Bits.PLLON
|
| 5644 |
|
|
#define PLLCTL_CME _PLLCTL.Bits.CME
|
| 5645 |
|
|
|
| 5646 |
|
|
|
| 5647 |
|
|
/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/
|
| 5648 |
|
|
typedef union {
|
| 5649 |
|
|
byte Byte;
|
| 5650 |
|
|
struct {
|
| 5651 |
|
|
byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */
|
| 5652 |
|
|
byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */
|
| 5653 |
|
|
byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */
|
| 5654 |
|
|
byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */
|
| 5655 |
|
|
byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */
|
| 5656 |
|
|
byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */
|
| 5657 |
|
|
byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */
|
| 5658 |
|
|
byte :1;
|
| 5659 |
|
|
} Bits;
|
| 5660 |
|
|
struct {
|
| 5661 |
|
|
byte grpRTR :7;
|
| 5662 |
|
|
byte :1;
|
| 5663 |
|
|
} MergedBits;
|
| 5664 |
|
|
} RTICTLSTR;
|
| 5665 |
|
|
extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B);
|
| 5666 |
|
|
#define RTICTL _RTICTL.Byte
|
| 5667 |
|
|
#define RTICTL_RTR0 _RTICTL.Bits.RTR0
|
| 5668 |
|
|
#define RTICTL_RTR1 _RTICTL.Bits.RTR1
|
| 5669 |
|
|
#define RTICTL_RTR2 _RTICTL.Bits.RTR2
|
| 5670 |
|
|
#define RTICTL_RTR3 _RTICTL.Bits.RTR3
|
| 5671 |
|
|
#define RTICTL_RTR4 _RTICTL.Bits.RTR4
|
| 5672 |
|
|
#define RTICTL_RTR5 _RTICTL.Bits.RTR5
|
| 5673 |
|
|
#define RTICTL_RTR6 _RTICTL.Bits.RTR6
|
| 5674 |
|
|
#define RTICTL_RTR _RTICTL.MergedBits.grpRTR
|
| 5675 |
|
|
|
| 5676 |
|
|
|
| 5677 |
|
|
/*** COPCTL - CRG COP Control Register; 0x0000003C ***/
|
| 5678 |
|
|
typedef union {
|
| 5679 |
|
|
byte Byte;
|
| 5680 |
|
|
struct {
|
| 5681 |
|
|
byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */
|
| 5682 |
|
|
byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */
|
| 5683 |
|
|
byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */
|
| 5684 |
|
|
byte :1;
|
| 5685 |
|
|
byte :1;
|
| 5686 |
|
|
byte :1;
|
| 5687 |
|
|
byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */
|
| 5688 |
|
|
byte WCOP :1; /* Window COP mode */
|
| 5689 |
|
|
} Bits;
|
| 5690 |
|
|
struct {
|
| 5691 |
|
|
byte grpCR :3;
|
| 5692 |
|
|
byte :1;
|
| 5693 |
|
|
byte :1;
|
| 5694 |
|
|
byte :1;
|
| 5695 |
|
|
byte :1;
|
| 5696 |
|
|
byte :1;
|
| 5697 |
|
|
} MergedBits;
|
| 5698 |
|
|
} COPCTLSTR;
|
| 5699 |
|
|
extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C);
|
| 5700 |
|
|
#define COPCTL _COPCTL.Byte
|
| 5701 |
|
|
#define COPCTL_CR0 _COPCTL.Bits.CR0
|
| 5702 |
|
|
#define COPCTL_CR1 _COPCTL.Bits.CR1
|
| 5703 |
|
|
#define COPCTL_CR2 _COPCTL.Bits.CR2
|
| 5704 |
|
|
#define COPCTL_RSBCK _COPCTL.Bits.RSBCK
|
| 5705 |
|
|
#define COPCTL_WCOP _COPCTL.Bits.WCOP
|
| 5706 |
|
|
#define COPCTL_CR _COPCTL.MergedBits.grpCR
|
| 5707 |
|
|
|
| 5708 |
|
|
|
| 5709 |
|
|
/*** FORBYP - Crg force and bypass test register; 0x0000003D ***/
|
| 5710 |
|
|
typedef union {
|
| 5711 |
|
|
byte Byte;
|
| 5712 |
|
|
struct {
|
| 5713 |
|
|
byte BIT0 :1; /* Bit 0 */
|
| 5714 |
|
|
byte BIT1 :1; /* Bit 1 */
|
| 5715 |
|
|
byte BIT2 :1; /* Bit 2 */
|
| 5716 |
|
|
byte BIT3 :1; /* Bit 3 */
|
| 5717 |
|
|
byte BIT4 :1; /* Bit 4 */
|
| 5718 |
|
|
byte BIT5 :1; /* Bit 5 */
|
| 5719 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 5720 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 5721 |
|
|
} Bits;
|
| 5722 |
|
|
struct {
|
| 5723 |
|
|
byte grpBIT :8;
|
| 5724 |
|
|
} MergedBits;
|
| 5725 |
|
|
} FORBYPSTR;
|
| 5726 |
|
|
extern volatile FORBYPSTR _FORBYP @(REG_BASE + 0x0000003D);
|
| 5727 |
|
|
#define FORBYP _FORBYP.Byte
|
| 5728 |
|
|
#define FORBYP_BIT0 _FORBYP.Bits.BIT0
|
| 5729 |
|
|
#define FORBYP_BIT1 _FORBYP.Bits.BIT1
|
| 5730 |
|
|
#define FORBYP_BIT2 _FORBYP.Bits.BIT2
|
| 5731 |
|
|
#define FORBYP_BIT3 _FORBYP.Bits.BIT3
|
| 5732 |
|
|
#define FORBYP_BIT4 _FORBYP.Bits.BIT4
|
| 5733 |
|
|
#define FORBYP_BIT5 _FORBYP.Bits.BIT5
|
| 5734 |
|
|
#define FORBYP_BIT6 _FORBYP.Bits.BIT6
|
| 5735 |
|
|
#define FORBYP_BIT7 _FORBYP.Bits.BIT7
|
| 5736 |
|
|
#define FORBYP_BIT _FORBYP.MergedBits.grpBIT
|
| 5737 |
|
|
|
| 5738 |
|
|
|
| 5739 |
|
|
/*** CTCTL - CRG Test Control Register; 0x0000003E ***/
|
| 5740 |
|
|
typedef union {
|
| 5741 |
|
|
byte Byte;
|
| 5742 |
|
|
struct {
|
| 5743 |
|
|
byte TCTL0 :1; /* CRG Test Control Bit 0 */
|
| 5744 |
|
|
byte TCTL1 :1; /* CRG Test Control Bit 1 */
|
| 5745 |
|
|
byte TCTL2 :1; /* CRG Test Control Bit 2 */
|
| 5746 |
|
|
byte TCTL3 :1; /* CRG Test Control Bit 3 */
|
| 5747 |
|
|
byte TCTL4 :1; /* CRG Test Control Bit 4 */
|
| 5748 |
|
|
byte TCTL5 :1; /* CRG Test Control Bit 5 */
|
| 5749 |
|
|
byte TCTL6 :1; /* CRG Test Control Bit 6 */
|
| 5750 |
|
|
byte TCTL7 :1; /* CRG Test Control Bit 7 */
|
| 5751 |
|
|
} Bits;
|
| 5752 |
|
|
struct {
|
| 5753 |
|
|
byte grpTCTL :8;
|
| 5754 |
|
|
} MergedBits;
|
| 5755 |
|
|
} CTCTLSTR;
|
| 5756 |
|
|
extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E);
|
| 5757 |
|
|
#define CTCTL _CTCTL.Byte
|
| 5758 |
|
|
#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0
|
| 5759 |
|
|
#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1
|
| 5760 |
|
|
#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2
|
| 5761 |
|
|
#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3
|
| 5762 |
|
|
#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4
|
| 5763 |
|
|
#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5
|
| 5764 |
|
|
#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6
|
| 5765 |
|
|
#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7
|
| 5766 |
|
|
#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL
|
| 5767 |
|
|
|
| 5768 |
|
|
|
| 5769 |
|
|
/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/
|
| 5770 |
|
|
typedef union {
|
| 5771 |
|
|
byte Byte;
|
| 5772 |
|
|
struct {
|
| 5773 |
|
|
byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */
|
| 5774 |
|
|
byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */
|
| 5775 |
|
|
byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */
|
| 5776 |
|
|
byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */
|
| 5777 |
|
|
byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */
|
| 5778 |
|
|
byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */
|
| 5779 |
|
|
byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */
|
| 5780 |
|
|
byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */
|
| 5781 |
|
|
} Bits;
|
| 5782 |
|
|
struct {
|
| 5783 |
|
|
byte grpBIT :8;
|
| 5784 |
|
|
} MergedBits;
|
| 5785 |
|
|
} ARMCOPSTR;
|
| 5786 |
|
|
extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F);
|
| 5787 |
|
|
#define ARMCOP _ARMCOP.Byte
|
| 5788 |
|
|
#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0
|
| 5789 |
|
|
#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1
|
| 5790 |
|
|
#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2
|
| 5791 |
|
|
#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3
|
| 5792 |
|
|
#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4
|
| 5793 |
|
|
#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5
|
| 5794 |
|
|
#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6
|
| 5795 |
|
|
#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7
|
| 5796 |
|
|
#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT
|
| 5797 |
|
|
|
| 5798 |
|
|
|
| 5799 |
|
|
/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/
|
| 5800 |
|
|
typedef union {
|
| 5801 |
|
|
byte Byte;
|
| 5802 |
|
|
struct {
|
| 5803 |
|
|
byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */
|
| 5804 |
|
|
byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */
|
| 5805 |
|
|
byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */
|
| 5806 |
|
|
byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */
|
| 5807 |
|
|
byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */
|
| 5808 |
|
|
byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */
|
| 5809 |
|
|
byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */
|
| 5810 |
|
|
byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */
|
| 5811 |
|
|
} Bits;
|
| 5812 |
|
|
struct {
|
| 5813 |
|
|
byte grpIOS :8;
|
| 5814 |
|
|
} MergedBits;
|
| 5815 |
|
|
} TIOSSTR;
|
| 5816 |
|
|
extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040);
|
| 5817 |
|
|
#define TIOS _TIOS.Byte
|
| 5818 |
|
|
#define TIOS_IOS0 _TIOS.Bits.IOS0
|
| 5819 |
|
|
#define TIOS_IOS1 _TIOS.Bits.IOS1
|
| 5820 |
|
|
#define TIOS_IOS2 _TIOS.Bits.IOS2
|
| 5821 |
|
|
#define TIOS_IOS3 _TIOS.Bits.IOS3
|
| 5822 |
|
|
#define TIOS_IOS4 _TIOS.Bits.IOS4
|
| 5823 |
|
|
#define TIOS_IOS5 _TIOS.Bits.IOS5
|
| 5824 |
|
|
#define TIOS_IOS6 _TIOS.Bits.IOS6
|
| 5825 |
|
|
#define TIOS_IOS7 _TIOS.Bits.IOS7
|
| 5826 |
|
|
#define TIOS_IOS _TIOS.MergedBits.grpIOS
|
| 5827 |
|
|
|
| 5828 |
|
|
|
| 5829 |
|
|
/*** CFORC - Timer Compare Force Register; 0x00000041 ***/
|
| 5830 |
|
|
typedef union {
|
| 5831 |
|
|
byte Byte;
|
| 5832 |
|
|
struct {
|
| 5833 |
|
|
byte FOC0 :1; /* Force Output Compare Action for Channel 0 */
|
| 5834 |
|
|
byte FOC1 :1; /* Force Output Compare Action for Channel 1 */
|
| 5835 |
|
|
byte FOC2 :1; /* Force Output Compare Action for Channel 2 */
|
| 5836 |
|
|
byte FOC3 :1; /* Force Output Compare Action for Channel 3 */
|
| 5837 |
|
|
byte FOC4 :1; /* Force Output Compare Action for Channel 4 */
|
| 5838 |
|
|
byte FOC5 :1; /* Force Output Compare Action for Channel 5 */
|
| 5839 |
|
|
byte FOC6 :1; /* Force Output Compare Action for Channel 6 */
|
| 5840 |
|
|
byte FOC7 :1; /* Force Output Compare Action for Channel 7 */
|
| 5841 |
|
|
} Bits;
|
| 5842 |
|
|
struct {
|
| 5843 |
|
|
byte grpFOC :8;
|
| 5844 |
|
|
} MergedBits;
|
| 5845 |
|
|
} CFORCSTR;
|
| 5846 |
|
|
extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041);
|
| 5847 |
|
|
#define CFORC _CFORC.Byte
|
| 5848 |
|
|
#define CFORC_FOC0 _CFORC.Bits.FOC0
|
| 5849 |
|
|
#define CFORC_FOC1 _CFORC.Bits.FOC1
|
| 5850 |
|
|
#define CFORC_FOC2 _CFORC.Bits.FOC2
|
| 5851 |
|
|
#define CFORC_FOC3 _CFORC.Bits.FOC3
|
| 5852 |
|
|
#define CFORC_FOC4 _CFORC.Bits.FOC4
|
| 5853 |
|
|
#define CFORC_FOC5 _CFORC.Bits.FOC5
|
| 5854 |
|
|
#define CFORC_FOC6 _CFORC.Bits.FOC6
|
| 5855 |
|
|
#define CFORC_FOC7 _CFORC.Bits.FOC7
|
| 5856 |
|
|
#define CFORC_FOC _CFORC.MergedBits.grpFOC
|
| 5857 |
|
|
|
| 5858 |
|
|
|
| 5859 |
|
|
/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/
|
| 5860 |
|
|
typedef union {
|
| 5861 |
|
|
byte Byte;
|
| 5862 |
|
|
struct {
|
| 5863 |
|
|
byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */
|
| 5864 |
|
|
byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */
|
| 5865 |
|
|
byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */
|
| 5866 |
|
|
byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */
|
| 5867 |
|
|
byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */
|
| 5868 |
|
|
byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */
|
| 5869 |
|
|
byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */
|
| 5870 |
|
|
byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */
|
| 5871 |
|
|
} Bits;
|
| 5872 |
|
|
struct {
|
| 5873 |
|
|
byte grpOC7M :8;
|
| 5874 |
|
|
} MergedBits;
|
| 5875 |
|
|
} OC7MSTR;
|
| 5876 |
|
|
extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042);
|
| 5877 |
|
|
#define OC7M _OC7M.Byte
|
| 5878 |
|
|
#define OC7M_OC7M0 _OC7M.Bits.OC7M0
|
| 5879 |
|
|
#define OC7M_OC7M1 _OC7M.Bits.OC7M1
|
| 5880 |
|
|
#define OC7M_OC7M2 _OC7M.Bits.OC7M2
|
| 5881 |
|
|
#define OC7M_OC7M3 _OC7M.Bits.OC7M3
|
| 5882 |
|
|
#define OC7M_OC7M4 _OC7M.Bits.OC7M4
|
| 5883 |
|
|
#define OC7M_OC7M5 _OC7M.Bits.OC7M5
|
| 5884 |
|
|
#define OC7M_OC7M6 _OC7M.Bits.OC7M6
|
| 5885 |
|
|
#define OC7M_OC7M7 _OC7M.Bits.OC7M7
|
| 5886 |
|
|
#define OC7M_OC7M _OC7M.MergedBits.grpOC7M
|
| 5887 |
|
|
|
| 5888 |
|
|
|
| 5889 |
|
|
/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/
|
| 5890 |
|
|
typedef union {
|
| 5891 |
|
|
byte Byte;
|
| 5892 |
|
|
struct {
|
| 5893 |
|
|
byte grpOC7D :8;
|
| 5894 |
|
|
} MergedBits;
|
| 5895 |
|
|
} OC7DSTR;
|
| 5896 |
|
|
extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043);
|
| 5897 |
|
|
#define OC7D _OC7D.Byte
|
| 5898 |
|
|
#define OC7D_OC7D _OC7D.MergedBits.grpOC7D
|
| 5899 |
|
|
|
| 5900 |
|
|
|
| 5901 |
|
|
/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/
|
| 5902 |
|
|
typedef union {
|
| 5903 |
|
|
byte Byte;
|
| 5904 |
|
|
struct {
|
| 5905 |
|
|
byte :1;
|
| 5906 |
|
|
byte :1;
|
| 5907 |
|
|
byte :1;
|
| 5908 |
|
|
byte :1;
|
| 5909 |
|
|
byte TFFCA :1; /* Timer Fast Flag Clear All */
|
| 5910 |
|
|
byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */
|
| 5911 |
|
|
byte TSWAI :1; /* Timer Module Stops While in Wait */
|
| 5912 |
|
|
byte TEN :1; /* Timer Enable */
|
| 5913 |
|
|
} Bits;
|
| 5914 |
|
|
} TSCR1STR;
|
| 5915 |
|
|
extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046);
|
| 5916 |
|
|
#define TSCR1 _TSCR1.Byte
|
| 5917 |
|
|
#define TSCR1_TFFCA _TSCR1.Bits.TFFCA
|
| 5918 |
|
|
#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ
|
| 5919 |
|
|
#define TSCR1_TSWAI _TSCR1.Bits.TSWAI
|
| 5920 |
|
|
#define TSCR1_TEN _TSCR1.Bits.TEN
|
| 5921 |
|
|
|
| 5922 |
|
|
|
| 5923 |
|
|
/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/
|
| 5924 |
|
|
typedef union {
|
| 5925 |
|
|
byte Byte;
|
| 5926 |
|
|
struct {
|
| 5927 |
|
|
byte TOV0 :1; /* Toggle On Overflow Bit 0 */
|
| 5928 |
|
|
byte TOV1 :1; /* Toggle On Overflow Bit 1 */
|
| 5929 |
|
|
byte TOV2 :1; /* Toggle On Overflow Bit 2 */
|
| 5930 |
|
|
byte TOV3 :1; /* Toggle On Overflow Bit 3 */
|
| 5931 |
|
|
byte TOV4 :1; /* Toggle On Overflow Bit 4 */
|
| 5932 |
|
|
byte TOV5 :1; /* Toggle On Overflow Bit 5 */
|
| 5933 |
|
|
byte TOV6 :1; /* Toggle On Overflow Bit 6 */
|
| 5934 |
|
|
byte TOV7 :1; /* Toggle On Overflow Bit 7 */
|
| 5935 |
|
|
} Bits;
|
| 5936 |
|
|
struct {
|
| 5937 |
|
|
byte grpTOV :8;
|
| 5938 |
|
|
} MergedBits;
|
| 5939 |
|
|
} TTOVSTR;
|
| 5940 |
|
|
extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047);
|
| 5941 |
|
|
#define TTOV _TTOV.Byte
|
| 5942 |
|
|
#define TTOV_TOV0 _TTOV.Bits.TOV0
|
| 5943 |
|
|
#define TTOV_TOV1 _TTOV.Bits.TOV1
|
| 5944 |
|
|
#define TTOV_TOV2 _TTOV.Bits.TOV2
|
| 5945 |
|
|
#define TTOV_TOV3 _TTOV.Bits.TOV3
|
| 5946 |
|
|
#define TTOV_TOV4 _TTOV.Bits.TOV4
|
| 5947 |
|
|
#define TTOV_TOV5 _TTOV.Bits.TOV5
|
| 5948 |
|
|
#define TTOV_TOV6 _TTOV.Bits.TOV6
|
| 5949 |
|
|
#define TTOV_TOV7 _TTOV.Bits.TOV7
|
| 5950 |
|
|
#define TTOV_TOV _TTOV.MergedBits.grpTOV
|
| 5951 |
|
|
|
| 5952 |
|
|
|
| 5953 |
|
|
/*** TCTL1 - Timer Control Registers 1; 0x00000048 ***/
|
| 5954 |
|
|
typedef union {
|
| 5955 |
|
|
byte Byte;
|
| 5956 |
|
|
struct {
|
| 5957 |
|
|
byte OL4 :1; /* Output Level Bit 4 */
|
| 5958 |
|
|
byte OM4 :1; /* Output Mode Bit 4 */
|
| 5959 |
|
|
byte OL5 :1; /* Output Level Bit 5 */
|
| 5960 |
|
|
byte OM5 :1; /* Output Mode Bit 5 */
|
| 5961 |
|
|
byte OL6 :1; /* Output Level Bit 6 */
|
| 5962 |
|
|
byte OM6 :1; /* Output Mode Bit 6 */
|
| 5963 |
|
|
byte OL7 :1; /* Output Level Bit 7 */
|
| 5964 |
|
|
byte OM7 :1; /* Output Mode Bit 7 */
|
| 5965 |
|
|
} Bits;
|
| 5966 |
|
|
} TCTL1STR;
|
| 5967 |
|
|
extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048);
|
| 5968 |
|
|
#define TCTL1 _TCTL1.Byte
|
| 5969 |
|
|
#define TCTL1_OL4 _TCTL1.Bits.OL4
|
| 5970 |
|
|
#define TCTL1_OM4 _TCTL1.Bits.OM4
|
| 5971 |
|
|
#define TCTL1_OL5 _TCTL1.Bits.OL5
|
| 5972 |
|
|
#define TCTL1_OM5 _TCTL1.Bits.OM5
|
| 5973 |
|
|
#define TCTL1_OL6 _TCTL1.Bits.OL6
|
| 5974 |
|
|
#define TCTL1_OM6 _TCTL1.Bits.OM6
|
| 5975 |
|
|
#define TCTL1_OL7 _TCTL1.Bits.OL7
|
| 5976 |
|
|
#define TCTL1_OM7 _TCTL1.Bits.OM7
|
| 5977 |
|
|
|
| 5978 |
|
|
|
| 5979 |
|
|
/*** TCTL2 - Timer Control Registers 2; 0x00000049 ***/
|
| 5980 |
|
|
typedef union {
|
| 5981 |
|
|
byte Byte;
|
| 5982 |
|
|
struct {
|
| 5983 |
|
|
byte OL0 :1; /* Output Level Bit 0 */
|
| 5984 |
|
|
byte OM0 :1; /* Output Mode Bit 0 */
|
| 5985 |
|
|
byte OL1 :1; /* Output Level Bit 1 */
|
| 5986 |
|
|
byte OM1 :1; /* Output Mode Bit 1 */
|
| 5987 |
|
|
byte OL2 :1; /* Output Level Bit 2 */
|
| 5988 |
|
|
byte OM2 :1; /* Output Mode Bit 2 */
|
| 5989 |
|
|
byte OL3 :1; /* Output Level Bit 3 */
|
| 5990 |
|
|
byte OM3 :1; /* Output Mode Bit 3 */
|
| 5991 |
|
|
} Bits;
|
| 5992 |
|
|
} TCTL2STR;
|
| 5993 |
|
|
extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049);
|
| 5994 |
|
|
#define TCTL2 _TCTL2.Byte
|
| 5995 |
|
|
#define TCTL2_OL0 _TCTL2.Bits.OL0
|
| 5996 |
|
|
#define TCTL2_OM0 _TCTL2.Bits.OM0
|
| 5997 |
|
|
#define TCTL2_OL1 _TCTL2.Bits.OL1
|
| 5998 |
|
|
#define TCTL2_OM1 _TCTL2.Bits.OM1
|
| 5999 |
|
|
#define TCTL2_OL2 _TCTL2.Bits.OL2
|
| 6000 |
|
|
#define TCTL2_OM2 _TCTL2.Bits.OM2
|
| 6001 |
|
|
#define TCTL2_OL3 _TCTL2.Bits.OL3
|
| 6002 |
|
|
#define TCTL2_OM3 _TCTL2.Bits.OM3
|
| 6003 |
|
|
|
| 6004 |
|
|
|
| 6005 |
|
|
/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/
|
| 6006 |
|
|
typedef union {
|
| 6007 |
|
|
byte Byte;
|
| 6008 |
|
|
struct {
|
| 6009 |
|
|
byte EDG4A :1; /* Input Capture Edge Control 4A */
|
| 6010 |
|
|
byte EDG4B :1; /* Input Capture Edge Control 4B */
|
| 6011 |
|
|
byte EDG5A :1; /* Input Capture Edge Control 5A */
|
| 6012 |
|
|
byte EDG5B :1; /* Input Capture Edge Control 5B */
|
| 6013 |
|
|
byte EDG6A :1; /* Input Capture Edge Control 6A */
|
| 6014 |
|
|
byte EDG6B :1; /* Input Capture Edge Control 6B */
|
| 6015 |
|
|
byte EDG7A :1; /* Input Capture Edge Control 7A */
|
| 6016 |
|
|
byte EDG7B :1; /* Input Capture Edge Control 7B */
|
| 6017 |
|
|
} Bits;
|
| 6018 |
|
|
} TCTL3STR;
|
| 6019 |
|
|
extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A);
|
| 6020 |
|
|
#define TCTL3 _TCTL3.Byte
|
| 6021 |
|
|
#define TCTL3_EDG4A _TCTL3.Bits.EDG4A
|
| 6022 |
|
|
#define TCTL3_EDG4B _TCTL3.Bits.EDG4B
|
| 6023 |
|
|
#define TCTL3_EDG5A _TCTL3.Bits.EDG5A
|
| 6024 |
|
|
#define TCTL3_EDG5B _TCTL3.Bits.EDG5B
|
| 6025 |
|
|
#define TCTL3_EDG6A _TCTL3.Bits.EDG6A
|
| 6026 |
|
|
#define TCTL3_EDG6B _TCTL3.Bits.EDG6B
|
| 6027 |
|
|
#define TCTL3_EDG7A _TCTL3.Bits.EDG7A
|
| 6028 |
|
|
#define TCTL3_EDG7B _TCTL3.Bits.EDG7B
|
| 6029 |
|
|
|
| 6030 |
|
|
|
| 6031 |
|
|
/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/
|
| 6032 |
|
|
typedef union {
|
| 6033 |
|
|
byte Byte;
|
| 6034 |
|
|
struct {
|
| 6035 |
|
|
byte EDG0A :1; /* Input Capture Edge Control 0A */
|
| 6036 |
|
|
byte EDG0B :1; /* Input Capture Edge Control 0B */
|
| 6037 |
|
|
byte EDG1A :1; /* Input Capture Edge Control 1A */
|
| 6038 |
|
|
byte EDG1B :1; /* Input Capture Edge Control 1B */
|
| 6039 |
|
|
byte EDG2A :1; /* Input Capture Edge Control 2A */
|
| 6040 |
|
|
byte EDG2B :1; /* Input Capture Edge Control 2B */
|
| 6041 |
|
|
byte EDG3A :1; /* Input Capture Edge Control 3A */
|
| 6042 |
|
|
byte EDG3B :1; /* Input Capture Edge Control 3B */
|
| 6043 |
|
|
} Bits;
|
| 6044 |
|
|
} TCTL4STR;
|
| 6045 |
|
|
extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B);
|
| 6046 |
|
|
#define TCTL4 _TCTL4.Byte
|
| 6047 |
|
|
#define TCTL4_EDG0A _TCTL4.Bits.EDG0A
|
| 6048 |
|
|
#define TCTL4_EDG0B _TCTL4.Bits.EDG0B
|
| 6049 |
|
|
#define TCTL4_EDG1A _TCTL4.Bits.EDG1A
|
| 6050 |
|
|
#define TCTL4_EDG1B _TCTL4.Bits.EDG1B
|
| 6051 |
|
|
#define TCTL4_EDG2A _TCTL4.Bits.EDG2A
|
| 6052 |
|
|
#define TCTL4_EDG2B _TCTL4.Bits.EDG2B
|
| 6053 |
|
|
#define TCTL4_EDG3A _TCTL4.Bits.EDG3A
|
| 6054 |
|
|
#define TCTL4_EDG3B _TCTL4.Bits.EDG3B
|
| 6055 |
|
|
|
| 6056 |
|
|
|
| 6057 |
|
|
/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/
|
| 6058 |
|
|
typedef union {
|
| 6059 |
|
|
byte Byte;
|
| 6060 |
|
|
struct {
|
| 6061 |
|
|
byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */
|
| 6062 |
|
|
byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */
|
| 6063 |
|
|
byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */
|
| 6064 |
|
|
byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */
|
| 6065 |
|
|
byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */
|
| 6066 |
|
|
byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */
|
| 6067 |
|
|
byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */
|
| 6068 |
|
|
byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */
|
| 6069 |
|
|
} Bits;
|
| 6070 |
|
|
} TIESTR;
|
| 6071 |
|
|
extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C);
|
| 6072 |
|
|
#define TIE _TIE.Byte
|
| 6073 |
|
|
#define TIE_C0I _TIE.Bits.C0I
|
| 6074 |
|
|
#define TIE_C1I _TIE.Bits.C1I
|
| 6075 |
|
|
#define TIE_C2I _TIE.Bits.C2I
|
| 6076 |
|
|
#define TIE_C3I _TIE.Bits.C3I
|
| 6077 |
|
|
#define TIE_C4I _TIE.Bits.C4I
|
| 6078 |
|
|
#define TIE_C5I _TIE.Bits.C5I
|
| 6079 |
|
|
#define TIE_C6I _TIE.Bits.C6I
|
| 6080 |
|
|
#define TIE_C7I _TIE.Bits.C7I
|
| 6081 |
|
|
|
| 6082 |
|
|
|
| 6083 |
|
|
/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/
|
| 6084 |
|
|
typedef union {
|
| 6085 |
|
|
byte Byte;
|
| 6086 |
|
|
struct {
|
| 6087 |
|
|
byte PR0 :1; /* Timer Prescaler Select Bit 0 */
|
| 6088 |
|
|
byte PR1 :1; /* Timer Prescaler Select Bit 1 */
|
| 6089 |
|
|
byte PR2 :1; /* Timer Prescaler Select Bit 2 */
|
| 6090 |
|
|
byte TCRE :1; /* Timer Counter Reset Enable */
|
| 6091 |
|
|
byte :1;
|
| 6092 |
|
|
byte :1;
|
| 6093 |
|
|
byte :1;
|
| 6094 |
|
|
byte TOI :1; /* Timer Overflow Interrupt Enable */
|
| 6095 |
|
|
} Bits;
|
| 6096 |
|
|
struct {
|
| 6097 |
|
|
byte grpPR :3;
|
| 6098 |
|
|
byte :1;
|
| 6099 |
|
|
byte :1;
|
| 6100 |
|
|
byte :1;
|
| 6101 |
|
|
byte :1;
|
| 6102 |
|
|
byte :1;
|
| 6103 |
|
|
} MergedBits;
|
| 6104 |
|
|
} TSCR2STR;
|
| 6105 |
|
|
extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D);
|
| 6106 |
|
|
#define TSCR2 _TSCR2.Byte
|
| 6107 |
|
|
#define TSCR2_PR0 _TSCR2.Bits.PR0
|
| 6108 |
|
|
#define TSCR2_PR1 _TSCR2.Bits.PR1
|
| 6109 |
|
|
#define TSCR2_PR2 _TSCR2.Bits.PR2
|
| 6110 |
|
|
#define TSCR2_TCRE _TSCR2.Bits.TCRE
|
| 6111 |
|
|
#define TSCR2_TOI _TSCR2.Bits.TOI
|
| 6112 |
|
|
#define TSCR2_PR _TSCR2.MergedBits.grpPR
|
| 6113 |
|
|
|
| 6114 |
|
|
|
| 6115 |
|
|
/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/
|
| 6116 |
|
|
typedef union {
|
| 6117 |
|
|
byte Byte;
|
| 6118 |
|
|
struct {
|
| 6119 |
|
|
byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */
|
| 6120 |
|
|
byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */
|
| 6121 |
|
|
byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */
|
| 6122 |
|
|
byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */
|
| 6123 |
|
|
byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */
|
| 6124 |
|
|
byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */
|
| 6125 |
|
|
byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */
|
| 6126 |
|
|
byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */
|
| 6127 |
|
|
} Bits;
|
| 6128 |
|
|
} TFLG1STR;
|
| 6129 |
|
|
extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E);
|
| 6130 |
|
|
#define TFLG1 _TFLG1.Byte
|
| 6131 |
|
|
#define TFLG1_C0F _TFLG1.Bits.C0F
|
| 6132 |
|
|
#define TFLG1_C1F _TFLG1.Bits.C1F
|
| 6133 |
|
|
#define TFLG1_C2F _TFLG1.Bits.C2F
|
| 6134 |
|
|
#define TFLG1_C3F _TFLG1.Bits.C3F
|
| 6135 |
|
|
#define TFLG1_C4F _TFLG1.Bits.C4F
|
| 6136 |
|
|
#define TFLG1_C5F _TFLG1.Bits.C5F
|
| 6137 |
|
|
#define TFLG1_C6F _TFLG1.Bits.C6F
|
| 6138 |
|
|
#define TFLG1_C7F _TFLG1.Bits.C7F
|
| 6139 |
|
|
|
| 6140 |
|
|
|
| 6141 |
|
|
/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/
|
| 6142 |
|
|
typedef union {
|
| 6143 |
|
|
byte Byte;
|
| 6144 |
|
|
struct {
|
| 6145 |
|
|
byte :1;
|
| 6146 |
|
|
byte :1;
|
| 6147 |
|
|
byte :1;
|
| 6148 |
|
|
byte :1;
|
| 6149 |
|
|
byte :1;
|
| 6150 |
|
|
byte :1;
|
| 6151 |
|
|
byte :1;
|
| 6152 |
|
|
byte TOF :1; /* Timer Overflow Flag */
|
| 6153 |
|
|
} Bits;
|
| 6154 |
|
|
} TFLG2STR;
|
| 6155 |
|
|
extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F);
|
| 6156 |
|
|
#define TFLG2 _TFLG2.Byte
|
| 6157 |
|
|
#define TFLG2_TOF _TFLG2.Bits.TOF
|
| 6158 |
|
|
|
| 6159 |
|
|
|
| 6160 |
|
|
/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/
|
| 6161 |
|
|
typedef union {
|
| 6162 |
|
|
byte Byte;
|
| 6163 |
|
|
struct {
|
| 6164 |
|
|
byte PAI :1; /* Pulse Accumulator Input Interrupt enable */
|
| 6165 |
|
|
byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */
|
| 6166 |
|
|
byte CLK0 :1; /* Clock Select Bit 0 */
|
| 6167 |
|
|
byte CLK1 :1; /* Clock Select Bit 1 */
|
| 6168 |
|
|
byte PEDGE :1; /* Pulse Accumulator Edge Control */
|
| 6169 |
|
|
byte PAMOD :1; /* Pulse Accumulator Mode */
|
| 6170 |
|
|
byte PAEN :1; /* Pulse Accumulator A System Enable */
|
| 6171 |
|
|
byte :1;
|
| 6172 |
|
|
} Bits;
|
| 6173 |
|
|
struct {
|
| 6174 |
|
|
byte :1;
|
| 6175 |
|
|
byte :1;
|
| 6176 |
|
|
byte grpCLK :2;
|
| 6177 |
|
|
byte :1;
|
| 6178 |
|
|
byte :1;
|
| 6179 |
|
|
byte :1;
|
| 6180 |
|
|
byte :1;
|
| 6181 |
|
|
} MergedBits;
|
| 6182 |
|
|
} PACTLSTR;
|
| 6183 |
|
|
extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060);
|
| 6184 |
|
|
#define PACTL _PACTL.Byte
|
| 6185 |
|
|
#define PACTL_PAI _PACTL.Bits.PAI
|
| 6186 |
|
|
#define PACTL_PAOVI _PACTL.Bits.PAOVI
|
| 6187 |
|
|
#define PACTL_CLK0 _PACTL.Bits.CLK0
|
| 6188 |
|
|
#define PACTL_CLK1 _PACTL.Bits.CLK1
|
| 6189 |
|
|
#define PACTL_PEDGE _PACTL.Bits.PEDGE
|
| 6190 |
|
|
#define PACTL_PAMOD _PACTL.Bits.PAMOD
|
| 6191 |
|
|
#define PACTL_PAEN _PACTL.Bits.PAEN
|
| 6192 |
|
|
#define PACTL_CLK _PACTL.MergedBits.grpCLK
|
| 6193 |
|
|
|
| 6194 |
|
|
|
| 6195 |
|
|
/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/
|
| 6196 |
|
|
typedef union {
|
| 6197 |
|
|
byte Byte;
|
| 6198 |
|
|
struct {
|
| 6199 |
|
|
byte PAIF :1; /* Pulse Accumulator Input edge Flag */
|
| 6200 |
|
|
byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */
|
| 6201 |
|
|
byte :1;
|
| 6202 |
|
|
byte :1;
|
| 6203 |
|
|
byte :1;
|
| 6204 |
|
|
byte :1;
|
| 6205 |
|
|
byte :1;
|
| 6206 |
|
|
byte :1;
|
| 6207 |
|
|
} Bits;
|
| 6208 |
|
|
} PAFLGSTR;
|
| 6209 |
|
|
extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061);
|
| 6210 |
|
|
#define PAFLG _PAFLG.Byte
|
| 6211 |
|
|
#define PAFLG_PAIF _PAFLG.Bits.PAIF
|
| 6212 |
|
|
#define PAFLG_PAOVF _PAFLG.Bits.PAOVF
|
| 6213 |
|
|
|
| 6214 |
|
|
|
| 6215 |
|
|
/*** MCCTL - Modulus Down Counter underflow; 0x00000066 ***/
|
| 6216 |
|
|
typedef union {
|
| 6217 |
|
|
byte Byte;
|
| 6218 |
|
|
struct {
|
| 6219 |
|
|
byte MCPR0 :1; /* Modulus Counter Prescaler select 0 */
|
| 6220 |
|
|
byte MCPR1 :1; /* Modulus Counter Prescaler select 1 */
|
| 6221 |
|
|
byte MCEN :1; /* Modulus Down-Counter Enable */
|
| 6222 |
|
|
byte FLMC :1; /* Force Load Register into the Modulus Counter Count Register */
|
| 6223 |
|
|
byte ICLAT :1; /* Input Capture Force Latch Action */
|
| 6224 |
|
|
byte RDMCL :1; /* Read Modulus Down-Counter Load */
|
| 6225 |
|
|
byte MODMC :1; /* Modulus Mode Enable */
|
| 6226 |
|
|
byte MCZI :1; /* Modulus Counter Underflow Interrupt Enable */
|
| 6227 |
|
|
} Bits;
|
| 6228 |
|
|
struct {
|
| 6229 |
|
|
byte grpMCPR :2;
|
| 6230 |
|
|
byte :1;
|
| 6231 |
|
|
byte :1;
|
| 6232 |
|
|
byte :1;
|
| 6233 |
|
|
byte :1;
|
| 6234 |
|
|
byte :1;
|
| 6235 |
|
|
byte :1;
|
| 6236 |
|
|
} MergedBits;
|
| 6237 |
|
|
} MCCTLSTR;
|
| 6238 |
|
|
extern volatile MCCTLSTR _MCCTL @(REG_BASE + 0x00000066);
|
| 6239 |
|
|
#define MCCTL _MCCTL.Byte
|
| 6240 |
|
|
#define MCCTL_MCPR0 _MCCTL.Bits.MCPR0
|
| 6241 |
|
|
#define MCCTL_MCPR1 _MCCTL.Bits.MCPR1
|
| 6242 |
|
|
#define MCCTL_MCEN _MCCTL.Bits.MCEN
|
| 6243 |
|
|
#define MCCTL_FLMC _MCCTL.Bits.FLMC
|
| 6244 |
|
|
#define MCCTL_ICLAT _MCCTL.Bits.ICLAT
|
| 6245 |
|
|
#define MCCTL_RDMCL _MCCTL.Bits.RDMCL
|
| 6246 |
|
|
#define MCCTL_MODMC _MCCTL.Bits.MODMC
|
| 6247 |
|
|
#define MCCTL_MCZI _MCCTL.Bits.MCZI
|
| 6248 |
|
|
#define MCCTL_MCPR _MCCTL.MergedBits.grpMCPR
|
| 6249 |
|
|
|
| 6250 |
|
|
|
| 6251 |
|
|
/*** MCFLG - 16-Bit Modulus Down Counter Flag Register; 0x00000067 ***/
|
| 6252 |
|
|
typedef union {
|
| 6253 |
|
|
byte Byte;
|
| 6254 |
|
|
struct {
|
| 6255 |
|
|
byte POLF0 :1; /* First Input Capture Polarity Status 0 */
|
| 6256 |
|
|
byte POLF1 :1; /* First Input Capture Polarity Status 1 */
|
| 6257 |
|
|
byte POLF2 :1; /* First Input Capture Polarity Status 2 */
|
| 6258 |
|
|
byte POLF3 :1; /* First Input Capture Polarity Status 3 */
|
| 6259 |
|
|
byte :1;
|
| 6260 |
|
|
byte :1;
|
| 6261 |
|
|
byte :1;
|
| 6262 |
|
|
byte MCZF :1; /* Modulus Counter Underflow Flag */
|
| 6263 |
|
|
} Bits;
|
| 6264 |
|
|
struct {
|
| 6265 |
|
|
byte grpPOLF :4;
|
| 6266 |
|
|
byte :1;
|
| 6267 |
|
|
byte :1;
|
| 6268 |
|
|
byte :1;
|
| 6269 |
|
|
byte :1;
|
| 6270 |
|
|
} MergedBits;
|
| 6271 |
|
|
} MCFLGSTR;
|
| 6272 |
|
|
extern volatile MCFLGSTR _MCFLG @(REG_BASE + 0x00000067);
|
| 6273 |
|
|
#define MCFLG _MCFLG.Byte
|
| 6274 |
|
|
#define MCFLG_POLF0 _MCFLG.Bits.POLF0
|
| 6275 |
|
|
#define MCFLG_POLF1 _MCFLG.Bits.POLF1
|
| 6276 |
|
|
#define MCFLG_POLF2 _MCFLG.Bits.POLF2
|
| 6277 |
|
|
#define MCFLG_POLF3 _MCFLG.Bits.POLF3
|
| 6278 |
|
|
#define MCFLG_MCZF _MCFLG.Bits.MCZF
|
| 6279 |
|
|
#define MCFLG_POLF _MCFLG.MergedBits.grpPOLF
|
| 6280 |
|
|
|
| 6281 |
|
|
|
| 6282 |
|
|
/*** ICPAR - Input Control Pulse Accumulator Register; 0x00000068 ***/
|
| 6283 |
|
|
typedef union {
|
| 6284 |
|
|
byte Byte;
|
| 6285 |
|
|
struct {
|
| 6286 |
|
|
byte PA0EN :1; /* 8-Bit Pulse Accumulator 0 Enable */
|
| 6287 |
|
|
byte PA1EN :1; /* 8-Bit Pulse Accumulator 1 Enable */
|
| 6288 |
|
|
byte PA2EN :1; /* 8-Bit Pulse Accumulator 2 Enable */
|
| 6289 |
|
|
byte PA3EN :1; /* 8-Bit Pulse Accumulator 3 Enable */
|
| 6290 |
|
|
byte :1;
|
| 6291 |
|
|
byte :1;
|
| 6292 |
|
|
byte :1;
|
| 6293 |
|
|
byte :1;
|
| 6294 |
|
|
} Bits;
|
| 6295 |
|
|
} ICPARSTR;
|
| 6296 |
|
|
extern volatile ICPARSTR _ICPAR @(REG_BASE + 0x00000068);
|
| 6297 |
|
|
#define ICPAR _ICPAR.Byte
|
| 6298 |
|
|
#define ICPAR_PA0EN _ICPAR.Bits.PA0EN
|
| 6299 |
|
|
#define ICPAR_PA1EN _ICPAR.Bits.PA1EN
|
| 6300 |
|
|
#define ICPAR_PA2EN _ICPAR.Bits.PA2EN
|
| 6301 |
|
|
#define ICPAR_PA3EN _ICPAR.Bits.PA3EN
|
| 6302 |
|
|
|
| 6303 |
|
|
|
| 6304 |
|
|
/*** DLYCT - Delay Counter Control Register; 0x00000069 ***/
|
| 6305 |
|
|
typedef union {
|
| 6306 |
|
|
byte Byte;
|
| 6307 |
|
|
struct {
|
| 6308 |
|
|
byte DLY0 :1; /* Delay Counter Select 0 */
|
| 6309 |
|
|
byte DLY1 :1; /* Delay Counter Select 1 */
|
| 6310 |
|
|
byte :1;
|
| 6311 |
|
|
byte :1;
|
| 6312 |
|
|
byte :1;
|
| 6313 |
|
|
byte :1;
|
| 6314 |
|
|
byte :1;
|
| 6315 |
|
|
byte :1;
|
| 6316 |
|
|
} Bits;
|
| 6317 |
|
|
struct {
|
| 6318 |
|
|
byte grpDLY :2;
|
| 6319 |
|
|
byte :1;
|
| 6320 |
|
|
byte :1;
|
| 6321 |
|
|
byte :1;
|
| 6322 |
|
|
byte :1;
|
| 6323 |
|
|
byte :1;
|
| 6324 |
|
|
byte :1;
|
| 6325 |
|
|
} MergedBits;
|
| 6326 |
|
|
} DLYCTSTR;
|
| 6327 |
|
|
extern volatile DLYCTSTR _DLYCT @(REG_BASE + 0x00000069);
|
| 6328 |
|
|
#define DLYCT _DLYCT.Byte
|
| 6329 |
|
|
#define DLYCT_DLY0 _DLYCT.Bits.DLY0
|
| 6330 |
|
|
#define DLYCT_DLY1 _DLYCT.Bits.DLY1
|
| 6331 |
|
|
#define DLYCT_DLY _DLYCT.MergedBits.grpDLY
|
| 6332 |
|
|
|
| 6333 |
|
|
|
| 6334 |
|
|
/*** ICOVW - Input Control Overwrite Register; 0x0000006A ***/
|
| 6335 |
|
|
typedef union {
|
| 6336 |
|
|
byte Byte;
|
| 6337 |
|
|
struct {
|
| 6338 |
|
|
byte NOVW0 :1; /* No Input Capture Overwrite 0 */
|
| 6339 |
|
|
byte NOVW1 :1; /* No Input Capture Overwrite 1 */
|
| 6340 |
|
|
byte NOVW2 :1; /* No Input Capture Overwrite 2 */
|
| 6341 |
|
|
byte NOVW3 :1; /* No Input Capture Overwrite 3 */
|
| 6342 |
|
|
byte NOVW4 :1; /* No Input Capture Overwrite 4 */
|
| 6343 |
|
|
byte NOVW5 :1; /* No Input Capture Overwrite 5 */
|
| 6344 |
|
|
byte NOVW6 :1; /* No Input Capture Overwrite 6 */
|
| 6345 |
|
|
byte NOVW7 :1; /* No Input Capture Overwrite 7 */
|
| 6346 |
|
|
} Bits;
|
| 6347 |
|
|
struct {
|
| 6348 |
|
|
byte grpNOVW :8;
|
| 6349 |
|
|
} MergedBits;
|
| 6350 |
|
|
} ICOVWSTR;
|
| 6351 |
|
|
extern volatile ICOVWSTR _ICOVW @(REG_BASE + 0x0000006A);
|
| 6352 |
|
|
#define ICOVW _ICOVW.Byte
|
| 6353 |
|
|
#define ICOVW_NOVW0 _ICOVW.Bits.NOVW0
|
| 6354 |
|
|
#define ICOVW_NOVW1 _ICOVW.Bits.NOVW1
|
| 6355 |
|
|
#define ICOVW_NOVW2 _ICOVW.Bits.NOVW2
|
| 6356 |
|
|
#define ICOVW_NOVW3 _ICOVW.Bits.NOVW3
|
| 6357 |
|
|
#define ICOVW_NOVW4 _ICOVW.Bits.NOVW4
|
| 6358 |
|
|
#define ICOVW_NOVW5 _ICOVW.Bits.NOVW5
|
| 6359 |
|
|
#define ICOVW_NOVW6 _ICOVW.Bits.NOVW6
|
| 6360 |
|
|
#define ICOVW_NOVW7 _ICOVW.Bits.NOVW7
|
| 6361 |
|
|
#define ICOVW_NOVW _ICOVW.MergedBits.grpNOVW
|
| 6362 |
|
|
|
| 6363 |
|
|
|
| 6364 |
|
|
/*** ICSYS - Input Control System Control Register; 0x0000006B ***/
|
| 6365 |
|
|
typedef union {
|
| 6366 |
|
|
byte Byte;
|
| 6367 |
|
|
struct {
|
| 6368 |
|
|
byte LATQ :1; /* Input Control Latch or Queue Mode Enable */
|
| 6369 |
|
|
byte BUFEN :1; /* IC Buffer Enable */
|
| 6370 |
|
|
byte PACMX :1; /* 8-Bit Pulse Accumulators Maximum Count */
|
| 6371 |
|
|
byte TFMOD :1; /* Timer Flag-setting Mode */
|
| 6372 |
|
|
byte SH04 :1; /* Share Input action of Input Capture Channels 0 and 4 */
|
| 6373 |
|
|
byte SH15 :1; /* Share Input action of Input Capture Channels 1 and 5 */
|
| 6374 |
|
|
byte SH26 :1; /* Share Input action of Input Capture Channels 2 and 6 */
|
| 6375 |
|
|
byte SH37 :1; /* Share Input action of Input Capture Channels 3 and 7 */
|
| 6376 |
|
|
} Bits;
|
| 6377 |
|
|
} ICSYSSTR;
|
| 6378 |
|
|
extern volatile ICSYSSTR _ICSYS @(REG_BASE + 0x0000006B);
|
| 6379 |
|
|
#define ICSYS _ICSYS.Byte
|
| 6380 |
|
|
#define ICSYS_LATQ _ICSYS.Bits.LATQ
|
| 6381 |
|
|
#define ICSYS_BUFEN _ICSYS.Bits.BUFEN
|
| 6382 |
|
|
#define ICSYS_PACMX _ICSYS.Bits.PACMX
|
| 6383 |
|
|
#define ICSYS_TFMOD _ICSYS.Bits.TFMOD
|
| 6384 |
|
|
#define ICSYS_SH04 _ICSYS.Bits.SH04
|
| 6385 |
|
|
#define ICSYS_SH15 _ICSYS.Bits.SH15
|
| 6386 |
|
|
#define ICSYS_SH26 _ICSYS.Bits.SH26
|
| 6387 |
|
|
#define ICSYS_SH37 _ICSYS.Bits.SH37
|
| 6388 |
|
|
|
| 6389 |
|
|
|
| 6390 |
|
|
/*** TIMTST - Timer Test Register; 0x0000006D ***/
|
| 6391 |
|
|
typedef union {
|
| 6392 |
|
|
byte Byte;
|
| 6393 |
|
|
struct {
|
| 6394 |
|
|
byte :1;
|
| 6395 |
|
|
byte TCBYP :1; /* Main Timer Divider Chain Bypass */
|
| 6396 |
|
|
byte :1;
|
| 6397 |
|
|
byte :1;
|
| 6398 |
|
|
byte :1;
|
| 6399 |
|
|
byte :1;
|
| 6400 |
|
|
byte :1;
|
| 6401 |
|
|
byte :1;
|
| 6402 |
|
|
} Bits;
|
| 6403 |
|
|
} TIMTSTSTR;
|
| 6404 |
|
|
extern volatile TIMTSTSTR _TIMTST @(REG_BASE + 0x0000006D);
|
| 6405 |
|
|
#define TIMTST _TIMTST.Byte
|
| 6406 |
|
|
#define TIMTST_TCBYP _TIMTST.Bits.TCBYP
|
| 6407 |
|
|
|
| 6408 |
|
|
|
| 6409 |
|
|
/*** PBCTL - 16-Bit Pulse Accumulator B Control Register; 0x00000070 ***/
|
| 6410 |
|
|
typedef union {
|
| 6411 |
|
|
byte Byte;
|
| 6412 |
|
|
struct {
|
| 6413 |
|
|
byte :1;
|
| 6414 |
|
|
byte PBOVI :1; /* Pulse Accumulator B Overflow Interrupt enable */
|
| 6415 |
|
|
byte :1;
|
| 6416 |
|
|
byte :1;
|
| 6417 |
|
|
byte :1;
|
| 6418 |
|
|
byte :1;
|
| 6419 |
|
|
byte PBEN :1; /* Pulse Accumulator B System Enable */
|
| 6420 |
|
|
byte :1;
|
| 6421 |
|
|
} Bits;
|
| 6422 |
|
|
} PBCTLSTR;
|
| 6423 |
|
|
extern volatile PBCTLSTR _PBCTL @(REG_BASE + 0x00000070);
|
| 6424 |
|
|
#define PBCTL _PBCTL.Byte
|
| 6425 |
|
|
#define PBCTL_PBOVI _PBCTL.Bits.PBOVI
|
| 6426 |
|
|
#define PBCTL_PBEN _PBCTL.Bits.PBEN
|
| 6427 |
|
|
|
| 6428 |
|
|
|
| 6429 |
|
|
/*** PBFLG - Pulse Accumulator B Flag Register; 0x00000071 ***/
|
| 6430 |
|
|
typedef union {
|
| 6431 |
|
|
byte Byte;
|
| 6432 |
|
|
struct {
|
| 6433 |
|
|
byte :1;
|
| 6434 |
|
|
byte PBOVF :1; /* Pulse Accumulator B Overflow Flag */
|
| 6435 |
|
|
byte :1;
|
| 6436 |
|
|
byte :1;
|
| 6437 |
|
|
byte :1;
|
| 6438 |
|
|
byte :1;
|
| 6439 |
|
|
byte :1;
|
| 6440 |
|
|
byte :1;
|
| 6441 |
|
|
} Bits;
|
| 6442 |
|
|
} PBFLGSTR;
|
| 6443 |
|
|
extern volatile PBFLGSTR _PBFLG @(REG_BASE + 0x00000071);
|
| 6444 |
|
|
#define PBFLG _PBFLG.Byte
|
| 6445 |
|
|
#define PBFLG_PBOVF _PBFLG.Bits.PBOVF
|
| 6446 |
|
|
|
| 6447 |
|
|
|
| 6448 |
|
|
/*** ATD0STAT0 - ATD 0 Status Register 0; 0x00000086 ***/
|
| 6449 |
|
|
typedef union {
|
| 6450 |
|
|
byte Byte;
|
| 6451 |
|
|
struct {
|
| 6452 |
|
|
byte CC0 :1; /* Conversion Counter 0 */
|
| 6453 |
|
|
byte CC1 :1; /* Conversion Counter 1 */
|
| 6454 |
|
|
byte CC2 :1; /* Conversion Counter 2 */
|
| 6455 |
|
|
byte :1;
|
| 6456 |
|
|
byte FIFOR :1; /* FIFO Over Run Flag */
|
| 6457 |
|
|
byte ETORF :1; /* External Trigger Overrun Flag */
|
| 6458 |
|
|
byte :1;
|
| 6459 |
|
|
byte SCF :1; /* Sequence Complete Flag */
|
| 6460 |
|
|
} Bits;
|
| 6461 |
|
|
struct {
|
| 6462 |
|
|
byte grpCC :3;
|
| 6463 |
|
|
byte :1;
|
| 6464 |
|
|
byte :1;
|
| 6465 |
|
|
byte :1;
|
| 6466 |
|
|
byte :1;
|
| 6467 |
|
|
byte :1;
|
| 6468 |
|
|
} MergedBits;
|
| 6469 |
|
|
} ATD0STAT0STR;
|
| 6470 |
|
|
extern volatile ATD0STAT0STR _ATD0STAT0 @(REG_BASE + 0x00000086);
|
| 6471 |
|
|
#define ATD0STAT0 _ATD0STAT0.Byte
|
| 6472 |
|
|
#define ATD0STAT0_CC0 _ATD0STAT0.Bits.CC0
|
| 6473 |
|
|
#define ATD0STAT0_CC1 _ATD0STAT0.Bits.CC1
|
| 6474 |
|
|
#define ATD0STAT0_CC2 _ATD0STAT0.Bits.CC2
|
| 6475 |
|
|
#define ATD0STAT0_FIFOR _ATD0STAT0.Bits.FIFOR
|
| 6476 |
|
|
#define ATD0STAT0_ETORF _ATD0STAT0.Bits.ETORF
|
| 6477 |
|
|
#define ATD0STAT0_SCF _ATD0STAT0.Bits.SCF
|
| 6478 |
|
|
#define ATD0STAT0_CC _ATD0STAT0.MergedBits.grpCC
|
| 6479 |
|
|
|
| 6480 |
|
|
|
| 6481 |
|
|
/*** ATD0STAT1 - ATD 0 Status Register 1; 0x0000008B ***/
|
| 6482 |
|
|
typedef union {
|
| 6483 |
|
|
byte Byte;
|
| 6484 |
|
|
struct {
|
| 6485 |
|
|
byte CCF0 :1; /* Conversion Complete Flag 0 */
|
| 6486 |
|
|
byte CCF1 :1; /* Conversion Complete Flag 1 */
|
| 6487 |
|
|
byte CCF2 :1; /* Conversion Complete Flag 2 */
|
| 6488 |
|
|
byte CCF3 :1; /* Conversion Complete Flag 3 */
|
| 6489 |
|
|
byte CCF4 :1; /* Conversion Complete Flag 4 */
|
| 6490 |
|
|
byte CCF5 :1; /* Conversion Complete Flag 5 */
|
| 6491 |
|
|
byte CCF6 :1; /* Conversion Complete Flag 6 */
|
| 6492 |
|
|
byte CCF7 :1; /* Conversion Complete Flag 7 */
|
| 6493 |
|
|
} Bits;
|
| 6494 |
|
|
struct {
|
| 6495 |
|
|
byte grpCCF :8;
|
| 6496 |
|
|
} MergedBits;
|
| 6497 |
|
|
} ATD0STAT1STR;
|
| 6498 |
|
|
extern volatile ATD0STAT1STR _ATD0STAT1 @(REG_BASE + 0x0000008B);
|
| 6499 |
|
|
#define ATD0STAT1 _ATD0STAT1.Byte
|
| 6500 |
|
|
#define ATD0STAT1_CCF0 _ATD0STAT1.Bits.CCF0
|
| 6501 |
|
|
#define ATD0STAT1_CCF1 _ATD0STAT1.Bits.CCF1
|
| 6502 |
|
|
#define ATD0STAT1_CCF2 _ATD0STAT1.Bits.CCF2
|
| 6503 |
|
|
#define ATD0STAT1_CCF3 _ATD0STAT1.Bits.CCF3
|
| 6504 |
|
|
#define ATD0STAT1_CCF4 _ATD0STAT1.Bits.CCF4
|
| 6505 |
|
|
#define ATD0STAT1_CCF5 _ATD0STAT1.Bits.CCF5
|
| 6506 |
|
|
#define ATD0STAT1_CCF6 _ATD0STAT1.Bits.CCF6
|
| 6507 |
|
|
#define ATD0STAT1_CCF7 _ATD0STAT1.Bits.CCF7
|
| 6508 |
|
|
#define ATD0STAT1_CCF _ATD0STAT1.MergedBits.grpCCF
|
| 6509 |
|
|
|
| 6510 |
|
|
|
| 6511 |
|
|
/*** ATD0DIEN - ATD 0 Input Enable Mask Register; 0x0000008D ***/
|
| 6512 |
|
|
typedef union {
|
| 6513 |
|
|
byte Byte;
|
| 6514 |
|
|
struct {
|
| 6515 |
|
|
byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */
|
| 6516 |
|
|
byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */
|
| 6517 |
|
|
byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */
|
| 6518 |
|
|
byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */
|
| 6519 |
|
|
byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */
|
| 6520 |
|
|
byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */
|
| 6521 |
|
|
byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */
|
| 6522 |
|
|
byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */
|
| 6523 |
|
|
} Bits;
|
| 6524 |
|
|
struct {
|
| 6525 |
|
|
byte grpBIT :8;
|
| 6526 |
|
|
} MergedBits;
|
| 6527 |
|
|
} ATD0DIENSTR;
|
| 6528 |
|
|
extern volatile ATD0DIENSTR _ATD0DIEN @(REG_BASE + 0x0000008D);
|
| 6529 |
|
|
#define ATD0DIEN _ATD0DIEN.Byte
|
| 6530 |
|
|
#define ATD0DIEN_BIT0 _ATD0DIEN.Bits.BIT0
|
| 6531 |
|
|
#define ATD0DIEN_BIT1 _ATD0DIEN.Bits.BIT1
|
| 6532 |
|
|
#define ATD0DIEN_BIT2 _ATD0DIEN.Bits.BIT2
|
| 6533 |
|
|
#define ATD0DIEN_BIT3 _ATD0DIEN.Bits.BIT3
|
| 6534 |
|
|
#define ATD0DIEN_BIT4 _ATD0DIEN.Bits.BIT4
|
| 6535 |
|
|
#define ATD0DIEN_BIT5 _ATD0DIEN.Bits.BIT5
|
| 6536 |
|
|
#define ATD0DIEN_BIT6 _ATD0DIEN.Bits.BIT6
|
| 6537 |
|
|
#define ATD0DIEN_BIT7 _ATD0DIEN.Bits.BIT7
|
| 6538 |
|
|
#define ATD0DIEN_BIT _ATD0DIEN.MergedBits.grpBIT
|
| 6539 |
|
|
|
| 6540 |
|
|
|
| 6541 |
|
|
/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/
|
| 6542 |
|
|
typedef union {
|
| 6543 |
|
|
byte Byte;
|
| 6544 |
|
|
struct {
|
| 6545 |
|
|
byte BIT0 :1; /* AN0 */
|
| 6546 |
|
|
byte BIT1 :1; /* AN1 */
|
| 6547 |
|
|
byte BIT2 :1; /* AN2 */
|
| 6548 |
|
|
byte BIT3 :1; /* AN3 */
|
| 6549 |
|
|
byte BIT4 :1; /* AN4 */
|
| 6550 |
|
|
byte BIT5 :1; /* AN5 */
|
| 6551 |
|
|
byte BIT6 :1; /* AN6 */
|
| 6552 |
|
|
byte BIT7 :1; /* AN7 */
|
| 6553 |
|
|
} Bits;
|
| 6554 |
|
|
struct {
|
| 6555 |
|
|
byte grpBIT :8;
|
| 6556 |
|
|
} MergedBits;
|
| 6557 |
|
|
} PORTAD0STR;
|
| 6558 |
|
|
extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F);
|
| 6559 |
|
|
#define PORTAD0 _PORTAD0.Byte
|
| 6560 |
|
|
#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0
|
| 6561 |
|
|
#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1
|
| 6562 |
|
|
#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2
|
| 6563 |
|
|
#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3
|
| 6564 |
|
|
#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4
|
| 6565 |
|
|
#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5
|
| 6566 |
|
|
#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6
|
| 6567 |
|
|
#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7
|
| 6568 |
|
|
#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT
|
| 6569 |
|
|
|
| 6570 |
|
|
|
| 6571 |
|
|
/*** PWME - PWM Enable Register; 0x000000A0 ***/
|
| 6572 |
|
|
typedef union {
|
| 6573 |
|
|
byte Byte;
|
| 6574 |
|
|
struct {
|
| 6575 |
|
|
byte PWME0 :1; /* Pulse Width Channel 0 Enable */
|
| 6576 |
|
|
byte PWME1 :1; /* Pulse Width Channel 1 Enable */
|
| 6577 |
|
|
byte PWME2 :1; /* Pulse Width Channel 2 Enable */
|
| 6578 |
|
|
byte PWME3 :1; /* Pulse Width Channel 3 Enable */
|
| 6579 |
|
|
byte PWME4 :1; /* Pulse Width Channel 4 Enable */
|
| 6580 |
|
|
byte PWME5 :1; /* Pulse Width Channel 5 Enable */
|
| 6581 |
|
|
byte PWME6 :1; /* Pulse Width Channel 6 Enable */
|
| 6582 |
|
|
byte PWME7 :1; /* Pulse Width Channel 7 Enable */
|
| 6583 |
|
|
} Bits;
|
| 6584 |
|
|
struct {
|
| 6585 |
|
|
byte grpPWME :8;
|
| 6586 |
|
|
} MergedBits;
|
| 6587 |
|
|
} PWMESTR;
|
| 6588 |
|
|
extern volatile PWMESTR _PWME @(REG_BASE + 0x000000A0);
|
| 6589 |
|
|
#define PWME _PWME.Byte
|
| 6590 |
|
|
#define PWME_PWME0 _PWME.Bits.PWME0
|
| 6591 |
|
|
#define PWME_PWME1 _PWME.Bits.PWME1
|
| 6592 |
|
|
#define PWME_PWME2 _PWME.Bits.PWME2
|
| 6593 |
|
|
#define PWME_PWME3 _PWME.Bits.PWME3
|
| 6594 |
|
|
#define PWME_PWME4 _PWME.Bits.PWME4
|
| 6595 |
|
|
#define PWME_PWME5 _PWME.Bits.PWME5
|
| 6596 |
|
|
#define PWME_PWME6 _PWME.Bits.PWME6
|
| 6597 |
|
|
#define PWME_PWME7 _PWME.Bits.PWME7
|
| 6598 |
|
|
#define PWME_PWME _PWME.MergedBits.grpPWME
|
| 6599 |
|
|
|
| 6600 |
|
|
|
| 6601 |
|
|
/*** PWMPOL - PWM Polarity Register; 0x000000A1 ***/
|
| 6602 |
|
|
typedef union {
|
| 6603 |
|
|
byte Byte;
|
| 6604 |
|
|
struct {
|
| 6605 |
|
|
byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */
|
| 6606 |
|
|
byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */
|
| 6607 |
|
|
byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */
|
| 6608 |
|
|
byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */
|
| 6609 |
|
|
byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */
|
| 6610 |
|
|
byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */
|
| 6611 |
|
|
byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */
|
| 6612 |
|
|
byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */
|
| 6613 |
|
|
} Bits;
|
| 6614 |
|
|
struct {
|
| 6615 |
|
|
byte grpPPOL :8;
|
| 6616 |
|
|
} MergedBits;
|
| 6617 |
|
|
} PWMPOLSTR;
|
| 6618 |
|
|
extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000A1);
|
| 6619 |
|
|
#define PWMPOL _PWMPOL.Byte
|
| 6620 |
|
|
#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0
|
| 6621 |
|
|
#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1
|
| 6622 |
|
|
#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2
|
| 6623 |
|
|
#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3
|
| 6624 |
|
|
#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4
|
| 6625 |
|
|
#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5
|
| 6626 |
|
|
#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6
|
| 6627 |
|
|
#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7
|
| 6628 |
|
|
#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL
|
| 6629 |
|
|
|
| 6630 |
|
|
|
| 6631 |
|
|
/*** PWMCLK - PWM Clock Select Register; 0x000000A2 ***/
|
| 6632 |
|
|
typedef union {
|
| 6633 |
|
|
byte Byte;
|
| 6634 |
|
|
struct {
|
| 6635 |
|
|
byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */
|
| 6636 |
|
|
byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */
|
| 6637 |
|
|
byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */
|
| 6638 |
|
|
byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */
|
| 6639 |
|
|
byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */
|
| 6640 |
|
|
byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */
|
| 6641 |
|
|
byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */
|
| 6642 |
|
|
byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */
|
| 6643 |
|
|
} Bits;
|
| 6644 |
|
|
struct {
|
| 6645 |
|
|
byte grpPCLK :8;
|
| 6646 |
|
|
} MergedBits;
|
| 6647 |
|
|
} PWMCLKSTR;
|
| 6648 |
|
|
extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000A2);
|
| 6649 |
|
|
#define PWMCLK _PWMCLK.Byte
|
| 6650 |
|
|
#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0
|
| 6651 |
|
|
#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1
|
| 6652 |
|
|
#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2
|
| 6653 |
|
|
#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3
|
| 6654 |
|
|
#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4
|
| 6655 |
|
|
#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5
|
| 6656 |
|
|
#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6
|
| 6657 |
|
|
#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7
|
| 6658 |
|
|
#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK
|
| 6659 |
|
|
|
| 6660 |
|
|
|
| 6661 |
|
|
/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000A3 ***/
|
| 6662 |
|
|
typedef union {
|
| 6663 |
|
|
byte Byte;
|
| 6664 |
|
|
struct {
|
| 6665 |
|
|
byte PCKA0 :1; /* Prescaler Select for Clock A 0 */
|
| 6666 |
|
|
byte PCKA1 :1; /* Prescaler Select for Clock A 1 */
|
| 6667 |
|
|
byte PCKA2 :1; /* Prescaler Select for Clock A 2 */
|
| 6668 |
|
|
byte :1;
|
| 6669 |
|
|
byte PCKB0 :1; /* Prescaler Select for Clock B 0 */
|
| 6670 |
|
|
byte PCKB1 :1; /* Prescaler Select for Clock B 1 */
|
| 6671 |
|
|
byte PCKB2 :1; /* Prescaler Select for Clock B 2 */
|
| 6672 |
|
|
byte :1;
|
| 6673 |
|
|
} Bits;
|
| 6674 |
|
|
struct {
|
| 6675 |
|
|
byte grpPCKA :3;
|
| 6676 |
|
|
byte :1;
|
| 6677 |
|
|
byte grpPCKB :3;
|
| 6678 |
|
|
byte :1;
|
| 6679 |
|
|
} MergedBits;
|
| 6680 |
|
|
} PWMPRCLKSTR;
|
| 6681 |
|
|
extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000A3);
|
| 6682 |
|
|
#define PWMPRCLK _PWMPRCLK.Byte
|
| 6683 |
|
|
#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0
|
| 6684 |
|
|
#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1
|
| 6685 |
|
|
#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2
|
| 6686 |
|
|
#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0
|
| 6687 |
|
|
#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1
|
| 6688 |
|
|
#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2
|
| 6689 |
|
|
#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA
|
| 6690 |
|
|
#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB
|
| 6691 |
|
|
|
| 6692 |
|
|
|
| 6693 |
|
|
/*** PWMCAE - PWM Center Align Enable Register; 0x000000A4 ***/
|
| 6694 |
|
|
typedef union {
|
| 6695 |
|
|
byte Byte;
|
| 6696 |
|
|
struct {
|
| 6697 |
|
|
byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */
|
| 6698 |
|
|
byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */
|
| 6699 |
|
|
byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */
|
| 6700 |
|
|
byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */
|
| 6701 |
|
|
byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */
|
| 6702 |
|
|
byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */
|
| 6703 |
|
|
byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */
|
| 6704 |
|
|
byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */
|
| 6705 |
|
|
} Bits;
|
| 6706 |
|
|
struct {
|
| 6707 |
|
|
byte grpCAE :8;
|
| 6708 |
|
|
} MergedBits;
|
| 6709 |
|
|
} PWMCAESTR;
|
| 6710 |
|
|
extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000A4);
|
| 6711 |
|
|
#define PWMCAE _PWMCAE.Byte
|
| 6712 |
|
|
#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0
|
| 6713 |
|
|
#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1
|
| 6714 |
|
|
#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2
|
| 6715 |
|
|
#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3
|
| 6716 |
|
|
#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4
|
| 6717 |
|
|
#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5
|
| 6718 |
|
|
#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6
|
| 6719 |
|
|
#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7
|
| 6720 |
|
|
#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE
|
| 6721 |
|
|
|
| 6722 |
|
|
|
| 6723 |
|
|
/*** PWMCTL - PWM Control Register; 0x000000A5 ***/
|
| 6724 |
|
|
typedef union {
|
| 6725 |
|
|
byte Byte;
|
| 6726 |
|
|
struct {
|
| 6727 |
|
|
byte :1;
|
| 6728 |
|
|
byte :1;
|
| 6729 |
|
|
byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */
|
| 6730 |
|
|
byte PSWAI :1; /* PWM Stops in Wait Mode */
|
| 6731 |
|
|
byte CON01 :1; /* Concatenate channels 0 and 1 */
|
| 6732 |
|
|
byte CON23 :1; /* Concatenate channels 2 and 3 */
|
| 6733 |
|
|
byte CON45 :1; /* Concatenate channels 4 and 5 */
|
| 6734 |
|
|
byte CON67 :1; /* Concatenate channels 6 and 7 */
|
| 6735 |
|
|
} Bits;
|
| 6736 |
|
|
} PWMCTLSTR;
|
| 6737 |
|
|
extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000A5);
|
| 6738 |
|
|
#define PWMCTL _PWMCTL.Byte
|
| 6739 |
|
|
#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ
|
| 6740 |
|
|
#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI
|
| 6741 |
|
|
#define PWMCTL_CON01 _PWMCTL.Bits.CON01
|
| 6742 |
|
|
#define PWMCTL_CON23 _PWMCTL.Bits.CON23
|
| 6743 |
|
|
#define PWMCTL_CON45 _PWMCTL.Bits.CON45
|
| 6744 |
|
|
#define PWMCTL_CON67 _PWMCTL.Bits.CON67
|
| 6745 |
|
|
|
| 6746 |
|
|
|
| 6747 |
|
|
/*** PWMSCLA - PWM Scale A Register; 0x000000A8 ***/
|
| 6748 |
|
|
typedef union {
|
| 6749 |
|
|
byte Byte;
|
| 6750 |
|
|
struct {
|
| 6751 |
|
|
byte BIT0 :1; /* PWM Scale A Bit 0 */
|
| 6752 |
|
|
byte BIT1 :1; /* PWM Scale A Bit 1 */
|
| 6753 |
|
|
byte BIT2 :1; /* PWM Scale A Bit 2 */
|
| 6754 |
|
|
byte BIT3 :1; /* PWM Scale A Bit 3 */
|
| 6755 |
|
|
byte BIT4 :1; /* PWM Scale A Bit 4 */
|
| 6756 |
|
|
byte BIT5 :1; /* PWM Scale A Bit 5 */
|
| 6757 |
|
|
byte BIT6 :1; /* PWM Scale A Bit 6 */
|
| 6758 |
|
|
byte BIT7 :1; /* PWM Scale A Bit 7 */
|
| 6759 |
|
|
} Bits;
|
| 6760 |
|
|
struct {
|
| 6761 |
|
|
byte grpBIT :8;
|
| 6762 |
|
|
} MergedBits;
|
| 6763 |
|
|
} PWMSCLASTR;
|
| 6764 |
|
|
extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000A8);
|
| 6765 |
|
|
#define PWMSCLA _PWMSCLA.Byte
|
| 6766 |
|
|
#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0
|
| 6767 |
|
|
#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1
|
| 6768 |
|
|
#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2
|
| 6769 |
|
|
#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3
|
| 6770 |
|
|
#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4
|
| 6771 |
|
|
#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5
|
| 6772 |
|
|
#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6
|
| 6773 |
|
|
#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7
|
| 6774 |
|
|
#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT
|
| 6775 |
|
|
|
| 6776 |
|
|
|
| 6777 |
|
|
/*** PWMSCLB - PWM Scale B Register; 0x000000A9 ***/
|
| 6778 |
|
|
typedef union {
|
| 6779 |
|
|
byte Byte;
|
| 6780 |
|
|
struct {
|
| 6781 |
|
|
byte BIT0 :1; /* PWM Scale B Bit 0 */
|
| 6782 |
|
|
byte BIT1 :1; /* PWM Scale B Bit 1 */
|
| 6783 |
|
|
byte BIT2 :1; /* PWM Scale B Bit 2 */
|
| 6784 |
|
|
byte BIT3 :1; /* PWM Scale B Bit 3 */
|
| 6785 |
|
|
byte BIT4 :1; /* PWM Scale B Bit 4 */
|
| 6786 |
|
|
byte BIT5 :1; /* PWM Scale B Bit 5 */
|
| 6787 |
|
|
byte BIT6 :1; /* PWM Scale B Bit 6 */
|
| 6788 |
|
|
byte BIT7 :1; /* PWM Scale B Bit 7 */
|
| 6789 |
|
|
} Bits;
|
| 6790 |
|
|
struct {
|
| 6791 |
|
|
byte grpBIT :8;
|
| 6792 |
|
|
} MergedBits;
|
| 6793 |
|
|
} PWMSCLBSTR;
|
| 6794 |
|
|
extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000A9);
|
| 6795 |
|
|
#define PWMSCLB _PWMSCLB.Byte
|
| 6796 |
|
|
#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0
|
| 6797 |
|
|
#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1
|
| 6798 |
|
|
#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2
|
| 6799 |
|
|
#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3
|
| 6800 |
|
|
#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4
|
| 6801 |
|
|
#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5
|
| 6802 |
|
|
#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6
|
| 6803 |
|
|
#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7
|
| 6804 |
|
|
#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT
|
| 6805 |
|
|
|
| 6806 |
|
|
|
| 6807 |
|
|
/*** PWMSDN - PWM Shutdown Register; 0x000000C4 ***/
|
| 6808 |
|
|
typedef union {
|
| 6809 |
|
|
byte Byte;
|
| 6810 |
|
|
struct {
|
| 6811 |
|
|
byte PWM7ENA :1; /* PWM emergency shutdown Enable */
|
| 6812 |
|
|
byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */
|
| 6813 |
|
|
byte PWM7IN :1; /* PWM channel 7 input status */
|
| 6814 |
|
|
byte :1;
|
| 6815 |
|
|
byte PWMLVL :1; /* PWM shutdown output Level */
|
| 6816 |
|
|
byte PWMRSTRT :1; /* PWM Restart */
|
| 6817 |
|
|
byte PWMIE :1; /* PWM Interrupt Enable */
|
| 6818 |
|
|
byte PWMIF :1; /* PWM Interrupt Flag */
|
| 6819 |
|
|
} Bits;
|
| 6820 |
|
|
} PWMSDNSTR;
|
| 6821 |
|
|
extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000C4);
|
| 6822 |
|
|
#define PWMSDN _PWMSDN.Byte
|
| 6823 |
|
|
#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA
|
| 6824 |
|
|
#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL
|
| 6825 |
|
|
#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN
|
| 6826 |
|
|
#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL
|
| 6827 |
|
|
#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT
|
| 6828 |
|
|
#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE
|
| 6829 |
|
|
#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF
|
| 6830 |
|
|
|
| 6831 |
|
|
|
| 6832 |
|
|
/*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***/
|
| 6833 |
|
|
typedef union {
|
| 6834 |
|
|
byte Byte;
|
| 6835 |
|
|
struct {
|
| 6836 |
|
|
byte PT :1; /* Parity Type Bit */
|
| 6837 |
|
|
byte PE :1; /* Parity Enable Bit */
|
| 6838 |
|
|
byte ILT :1; /* Idle Line Type Bit */
|
| 6839 |
|
|
byte WAKE :1; /* Wakeup Condition Bit */
|
| 6840 |
|
|
byte M :1; /* Data Format Mode Bit */
|
| 6841 |
|
|
byte RSRC :1; /* Receiver Source Bit */
|
| 6842 |
|
|
byte SCISWAI :1; /* SCI 0 Stop in Wait Mode Bit */
|
| 6843 |
|
|
byte LOOPS :1; /* Loop Select Bit */
|
| 6844 |
|
|
} Bits;
|
| 6845 |
|
|
} SCI0CR1STR;
|
| 6846 |
|
|
extern volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CA);
|
| 6847 |
|
|
#define SCI0CR1 _SCI0CR1.Byte
|
| 6848 |
|
|
#define SCI0CR1_PT _SCI0CR1.Bits.PT
|
| 6849 |
|
|
#define SCI0CR1_PE _SCI0CR1.Bits.PE
|
| 6850 |
|
|
#define SCI0CR1_ILT _SCI0CR1.Bits.ILT
|
| 6851 |
|
|
#define SCI0CR1_WAKE _SCI0CR1.Bits.WAKE
|
| 6852 |
|
|
#define SCI0CR1_M _SCI0CR1.Bits.M
|
| 6853 |
|
|
#define SCI0CR1_RSRC _SCI0CR1.Bits.RSRC
|
| 6854 |
|
|
#define SCI0CR1_SCISWAI _SCI0CR1.Bits.SCISWAI
|
| 6855 |
|
|
#define SCI0CR1_LOOPS _SCI0CR1.Bits.LOOPS
|
| 6856 |
|
|
|
| 6857 |
|
|
|
| 6858 |
|
|
/*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***/
|
| 6859 |
|
|
typedef union {
|
| 6860 |
|
|
byte Byte;
|
| 6861 |
|
|
struct {
|
| 6862 |
|
|
byte SBK :1; /* Send Break Bit */
|
| 6863 |
|
|
byte RWU :1; /* Receiver Wakeup Bit */
|
| 6864 |
|
|
byte RE :1; /* Receiver Enable Bit */
|
| 6865 |
|
|
byte TE :1; /* Transmitter Enable Bit */
|
| 6866 |
|
|
byte ILIE :1; /* Idle Line Interrupt Enable Bit */
|
| 6867 |
|
|
byte RIE :1; /* Receiver Full Interrupt Enable Bit */
|
| 6868 |
|
|
byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */
|
| 6869 |
|
|
byte SCTIE :1; /* Transmitter Interrupt Enable Bit */
|
| 6870 |
|
|
} Bits;
|
| 6871 |
|
|
} SCI0CR2STR;
|
| 6872 |
|
|
extern volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CB);
|
| 6873 |
|
|
#define SCI0CR2 _SCI0CR2.Byte
|
| 6874 |
|
|
#define SCI0CR2_SBK _SCI0CR2.Bits.SBK
|
| 6875 |
|
|
#define SCI0CR2_RWU _SCI0CR2.Bits.RWU
|
| 6876 |
|
|
#define SCI0CR2_RE _SCI0CR2.Bits.RE
|
| 6877 |
|
|
#define SCI0CR2_TE _SCI0CR2.Bits.TE
|
| 6878 |
|
|
#define SCI0CR2_ILIE _SCI0CR2.Bits.ILIE
|
| 6879 |
|
|
#define SCI0CR2_RIE _SCI0CR2.Bits.RIE
|
| 6880 |
|
|
#define SCI0CR2_TCIE _SCI0CR2.Bits.TCIE
|
| 6881 |
|
|
#define SCI0CR2_SCTIE _SCI0CR2.Bits.SCTIE
|
| 6882 |
|
|
|
| 6883 |
|
|
|
| 6884 |
|
|
/*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***/
|
| 6885 |
|
|
typedef union {
|
| 6886 |
|
|
byte Byte;
|
| 6887 |
|
|
struct {
|
| 6888 |
|
|
byte PF :1; /* Parity Error Flag */
|
| 6889 |
|
|
byte FE :1; /* Framing Error Flag */
|
| 6890 |
|
|
byte NF :1; /* Noise Flag */
|
| 6891 |
|
|
byte OR :1; /* Overrun Flag */
|
| 6892 |
|
|
byte IDLE :1; /* Idle Line Flag */
|
| 6893 |
|
|
byte RDRF :1; /* Receive Data Register Full Flag */
|
| 6894 |
|
|
byte TC :1; /* Transmit Complete Flag */
|
| 6895 |
|
|
byte TDRE :1; /* Transmit Data Register Empty Flag */
|
| 6896 |
|
|
} Bits;
|
| 6897 |
|
|
} SCI0SR1STR;
|
| 6898 |
|
|
extern volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CC);
|
| 6899 |
|
|
#define SCI0SR1 _SCI0SR1.Byte
|
| 6900 |
|
|
#define SCI0SR1_PF _SCI0SR1.Bits.PF
|
| 6901 |
|
|
#define SCI0SR1_FE _SCI0SR1.Bits.FE
|
| 6902 |
|
|
#define SCI0SR1_NF _SCI0SR1.Bits.NF
|
| 6903 |
|
|
#define SCI0SR1_OR _SCI0SR1.Bits.OR
|
| 6904 |
|
|
#define SCI0SR1_IDLE _SCI0SR1.Bits.IDLE
|
| 6905 |
|
|
#define SCI0SR1_RDRF _SCI0SR1.Bits.RDRF
|
| 6906 |
|
|
#define SCI0SR1_TC _SCI0SR1.Bits.TC
|
| 6907 |
|
|
#define SCI0SR1_TDRE _SCI0SR1.Bits.TDRE
|
| 6908 |
|
|
|
| 6909 |
|
|
|
| 6910 |
|
|
/*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***/
|
| 6911 |
|
|
typedef union {
|
| 6912 |
|
|
byte Byte;
|
| 6913 |
|
|
struct {
|
| 6914 |
|
|
byte RAF :1; /* Receiver Active Flag */
|
| 6915 |
|
|
byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */
|
| 6916 |
|
|
byte BRK13 :1; /* Break Transmit character length */
|
| 6917 |
|
|
byte :1;
|
| 6918 |
|
|
byte :1;
|
| 6919 |
|
|
byte :1;
|
| 6920 |
|
|
byte :1;
|
| 6921 |
|
|
byte :1;
|
| 6922 |
|
|
} Bits;
|
| 6923 |
|
|
} SCI0SR2STR;
|
| 6924 |
|
|
extern volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CD);
|
| 6925 |
|
|
#define SCI0SR2 _SCI0SR2.Byte
|
| 6926 |
|
|
#define SCI0SR2_RAF _SCI0SR2.Bits.RAF
|
| 6927 |
|
|
#define SCI0SR2_TXDIR _SCI0SR2.Bits.TXDIR
|
| 6928 |
|
|
#define SCI0SR2_BRK13 _SCI0SR2.Bits.BRK13
|
| 6929 |
|
|
|
| 6930 |
|
|
|
| 6931 |
|
|
/*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***/
|
| 6932 |
|
|
typedef union {
|
| 6933 |
|
|
byte Byte;
|
| 6934 |
|
|
struct {
|
| 6935 |
|
|
byte :1;
|
| 6936 |
|
|
byte :1;
|
| 6937 |
|
|
byte :1;
|
| 6938 |
|
|
byte :1;
|
| 6939 |
|
|
byte :1;
|
| 6940 |
|
|
byte :1;
|
| 6941 |
|
|
byte T8 :1; /* Transmit Bit 8 */
|
| 6942 |
|
|
byte R8 :1; /* Received Bit 8 */
|
| 6943 |
|
|
} Bits;
|
| 6944 |
|
|
} SCI0DRHSTR;
|
| 6945 |
|
|
extern volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CE);
|
| 6946 |
|
|
#define SCI0DRH _SCI0DRH.Byte
|
| 6947 |
|
|
#define SCI0DRH_T8 _SCI0DRH.Bits.T8
|
| 6948 |
|
|
#define SCI0DRH_R8 _SCI0DRH.Bits.R8
|
| 6949 |
|
|
|
| 6950 |
|
|
|
| 6951 |
|
|
/*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***/
|
| 6952 |
|
|
typedef union {
|
| 6953 |
|
|
byte Byte;
|
| 6954 |
|
|
struct {
|
| 6955 |
|
|
byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */
|
| 6956 |
|
|
byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */
|
| 6957 |
|
|
byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */
|
| 6958 |
|
|
byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */
|
| 6959 |
|
|
byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */
|
| 6960 |
|
|
byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */
|
| 6961 |
|
|
byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */
|
| 6962 |
|
|
byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */
|
| 6963 |
|
|
} Bits;
|
| 6964 |
|
|
} SCI0DRLSTR;
|
| 6965 |
|
|
extern volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CF);
|
| 6966 |
|
|
#define SCI0DRL _SCI0DRL.Byte
|
| 6967 |
|
|
#define SCI0DRL_R0_T0 _SCI0DRL.Bits.R0_T0
|
| 6968 |
|
|
#define SCI0DRL_R1_T1 _SCI0DRL.Bits.R1_T1
|
| 6969 |
|
|
#define SCI0DRL_R2_T2 _SCI0DRL.Bits.R2_T2
|
| 6970 |
|
|
#define SCI0DRL_R3_T3 _SCI0DRL.Bits.R3_T3
|
| 6971 |
|
|
#define SCI0DRL_R4_T4 _SCI0DRL.Bits.R4_T4
|
| 6972 |
|
|
#define SCI0DRL_R5_T5 _SCI0DRL.Bits.R5_T5
|
| 6973 |
|
|
#define SCI0DRL_R6_T6 _SCI0DRL.Bits.R6_T6
|
| 6974 |
|
|
#define SCI0DRL_R7_T7 _SCI0DRL.Bits.R7_T7
|
| 6975 |
|
|
|
| 6976 |
|
|
|
| 6977 |
|
|
/*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***/
|
| 6978 |
|
|
typedef union {
|
| 6979 |
|
|
byte Byte;
|
| 6980 |
|
|
struct {
|
| 6981 |
|
|
byte PT :1; /* Parity Type Bit */
|
| 6982 |
|
|
byte PE :1; /* Parity Enable Bit */
|
| 6983 |
|
|
byte ILT :1; /* Idle Line Type Bit */
|
| 6984 |
|
|
byte WAKE :1; /* Wakeup Condition Bit */
|
| 6985 |
|
|
byte M :1; /* Data Format Mode Bit */
|
| 6986 |
|
|
byte RSRC :1; /* Receiver Source Bit */
|
| 6987 |
|
|
byte SCISWAI :1; /* SCI 1 Stop in Wait Mode Bit */
|
| 6988 |
|
|
byte LOOPS :1; /* Loop Select Bit */
|
| 6989 |
|
|
} Bits;
|
| 6990 |
|
|
} SCI1CR1STR;
|
| 6991 |
|
|
extern volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2);
|
| 6992 |
|
|
#define SCI1CR1 _SCI1CR1.Byte
|
| 6993 |
|
|
#define SCI1CR1_PT _SCI1CR1.Bits.PT
|
| 6994 |
|
|
#define SCI1CR1_PE _SCI1CR1.Bits.PE
|
| 6995 |
|
|
#define SCI1CR1_ILT _SCI1CR1.Bits.ILT
|
| 6996 |
|
|
#define SCI1CR1_WAKE _SCI1CR1.Bits.WAKE
|
| 6997 |
|
|
#define SCI1CR1_M _SCI1CR1.Bits.M
|
| 6998 |
|
|
#define SCI1CR1_RSRC _SCI1CR1.Bits.RSRC
|
| 6999 |
|
|
#define SCI1CR1_SCISWAI _SCI1CR1.Bits.SCISWAI
|
| 7000 |
|
|
#define SCI1CR1_LOOPS _SCI1CR1.Bits.LOOPS
|
| 7001 |
|
|
|
| 7002 |
|
|
|
| 7003 |
|
|
/*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***/
|
| 7004 |
|
|
typedef union {
|
| 7005 |
|
|
byte Byte;
|
| 7006 |
|
|
struct {
|
| 7007 |
|
|
byte SBK :1; /* Send Break Bit */
|
| 7008 |
|
|
byte RWU :1; /* Receiver Wakeup Bit */
|
| 7009 |
|
|
byte RE :1; /* Receiver Enable Bit */
|
| 7010 |
|
|
byte TE :1; /* Transmitter Enable Bit */
|
| 7011 |
|
|
byte ILIE :1; /* Idle Line Interrupt Enable Bit */
|
| 7012 |
|
|
byte RIE :1; /* Receiver Full Interrupt Enable Bit */
|
| 7013 |
|
|
byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */
|
| 7014 |
|
|
byte SCTIE :1; /* Transmitter Interrupt Enable Bit */
|
| 7015 |
|
|
} Bits;
|
| 7016 |
|
|
} SCI1CR2STR;
|
| 7017 |
|
|
extern volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3);
|
| 7018 |
|
|
#define SCI1CR2 _SCI1CR2.Byte
|
| 7019 |
|
|
#define SCI1CR2_SBK _SCI1CR2.Bits.SBK
|
| 7020 |
|
|
#define SCI1CR2_RWU _SCI1CR2.Bits.RWU
|
| 7021 |
|
|
#define SCI1CR2_RE _SCI1CR2.Bits.RE
|
| 7022 |
|
|
#define SCI1CR2_TE _SCI1CR2.Bits.TE
|
| 7023 |
|
|
#define SCI1CR2_ILIE _SCI1CR2.Bits.ILIE
|
| 7024 |
|
|
#define SCI1CR2_RIE _SCI1CR2.Bits.RIE
|
| 7025 |
|
|
#define SCI1CR2_TCIE _SCI1CR2.Bits.TCIE
|
| 7026 |
|
|
#define SCI1CR2_SCTIE _SCI1CR2.Bits.SCTIE
|
| 7027 |
|
|
|
| 7028 |
|
|
|
| 7029 |
|
|
/*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***/
|
| 7030 |
|
|
typedef union {
|
| 7031 |
|
|
byte Byte;
|
| 7032 |
|
|
struct {
|
| 7033 |
|
|
byte PF :1; /* Parity Error Flag */
|
| 7034 |
|
|
byte FE :1; /* Framing Error Flag */
|
| 7035 |
|
|
byte NF :1; /* Noise Flag */
|
| 7036 |
|
|
byte OR :1; /* Overrun Flag */
|
| 7037 |
|
|
byte IDLE :1; /* Idle Line Flag */
|
| 7038 |
|
|
byte RDRF :1; /* Receive Data Register Full Flag */
|
| 7039 |
|
|
byte TC :1; /* Transmit Complete Flag */
|
| 7040 |
|
|
byte TDRE :1; /* Transmit Data Register Empty Flag */
|
| 7041 |
|
|
} Bits;
|
| 7042 |
|
|
} SCI1SR1STR;
|
| 7043 |
|
|
extern volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4);
|
| 7044 |
|
|
#define SCI1SR1 _SCI1SR1.Byte
|
| 7045 |
|
|
#define SCI1SR1_PF _SCI1SR1.Bits.PF
|
| 7046 |
|
|
#define SCI1SR1_FE _SCI1SR1.Bits.FE
|
| 7047 |
|
|
#define SCI1SR1_NF _SCI1SR1.Bits.NF
|
| 7048 |
|
|
#define SCI1SR1_OR _SCI1SR1.Bits.OR
|
| 7049 |
|
|
#define SCI1SR1_IDLE _SCI1SR1.Bits.IDLE
|
| 7050 |
|
|
#define SCI1SR1_RDRF _SCI1SR1.Bits.RDRF
|
| 7051 |
|
|
#define SCI1SR1_TC _SCI1SR1.Bits.TC
|
| 7052 |
|
|
#define SCI1SR1_TDRE _SCI1SR1.Bits.TDRE
|
| 7053 |
|
|
|
| 7054 |
|
|
|
| 7055 |
|
|
/*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***/
|
| 7056 |
|
|
typedef union {
|
| 7057 |
|
|
byte Byte;
|
| 7058 |
|
|
struct {
|
| 7059 |
|
|
byte RAF :1; /* Receiver Active Flag */
|
| 7060 |
|
|
byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */
|
| 7061 |
|
|
byte BRK13 :1; /* Break Transmit character length */
|
| 7062 |
|
|
byte :1;
|
| 7063 |
|
|
byte :1;
|
| 7064 |
|
|
byte :1;
|
| 7065 |
|
|
byte :1;
|
| 7066 |
|
|
byte :1;
|
| 7067 |
|
|
} Bits;
|
| 7068 |
|
|
} SCI1SR2STR;
|
| 7069 |
|
|
extern volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5);
|
| 7070 |
|
|
#define SCI1SR2 _SCI1SR2.Byte
|
| 7071 |
|
|
#define SCI1SR2_RAF _SCI1SR2.Bits.RAF
|
| 7072 |
|
|
#define SCI1SR2_TXDIR _SCI1SR2.Bits.TXDIR
|
| 7073 |
|
|
#define SCI1SR2_BRK13 _SCI1SR2.Bits.BRK13
|
| 7074 |
|
|
|
| 7075 |
|
|
|
| 7076 |
|
|
/*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***/
|
| 7077 |
|
|
typedef union {
|
| 7078 |
|
|
byte Byte;
|
| 7079 |
|
|
struct {
|
| 7080 |
|
|
byte :1;
|
| 7081 |
|
|
byte :1;
|
| 7082 |
|
|
byte :1;
|
| 7083 |
|
|
byte :1;
|
| 7084 |
|
|
byte :1;
|
| 7085 |
|
|
byte :1;
|
| 7086 |
|
|
byte T8 :1; /* Transmit Bit 8 */
|
| 7087 |
|
|
byte R8 :1; /* Received Bit 8 */
|
| 7088 |
|
|
} Bits;
|
| 7089 |
|
|
} SCI1DRHSTR;
|
| 7090 |
|
|
extern volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6);
|
| 7091 |
|
|
#define SCI1DRH _SCI1DRH.Byte
|
| 7092 |
|
|
#define SCI1DRH_T8 _SCI1DRH.Bits.T8
|
| 7093 |
|
|
#define SCI1DRH_R8 _SCI1DRH.Bits.R8
|
| 7094 |
|
|
|
| 7095 |
|
|
|
| 7096 |
|
|
/*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***/
|
| 7097 |
|
|
typedef union {
|
| 7098 |
|
|
byte Byte;
|
| 7099 |
|
|
struct {
|
| 7100 |
|
|
byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */
|
| 7101 |
|
|
byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */
|
| 7102 |
|
|
byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */
|
| 7103 |
|
|
byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */
|
| 7104 |
|
|
byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */
|
| 7105 |
|
|
byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */
|
| 7106 |
|
|
byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */
|
| 7107 |
|
|
byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */
|
| 7108 |
|
|
} Bits;
|
| 7109 |
|
|
} SCI1DRLSTR;
|
| 7110 |
|
|
extern volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7);
|
| 7111 |
|
|
#define SCI1DRL _SCI1DRL.Byte
|
| 7112 |
|
|
#define SCI1DRL_R0_T0 _SCI1DRL.Bits.R0_T0
|
| 7113 |
|
|
#define SCI1DRL_R1_T1 _SCI1DRL.Bits.R1_T1
|
| 7114 |
|
|
#define SCI1DRL_R2_T2 _SCI1DRL.Bits.R2_T2
|
| 7115 |
|
|
#define SCI1DRL_R3_T3 _SCI1DRL.Bits.R3_T3
|
| 7116 |
|
|
#define SCI1DRL_R4_T4 _SCI1DRL.Bits.R4_T4
|
| 7117 |
|
|
#define SCI1DRL_R5_T5 _SCI1DRL.Bits.R5_T5
|
| 7118 |
|
|
#define SCI1DRL_R6_T6 _SCI1DRL.Bits.R6_T6
|
| 7119 |
|
|
#define SCI1DRL_R7_T7 _SCI1DRL.Bits.R7_T7
|
| 7120 |
|
|
|
| 7121 |
|
|
|
| 7122 |
|
|
/*** SPI0CR1 - SPI 0 Control Register; 0x000000D8 ***/
|
| 7123 |
|
|
typedef union {
|
| 7124 |
|
|
byte Byte;
|
| 7125 |
|
|
struct {
|
| 7126 |
|
|
byte LSBFE :1; /* SPI 0 LSB-First Enable */
|
| 7127 |
|
|
byte SSOE :1; /* Slave Select Output Enable */
|
| 7128 |
|
|
byte CPHA :1; /* SPI 0 Clock Phase Bit */
|
| 7129 |
|
|
byte CPOL :1; /* SPI 0 Clock Polarity Bit */
|
| 7130 |
|
|
byte MSTR :1; /* SPI 0 Master/Slave Mode Select Bit */
|
| 7131 |
|
|
byte SPTIE :1; /* SPI 0 Transmit Interrupt Enable */
|
| 7132 |
|
|
byte SPE :1; /* SPI 0 System Enable Bit */
|
| 7133 |
|
|
byte SPIE :1; /* SPI 0 Interrupt Enable Bit */
|
| 7134 |
|
|
} Bits;
|
| 7135 |
|
|
} SPI0CR1STR;
|
| 7136 |
|
|
extern volatile SPI0CR1STR _SPI0CR1 @(REG_BASE + 0x000000D8);
|
| 7137 |
|
|
#define SPI0CR1 _SPI0CR1.Byte
|
| 7138 |
|
|
#define SPI0CR1_LSBFE _SPI0CR1.Bits.LSBFE
|
| 7139 |
|
|
#define SPI0CR1_SSOE _SPI0CR1.Bits.SSOE
|
| 7140 |
|
|
#define SPI0CR1_CPHA _SPI0CR1.Bits.CPHA
|
| 7141 |
|
|
#define SPI0CR1_CPOL _SPI0CR1.Bits.CPOL
|
| 7142 |
|
|
#define SPI0CR1_MSTR _SPI0CR1.Bits.MSTR
|
| 7143 |
|
|
#define SPI0CR1_SPTIE _SPI0CR1.Bits.SPTIE
|
| 7144 |
|
|
#define SPI0CR1_SPE _SPI0CR1.Bits.SPE
|
| 7145 |
|
|
#define SPI0CR1_SPIE _SPI0CR1.Bits.SPIE
|
| 7146 |
|
|
|
| 7147 |
|
|
|
| 7148 |
|
|
/*** SPI0CR2 - SPI 0 Control Register 2; 0x000000D9 ***/
|
| 7149 |
|
|
typedef union {
|
| 7150 |
|
|
byte Byte;
|
| 7151 |
|
|
struct {
|
| 7152 |
|
|
byte SPC0 :1; /* Serial Pin Control Bit 0 */
|
| 7153 |
|
|
byte SPISWAI :1; /* SPI 0 Stop in Wait Mode Bit */
|
| 7154 |
|
|
byte :1;
|
| 7155 |
|
|
byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */
|
| 7156 |
|
|
byte MODFEN :1; /* Mode Fault Enable Bit */
|
| 7157 |
|
|
byte :1;
|
| 7158 |
|
|
byte :1;
|
| 7159 |
|
|
byte :1;
|
| 7160 |
|
|
} Bits;
|
| 7161 |
|
|
} SPI0CR2STR;
|
| 7162 |
|
|
extern volatile SPI0CR2STR _SPI0CR2 @(REG_BASE + 0x000000D9);
|
| 7163 |
|
|
#define SPI0CR2 _SPI0CR2.Byte
|
| 7164 |
|
|
#define SPI0CR2_SPC0 _SPI0CR2.Bits.SPC0
|
| 7165 |
|
|
#define SPI0CR2_SPISWAI _SPI0CR2.Bits.SPISWAI
|
| 7166 |
|
|
#define SPI0CR2_BIDIROE _SPI0CR2.Bits.BIDIROE
|
| 7167 |
|
|
#define SPI0CR2_MODFEN _SPI0CR2.Bits.MODFEN
|
| 7168 |
|
|
|
| 7169 |
|
|
|
| 7170 |
|
|
/*** SPI0BR - SPI 0 Baud Rate Register; 0x000000DA ***/
|
| 7171 |
|
|
typedef union {
|
| 7172 |
|
|
byte Byte;
|
| 7173 |
|
|
struct {
|
| 7174 |
|
|
byte SPR0 :1; /* SPI 0 Baud Rate Selection Bit 0 */
|
| 7175 |
|
|
byte SPR1 :1; /* SPI 0 Baud Rate Selection Bit 1 */
|
| 7176 |
|
|
byte SPR2 :1; /* SPI 0 Baud Rate Selection Bit 2 */
|
| 7177 |
|
|
byte :1;
|
| 7178 |
|
|
byte SPPR0 :1; /* SPI 0 Baud Rate Preselection Bits 0 */
|
| 7179 |
|
|
byte SPPR1 :1; /* SPI 0 Baud Rate Preselection Bits 1 */
|
| 7180 |
|
|
byte SPPR2 :1; /* SPI 0 Baud Rate Preselection Bits 2 */
|
| 7181 |
|
|
byte :1;
|
| 7182 |
|
|
} Bits;
|
| 7183 |
|
|
struct {
|
| 7184 |
|
|
byte grpSPR :3;
|
| 7185 |
|
|
byte :1;
|
| 7186 |
|
|
byte grpSPPR :3;
|
| 7187 |
|
|
byte :1;
|
| 7188 |
|
|
} MergedBits;
|
| 7189 |
|
|
} SPI0BRSTR;
|
| 7190 |
|
|
extern volatile SPI0BRSTR _SPI0BR @(REG_BASE + 0x000000DA);
|
| 7191 |
|
|
#define SPI0BR _SPI0BR.Byte
|
| 7192 |
|
|
#define SPI0BR_SPR0 _SPI0BR.Bits.SPR0
|
| 7193 |
|
|
#define SPI0BR_SPR1 _SPI0BR.Bits.SPR1
|
| 7194 |
|
|
#define SPI0BR_SPR2 _SPI0BR.Bits.SPR2
|
| 7195 |
|
|
#define SPI0BR_SPPR0 _SPI0BR.Bits.SPPR0
|
| 7196 |
|
|
#define SPI0BR_SPPR1 _SPI0BR.Bits.SPPR1
|
| 7197 |
|
|
#define SPI0BR_SPPR2 _SPI0BR.Bits.SPPR2
|
| 7198 |
|
|
#define SPI0BR_SPR _SPI0BR.MergedBits.grpSPR
|
| 7199 |
|
|
#define SPI0BR_SPPR _SPI0BR.MergedBits.grpSPPR
|
| 7200 |
|
|
|
| 7201 |
|
|
|
| 7202 |
|
|
/*** SPI0SR - SPI 0 Status Register; 0x000000DB ***/
|
| 7203 |
|
|
typedef union {
|
| 7204 |
|
|
byte Byte;
|
| 7205 |
|
|
struct {
|
| 7206 |
|
|
byte :1;
|
| 7207 |
|
|
byte :1;
|
| 7208 |
|
|
byte :1;
|
| 7209 |
|
|
byte :1;
|
| 7210 |
|
|
byte MODF :1; /* Mode Fault Flag */
|
| 7211 |
|
|
byte SPTEF :1; /* SPI 0 Transmit Empty Interrupt Flag */
|
| 7212 |
|
|
byte :1;
|
| 7213 |
|
|
byte SPIF :1; /* SPIF Receive Interrupt Flag */
|
| 7214 |
|
|
} Bits;
|
| 7215 |
|
|
} SPI0SRSTR;
|
| 7216 |
|
|
extern volatile SPI0SRSTR _SPI0SR @(REG_BASE + 0x000000DB);
|
| 7217 |
|
|
#define SPI0SR _SPI0SR.Byte
|
| 7218 |
|
|
#define SPI0SR_MODF _SPI0SR.Bits.MODF
|
| 7219 |
|
|
#define SPI0SR_SPTEF _SPI0SR.Bits.SPTEF
|
| 7220 |
|
|
#define SPI0SR_SPIF _SPI0SR.Bits.SPIF
|
| 7221 |
|
|
|
| 7222 |
|
|
|
| 7223 |
|
|
/*** SPI0DR - SPI 0 Data Register; 0x000000DD ***/
|
| 7224 |
|
|
typedef union {
|
| 7225 |
|
|
byte Byte;
|
| 7226 |
|
|
struct {
|
| 7227 |
|
|
byte grpBIT :8;
|
| 7228 |
|
|
} MergedBits;
|
| 7229 |
|
|
} SPI0DRSTR;
|
| 7230 |
|
|
extern volatile SPI0DRSTR _SPI0DR @(REG_BASE + 0x000000DD);
|
| 7231 |
|
|
#define SPI0DR _SPI0DR.Byte
|
| 7232 |
|
|
#define SPI0DR_BIT _SPI0DR.MergedBits.grpBIT
|
| 7233 |
|
|
|
| 7234 |
|
|
|
| 7235 |
|
|
/*** IBAD - IIC Address Register; 0x000000E0 ***/
|
| 7236 |
|
|
typedef union {
|
| 7237 |
|
|
byte Byte;
|
| 7238 |
|
|
struct {
|
| 7239 |
|
|
byte :1;
|
| 7240 |
|
|
byte ADR1 :1; /* Slave Address Bit 1 */
|
| 7241 |
|
|
byte ADR2 :1; /* Slave Address Bit 2 */
|
| 7242 |
|
|
byte ADR3 :1; /* Slave Address Bit 3 */
|
| 7243 |
|
|
byte ADR4 :1; /* Slave Address Bit 4 */
|
| 7244 |
|
|
byte ADR5 :1; /* Slave Address Bit 5 */
|
| 7245 |
|
|
byte ADR6 :1; /* Slave Address Bit 6 */
|
| 7246 |
|
|
byte ADR7 :1; /* Slave Address Bit 7 */
|
| 7247 |
|
|
} Bits;
|
| 7248 |
|
|
struct {
|
| 7249 |
|
|
byte :1;
|
| 7250 |
|
|
byte grpADR_1 :7;
|
| 7251 |
|
|
} MergedBits;
|
| 7252 |
|
|
} IBADSTR;
|
| 7253 |
|
|
extern volatile IBADSTR _IBAD @(REG_BASE + 0x000000E0);
|
| 7254 |
|
|
#define IBAD _IBAD.Byte
|
| 7255 |
|
|
#define IBAD_ADR1 _IBAD.Bits.ADR1
|
| 7256 |
|
|
#define IBAD_ADR2 _IBAD.Bits.ADR2
|
| 7257 |
|
|
#define IBAD_ADR3 _IBAD.Bits.ADR3
|
| 7258 |
|
|
#define IBAD_ADR4 _IBAD.Bits.ADR4
|
| 7259 |
|
|
#define IBAD_ADR5 _IBAD.Bits.ADR5
|
| 7260 |
|
|
#define IBAD_ADR6 _IBAD.Bits.ADR6
|
| 7261 |
|
|
#define IBAD_ADR7 _IBAD.Bits.ADR7
|
| 7262 |
|
|
#define IBAD_ADR_1 _IBAD.MergedBits.grpADR_1
|
| 7263 |
|
|
#define IBAD_ADR IBAD_ADR_1
|
| 7264 |
|
|
|
| 7265 |
|
|
|
| 7266 |
|
|
/*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***/
|
| 7267 |
|
|
typedef union {
|
| 7268 |
|
|
byte Byte;
|
| 7269 |
|
|
struct {
|
| 7270 |
|
|
byte IBC0 :1; /* I-Bus Clock Rate 0 */
|
| 7271 |
|
|
byte IBC1 :1; /* I-Bus Clock Rate 1 */
|
| 7272 |
|
|
byte IBC2 :1; /* I-Bus Clock Rate 2 */
|
| 7273 |
|
|
byte IBC3 :1; /* I-Bus Clock Rate 3 */
|
| 7274 |
|
|
byte IBC4 :1; /* I-Bus Clock Rate 4 */
|
| 7275 |
|
|
byte IBC5 :1; /* I-Bus Clock Rate 5 */
|
| 7276 |
|
|
byte IBC6 :1; /* I-Bus Clock Rate 6 */
|
| 7277 |
|
|
byte IBC7 :1; /* I-Bus Clock Rate 7 */
|
| 7278 |
|
|
} Bits;
|
| 7279 |
|
|
struct {
|
| 7280 |
|
|
byte grpIBC :8;
|
| 7281 |
|
|
} MergedBits;
|
| 7282 |
|
|
} IBFDSTR;
|
| 7283 |
|
|
extern volatile IBFDSTR _IBFD @(REG_BASE + 0x000000E1);
|
| 7284 |
|
|
#define IBFD _IBFD.Byte
|
| 7285 |
|
|
#define IBFD_IBC0 _IBFD.Bits.IBC0
|
| 7286 |
|
|
#define IBFD_IBC1 _IBFD.Bits.IBC1
|
| 7287 |
|
|
#define IBFD_IBC2 _IBFD.Bits.IBC2
|
| 7288 |
|
|
#define IBFD_IBC3 _IBFD.Bits.IBC3
|
| 7289 |
|
|
#define IBFD_IBC4 _IBFD.Bits.IBC4
|
| 7290 |
|
|
#define IBFD_IBC5 _IBFD.Bits.IBC5
|
| 7291 |
|
|
#define IBFD_IBC6 _IBFD.Bits.IBC6
|
| 7292 |
|
|
#define IBFD_IBC7 _IBFD.Bits.IBC7
|
| 7293 |
|
|
#define IBFD_IBC _IBFD.MergedBits.grpIBC
|
| 7294 |
|
|
|
| 7295 |
|
|
|
| 7296 |
|
|
/*** IBCR - IIC Control Register; 0x000000E2 ***/
|
| 7297 |
|
|
typedef union {
|
| 7298 |
|
|
byte Byte;
|
| 7299 |
|
|
struct {
|
| 7300 |
|
|
byte IBSWAI :1; /* I-Bus Interface Stop in WAIT mode */
|
| 7301 |
|
|
byte :1;
|
| 7302 |
|
|
byte RSTA :1; /* Repeat Start */
|
| 7303 |
|
|
byte TXAK :1; /* Transmit Acknowledge enable */
|
| 7304 |
|
|
byte TX_RX :1; /* Transmit/Receive mode select bit */
|
| 7305 |
|
|
byte MS_SL :1; /* Master/Slave mode select bit */
|
| 7306 |
|
|
byte IBIE :1; /* I-Bus Interrupt Enable */
|
| 7307 |
|
|
byte IBEN :1; /* I-Bus Enable */
|
| 7308 |
|
|
} Bits;
|
| 7309 |
|
|
} IBCRSTR;
|
| 7310 |
|
|
extern volatile IBCRSTR _IBCR @(REG_BASE + 0x000000E2);
|
| 7311 |
|
|
#define IBCR _IBCR.Byte
|
| 7312 |
|
|
#define IBCR_IBSWAI _IBCR.Bits.IBSWAI
|
| 7313 |
|
|
#define IBCR_RSTA _IBCR.Bits.RSTA
|
| 7314 |
|
|
#define IBCR_TXAK _IBCR.Bits.TXAK
|
| 7315 |
|
|
#define IBCR_TX_RX _IBCR.Bits.TX_RX
|
| 7316 |
|
|
#define IBCR_MS_SL _IBCR.Bits.MS_SL
|
| 7317 |
|
|
#define IBCR_IBIE _IBCR.Bits.IBIE
|
| 7318 |
|
|
#define IBCR_IBEN _IBCR.Bits.IBEN
|
| 7319 |
|
|
|
| 7320 |
|
|
|
| 7321 |
|
|
/*** IBSR - IIC Status Register; 0x000000E3 ***/
|
| 7322 |
|
|
typedef union {
|
| 7323 |
|
|
byte Byte;
|
| 7324 |
|
|
struct {
|
| 7325 |
|
|
byte RXAK :1; /* Received Acknowledge */
|
| 7326 |
|
|
byte IBIF :1; /* I-Bus Interrupt */
|
| 7327 |
|
|
byte SRW :1; /* Slave Read/Write */
|
| 7328 |
|
|
byte :1;
|
| 7329 |
|
|
byte IBAL :1; /* Arbitration Lost */
|
| 7330 |
|
|
byte IBB :1; /* Bus busy bit */
|
| 7331 |
|
|
byte IAAS :1; /* Addressed as a slave bit */
|
| 7332 |
|
|
byte TCF :1; /* Data transferring bit */
|
| 7333 |
|
|
} Bits;
|
| 7334 |
|
|
} IBSRSTR;
|
| 7335 |
|
|
extern volatile IBSRSTR _IBSR @(REG_BASE + 0x000000E3);
|
| 7336 |
|
|
#define IBSR _IBSR.Byte
|
| 7337 |
|
|
#define IBSR_RXAK _IBSR.Bits.RXAK
|
| 7338 |
|
|
#define IBSR_IBIF _IBSR.Bits.IBIF
|
| 7339 |
|
|
#define IBSR_SRW _IBSR.Bits.SRW
|
| 7340 |
|
|
#define IBSR_IBAL _IBSR.Bits.IBAL
|
| 7341 |
|
|
#define IBSR_IBB _IBSR.Bits.IBB
|
| 7342 |
|
|
#define IBSR_IAAS _IBSR.Bits.IAAS
|
| 7343 |
|
|
#define IBSR_TCF _IBSR.Bits.TCF
|
| 7344 |
|
|
|
| 7345 |
|
|
|
| 7346 |
|
|
/*** IBDR - IIC Data I/O Register; 0x000000E4 ***/
|
| 7347 |
|
|
typedef union {
|
| 7348 |
|
|
byte Byte;
|
| 7349 |
|
|
struct {
|
| 7350 |
|
|
byte D0 :1; /* IIC Data Bit 0 */
|
| 7351 |
|
|
byte D1 :1; /* IIC Data Bit 1 */
|
| 7352 |
|
|
byte D2 :1; /* IIC Data Bit 2 */
|
| 7353 |
|
|
byte D3 :1; /* IIC Data Bit 3 */
|
| 7354 |
|
|
byte D4 :1; /* IIC Data Bit 4 */
|
| 7355 |
|
|
byte D5 :1; /* IIC Data Bit 5 */
|
| 7356 |
|
|
byte D6 :1; /* IIC Data Bit 6 */
|
| 7357 |
|
|
byte D7 :1; /* IIC Data Bit 7 */
|
| 7358 |
|
|
} Bits;
|
| 7359 |
|
|
struct {
|
| 7360 |
|
|
byte grpD :8;
|
| 7361 |
|
|
} MergedBits;
|
| 7362 |
|
|
} IBDRSTR;
|
| 7363 |
|
|
extern volatile IBDRSTR _IBDR @(REG_BASE + 0x000000E4);
|
| 7364 |
|
|
#define IBDR _IBDR.Byte
|
| 7365 |
|
|
#define IBDR_D0 _IBDR.Bits.D0
|
| 7366 |
|
|
#define IBDR_D1 _IBDR.Bits.D1
|
| 7367 |
|
|
#define IBDR_D2 _IBDR.Bits.D2
|
| 7368 |
|
|
#define IBDR_D3 _IBDR.Bits.D3
|
| 7369 |
|
|
#define IBDR_D4 _IBDR.Bits.D4
|
| 7370 |
|
|
#define IBDR_D5 _IBDR.Bits.D5
|
| 7371 |
|
|
#define IBDR_D6 _IBDR.Bits.D6
|
| 7372 |
|
|
#define IBDR_D7 _IBDR.Bits.D7
|
| 7373 |
|
|
#define IBDR_D _IBDR.MergedBits.grpD
|
| 7374 |
|
|
|
| 7375 |
|
|
|
| 7376 |
|
|
/*** DLCBCR1 - BDLC Control Register 1; 0x000000E8 ***/
|
| 7377 |
|
|
typedef union {
|
| 7378 |
|
|
byte Byte;
|
| 7379 |
|
|
struct {
|
| 7380 |
|
|
byte WCM :1; /* Wait Clock Mode */
|
| 7381 |
|
|
byte IE :1; /* Interrupt Enable */
|
| 7382 |
|
|
byte :1;
|
| 7383 |
|
|
byte :1;
|
| 7384 |
|
|
byte :1;
|
| 7385 |
|
|
byte :1;
|
| 7386 |
|
|
byte CLKS :1; /* Clock Select */
|
| 7387 |
|
|
byte IMSG :1; /* Ignore Message */
|
| 7388 |
|
|
} Bits;
|
| 7389 |
|
|
} DLCBCR1STR;
|
| 7390 |
|
|
extern volatile DLCBCR1STR _DLCBCR1 @(REG_BASE + 0x000000E8);
|
| 7391 |
|
|
#define DLCBCR1 _DLCBCR1.Byte
|
| 7392 |
|
|
#define DLCBCR1_WCM _DLCBCR1.Bits.WCM
|
| 7393 |
|
|
#define DLCBCR1_IE _DLCBCR1.Bits.IE
|
| 7394 |
|
|
#define DLCBCR1_CLKS _DLCBCR1.Bits.CLKS
|
| 7395 |
|
|
#define DLCBCR1_IMSG _DLCBCR1.Bits.IMSG
|
| 7396 |
|
|
|
| 7397 |
|
|
|
| 7398 |
|
|
/*** DLCBSVR - BDLC State Vector Register; 0x000000E9 ***/
|
| 7399 |
|
|
typedef union {
|
| 7400 |
|
|
byte Byte;
|
| 7401 |
|
|
struct {
|
| 7402 |
|
|
byte :1;
|
| 7403 |
|
|
byte :1;
|
| 7404 |
|
|
byte I0 :1; /* Interrupt State Vector Bit 0 */
|
| 7405 |
|
|
byte I1 :1; /* Interrupt State Vector Bit 1 */
|
| 7406 |
|
|
byte I2 :1; /* Interrupt State Vector Bit 2 */
|
| 7407 |
|
|
byte I3 :1; /* Interrupt State Vector Bit 3 */
|
| 7408 |
|
|
byte :1;
|
| 7409 |
|
|
byte :1;
|
| 7410 |
|
|
} Bits;
|
| 7411 |
|
|
struct {
|
| 7412 |
|
|
byte :1;
|
| 7413 |
|
|
byte :1;
|
| 7414 |
|
|
byte grpI :4;
|
| 7415 |
|
|
byte :1;
|
| 7416 |
|
|
byte :1;
|
| 7417 |
|
|
} MergedBits;
|
| 7418 |
|
|
} DLCBSVRSTR;
|
| 7419 |
|
|
extern volatile DLCBSVRSTR _DLCBSVR @(REG_BASE + 0x000000E9);
|
| 7420 |
|
|
#define DLCBSVR _DLCBSVR.Byte
|
| 7421 |
|
|
#define DLCBSVR_I0 _DLCBSVR.Bits.I0
|
| 7422 |
|
|
#define DLCBSVR_I1 _DLCBSVR.Bits.I1
|
| 7423 |
|
|
#define DLCBSVR_I2 _DLCBSVR.Bits.I2
|
| 7424 |
|
|
#define DLCBSVR_I3 _DLCBSVR.Bits.I3
|
| 7425 |
|
|
#define DLCBSVR_I _DLCBSVR.MergedBits.grpI
|
| 7426 |
|
|
|
| 7427 |
|
|
|
| 7428 |
|
|
/*** DLCBCR2 - BDLC Control Register 2; 0x000000EA ***/
|
| 7429 |
|
|
typedef union {
|
| 7430 |
|
|
byte Byte;
|
| 7431 |
|
|
struct {
|
| 7432 |
|
|
byte TMIFR0 :1; /* Transmit In-Frame Response Control 0 */
|
| 7433 |
|
|
byte TMIFR1 :1; /* Transmit In-Frame Response Control 1 */
|
| 7434 |
|
|
byte TSIFR :1; /* Transmit In-Frame Response Control 2 */
|
| 7435 |
|
|
byte TEOD :1; /* Transmit End of Data */
|
| 7436 |
|
|
byte NBFS :1; /* Normalization Bit Format Select */
|
| 7437 |
|
|
byte RX4XE :1; /* Receive 4X Enable */
|
| 7438 |
|
|
byte DLOOP :1; /* Digital Loopback Mode */
|
| 7439 |
|
|
byte SMRST :1; /* State Machine Reset */
|
| 7440 |
|
|
} Bits;
|
| 7441 |
|
|
struct {
|
| 7442 |
|
|
byte grpTMIFR :2;
|
| 7443 |
|
|
byte :1;
|
| 7444 |
|
|
byte :1;
|
| 7445 |
|
|
byte :1;
|
| 7446 |
|
|
byte :1;
|
| 7447 |
|
|
byte :1;
|
| 7448 |
|
|
byte :1;
|
| 7449 |
|
|
} MergedBits;
|
| 7450 |
|
|
} DLCBCR2STR;
|
| 7451 |
|
|
extern volatile DLCBCR2STR _DLCBCR2 @(REG_BASE + 0x000000EA);
|
| 7452 |
|
|
#define DLCBCR2 _DLCBCR2.Byte
|
| 7453 |
|
|
#define DLCBCR2_TMIFR0 _DLCBCR2.Bits.TMIFR0
|
| 7454 |
|
|
#define DLCBCR2_TMIFR1 _DLCBCR2.Bits.TMIFR1
|
| 7455 |
|
|
#define DLCBCR2_TSIFR _DLCBCR2.Bits.TSIFR
|
| 7456 |
|
|
#define DLCBCR2_TEOD _DLCBCR2.Bits.TEOD
|
| 7457 |
|
|
#define DLCBCR2_NBFS _DLCBCR2.Bits.NBFS
|
| 7458 |
|
|
#define DLCBCR2_RX4XE _DLCBCR2.Bits.RX4XE
|
| 7459 |
|
|
#define DLCBCR2_DLOOP _DLCBCR2.Bits.DLOOP
|
| 7460 |
|
|
#define DLCBCR2_SMRST _DLCBCR2.Bits.SMRST
|
| 7461 |
|
|
#define DLCBCR2_TMIFR _DLCBCR2.MergedBits.grpTMIFR
|
| 7462 |
|
|
|
| 7463 |
|
|
|
| 7464 |
|
|
/*** DLCBDR - BDLC Data Register; 0x000000EB ***/
|
| 7465 |
|
|
typedef union {
|
| 7466 |
|
|
byte Byte;
|
| 7467 |
|
|
struct {
|
| 7468 |
|
|
byte D0 :1; /* Receive/Transmit Data Bit 0 */
|
| 7469 |
|
|
byte D1 :1; /* Receive/Transmit Data Bit 1 */
|
| 7470 |
|
|
byte D2 :1; /* Receive/Transmit Data Bit 2 */
|
| 7471 |
|
|
byte D3 :1; /* Receive/Transmit Data Bit 3 */
|
| 7472 |
|
|
byte D4 :1; /* Receive/Transmit Data Bit 4 */
|
| 7473 |
|
|
byte D5 :1; /* Receive/Transmit Data Bit 5 */
|
| 7474 |
|
|
byte D6 :1; /* Receive/Transmit Data Bit 6 */
|
| 7475 |
|
|
byte D7 :1; /* Receive/Transmit Data Bit 7 */
|
| 7476 |
|
|
} Bits;
|
| 7477 |
|
|
struct {
|
| 7478 |
|
|
byte grpD :8;
|
| 7479 |
|
|
} MergedBits;
|
| 7480 |
|
|
} DLCBDRSTR;
|
| 7481 |
|
|
extern volatile DLCBDRSTR _DLCBDR @(REG_BASE + 0x000000EB);
|
| 7482 |
|
|
#define DLCBDR _DLCBDR.Byte
|
| 7483 |
|
|
#define DLCBDR_D0 _DLCBDR.Bits.D0
|
| 7484 |
|
|
#define DLCBDR_D1 _DLCBDR.Bits.D1
|
| 7485 |
|
|
#define DLCBDR_D2 _DLCBDR.Bits.D2
|
| 7486 |
|
|
#define DLCBDR_D3 _DLCBDR.Bits.D3
|
| 7487 |
|
|
#define DLCBDR_D4 _DLCBDR.Bits.D4
|
| 7488 |
|
|
#define DLCBDR_D5 _DLCBDR.Bits.D5
|
| 7489 |
|
|
#define DLCBDR_D6 _DLCBDR.Bits.D6
|
| 7490 |
|
|
#define DLCBDR_D7 _DLCBDR.Bits.D7
|
| 7491 |
|
|
#define DLCBDR_D _DLCBDR.MergedBits.grpD
|
| 7492 |
|
|
|
| 7493 |
|
|
|
| 7494 |
|
|
/*** DLCBARD - BDLC Analog Round Trip Delay Register; 0x000000EC ***/
|
| 7495 |
|
|
typedef union {
|
| 7496 |
|
|
byte Byte;
|
| 7497 |
|
|
struct {
|
| 7498 |
|
|
byte BO0 :1; /* BDLC Analog Roundtrip Delay Offset Field 0 */
|
| 7499 |
|
|
byte BO1 :1; /* BDLC Analog Roundtrip Delay Offset Field 1 */
|
| 7500 |
|
|
byte BO2 :1; /* BDLC Analog Roundtrip Delay Offset Field 2 */
|
| 7501 |
|
|
byte BO3 :1; /* BDLC Analog Roundtrip Delay Offset Field 3 */
|
| 7502 |
|
|
byte :1;
|
| 7503 |
|
|
byte :1;
|
| 7504 |
|
|
byte RXPOL :1; /* Receive Pin Polarity */
|
| 7505 |
|
|
byte :1;
|
| 7506 |
|
|
} Bits;
|
| 7507 |
|
|
struct {
|
| 7508 |
|
|
byte grpBO :4;
|
| 7509 |
|
|
byte :1;
|
| 7510 |
|
|
byte :1;
|
| 7511 |
|
|
byte :1;
|
| 7512 |
|
|
byte :1;
|
| 7513 |
|
|
} MergedBits;
|
| 7514 |
|
|
} DLCBARDSTR;
|
| 7515 |
|
|
extern volatile DLCBARDSTR _DLCBARD @(REG_BASE + 0x000000EC);
|
| 7516 |
|
|
#define DLCBARD _DLCBARD.Byte
|
| 7517 |
|
|
#define DLCBARD_BO0 _DLCBARD.Bits.BO0
|
| 7518 |
|
|
#define DLCBARD_BO1 _DLCBARD.Bits.BO1
|
| 7519 |
|
|
#define DLCBARD_BO2 _DLCBARD.Bits.BO2
|
| 7520 |
|
|
#define DLCBARD_BO3 _DLCBARD.Bits.BO3
|
| 7521 |
|
|
#define DLCBARD_RXPOL _DLCBARD.Bits.RXPOL
|
| 7522 |
|
|
#define DLCBARD_BO _DLCBARD.MergedBits.grpBO
|
| 7523 |
|
|
|
| 7524 |
|
|
|
| 7525 |
|
|
/*** DLCBRSR - BDLC Rate Select Register; 0x000000ED ***/
|
| 7526 |
|
|
typedef union {
|
| 7527 |
|
|
byte Byte;
|
| 7528 |
|
|
struct {
|
| 7529 |
|
|
byte R0 :1; /* Rate Select 0 */
|
| 7530 |
|
|
byte R1 :1; /* Rate Select 1 */
|
| 7531 |
|
|
byte R2 :1; /* Rate Select 2 */
|
| 7532 |
|
|
byte R3 :1; /* Rate Select 3 */
|
| 7533 |
|
|
byte R4 :1; /* Rate Select 4 */
|
| 7534 |
|
|
byte R5 :1; /* Rate Select 5 */
|
| 7535 |
|
|
byte :1;
|
| 7536 |
|
|
byte :1;
|
| 7537 |
|
|
} Bits;
|
| 7538 |
|
|
struct {
|
| 7539 |
|
|
byte grpR :6;
|
| 7540 |
|
|
byte :1;
|
| 7541 |
|
|
byte :1;
|
| 7542 |
|
|
} MergedBits;
|
| 7543 |
|
|
} DLCBRSRSTR;
|
| 7544 |
|
|
extern volatile DLCBRSRSTR _DLCBRSR @(REG_BASE + 0x000000ED);
|
| 7545 |
|
|
#define DLCBRSR _DLCBRSR.Byte
|
| 7546 |
|
|
#define DLCBRSR_R0 _DLCBRSR.Bits.R0
|
| 7547 |
|
|
#define DLCBRSR_R1 _DLCBRSR.Bits.R1
|
| 7548 |
|
|
#define DLCBRSR_R2 _DLCBRSR.Bits.R2
|
| 7549 |
|
|
#define DLCBRSR_R3 _DLCBRSR.Bits.R3
|
| 7550 |
|
|
#define DLCBRSR_R4 _DLCBRSR.Bits.R4
|
| 7551 |
|
|
#define DLCBRSR_R5 _DLCBRSR.Bits.R5
|
| 7552 |
|
|
#define DLCBRSR_R _DLCBRSR.MergedBits.grpR
|
| 7553 |
|
|
|
| 7554 |
|
|
|
| 7555 |
|
|
/*** DLCSCR - BDLC Control Register; 0x000000EE ***/
|
| 7556 |
|
|
typedef union {
|
| 7557 |
|
|
byte Byte;
|
| 7558 |
|
|
struct {
|
| 7559 |
|
|
byte :1;
|
| 7560 |
|
|
byte :1;
|
| 7561 |
|
|
byte :1;
|
| 7562 |
|
|
byte :1;
|
| 7563 |
|
|
byte BDLCE :1; /* BDLC Enable */
|
| 7564 |
|
|
byte :1;
|
| 7565 |
|
|
byte :1;
|
| 7566 |
|
|
byte :1;
|
| 7567 |
|
|
} Bits;
|
| 7568 |
|
|
} DLCSCRSTR;
|
| 7569 |
|
|
extern volatile DLCSCRSTR _DLCSCR @(REG_BASE + 0x000000EE);
|
| 7570 |
|
|
#define DLCSCR _DLCSCR.Byte
|
| 7571 |
|
|
#define DLCSCR_BDLCE _DLCSCR.Bits.BDLCE
|
| 7572 |
|
|
|
| 7573 |
|
|
|
| 7574 |
|
|
/*** SPI1CR1 - SPI 1 Control Register; 0x000000F0 ***/
|
| 7575 |
|
|
typedef union {
|
| 7576 |
|
|
byte Byte;
|
| 7577 |
|
|
struct {
|
| 7578 |
|
|
byte LSBFE :1; /* SPI 1 LSB-First Enable */
|
| 7579 |
|
|
byte SSOE :1; /* Slave Select Output Enable */
|
| 7580 |
|
|
byte CPHA :1; /* SPI 1 Clock Phase Bit */
|
| 7581 |
|
|
byte CPOL :1; /* SPI 1 Clock Polarity Bit */
|
| 7582 |
|
|
byte MSTR :1; /* SPI 1 Master/Slave Mode Select Bit */
|
| 7583 |
|
|
byte SPTIE :1; /* SPI 1 Transmit Interrupt Enable */
|
| 7584 |
|
|
byte SPE :1; /* SPI 1 System Enable Bit */
|
| 7585 |
|
|
byte SPIE :1; /* SPI 1 Interrupt Enable Bit */
|
| 7586 |
|
|
} Bits;
|
| 7587 |
|
|
} SPI1CR1STR;
|
| 7588 |
|
|
extern volatile SPI1CR1STR _SPI1CR1 @(REG_BASE + 0x000000F0);
|
| 7589 |
|
|
#define SPI1CR1 _SPI1CR1.Byte
|
| 7590 |
|
|
#define SPI1CR1_LSBFE _SPI1CR1.Bits.LSBFE
|
| 7591 |
|
|
#define SPI1CR1_SSOE _SPI1CR1.Bits.SSOE
|
| 7592 |
|
|
#define SPI1CR1_CPHA _SPI1CR1.Bits.CPHA
|
| 7593 |
|
|
#define SPI1CR1_CPOL _SPI1CR1.Bits.CPOL
|
| 7594 |
|
|
#define SPI1CR1_MSTR _SPI1CR1.Bits.MSTR
|
| 7595 |
|
|
#define SPI1CR1_SPTIE _SPI1CR1.Bits.SPTIE
|
| 7596 |
|
|
#define SPI1CR1_SPE _SPI1CR1.Bits.SPE
|
| 7597 |
|
|
#define SPI1CR1_SPIE _SPI1CR1.Bits.SPIE
|
| 7598 |
|
|
|
| 7599 |
|
|
|
| 7600 |
|
|
/*** SPI1CR2 - SPI 1 Control Register 2; 0x000000F1 ***/
|
| 7601 |
|
|
typedef union {
|
| 7602 |
|
|
byte Byte;
|
| 7603 |
|
|
struct {
|
| 7604 |
|
|
byte SPC0 :1; /* Serial Pin Control Bit 0 */
|
| 7605 |
|
|
byte SPISWAI :1; /* SPI 1 Stop in Wait Mode Bit */
|
| 7606 |
|
|
byte :1;
|
| 7607 |
|
|
byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */
|
| 7608 |
|
|
byte MODFEN :1; /* Mode Fault Enable Bit */
|
| 7609 |
|
|
byte :1;
|
| 7610 |
|
|
byte :1;
|
| 7611 |
|
|
byte :1;
|
| 7612 |
|
|
} Bits;
|
| 7613 |
|
|
} SPI1CR2STR;
|
| 7614 |
|
|
extern volatile SPI1CR2STR _SPI1CR2 @(REG_BASE + 0x000000F1);
|
| 7615 |
|
|
#define SPI1CR2 _SPI1CR2.Byte
|
| 7616 |
|
|
#define SPI1CR2_SPC0 _SPI1CR2.Bits.SPC0
|
| 7617 |
|
|
#define SPI1CR2_SPISWAI _SPI1CR2.Bits.SPISWAI
|
| 7618 |
|
|
#define SPI1CR2_BIDIROE _SPI1CR2.Bits.BIDIROE
|
| 7619 |
|
|
#define SPI1CR2_MODFEN _SPI1CR2.Bits.MODFEN
|
| 7620 |
|
|
|
| 7621 |
|
|
|
| 7622 |
|
|
/*** SPI1BR - SPI 1 Baud Rate Register; 0x000000F2 ***/
|
| 7623 |
|
|
typedef union {
|
| 7624 |
|
|
byte Byte;
|
| 7625 |
|
|
struct {
|
| 7626 |
|
|
byte SPR0 :1; /* SPI 1 Baud Rate Selection Bit 0 */
|
| 7627 |
|
|
byte SPR1 :1; /* SPI 1 Baud Rate Selection Bit 1 */
|
| 7628 |
|
|
byte SPR2 :1; /* SPI 1 Baud Rate Selection Bit 2 */
|
| 7629 |
|
|
byte :1;
|
| 7630 |
|
|
byte SPPR0 :1; /* SPI 1 Baud Rate Preselection Bits 0 */
|
| 7631 |
|
|
byte SPPR1 :1; /* SPI 1 Baud Rate Preselection Bits 1 */
|
| 7632 |
|
|
byte SPPR2 :1; /* SPI 1 Baud Rate Preselection Bits 2 */
|
| 7633 |
|
|
byte :1;
|
| 7634 |
|
|
} Bits;
|
| 7635 |
|
|
struct {
|
| 7636 |
|
|
byte grpSPR :3;
|
| 7637 |
|
|
byte :1;
|
| 7638 |
|
|
byte grpSPPR :3;
|
| 7639 |
|
|
byte :1;
|
| 7640 |
|
|
} MergedBits;
|
| 7641 |
|
|
} SPI1BRSTR;
|
| 7642 |
|
|
extern volatile SPI1BRSTR _SPI1BR @(REG_BASE + 0x000000F2);
|
| 7643 |
|
|
#define SPI1BR _SPI1BR.Byte
|
| 7644 |
|
|
#define SPI1BR_SPR0 _SPI1BR.Bits.SPR0
|
| 7645 |
|
|
#define SPI1BR_SPR1 _SPI1BR.Bits.SPR1
|
| 7646 |
|
|
#define SPI1BR_SPR2 _SPI1BR.Bits.SPR2
|
| 7647 |
|
|
#define SPI1BR_SPPR0 _SPI1BR.Bits.SPPR0
|
| 7648 |
|
|
#define SPI1BR_SPPR1 _SPI1BR.Bits.SPPR1
|
| 7649 |
|
|
#define SPI1BR_SPPR2 _SPI1BR.Bits.SPPR2
|
| 7650 |
|
|
#define SPI1BR_SPR _SPI1BR.MergedBits.grpSPR
|
| 7651 |
|
|
#define SPI1BR_SPPR _SPI1BR.MergedBits.grpSPPR
|
| 7652 |
|
|
|
| 7653 |
|
|
|
| 7654 |
|
|
/*** SPI1SR - SPI 1 Status Register; 0x000000F3 ***/
|
| 7655 |
|
|
typedef union {
|
| 7656 |
|
|
byte Byte;
|
| 7657 |
|
|
struct {
|
| 7658 |
|
|
byte :1;
|
| 7659 |
|
|
byte :1;
|
| 7660 |
|
|
byte :1;
|
| 7661 |
|
|
byte :1;
|
| 7662 |
|
|
byte MODF :1; /* Mode Fault Flag */
|
| 7663 |
|
|
byte SPTEF :1; /* SPI 1 Transmit Empty Interrupt Flag */
|
| 7664 |
|
|
byte :1;
|
| 7665 |
|
|
byte SPIF :1; /* SPIF Receive Interrupt Flag */
|
| 7666 |
|
|
} Bits;
|
| 7667 |
|
|
} SPI1SRSTR;
|
| 7668 |
|
|
extern volatile SPI1SRSTR _SPI1SR @(REG_BASE + 0x000000F3);
|
| 7669 |
|
|
#define SPI1SR _SPI1SR.Byte
|
| 7670 |
|
|
#define SPI1SR_MODF _SPI1SR.Bits.MODF
|
| 7671 |
|
|
#define SPI1SR_SPTEF _SPI1SR.Bits.SPTEF
|
| 7672 |
|
|
#define SPI1SR_SPIF _SPI1SR.Bits.SPIF
|
| 7673 |
|
|
|
| 7674 |
|
|
|
| 7675 |
|
|
/*** SPI1DR - SPI 1 Data Register; 0x000000F5 ***/
|
| 7676 |
|
|
typedef union {
|
| 7677 |
|
|
byte Byte;
|
| 7678 |
|
|
struct {
|
| 7679 |
|
|
byte grpBIT :8;
|
| 7680 |
|
|
} MergedBits;
|
| 7681 |
|
|
} SPI1DRSTR;
|
| 7682 |
|
|
extern volatile SPI1DRSTR _SPI1DR @(REG_BASE + 0x000000F5);
|
| 7683 |
|
|
#define SPI1DR _SPI1DR.Byte
|
| 7684 |
|
|
#define SPI1DR_BIT _SPI1DR.MergedBits.grpBIT
|
| 7685 |
|
|
|
| 7686 |
|
|
|
| 7687 |
|
|
/*** SPI2CR1 - SPI 2 Control Register; 0x000000F8 ***/
|
| 7688 |
|
|
typedef union {
|
| 7689 |
|
|
byte Byte;
|
| 7690 |
|
|
struct {
|
| 7691 |
|
|
byte LSBFE :1; /* SPI 2 LSB-First Enable */
|
| 7692 |
|
|
byte SSOE :1; /* Slave Select Output Enable */
|
| 7693 |
|
|
byte CPHA :1; /* SPI 2 Clock Phase Bit */
|
| 7694 |
|
|
byte CPOL :1; /* SPI 2 Clock Polarity Bit */
|
| 7695 |
|
|
byte MSTR :1; /* SPI 2 Master/Slave Mode Select Bit */
|
| 7696 |
|
|
byte SPTIE :1; /* SPI 2 Transmit Interrupt Enable */
|
| 7697 |
|
|
byte SPE :1; /* SPI 2 System Enable Bit */
|
| 7698 |
|
|
byte SPIE :1; /* SPI 2 Interrupt Enable Bit */
|
| 7699 |
|
|
} Bits;
|
| 7700 |
|
|
} SPI2CR1STR;
|
| 7701 |
|
|
extern volatile SPI2CR1STR _SPI2CR1 @(REG_BASE + 0x000000F8);
|
| 7702 |
|
|
#define SPI2CR1 _SPI2CR1.Byte
|
| 7703 |
|
|
#define SPI2CR1_LSBFE _SPI2CR1.Bits.LSBFE
|
| 7704 |
|
|
#define SPI2CR1_SSOE _SPI2CR1.Bits.SSOE
|
| 7705 |
|
|
#define SPI2CR1_CPHA _SPI2CR1.Bits.CPHA
|
| 7706 |
|
|
#define SPI2CR1_CPOL _SPI2CR1.Bits.CPOL
|
| 7707 |
|
|
#define SPI2CR1_MSTR _SPI2CR1.Bits.MSTR
|
| 7708 |
|
|
#define SPI2CR1_SPTIE _SPI2CR1.Bits.SPTIE
|
| 7709 |
|
|
#define SPI2CR1_SPE _SPI2CR1.Bits.SPE
|
| 7710 |
|
|
#define SPI2CR1_SPIE _SPI2CR1.Bits.SPIE
|
| 7711 |
|
|
|
| 7712 |
|
|
|
| 7713 |
|
|
/*** SPI2CR2 - SPI 2 Control Register 2; 0x000000F9 ***/
|
| 7714 |
|
|
typedef union {
|
| 7715 |
|
|
byte Byte;
|
| 7716 |
|
|
struct {
|
| 7717 |
|
|
byte SPC0 :1; /* Serial Pin Control Bit 0 */
|
| 7718 |
|
|
byte SPISWAI :1; /* SPI 2 Stop in Wait Mode Bit */
|
| 7719 |
|
|
byte :1;
|
| 7720 |
|
|
byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */
|
| 7721 |
|
|
byte MODFEN :1; /* Mode Fault Enable Bit */
|
| 7722 |
|
|
byte :1;
|
| 7723 |
|
|
byte :1;
|
| 7724 |
|
|
byte :1;
|
| 7725 |
|
|
} Bits;
|
| 7726 |
|
|
} SPI2CR2STR;
|
| 7727 |
|
|
extern volatile SPI2CR2STR _SPI2CR2 @(REG_BASE + 0x000000F9);
|
| 7728 |
|
|
#define SPI2CR2 _SPI2CR2.Byte
|
| 7729 |
|
|
#define SPI2CR2_SPC0 _SPI2CR2.Bits.SPC0
|
| 7730 |
|
|
#define SPI2CR2_SPISWAI _SPI2CR2.Bits.SPISWAI
|
| 7731 |
|
|
#define SPI2CR2_BIDIROE _SPI2CR2.Bits.BIDIROE
|
| 7732 |
|
|
#define SPI2CR2_MODFEN _SPI2CR2.Bits.MODFEN
|
| 7733 |
|
|
|
| 7734 |
|
|
|
| 7735 |
|
|
/*** SPI2BR - SPI 2 Baud Rate Register; 0x000000FA ***/
|
| 7736 |
|
|
typedef union {
|
| 7737 |
|
|
byte Byte;
|
| 7738 |
|
|
struct {
|
| 7739 |
|
|
byte SPR0 :1; /* SPI 2 Baud Rate Selection Bit 0 */
|
| 7740 |
|
|
byte SPR1 :1; /* SPI 2 Baud Rate Selection Bit 1 */
|
| 7741 |
|
|
byte SPR2 :1; /* SPI 2 Baud Rate Selection Bit 2 */
|
| 7742 |
|
|
byte :1;
|
| 7743 |
|
|
byte SPPR0 :1; /* SPI 2 Baud Rate Preselection Bits 0 */
|
| 7744 |
|
|
byte SPPR1 :1; /* SPI 2 Baud Rate Preselection Bits 1 */
|
| 7745 |
|
|
byte SPPR2 :1; /* SPI 2 Baud Rate Preselection Bits 2 */
|
| 7746 |
|
|
byte :1;
|
| 7747 |
|
|
} Bits;
|
| 7748 |
|
|
struct {
|
| 7749 |
|
|
byte grpSPR :3;
|
| 7750 |
|
|
byte :1;
|
| 7751 |
|
|
byte grpSPPR :3;
|
| 7752 |
|
|
byte :1;
|
| 7753 |
|
|
} MergedBits;
|
| 7754 |
|
|
} SPI2BRSTR;
|
| 7755 |
|
|
extern volatile SPI2BRSTR _SPI2BR @(REG_BASE + 0x000000FA);
|
| 7756 |
|
|
#define SPI2BR _SPI2BR.Byte
|
| 7757 |
|
|
#define SPI2BR_SPR0 _SPI2BR.Bits.SPR0
|
| 7758 |
|
|
#define SPI2BR_SPR1 _SPI2BR.Bits.SPR1
|
| 7759 |
|
|
#define SPI2BR_SPR2 _SPI2BR.Bits.SPR2
|
| 7760 |
|
|
#define SPI2BR_SPPR0 _SPI2BR.Bits.SPPR0
|
| 7761 |
|
|
#define SPI2BR_SPPR1 _SPI2BR.Bits.SPPR1
|
| 7762 |
|
|
#define SPI2BR_SPPR2 _SPI2BR.Bits.SPPR2
|
| 7763 |
|
|
#define SPI2BR_SPR _SPI2BR.MergedBits.grpSPR
|
| 7764 |
|
|
#define SPI2BR_SPPR _SPI2BR.MergedBits.grpSPPR
|
| 7765 |
|
|
|
| 7766 |
|
|
|
| 7767 |
|
|
/*** SPI2SR - SPI 2 Status Register; 0x000000FB ***/
|
| 7768 |
|
|
typedef union {
|
| 7769 |
|
|
byte Byte;
|
| 7770 |
|
|
struct {
|
| 7771 |
|
|
byte :1;
|
| 7772 |
|
|
byte :1;
|
| 7773 |
|
|
byte :1;
|
| 7774 |
|
|
byte :1;
|
| 7775 |
|
|
byte MODF :1; /* Mode Fault Flag */
|
| 7776 |
|
|
byte SPTEF :1; /* SPI 2 Transmit Empty Interrupt Flag */
|
| 7777 |
|
|
byte :1;
|
| 7778 |
|
|
byte SPIF :1; /* SPIF Receive Interrupt Flag */
|
| 7779 |
|
|
} Bits;
|
| 7780 |
|
|
} SPI2SRSTR;
|
| 7781 |
|
|
extern volatile SPI2SRSTR _SPI2SR @(REG_BASE + 0x000000FB);
|
| 7782 |
|
|
#define SPI2SR _SPI2SR.Byte
|
| 7783 |
|
|
#define SPI2SR_MODF _SPI2SR.Bits.MODF
|
| 7784 |
|
|
#define SPI2SR_SPTEF _SPI2SR.Bits.SPTEF
|
| 7785 |
|
|
#define SPI2SR_SPIF _SPI2SR.Bits.SPIF
|
| 7786 |
|
|
|
| 7787 |
|
|
|
| 7788 |
|
|
/*** SPI2DR - SPI 2 Data Register; 0x000000FD ***/
|
| 7789 |
|
|
typedef union {
|
| 7790 |
|
|
byte Byte;
|
| 7791 |
|
|
struct {
|
| 7792 |
|
|
byte grpBIT :8;
|
| 7793 |
|
|
} MergedBits;
|
| 7794 |
|
|
} SPI2DRSTR;
|
| 7795 |
|
|
extern volatile SPI2DRSTR _SPI2DR @(REG_BASE + 0x000000FD);
|
| 7796 |
|
|
#define SPI2DR _SPI2DR.Byte
|
| 7797 |
|
|
#define SPI2DR_BIT _SPI2DR.MergedBits.grpBIT
|
| 7798 |
|
|
|
| 7799 |
|
|
|
| 7800 |
|
|
/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/
|
| 7801 |
|
|
typedef union {
|
| 7802 |
|
|
byte Byte;
|
| 7803 |
|
|
struct {
|
| 7804 |
|
|
byte FDIV0 :1; /* Flash Clock Divider Bit 0 */
|
| 7805 |
|
|
byte FDIV1 :1; /* Flash Clock Divider Bit 1 */
|
| 7806 |
|
|
byte FDIV2 :1; /* Flash Clock Divider Bit 2 */
|
| 7807 |
|
|
byte FDIV3 :1; /* Flash Clock Divider Bit 3 */
|
| 7808 |
|
|
byte FDIV4 :1; /* Flash Clock Divider Bit 4 */
|
| 7809 |
|
|
byte FDIV5 :1; /* Flash Clock Divider Bit 5 */
|
| 7810 |
|
|
byte PRDIV8 :1; /* Enable Prescaler by 8 */
|
| 7811 |
|
|
byte FDIVLD :1; /* Flash Clock Divider Loaded */
|
| 7812 |
|
|
} Bits;
|
| 7813 |
|
|
struct {
|
| 7814 |
|
|
byte grpFDIV :6;
|
| 7815 |
|
|
byte grpPRDIV_8 :1;
|
| 7816 |
|
|
byte :1;
|
| 7817 |
|
|
} MergedBits;
|
| 7818 |
|
|
} FCLKDIVSTR;
|
| 7819 |
|
|
extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100);
|
| 7820 |
|
|
#define FCLKDIV _FCLKDIV.Byte
|
| 7821 |
|
|
#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0
|
| 7822 |
|
|
#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1
|
| 7823 |
|
|
#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2
|
| 7824 |
|
|
#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3
|
| 7825 |
|
|
#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4
|
| 7826 |
|
|
#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5
|
| 7827 |
|
|
#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8
|
| 7828 |
|
|
#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD
|
| 7829 |
|
|
#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV
|
| 7830 |
|
|
|
| 7831 |
|
|
|
| 7832 |
|
|
/*** FSEC - Flash Security Register; 0x00000101 ***/
|
| 7833 |
|
|
typedef union {
|
| 7834 |
|
|
byte Byte;
|
| 7835 |
|
|
struct {
|
| 7836 |
|
|
byte SEC0 :1; /* Memory security bit 0 */
|
| 7837 |
|
|
byte SEC1 :1; /* Memory security bit 1 */
|
| 7838 |
|
|
byte NV2 :1; /* Non Volatile flag bit 2 */
|
| 7839 |
|
|
byte NV3 :1; /* Non Volatile flag bit 3 */
|
| 7840 |
|
|
byte NV4 :1; /* Non Volatile flag bit 4 */
|
| 7841 |
|
|
byte NV5 :1; /* Non Volatile flag bit 5 */
|
| 7842 |
|
|
byte NV6 :1; /* Non Volatile flag bit 6 */
|
| 7843 |
|
|
byte KEYEN :1; /* Enable backdoor key to security */
|
| 7844 |
|
|
} Bits;
|
| 7845 |
|
|
struct {
|
| 7846 |
|
|
byte grpSEC :2;
|
| 7847 |
|
|
byte grpNV_2 :5;
|
| 7848 |
|
|
byte :1;
|
| 7849 |
|
|
} MergedBits;
|
| 7850 |
|
|
} FSECSTR;
|
| 7851 |
|
|
extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101);
|
| 7852 |
|
|
#define FSEC _FSEC.Byte
|
| 7853 |
|
|
#define FSEC_SEC0 _FSEC.Bits.SEC0
|
| 7854 |
|
|
#define FSEC_SEC1 _FSEC.Bits.SEC1
|
| 7855 |
|
|
#define FSEC_NV2 _FSEC.Bits.NV2
|
| 7856 |
|
|
#define FSEC_NV3 _FSEC.Bits.NV3
|
| 7857 |
|
|
#define FSEC_NV4 _FSEC.Bits.NV4
|
| 7858 |
|
|
#define FSEC_NV5 _FSEC.Bits.NV5
|
| 7859 |
|
|
#define FSEC_NV6 _FSEC.Bits.NV6
|
| 7860 |
|
|
#define FSEC_KEYEN _FSEC.Bits.KEYEN
|
| 7861 |
|
|
#define FSEC_SEC _FSEC.MergedBits.grpSEC
|
| 7862 |
|
|
#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2
|
| 7863 |
|
|
#define FSEC_NV FSEC_NV_2
|
| 7864 |
|
|
|
| 7865 |
|
|
|
| 7866 |
|
|
/*** FCNFG - Flash Configuration Register; 0x00000103 ***/
|
| 7867 |
|
|
typedef union {
|
| 7868 |
|
|
byte Byte;
|
| 7869 |
|
|
struct {
|
| 7870 |
|
|
byte BKSEL0 :1; /* Register bank select 0 */
|
| 7871 |
|
|
byte BKSEL1 :1; /* Register bank select 1 */
|
| 7872 |
|
|
byte :1;
|
| 7873 |
|
|
byte :1;
|
| 7874 |
|
|
byte :1;
|
| 7875 |
|
|
byte KEYACC :1; /* Enable Security Key Writing */
|
| 7876 |
|
|
byte CCIE :1; /* Command Complete Interrupt Enable */
|
| 7877 |
|
|
byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */
|
| 7878 |
|
|
} Bits;
|
| 7879 |
|
|
struct {
|
| 7880 |
|
|
byte grpBKSEL :2;
|
| 7881 |
|
|
byte :1;
|
| 7882 |
|
|
byte :1;
|
| 7883 |
|
|
byte :1;
|
| 7884 |
|
|
byte :1;
|
| 7885 |
|
|
byte :1;
|
| 7886 |
|
|
byte :1;
|
| 7887 |
|
|
} MergedBits;
|
| 7888 |
|
|
} FCNFGSTR;
|
| 7889 |
|
|
extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103);
|
| 7890 |
|
|
#define FCNFG _FCNFG.Byte
|
| 7891 |
|
|
#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0
|
| 7892 |
|
|
#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1
|
| 7893 |
|
|
#define FCNFG_KEYACC _FCNFG.Bits.KEYACC
|
| 7894 |
|
|
#define FCNFG_CCIE _FCNFG.Bits.CCIE
|
| 7895 |
|
|
#define FCNFG_CBEIE _FCNFG.Bits.CBEIE
|
| 7896 |
|
|
#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL
|
| 7897 |
|
|
|
| 7898 |
|
|
|
| 7899 |
|
|
/*** FPROT - Flash Protection Register; 0x00000104 ***/
|
| 7900 |
|
|
typedef union {
|
| 7901 |
|
|
byte Byte;
|
| 7902 |
|
|
struct {
|
| 7903 |
|
|
byte FPLS0 :1; /* Flash Protection Lower Address size 0 */
|
| 7904 |
|
|
byte FPLS1 :1; /* Flash Protection Lower Address size 1 */
|
| 7905 |
|
|
byte FPLDIS :1; /* Flash Protection Lower address range disable */
|
| 7906 |
|
|
byte FPHS0 :1; /* Flash Protection Higher address size 0 */
|
| 7907 |
|
|
byte FPHS1 :1; /* Flash Protection Higher address size 1 */
|
| 7908 |
|
|
byte FPHDIS :1; /* Flash Protection Higher address range disable */
|
| 7909 |
|
|
byte NV6 :1; /* Non Volatile Flag Bit */
|
| 7910 |
|
|
byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */
|
| 7911 |
|
|
} Bits;
|
| 7912 |
|
|
struct {
|
| 7913 |
|
|
byte grpFPLS :2;
|
| 7914 |
|
|
byte :1;
|
| 7915 |
|
|
byte grpFPHS :2;
|
| 7916 |
|
|
byte :1;
|
| 7917 |
|
|
byte grpNV_6 :1;
|
| 7918 |
|
|
byte :1;
|
| 7919 |
|
|
} MergedBits;
|
| 7920 |
|
|
} FPROTSTR;
|
| 7921 |
|
|
extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104);
|
| 7922 |
|
|
#define FPROT _FPROT.Byte
|
| 7923 |
|
|
#define FPROT_FPLS0 _FPROT.Bits.FPLS0
|
| 7924 |
|
|
#define FPROT_FPLS1 _FPROT.Bits.FPLS1
|
| 7925 |
|
|
#define FPROT_FPLDIS _FPROT.Bits.FPLDIS
|
| 7926 |
|
|
#define FPROT_FPHS0 _FPROT.Bits.FPHS0
|
| 7927 |
|
|
#define FPROT_FPHS1 _FPROT.Bits.FPHS1
|
| 7928 |
|
|
#define FPROT_FPHDIS _FPROT.Bits.FPHDIS
|
| 7929 |
|
|
#define FPROT_NV6 _FPROT.Bits.NV6
|
| 7930 |
|
|
#define FPROT_FPOPEN _FPROT.Bits.FPOPEN
|
| 7931 |
|
|
#define FPROT_FPLS _FPROT.MergedBits.grpFPLS
|
| 7932 |
|
|
#define FPROT_FPHS _FPROT.MergedBits.grpFPHS
|
| 7933 |
|
|
|
| 7934 |
|
|
|
| 7935 |
|
|
/*** FSTAT - Flash Status Register; 0x00000105 ***/
|
| 7936 |
|
|
typedef union {
|
| 7937 |
|
|
byte Byte;
|
| 7938 |
|
|
struct {
|
| 7939 |
|
|
byte :1;
|
| 7940 |
|
|
byte :1;
|
| 7941 |
|
|
byte BLANK :1; /* Blank Verify Flag */
|
| 7942 |
|
|
byte :1;
|
| 7943 |
|
|
byte ACCERR :1; /* Access error */
|
| 7944 |
|
|
byte PVIOL :1; /* Protection violation */
|
| 7945 |
|
|
byte CCIF :1; /* Command Complete Interrupt Flag */
|
| 7946 |
|
|
byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */
|
| 7947 |
|
|
} Bits;
|
| 7948 |
|
|
} FSTATSTR;
|
| 7949 |
|
|
extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105);
|
| 7950 |
|
|
#define FSTAT _FSTAT.Byte
|
| 7951 |
|
|
#define FSTAT_BLANK _FSTAT.Bits.BLANK
|
| 7952 |
|
|
#define FSTAT_ACCERR _FSTAT.Bits.ACCERR
|
| 7953 |
|
|
#define FSTAT_PVIOL _FSTAT.Bits.PVIOL
|
| 7954 |
|
|
#define FSTAT_CCIF _FSTAT.Bits.CCIF
|
| 7955 |
|
|
#define FSTAT_CBEIF _FSTAT.Bits.CBEIF
|
| 7956 |
|
|
|
| 7957 |
|
|
|
| 7958 |
|
|
/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/
|
| 7959 |
|
|
typedef union {
|
| 7960 |
|
|
byte Byte;
|
| 7961 |
|
|
struct {
|
| 7962 |
|
|
byte CMDB0 :1; /* NVM User Mode Command Bit 0 */
|
| 7963 |
|
|
byte :1;
|
| 7964 |
|
|
byte CMDB2 :1; /* NVM User Mode Command Bit 2 */
|
| 7965 |
|
|
byte :1;
|
| 7966 |
|
|
byte :1;
|
| 7967 |
|
|
byte CMDB5 :1; /* NVM User Mode Command Bit 5 */
|
| 7968 |
|
|
byte CMDB6 :1; /* NVM User Mode Command Bit 6 */
|
| 7969 |
|
|
byte :1;
|
| 7970 |
|
|
} Bits;
|
| 7971 |
|
|
struct {
|
| 7972 |
|
|
byte grpCMDB :1;
|
| 7973 |
|
|
byte :1;
|
| 7974 |
|
|
byte grpCMDB_2 :1;
|
| 7975 |
|
|
byte :1;
|
| 7976 |
|
|
byte :1;
|
| 7977 |
|
|
byte grpCMDB_5 :2;
|
| 7978 |
|
|
byte :1;
|
| 7979 |
|
|
} MergedBits;
|
| 7980 |
|
|
} FCMDSTR;
|
| 7981 |
|
|
extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106);
|
| 7982 |
|
|
#define FCMD _FCMD.Byte
|
| 7983 |
|
|
#define FCMD_CMDB0 _FCMD.Bits.CMDB0
|
| 7984 |
|
|
#define FCMD_CMDB2 _FCMD.Bits.CMDB2
|
| 7985 |
|
|
#define FCMD_CMDB5 _FCMD.Bits.CMDB5
|
| 7986 |
|
|
#define FCMD_CMDB6 _FCMD.Bits.CMDB6
|
| 7987 |
|
|
#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5
|
| 7988 |
|
|
#define FCMD_CMDB FCMD_CMDB_5
|
| 7989 |
|
|
|
| 7990 |
|
|
|
| 7991 |
|
|
/*** ECLKDIV - EEPROM Clock Divider Register; 0x00000110 ***/
|
| 7992 |
|
|
typedef union {
|
| 7993 |
|
|
byte Byte;
|
| 7994 |
|
|
struct {
|
| 7995 |
|
|
byte EDIV0 :1; /* EEPROM Clock Divider 0 */
|
| 7996 |
|
|
byte EDIV1 :1; /* EEPROM Clock Divider 1 */
|
| 7997 |
|
|
byte EDIV2 :1; /* EEPROM Clock Divider 2 */
|
| 7998 |
|
|
byte EDIV3 :1; /* EEPROM Clock Divider 3 */
|
| 7999 |
|
|
byte EDIV4 :1; /* EEPROM Clock Divider 4 */
|
| 8000 |
|
|
byte EDIV5 :1; /* EEPROM Clock Divider 5 */
|
| 8001 |
|
|
byte PRDIV8 :1; /* Enable Prescaler by 8 */
|
| 8002 |
|
|
byte EDIVLD :1; /* EEPROM Clock Divider Loaded */
|
| 8003 |
|
|
} Bits;
|
| 8004 |
|
|
struct {
|
| 8005 |
|
|
byte grpEDIV :6;
|
| 8006 |
|
|
byte grpPRDIV_8 :1;
|
| 8007 |
|
|
byte :1;
|
| 8008 |
|
|
} MergedBits;
|
| 8009 |
|
|
} ECLKDIVSTR;
|
| 8010 |
|
|
extern volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110);
|
| 8011 |
|
|
#define ECLKDIV _ECLKDIV.Byte
|
| 8012 |
|
|
#define ECLKDIV_EDIV0 _ECLKDIV.Bits.EDIV0
|
| 8013 |
|
|
#define ECLKDIV_EDIV1 _ECLKDIV.Bits.EDIV1
|
| 8014 |
|
|
#define ECLKDIV_EDIV2 _ECLKDIV.Bits.EDIV2
|
| 8015 |
|
|
#define ECLKDIV_EDIV3 _ECLKDIV.Bits.EDIV3
|
| 8016 |
|
|
#define ECLKDIV_EDIV4 _ECLKDIV.Bits.EDIV4
|
| 8017 |
|
|
#define ECLKDIV_EDIV5 _ECLKDIV.Bits.EDIV5
|
| 8018 |
|
|
#define ECLKDIV_PRDIV8 _ECLKDIV.Bits.PRDIV8
|
| 8019 |
|
|
#define ECLKDIV_EDIVLD _ECLKDIV.Bits.EDIVLD
|
| 8020 |
|
|
#define ECLKDIV_EDIV _ECLKDIV.MergedBits.grpEDIV
|
| 8021 |
|
|
|
| 8022 |
|
|
|
| 8023 |
|
|
/*** ECNFG - EEPROM Configuration Register; 0x00000113 ***/
|
| 8024 |
|
|
typedef union {
|
| 8025 |
|
|
byte Byte;
|
| 8026 |
|
|
struct {
|
| 8027 |
|
|
byte :1;
|
| 8028 |
|
|
byte :1;
|
| 8029 |
|
|
byte :1;
|
| 8030 |
|
|
byte :1;
|
| 8031 |
|
|
byte :1;
|
| 8032 |
|
|
byte :1;
|
| 8033 |
|
|
byte CCIE :1; /* Command Complete Interrupt Enable */
|
| 8034 |
|
|
byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */
|
| 8035 |
|
|
} Bits;
|
| 8036 |
|
|
} ECNFGSTR;
|
| 8037 |
|
|
extern volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113);
|
| 8038 |
|
|
#define ECNFG _ECNFG.Byte
|
| 8039 |
|
|
#define ECNFG_CCIE _ECNFG.Bits.CCIE
|
| 8040 |
|
|
#define ECNFG_CBEIE _ECNFG.Bits.CBEIE
|
| 8041 |
|
|
|
| 8042 |
|
|
|
| 8043 |
|
|
/*** EPROT - EEPROM Protection Register; 0x00000114 ***/
|
| 8044 |
|
|
typedef union {
|
| 8045 |
|
|
byte Byte;
|
| 8046 |
|
|
struct {
|
| 8047 |
|
|
byte EP0 :1; /* EEPROM Protection address size 0 */
|
| 8048 |
|
|
byte EP1 :1; /* EEPROM Protection address size 1 */
|
| 8049 |
|
|
byte EP2 :1; /* EEPROM Protection address size 2 */
|
| 8050 |
|
|
byte EPDIS :1; /* EEPROM Protection disable */
|
| 8051 |
|
|
byte :1;
|
| 8052 |
|
|
byte :1;
|
| 8053 |
|
|
byte :1;
|
| 8054 |
|
|
byte EPOPEN :1; /* Opens the EEPROM block or a subsection of it for program or erase */
|
| 8055 |
|
|
} Bits;
|
| 8056 |
|
|
struct {
|
| 8057 |
|
|
byte grpEP :3;
|
| 8058 |
|
|
byte :1;
|
| 8059 |
|
|
byte :1;
|
| 8060 |
|
|
byte :1;
|
| 8061 |
|
|
byte :1;
|
| 8062 |
|
|
byte :1;
|
| 8063 |
|
|
} MergedBits;
|
| 8064 |
|
|
} EPROTSTR;
|
| 8065 |
|
|
extern volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114);
|
| 8066 |
|
|
#define EPROT _EPROT.Byte
|
| 8067 |
|
|
#define EPROT_EP0 _EPROT.Bits.EP0
|
| 8068 |
|
|
#define EPROT_EP1 _EPROT.Bits.EP1
|
| 8069 |
|
|
#define EPROT_EP2 _EPROT.Bits.EP2
|
| 8070 |
|
|
#define EPROT_EPDIS _EPROT.Bits.EPDIS
|
| 8071 |
|
|
#define EPROT_EPOPEN _EPROT.Bits.EPOPEN
|
| 8072 |
|
|
#define EPROT_EP _EPROT.MergedBits.grpEP
|
| 8073 |
|
|
|
| 8074 |
|
|
|
| 8075 |
|
|
/*** ESTAT - EEPROM Status Register; 0x00000115 ***/
|
| 8076 |
|
|
typedef union {
|
| 8077 |
|
|
byte Byte;
|
| 8078 |
|
|
struct {
|
| 8079 |
|
|
byte :1;
|
| 8080 |
|
|
byte :1;
|
| 8081 |
|
|
byte BLANK :1; /* Blank Verify Flag */
|
| 8082 |
|
|
byte :1;
|
| 8083 |
|
|
byte ACCERR :1; /* Access error */
|
| 8084 |
|
|
byte PVIOL :1; /* Protection violation */
|
| 8085 |
|
|
byte CCIF :1; /* Command Complete Interrupt Flag */
|
| 8086 |
|
|
byte CBEIF :1; /* Command Buffer Empty Interrupt Flag */
|
| 8087 |
|
|
} Bits;
|
| 8088 |
|
|
} ESTATSTR;
|
| 8089 |
|
|
extern volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115);
|
| 8090 |
|
|
#define ESTAT _ESTAT.Byte
|
| 8091 |
|
|
#define ESTAT_BLANK _ESTAT.Bits.BLANK
|
| 8092 |
|
|
#define ESTAT_ACCERR _ESTAT.Bits.ACCERR
|
| 8093 |
|
|
#define ESTAT_PVIOL _ESTAT.Bits.PVIOL
|
| 8094 |
|
|
#define ESTAT_CCIF _ESTAT.Bits.CCIF
|
| 8095 |
|
|
#define ESTAT_CBEIF _ESTAT.Bits.CBEIF
|
| 8096 |
|
|
|
| 8097 |
|
|
|
| 8098 |
|
|
/*** ECMD - EEPROM Command Buffer and Register; 0x00000116 ***/
|
| 8099 |
|
|
typedef union {
|
| 8100 |
|
|
byte Byte;
|
| 8101 |
|
|
struct {
|
| 8102 |
|
|
byte CMDB0 :1; /* EEPROM User Mode Command 0 */
|
| 8103 |
|
|
byte :1;
|
| 8104 |
|
|
byte CMDB2 :1; /* EEPROM User Mode Command 2 */
|
| 8105 |
|
|
byte :1;
|
| 8106 |
|
|
byte :1;
|
| 8107 |
|
|
byte CMDB5 :1; /* EEPROM User Mode Command 5 */
|
| 8108 |
|
|
byte CMDB6 :1; /* EEPROM User Mode Command 6 */
|
| 8109 |
|
|
byte :1;
|
| 8110 |
|
|
} Bits;
|
| 8111 |
|
|
struct {
|
| 8112 |
|
|
byte grpCMDB :1;
|
| 8113 |
|
|
byte :1;
|
| 8114 |
|
|
byte grpCMDB_2 :1;
|
| 8115 |
|
|
byte :1;
|
| 8116 |
|
|
byte :1;
|
| 8117 |
|
|
byte grpCMDB_5 :2;
|
| 8118 |
|
|
byte :1;
|
| 8119 |
|
|
} MergedBits;
|
| 8120 |
|
|
} ECMDSTR;
|
| 8121 |
|
|
extern volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116);
|
| 8122 |
|
|
#define ECMD _ECMD.Byte
|
| 8123 |
|
|
#define ECMD_CMDB0 _ECMD.Bits.CMDB0
|
| 8124 |
|
|
#define ECMD_CMDB2 _ECMD.Bits.CMDB2
|
| 8125 |
|
|
#define ECMD_CMDB5 _ECMD.Bits.CMDB5
|
| 8126 |
|
|
#define ECMD_CMDB6 _ECMD.Bits.CMDB6
|
| 8127 |
|
|
#define ECMD_CMDB_5 _ECMD.MergedBits.grpCMDB_5
|
| 8128 |
|
|
#define ECMD_CMDB ECMD_CMDB_5
|
| 8129 |
|
|
|
| 8130 |
|
|
|
| 8131 |
|
|
/*** ATD1STAT0 - ATD 1 Status Register 0; 0x00000126 ***/
|
| 8132 |
|
|
typedef union {
|
| 8133 |
|
|
byte Byte;
|
| 8134 |
|
|
struct {
|
| 8135 |
|
|
byte CC0 :1; /* Conversion Counter 0 */
|
| 8136 |
|
|
byte CC1 :1; /* Conversion Counter 1 */
|
| 8137 |
|
|
byte CC2 :1; /* Conversion Counter 2 */
|
| 8138 |
|
|
byte :1;
|
| 8139 |
|
|
byte FIFOR :1; /* FIFO Over Run Flag */
|
| 8140 |
|
|
byte ETORF :1; /* External Trigger Overrun Flag */
|
| 8141 |
|
|
byte :1;
|
| 8142 |
|
|
byte SCF :1; /* Sequence Complete Flag */
|
| 8143 |
|
|
} Bits;
|
| 8144 |
|
|
struct {
|
| 8145 |
|
|
byte grpCC :3;
|
| 8146 |
|
|
byte :1;
|
| 8147 |
|
|
byte :1;
|
| 8148 |
|
|
byte :1;
|
| 8149 |
|
|
byte :1;
|
| 8150 |
|
|
byte :1;
|
| 8151 |
|
|
} MergedBits;
|
| 8152 |
|
|
} ATD1STAT0STR;
|
| 8153 |
|
|
extern volatile ATD1STAT0STR _ATD1STAT0 @(REG_BASE + 0x00000126);
|
| 8154 |
|
|
#define ATD1STAT0 _ATD1STAT0.Byte
|
| 8155 |
|
|
#define ATD1STAT0_CC0 _ATD1STAT0.Bits.CC0
|
| 8156 |
|
|
#define ATD1STAT0_CC1 _ATD1STAT0.Bits.CC1
|
| 8157 |
|
|
#define ATD1STAT0_CC2 _ATD1STAT0.Bits.CC2
|
| 8158 |
|
|
#define ATD1STAT0_FIFOR _ATD1STAT0.Bits.FIFOR
|
| 8159 |
|
|
#define ATD1STAT0_ETORF _ATD1STAT0.Bits.ETORF
|
| 8160 |
|
|
#define ATD1STAT0_SCF _ATD1STAT0.Bits.SCF
|
| 8161 |
|
|
#define ATD1STAT0_CC _ATD1STAT0.MergedBits.grpCC
|
| 8162 |
|
|
|
| 8163 |
|
|
|
| 8164 |
|
|
/*** ATD1STAT1 - ATD 1 Status Register 1; 0x0000012B ***/
|
| 8165 |
|
|
typedef union {
|
| 8166 |
|
|
byte Byte;
|
| 8167 |
|
|
struct {
|
| 8168 |
|
|
byte CCF0 :1; /* Conversion Complete Flag 0 */
|
| 8169 |
|
|
byte CCF1 :1; /* Conversion Complete Flag 1 */
|
| 8170 |
|
|
byte CCF2 :1; /* Conversion Complete Flag 2 */
|
| 8171 |
|
|
byte CCF3 :1; /* Conversion Complete Flag 3 */
|
| 8172 |
|
|
byte CCF4 :1; /* Conversion Complete Flag 4 */
|
| 8173 |
|
|
byte CCF5 :1; /* Conversion Complete Flag 5 */
|
| 8174 |
|
|
byte CCF6 :1; /* Conversion Complete Flag 6 */
|
| 8175 |
|
|
byte CCF7 :1; /* Conversion Complete Flag 7 */
|
| 8176 |
|
|
} Bits;
|
| 8177 |
|
|
struct {
|
| 8178 |
|
|
byte grpCCF :8;
|
| 8179 |
|
|
} MergedBits;
|
| 8180 |
|
|
} ATD1STAT1STR;
|
| 8181 |
|
|
extern volatile ATD1STAT1STR _ATD1STAT1 @(REG_BASE + 0x0000012B);
|
| 8182 |
|
|
#define ATD1STAT1 _ATD1STAT1.Byte
|
| 8183 |
|
|
#define ATD1STAT1_CCF0 _ATD1STAT1.Bits.CCF0
|
| 8184 |
|
|
#define ATD1STAT1_CCF1 _ATD1STAT1.Bits.CCF1
|
| 8185 |
|
|
#define ATD1STAT1_CCF2 _ATD1STAT1.Bits.CCF2
|
| 8186 |
|
|
#define ATD1STAT1_CCF3 _ATD1STAT1.Bits.CCF3
|
| 8187 |
|
|
#define ATD1STAT1_CCF4 _ATD1STAT1.Bits.CCF4
|
| 8188 |
|
|
#define ATD1STAT1_CCF5 _ATD1STAT1.Bits.CCF5
|
| 8189 |
|
|
#define ATD1STAT1_CCF6 _ATD1STAT1.Bits.CCF6
|
| 8190 |
|
|
#define ATD1STAT1_CCF7 _ATD1STAT1.Bits.CCF7
|
| 8191 |
|
|
#define ATD1STAT1_CCF _ATD1STAT1.MergedBits.grpCCF
|
| 8192 |
|
|
|
| 8193 |
|
|
|
| 8194 |
|
|
/*** ATD1DIEN - ATD 1 Input Enable Mask Register; 0x0000012D ***/
|
| 8195 |
|
|
typedef union {
|
| 8196 |
|
|
byte Byte;
|
| 8197 |
|
|
struct {
|
| 8198 |
|
|
byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */
|
| 8199 |
|
|
byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */
|
| 8200 |
|
|
byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */
|
| 8201 |
|
|
byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */
|
| 8202 |
|
|
byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */
|
| 8203 |
|
|
byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */
|
| 8204 |
|
|
byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */
|
| 8205 |
|
|
byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */
|
| 8206 |
|
|
} Bits;
|
| 8207 |
|
|
struct {
|
| 8208 |
|
|
byte grpBIT :8;
|
| 8209 |
|
|
} MergedBits;
|
| 8210 |
|
|
} ATD1DIENSTR;
|
| 8211 |
|
|
extern volatile ATD1DIENSTR _ATD1DIEN @(REG_BASE + 0x0000012D);
|
| 8212 |
|
|
#define ATD1DIEN _ATD1DIEN.Byte
|
| 8213 |
|
|
#define ATD1DIEN_BIT0 _ATD1DIEN.Bits.BIT0
|
| 8214 |
|
|
#define ATD1DIEN_BIT1 _ATD1DIEN.Bits.BIT1
|
| 8215 |
|
|
#define ATD1DIEN_BIT2 _ATD1DIEN.Bits.BIT2
|
| 8216 |
|
|
#define ATD1DIEN_BIT3 _ATD1DIEN.Bits.BIT3
|
| 8217 |
|
|
#define ATD1DIEN_BIT4 _ATD1DIEN.Bits.BIT4
|
| 8218 |
|
|
#define ATD1DIEN_BIT5 _ATD1DIEN.Bits.BIT5
|
| 8219 |
|
|
#define ATD1DIEN_BIT6 _ATD1DIEN.Bits.BIT6
|
| 8220 |
|
|
#define ATD1DIEN_BIT7 _ATD1DIEN.Bits.BIT7
|
| 8221 |
|
|
#define ATD1DIEN_BIT _ATD1DIEN.MergedBits.grpBIT
|
| 8222 |
|
|
|
| 8223 |
|
|
|
| 8224 |
|
|
/*** PORTAD1 - Port AD1 Register; 0x0000012F ***/
|
| 8225 |
|
|
typedef union {
|
| 8226 |
|
|
byte Byte;
|
| 8227 |
|
|
struct {
|
| 8228 |
|
|
byte BIT0 :1; /* AN0 */
|
| 8229 |
|
|
byte BIT1 :1; /* AN1 */
|
| 8230 |
|
|
byte BIT2 :1; /* AN2 */
|
| 8231 |
|
|
byte BIT3 :1; /* AN3 */
|
| 8232 |
|
|
byte BIT4 :1; /* AN4 */
|
| 8233 |
|
|
byte BIT5 :1; /* AN5 */
|
| 8234 |
|
|
byte BIT6 :1; /* AN6 */
|
| 8235 |
|
|
byte BIT7 :1; /* AN7 */
|
| 8236 |
|
|
} Bits;
|
| 8237 |
|
|
struct {
|
| 8238 |
|
|
byte grpBIT :8;
|
| 8239 |
|
|
} MergedBits;
|
| 8240 |
|
|
} PORTAD1STR;
|
| 8241 |
|
|
extern volatile PORTAD1STR _PORTAD1 @(REG_BASE + 0x0000012F);
|
| 8242 |
|
|
#define PORTAD1 _PORTAD1.Byte
|
| 8243 |
|
|
#define PORTAD1_BIT0 _PORTAD1.Bits.BIT0
|
| 8244 |
|
|
#define PORTAD1_BIT1 _PORTAD1.Bits.BIT1
|
| 8245 |
|
|
#define PORTAD1_BIT2 _PORTAD1.Bits.BIT2
|
| 8246 |
|
|
#define PORTAD1_BIT3 _PORTAD1.Bits.BIT3
|
| 8247 |
|
|
#define PORTAD1_BIT4 _PORTAD1.Bits.BIT4
|
| 8248 |
|
|
#define PORTAD1_BIT5 _PORTAD1.Bits.BIT5
|
| 8249 |
|
|
#define PORTAD1_BIT6 _PORTAD1.Bits.BIT6
|
| 8250 |
|
|
#define PORTAD1_BIT7 _PORTAD1.Bits.BIT7
|
| 8251 |
|
|
#define PORTAD1_BIT _PORTAD1.MergedBits.grpBIT
|
| 8252 |
|
|
|
| 8253 |
|
|
|
| 8254 |
|
|
/*** CAN0CTL0 - MSCAN 0 Control 0 Register; 0x00000140 ***/
|
| 8255 |
|
|
typedef union {
|
| 8256 |
|
|
byte Byte;
|
| 8257 |
|
|
struct {
|
| 8258 |
|
|
byte INITRQ :1; /* Initialization Mode Request */
|
| 8259 |
|
|
byte SLPRQ :1; /* Sleep Mode Request */
|
| 8260 |
|
|
byte WUPE :1; /* Wake-Up Enable */
|
| 8261 |
|
|
byte TIME :1; /* Timer Enable */
|
| 8262 |
|
|
byte SYNCH :1; /* Synchronized Status */
|
| 8263 |
|
|
byte CSWAI :1; /* CAN Stops in Wait Mode */
|
| 8264 |
|
|
byte RXACT :1; /* Receiver Active Status */
|
| 8265 |
|
|
byte RXFRM :1; /* Received Frame Flag */
|
| 8266 |
|
|
} Bits;
|
| 8267 |
|
|
} CAN0CTL0STR;
|
| 8268 |
|
|
extern volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140);
|
| 8269 |
|
|
#define CAN0CTL0 _CAN0CTL0.Byte
|
| 8270 |
|
|
#define CAN0CTL0_INITRQ _CAN0CTL0.Bits.INITRQ
|
| 8271 |
|
|
#define CAN0CTL0_SLPRQ _CAN0CTL0.Bits.SLPRQ
|
| 8272 |
|
|
#define CAN0CTL0_WUPE _CAN0CTL0.Bits.WUPE
|
| 8273 |
|
|
#define CAN0CTL0_TIME _CAN0CTL0.Bits.TIME
|
| 8274 |
|
|
#define CAN0CTL0_SYNCH _CAN0CTL0.Bits.SYNCH
|
| 8275 |
|
|
#define CAN0CTL0_CSWAI _CAN0CTL0.Bits.CSWAI
|
| 8276 |
|
|
#define CAN0CTL0_RXACT _CAN0CTL0.Bits.RXACT
|
| 8277 |
|
|
#define CAN0CTL0_RXFRM _CAN0CTL0.Bits.RXFRM
|
| 8278 |
|
|
|
| 8279 |
|
|
|
| 8280 |
|
|
/*** CAN0CTL1 - MSCAN 0 Control 1 Register; 0x00000141 ***/
|
| 8281 |
|
|
typedef union {
|
| 8282 |
|
|
byte Byte;
|
| 8283 |
|
|
struct {
|
| 8284 |
|
|
byte INITAK :1; /* Initialization Mode Acknowledge */
|
| 8285 |
|
|
byte SLPAK :1; /* Sleep Mode Acknowledge */
|
| 8286 |
|
|
byte WUPM :1; /* Wake-Up Mode */
|
| 8287 |
|
|
byte :1;
|
| 8288 |
|
|
byte LISTEN :1; /* Listen Only Mode */
|
| 8289 |
|
|
byte LOOPB :1; /* Loop Back Self Test Mode */
|
| 8290 |
|
|
byte CLKSRC :1; /* MSCAN 0 Clock Source */
|
| 8291 |
|
|
byte CANE :1; /* MSCAN 0 Enable */
|
| 8292 |
|
|
} Bits;
|
| 8293 |
|
|
} CAN0CTL1STR;
|
| 8294 |
|
|
extern volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141);
|
| 8295 |
|
|
#define CAN0CTL1 _CAN0CTL1.Byte
|
| 8296 |
|
|
#define CAN0CTL1_INITAK _CAN0CTL1.Bits.INITAK
|
| 8297 |
|
|
#define CAN0CTL1_SLPAK _CAN0CTL1.Bits.SLPAK
|
| 8298 |
|
|
#define CAN0CTL1_WUPM _CAN0CTL1.Bits.WUPM
|
| 8299 |
|
|
#define CAN0CTL1_LISTEN _CAN0CTL1.Bits.LISTEN
|
| 8300 |
|
|
#define CAN0CTL1_LOOPB _CAN0CTL1.Bits.LOOPB
|
| 8301 |
|
|
#define CAN0CTL1_CLKSRC _CAN0CTL1.Bits.CLKSRC
|
| 8302 |
|
|
#define CAN0CTL1_CANE _CAN0CTL1.Bits.CANE
|
| 8303 |
|
|
|
| 8304 |
|
|
|
| 8305 |
|
|
/*** CAN0BTR0 - MSCAN 0 Bus Timing Register 0; 0x00000142 ***/
|
| 8306 |
|
|
typedef union {
|
| 8307 |
|
|
byte Byte;
|
| 8308 |
|
|
struct {
|
| 8309 |
|
|
byte BRP0 :1; /* Baud Rate Prescaler 0 */
|
| 8310 |
|
|
byte BRP1 :1; /* Baud Rate Prescaler 1 */
|
| 8311 |
|
|
byte BRP2 :1; /* Baud Rate Prescaler 2 */
|
| 8312 |
|
|
byte BRP3 :1; /* Baud Rate Prescaler 3 */
|
| 8313 |
|
|
byte BRP4 :1; /* Baud Rate Prescaler 4 */
|
| 8314 |
|
|
byte BRP5 :1; /* Baud Rate Prescaler 5 */
|
| 8315 |
|
|
byte SJW0 :1; /* Synchronization Jump Width 0 */
|
| 8316 |
|
|
byte SJW1 :1; /* Synchronization Jump Width 1 */
|
| 8317 |
|
|
} Bits;
|
| 8318 |
|
|
struct {
|
| 8319 |
|
|
byte grpBRP :6;
|
| 8320 |
|
|
byte grpSJW :2;
|
| 8321 |
|
|
} MergedBits;
|
| 8322 |
|
|
} CAN0BTR0STR;
|
| 8323 |
|
|
extern volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142);
|
| 8324 |
|
|
#define CAN0BTR0 _CAN0BTR0.Byte
|
| 8325 |
|
|
#define CAN0BTR0_BRP0 _CAN0BTR0.Bits.BRP0
|
| 8326 |
|
|
#define CAN0BTR0_BRP1 _CAN0BTR0.Bits.BRP1
|
| 8327 |
|
|
#define CAN0BTR0_BRP2 _CAN0BTR0.Bits.BRP2
|
| 8328 |
|
|
#define CAN0BTR0_BRP3 _CAN0BTR0.Bits.BRP3
|
| 8329 |
|
|
#define CAN0BTR0_BRP4 _CAN0BTR0.Bits.BRP4
|
| 8330 |
|
|
#define CAN0BTR0_BRP5 _CAN0BTR0.Bits.BRP5
|
| 8331 |
|
|
#define CAN0BTR0_SJW0 _CAN0BTR0.Bits.SJW0
|
| 8332 |
|
|
#define CAN0BTR0_SJW1 _CAN0BTR0.Bits.SJW1
|
| 8333 |
|
|
#define CAN0BTR0_BRP _CAN0BTR0.MergedBits.grpBRP
|
| 8334 |
|
|
#define CAN0BTR0_SJW _CAN0BTR0.MergedBits.grpSJW
|
| 8335 |
|
|
|
| 8336 |
|
|
|
| 8337 |
|
|
/*** CAN0BTR1 - MSCAN 0 Bus Timing Register 1; 0x00000143 ***/
|
| 8338 |
|
|
typedef union {
|
| 8339 |
|
|
byte Byte;
|
| 8340 |
|
|
struct {
|
| 8341 |
|
|
byte TSEG10 :1; /* Time Segment 1 */
|
| 8342 |
|
|
byte TSEG11 :1; /* Time Segment 1 */
|
| 8343 |
|
|
byte TSEG12 :1; /* Time Segment 1 */
|
| 8344 |
|
|
byte TSEG13 :1; /* Time Segment 1 */
|
| 8345 |
|
|
byte TSEG20 :1; /* Time Segment 2 */
|
| 8346 |
|
|
byte TSEG21 :1; /* Time Segment 2 */
|
| 8347 |
|
|
byte TSEG22 :1; /* Time Segment 2 */
|
| 8348 |
|
|
byte SAMP :1; /* Sampling */
|
| 8349 |
|
|
} Bits;
|
| 8350 |
|
|
struct {
|
| 8351 |
|
|
byte grpTSEG_10 :4;
|
| 8352 |
|
|
byte grpTSEG_20 :3;
|
| 8353 |
|
|
byte :1;
|
| 8354 |
|
|
} MergedBits;
|
| 8355 |
|
|
} CAN0BTR1STR;
|
| 8356 |
|
|
extern volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143);
|
| 8357 |
|
|
#define CAN0BTR1 _CAN0BTR1.Byte
|
| 8358 |
|
|
#define CAN0BTR1_TSEG10 _CAN0BTR1.Bits.TSEG10
|
| 8359 |
|
|
#define CAN0BTR1_TSEG11 _CAN0BTR1.Bits.TSEG11
|
| 8360 |
|
|
#define CAN0BTR1_TSEG12 _CAN0BTR1.Bits.TSEG12
|
| 8361 |
|
|
#define CAN0BTR1_TSEG13 _CAN0BTR1.Bits.TSEG13
|
| 8362 |
|
|
#define CAN0BTR1_TSEG20 _CAN0BTR1.Bits.TSEG20
|
| 8363 |
|
|
#define CAN0BTR1_TSEG21 _CAN0BTR1.Bits.TSEG21
|
| 8364 |
|
|
#define CAN0BTR1_TSEG22 _CAN0BTR1.Bits.TSEG22
|
| 8365 |
|
|
#define CAN0BTR1_SAMP _CAN0BTR1.Bits.SAMP
|
| 8366 |
|
|
#define CAN0BTR1_TSEG_10 _CAN0BTR1.MergedBits.grpTSEG_10
|
| 8367 |
|
|
#define CAN0BTR1_TSEG_20 _CAN0BTR1.MergedBits.grpTSEG_20
|
| 8368 |
|
|
#define CAN0BTR1_TSEG CAN0BTR1_TSEG_10
|
| 8369 |
|
|
|
| 8370 |
|
|
|
| 8371 |
|
|
/*** CAN0RFLG - MSCAN 0 Receiver Flag Register; 0x00000144 ***/
|
| 8372 |
|
|
typedef union {
|
| 8373 |
|
|
byte Byte;
|
| 8374 |
|
|
struct {
|
| 8375 |
|
|
byte RXF :1; /* Receive Buffer Full */
|
| 8376 |
|
|
byte OVRIF :1; /* Overrun Interrupt Flag */
|
| 8377 |
|
|
byte TSTAT0 :1; /* Transmitter Status Bit 0 */
|
| 8378 |
|
|
byte TSTAT1 :1; /* Transmitter Status Bit 1 */
|
| 8379 |
|
|
byte RSTAT0 :1; /* Receiver Status Bit 0 */
|
| 8380 |
|
|
byte RSTAT1 :1; /* Receiver Status Bit 1 */
|
| 8381 |
|
|
byte CSCIF :1; /* CAN Status Change Interrupt Flag */
|
| 8382 |
|
|
byte WUPIF :1; /* Wake-up Interrupt Flag */
|
| 8383 |
|
|
} Bits;
|
| 8384 |
|
|
struct {
|
| 8385 |
|
|
byte :1;
|
| 8386 |
|
|
byte :1;
|
| 8387 |
|
|
byte grpTSTAT :2;
|
| 8388 |
|
|
byte grpRSTAT :2;
|
| 8389 |
|
|
byte :1;
|
| 8390 |
|
|
byte :1;
|
| 8391 |
|
|
} MergedBits;
|
| 8392 |
|
|
} CAN0RFLGSTR;
|
| 8393 |
|
|
extern volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144);
|
| 8394 |
|
|
#define CAN0RFLG _CAN0RFLG.Byte
|
| 8395 |
|
|
#define CAN0RFLG_RXF _CAN0RFLG.Bits.RXF
|
| 8396 |
|
|
#define CAN0RFLG_OVRIF _CAN0RFLG.Bits.OVRIF
|
| 8397 |
|
|
#define CAN0RFLG_TSTAT0 _CAN0RFLG.Bits.TSTAT0
|
| 8398 |
|
|
#define CAN0RFLG_TSTAT1 _CAN0RFLG.Bits.TSTAT1
|
| 8399 |
|
|
#define CAN0RFLG_RSTAT0 _CAN0RFLG.Bits.RSTAT0
|
| 8400 |
|
|
#define CAN0RFLG_RSTAT1 _CAN0RFLG.Bits.RSTAT1
|
| 8401 |
|
|
#define CAN0RFLG_CSCIF _CAN0RFLG.Bits.CSCIF
|
| 8402 |
|
|
#define CAN0RFLG_WUPIF _CAN0RFLG.Bits.WUPIF
|
| 8403 |
|
|
#define CAN0RFLG_TSTAT _CAN0RFLG.MergedBits.grpTSTAT
|
| 8404 |
|
|
#define CAN0RFLG_RSTAT _CAN0RFLG.MergedBits.grpRSTAT
|
| 8405 |
|
|
|
| 8406 |
|
|
|
| 8407 |
|
|
/*** CAN0RIER - MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 ***/
|
| 8408 |
|
|
typedef union {
|
| 8409 |
|
|
byte Byte;
|
| 8410 |
|
|
struct {
|
| 8411 |
|
|
byte RXFIE :1; /* Receiver Full Interrupt Enable */
|
| 8412 |
|
|
byte OVRIE :1; /* Overrun Interrupt Enable */
|
| 8413 |
|
|
byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
|
| 8414 |
|
|
byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
|
| 8415 |
|
|
byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
|
| 8416 |
|
|
byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
|
| 8417 |
|
|
byte CSCIE :1; /* CAN Status Change Interrupt Enable */
|
| 8418 |
|
|
byte WUPIE :1; /* Wake-up Interrupt Enable */
|
| 8419 |
|
|
} Bits;
|
| 8420 |
|
|
struct {
|
| 8421 |
|
|
byte :1;
|
| 8422 |
|
|
byte :1;
|
| 8423 |
|
|
byte grpTSTATE :2;
|
| 8424 |
|
|
byte grpRSTATE :2;
|
| 8425 |
|
|
byte :1;
|
| 8426 |
|
|
byte :1;
|
| 8427 |
|
|
} MergedBits;
|
| 8428 |
|
|
} CAN0RIERSTR;
|
| 8429 |
|
|
extern volatile CAN0RIERSTR _CAN0RIER @(REG_BASE + 0x00000145);
|
| 8430 |
|
|
#define CAN0RIER _CAN0RIER.Byte
|
| 8431 |
|
|
#define CAN0RIER_RXFIE _CAN0RIER.Bits.RXFIE
|
| 8432 |
|
|
#define CAN0RIER_OVRIE _CAN0RIER.Bits.OVRIE
|
| 8433 |
|
|
#define CAN0RIER_TSTATE0 _CAN0RIER.Bits.TSTATE0
|
| 8434 |
|
|
#define CAN0RIER_TSTATE1 _CAN0RIER.Bits.TSTATE1
|
| 8435 |
|
|
#define CAN0RIER_RSTATE0 _CAN0RIER.Bits.RSTATE0
|
| 8436 |
|
|
#define CAN0RIER_RSTATE1 _CAN0RIER.Bits.RSTATE1
|
| 8437 |
|
|
#define CAN0RIER_CSCIE _CAN0RIER.Bits.CSCIE
|
| 8438 |
|
|
#define CAN0RIER_WUPIE _CAN0RIER.Bits.WUPIE
|
| 8439 |
|
|
#define CAN0RIER_TSTATE _CAN0RIER.MergedBits.grpTSTATE
|
| 8440 |
|
|
#define CAN0RIER_RSTATE _CAN0RIER.MergedBits.grpRSTATE
|
| 8441 |
|
|
|
| 8442 |
|
|
|
| 8443 |
|
|
/*** CAN0TFLG - MSCAN 0 Transmitter Flag Register; 0x00000146 ***/
|
| 8444 |
|
|
typedef union {
|
| 8445 |
|
|
byte Byte;
|
| 8446 |
|
|
struct {
|
| 8447 |
|
|
byte TXE0 :1; /* Transmitter Buffer Empty 0 */
|
| 8448 |
|
|
byte TXE1 :1; /* Transmitter Buffer Empty 1 */
|
| 8449 |
|
|
byte TXE2 :1; /* Transmitter Buffer Empty 2 */
|
| 8450 |
|
|
byte :1;
|
| 8451 |
|
|
byte :1;
|
| 8452 |
|
|
byte :1;
|
| 8453 |
|
|
byte :1;
|
| 8454 |
|
|
byte :1;
|
| 8455 |
|
|
} Bits;
|
| 8456 |
|
|
struct {
|
| 8457 |
|
|
byte grpTXE :3;
|
| 8458 |
|
|
byte :1;
|
| 8459 |
|
|
byte :1;
|
| 8460 |
|
|
byte :1;
|
| 8461 |
|
|
byte :1;
|
| 8462 |
|
|
byte :1;
|
| 8463 |
|
|
} MergedBits;
|
| 8464 |
|
|
} CAN0TFLGSTR;
|
| 8465 |
|
|
extern volatile CAN0TFLGSTR _CAN0TFLG @(REG_BASE + 0x00000146);
|
| 8466 |
|
|
#define CAN0TFLG _CAN0TFLG.Byte
|
| 8467 |
|
|
#define CAN0TFLG_TXE0 _CAN0TFLG.Bits.TXE0
|
| 8468 |
|
|
#define CAN0TFLG_TXE1 _CAN0TFLG.Bits.TXE1
|
| 8469 |
|
|
#define CAN0TFLG_TXE2 _CAN0TFLG.Bits.TXE2
|
| 8470 |
|
|
#define CAN0TFLG_TXE _CAN0TFLG.MergedBits.grpTXE
|
| 8471 |
|
|
|
| 8472 |
|
|
|
| 8473 |
|
|
/*** CAN0TIER - MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 ***/
|
| 8474 |
|
|
typedef union {
|
| 8475 |
|
|
byte Byte;
|
| 8476 |
|
|
struct {
|
| 8477 |
|
|
byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
|
| 8478 |
|
|
byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
|
| 8479 |
|
|
byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
|
| 8480 |
|
|
byte :1;
|
| 8481 |
|
|
byte :1;
|
| 8482 |
|
|
byte :1;
|
| 8483 |
|
|
byte :1;
|
| 8484 |
|
|
byte :1;
|
| 8485 |
|
|
} Bits;
|
| 8486 |
|
|
struct {
|
| 8487 |
|
|
byte grpTXEIE :3;
|
| 8488 |
|
|
byte :1;
|
| 8489 |
|
|
byte :1;
|
| 8490 |
|
|
byte :1;
|
| 8491 |
|
|
byte :1;
|
| 8492 |
|
|
byte :1;
|
| 8493 |
|
|
} MergedBits;
|
| 8494 |
|
|
} CAN0TIERSTR;
|
| 8495 |
|
|
extern volatile CAN0TIERSTR _CAN0TIER @(REG_BASE + 0x00000147);
|
| 8496 |
|
|
#define CAN0TIER _CAN0TIER.Byte
|
| 8497 |
|
|
#define CAN0TIER_TXEIE0 _CAN0TIER.Bits.TXEIE0
|
| 8498 |
|
|
#define CAN0TIER_TXEIE1 _CAN0TIER.Bits.TXEIE1
|
| 8499 |
|
|
#define CAN0TIER_TXEIE2 _CAN0TIER.Bits.TXEIE2
|
| 8500 |
|
|
#define CAN0TIER_TXEIE _CAN0TIER.MergedBits.grpTXEIE
|
| 8501 |
|
|
|
| 8502 |
|
|
|
| 8503 |
|
|
/*** CAN0TARQ - MSCAN 0 Transmitter Message Abort Request; 0x00000148 ***/
|
| 8504 |
|
|
typedef union {
|
| 8505 |
|
|
byte Byte;
|
| 8506 |
|
|
struct {
|
| 8507 |
|
|
byte ABTRQ0 :1; /* Abort Request 0 */
|
| 8508 |
|
|
byte ABTRQ1 :1; /* Abort Request 1 */
|
| 8509 |
|
|
byte ABTRQ2 :1; /* Abort Request 2 */
|
| 8510 |
|
|
byte :1;
|
| 8511 |
|
|
byte :1;
|
| 8512 |
|
|
byte :1;
|
| 8513 |
|
|
byte :1;
|
| 8514 |
|
|
byte :1;
|
| 8515 |
|
|
} Bits;
|
| 8516 |
|
|
struct {
|
| 8517 |
|
|
byte grpABTRQ :3;
|
| 8518 |
|
|
byte :1;
|
| 8519 |
|
|
byte :1;
|
| 8520 |
|
|
byte :1;
|
| 8521 |
|
|
byte :1;
|
| 8522 |
|
|
byte :1;
|
| 8523 |
|
|
} MergedBits;
|
| 8524 |
|
|
} CAN0TARQSTR;
|
| 8525 |
|
|
extern volatile CAN0TARQSTR _CAN0TARQ @(REG_BASE + 0x00000148);
|
| 8526 |
|
|
#define CAN0TARQ _CAN0TARQ.Byte
|
| 8527 |
|
|
#define CAN0TARQ_ABTRQ0 _CAN0TARQ.Bits.ABTRQ0
|
| 8528 |
|
|
#define CAN0TARQ_ABTRQ1 _CAN0TARQ.Bits.ABTRQ1
|
| 8529 |
|
|
#define CAN0TARQ_ABTRQ2 _CAN0TARQ.Bits.ABTRQ2
|
| 8530 |
|
|
#define CAN0TARQ_ABTRQ _CAN0TARQ.MergedBits.grpABTRQ
|
| 8531 |
|
|
|
| 8532 |
|
|
|
| 8533 |
|
|
/*** CAN0TAAK - MSCAN 0 Transmitter Message Abort Control; 0x00000149 ***/
|
| 8534 |
|
|
typedef union {
|
| 8535 |
|
|
byte Byte;
|
| 8536 |
|
|
struct {
|
| 8537 |
|
|
byte ABTAK0 :1; /* Abort Acknowledge 0 */
|
| 8538 |
|
|
byte ABTAK1 :1; /* Abort Acknowledge 1 */
|
| 8539 |
|
|
byte ABTAK2 :1; /* Abort Acknowledge 2 */
|
| 8540 |
|
|
byte :1;
|
| 8541 |
|
|
byte :1;
|
| 8542 |
|
|
byte :1;
|
| 8543 |
|
|
byte :1;
|
| 8544 |
|
|
byte :1;
|
| 8545 |
|
|
} Bits;
|
| 8546 |
|
|
struct {
|
| 8547 |
|
|
byte grpABTAK :3;
|
| 8548 |
|
|
byte :1;
|
| 8549 |
|
|
byte :1;
|
| 8550 |
|
|
byte :1;
|
| 8551 |
|
|
byte :1;
|
| 8552 |
|
|
byte :1;
|
| 8553 |
|
|
} MergedBits;
|
| 8554 |
|
|
} CAN0TAAKSTR;
|
| 8555 |
|
|
extern volatile CAN0TAAKSTR _CAN0TAAK @(REG_BASE + 0x00000149);
|
| 8556 |
|
|
#define CAN0TAAK _CAN0TAAK.Byte
|
| 8557 |
|
|
#define CAN0TAAK_ABTAK0 _CAN0TAAK.Bits.ABTAK0
|
| 8558 |
|
|
#define CAN0TAAK_ABTAK1 _CAN0TAAK.Bits.ABTAK1
|
| 8559 |
|
|
#define CAN0TAAK_ABTAK2 _CAN0TAAK.Bits.ABTAK2
|
| 8560 |
|
|
#define CAN0TAAK_ABTAK _CAN0TAAK.MergedBits.grpABTAK
|
| 8561 |
|
|
|
| 8562 |
|
|
|
| 8563 |
|
|
/*** CAN0TBSEL - MSCAN 0 Transmit Buffer Selection; 0x0000014A ***/
|
| 8564 |
|
|
typedef union {
|
| 8565 |
|
|
byte Byte;
|
| 8566 |
|
|
struct {
|
| 8567 |
|
|
byte TX0 :1; /* Transmit Buffer Select 0 */
|
| 8568 |
|
|
byte TX1 :1; /* Transmit Buffer Select 1 */
|
| 8569 |
|
|
byte TX2 :1; /* Transmit Buffer Select 2 */
|
| 8570 |
|
|
byte :1;
|
| 8571 |
|
|
byte :1;
|
| 8572 |
|
|
byte :1;
|
| 8573 |
|
|
byte :1;
|
| 8574 |
|
|
byte :1;
|
| 8575 |
|
|
} Bits;
|
| 8576 |
|
|
struct {
|
| 8577 |
|
|
byte grpTX :3;
|
| 8578 |
|
|
byte :1;
|
| 8579 |
|
|
byte :1;
|
| 8580 |
|
|
byte :1;
|
| 8581 |
|
|
byte :1;
|
| 8582 |
|
|
byte :1;
|
| 8583 |
|
|
} MergedBits;
|
| 8584 |
|
|
} CAN0TBSELSTR;
|
| 8585 |
|
|
extern volatile CAN0TBSELSTR _CAN0TBSEL @(REG_BASE + 0x0000014A);
|
| 8586 |
|
|
#define CAN0TBSEL _CAN0TBSEL.Byte
|
| 8587 |
|
|
#define CAN0TBSEL_TX0 _CAN0TBSEL.Bits.TX0
|
| 8588 |
|
|
#define CAN0TBSEL_TX1 _CAN0TBSEL.Bits.TX1
|
| 8589 |
|
|
#define CAN0TBSEL_TX2 _CAN0TBSEL.Bits.TX2
|
| 8590 |
|
|
#define CAN0TBSEL_TX _CAN0TBSEL.MergedBits.grpTX
|
| 8591 |
|
|
|
| 8592 |
|
|
|
| 8593 |
|
|
/*** CAN0IDAC - MSCAN 0 Identifier Acceptance Control Register; 0x0000014B ***/
|
| 8594 |
|
|
typedef union {
|
| 8595 |
|
|
byte Byte;
|
| 8596 |
|
|
struct {
|
| 8597 |
|
|
byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
|
| 8598 |
|
|
byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
|
| 8599 |
|
|
byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
|
| 8600 |
|
|
byte :1;
|
| 8601 |
|
|
byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
|
| 8602 |
|
|
byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
|
| 8603 |
|
|
byte :1;
|
| 8604 |
|
|
byte :1;
|
| 8605 |
|
|
} Bits;
|
| 8606 |
|
|
struct {
|
| 8607 |
|
|
byte grpIDHIT :3;
|
| 8608 |
|
|
byte :1;
|
| 8609 |
|
|
byte grpIDAM :2;
|
| 8610 |
|
|
byte :1;
|
| 8611 |
|
|
byte :1;
|
| 8612 |
|
|
} MergedBits;
|
| 8613 |
|
|
} CAN0IDACSTR;
|
| 8614 |
|
|
extern volatile CAN0IDACSTR _CAN0IDAC @(REG_BASE + 0x0000014B);
|
| 8615 |
|
|
#define CAN0IDAC _CAN0IDAC.Byte
|
| 8616 |
|
|
#define CAN0IDAC_IDHIT0 _CAN0IDAC.Bits.IDHIT0
|
| 8617 |
|
|
#define CAN0IDAC_IDHIT1 _CAN0IDAC.Bits.IDHIT1
|
| 8618 |
|
|
#define CAN0IDAC_IDHIT2 _CAN0IDAC.Bits.IDHIT2
|
| 8619 |
|
|
#define CAN0IDAC_IDAM0 _CAN0IDAC.Bits.IDAM0
|
| 8620 |
|
|
#define CAN0IDAC_IDAM1 _CAN0IDAC.Bits.IDAM1
|
| 8621 |
|
|
#define CAN0IDAC_IDHIT _CAN0IDAC.MergedBits.grpIDHIT
|
| 8622 |
|
|
#define CAN0IDAC_IDAM _CAN0IDAC.MergedBits.grpIDAM
|
| 8623 |
|
|
|
| 8624 |
|
|
|
| 8625 |
|
|
/*** CAN0RXERR - MSCAN 0 Receive Error Counter Register; 0x0000014E ***/
|
| 8626 |
|
|
typedef union {
|
| 8627 |
|
|
byte Byte;
|
| 8628 |
|
|
struct {
|
| 8629 |
|
|
byte RXERR0 :1; /* Bit 0 */
|
| 8630 |
|
|
byte RXERR1 :1; /* Bit 1 */
|
| 8631 |
|
|
byte RXERR2 :1; /* Bit 2 */
|
| 8632 |
|
|
byte RXERR3 :1; /* Bit 3 */
|
| 8633 |
|
|
byte RXERR4 :1; /* Bit 4 */
|
| 8634 |
|
|
byte RXERR5 :1; /* Bit 5 */
|
| 8635 |
|
|
byte RXERR6 :1; /* Bit 6 */
|
| 8636 |
|
|
byte RXERR7 :1; /* Bit 7 */
|
| 8637 |
|
|
} Bits;
|
| 8638 |
|
|
struct {
|
| 8639 |
|
|
byte grpRXERR :8;
|
| 8640 |
|
|
} MergedBits;
|
| 8641 |
|
|
} CAN0RXERRSTR;
|
| 8642 |
|
|
extern volatile CAN0RXERRSTR _CAN0RXERR @(REG_BASE + 0x0000014E);
|
| 8643 |
|
|
#define CAN0RXERR _CAN0RXERR.Byte
|
| 8644 |
|
|
#define CAN0RXERR_RXERR0 _CAN0RXERR.Bits.RXERR0
|
| 8645 |
|
|
#define CAN0RXERR_RXERR1 _CAN0RXERR.Bits.RXERR1
|
| 8646 |
|
|
#define CAN0RXERR_RXERR2 _CAN0RXERR.Bits.RXERR2
|
| 8647 |
|
|
#define CAN0RXERR_RXERR3 _CAN0RXERR.Bits.RXERR3
|
| 8648 |
|
|
#define CAN0RXERR_RXERR4 _CAN0RXERR.Bits.RXERR4
|
| 8649 |
|
|
#define CAN0RXERR_RXERR5 _CAN0RXERR.Bits.RXERR5
|
| 8650 |
|
|
#define CAN0RXERR_RXERR6 _CAN0RXERR.Bits.RXERR6
|
| 8651 |
|
|
#define CAN0RXERR_RXERR7 _CAN0RXERR.Bits.RXERR7
|
| 8652 |
|
|
#define CAN0RXERR_RXERR _CAN0RXERR.MergedBits.grpRXERR
|
| 8653 |
|
|
|
| 8654 |
|
|
|
| 8655 |
|
|
/*** CAN0TXERR - MSCAN 0 Transmit Error Counter Register; 0x0000014F ***/
|
| 8656 |
|
|
typedef union {
|
| 8657 |
|
|
byte Byte;
|
| 8658 |
|
|
struct {
|
| 8659 |
|
|
byte TXERR0 :1; /* Bit 0 */
|
| 8660 |
|
|
byte TXERR1 :1; /* Bit 1 */
|
| 8661 |
|
|
byte TXERR2 :1; /* Bit 2 */
|
| 8662 |
|
|
byte TXERR3 :1; /* Bit 3 */
|
| 8663 |
|
|
byte TXERR4 :1; /* Bit 4 */
|
| 8664 |
|
|
byte TXERR5 :1; /* Bit 5 */
|
| 8665 |
|
|
byte TXERR6 :1; /* Bit 6 */
|
| 8666 |
|
|
byte TXERR7 :1; /* Bit 7 */
|
| 8667 |
|
|
} Bits;
|
| 8668 |
|
|
struct {
|
| 8669 |
|
|
byte grpTXERR :8;
|
| 8670 |
|
|
} MergedBits;
|
| 8671 |
|
|
} CAN0TXERRSTR;
|
| 8672 |
|
|
extern volatile CAN0TXERRSTR _CAN0TXERR @(REG_BASE + 0x0000014F);
|
| 8673 |
|
|
#define CAN0TXERR _CAN0TXERR.Byte
|
| 8674 |
|
|
#define CAN0TXERR_TXERR0 _CAN0TXERR.Bits.TXERR0
|
| 8675 |
|
|
#define CAN0TXERR_TXERR1 _CAN0TXERR.Bits.TXERR1
|
| 8676 |
|
|
#define CAN0TXERR_TXERR2 _CAN0TXERR.Bits.TXERR2
|
| 8677 |
|
|
#define CAN0TXERR_TXERR3 _CAN0TXERR.Bits.TXERR3
|
| 8678 |
|
|
#define CAN0TXERR_TXERR4 _CAN0TXERR.Bits.TXERR4
|
| 8679 |
|
|
#define CAN0TXERR_TXERR5 _CAN0TXERR.Bits.TXERR5
|
| 8680 |
|
|
#define CAN0TXERR_TXERR6 _CAN0TXERR.Bits.TXERR6
|
| 8681 |
|
|
#define CAN0TXERR_TXERR7 _CAN0TXERR.Bits.TXERR7
|
| 8682 |
|
|
#define CAN0TXERR_TXERR _CAN0TXERR.MergedBits.grpTXERR
|
| 8683 |
|
|
|
| 8684 |
|
|
|
| 8685 |
|
|
/*** CAN0IDAR0 - MSCAN 0 Identifier Acceptance Register 0; 0x00000150 ***/
|
| 8686 |
|
|
typedef union {
|
| 8687 |
|
|
byte Byte;
|
| 8688 |
|
|
struct {
|
| 8689 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 8690 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 8691 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 8692 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 8693 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 8694 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 8695 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 8696 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 8697 |
|
|
} Bits;
|
| 8698 |
|
|
struct {
|
| 8699 |
|
|
byte grpAC :8;
|
| 8700 |
|
|
} MergedBits;
|
| 8701 |
|
|
} CAN0IDAR0STR;
|
| 8702 |
|
|
extern volatile CAN0IDAR0STR _CAN0IDAR0 @(REG_BASE + 0x00000150);
|
| 8703 |
|
|
#define CAN0IDAR0 _CAN0IDAR0.Byte
|
| 8704 |
|
|
#define CAN0IDAR0_AC0 _CAN0IDAR0.Bits.AC0
|
| 8705 |
|
|
#define CAN0IDAR0_AC1 _CAN0IDAR0.Bits.AC1
|
| 8706 |
|
|
#define CAN0IDAR0_AC2 _CAN0IDAR0.Bits.AC2
|
| 8707 |
|
|
#define CAN0IDAR0_AC3 _CAN0IDAR0.Bits.AC3
|
| 8708 |
|
|
#define CAN0IDAR0_AC4 _CAN0IDAR0.Bits.AC4
|
| 8709 |
|
|
#define CAN0IDAR0_AC5 _CAN0IDAR0.Bits.AC5
|
| 8710 |
|
|
#define CAN0IDAR0_AC6 _CAN0IDAR0.Bits.AC6
|
| 8711 |
|
|
#define CAN0IDAR0_AC7 _CAN0IDAR0.Bits.AC7
|
| 8712 |
|
|
#define CAN0IDAR0_AC _CAN0IDAR0.MergedBits.grpAC
|
| 8713 |
|
|
|
| 8714 |
|
|
|
| 8715 |
|
|
/*** CAN0IDAR1 - MSCAN 0 Identifier Acceptance Register 1; 0x00000151 ***/
|
| 8716 |
|
|
typedef union {
|
| 8717 |
|
|
byte Byte;
|
| 8718 |
|
|
struct {
|
| 8719 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 8720 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 8721 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 8722 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 8723 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 8724 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 8725 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 8726 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 8727 |
|
|
} Bits;
|
| 8728 |
|
|
struct {
|
| 8729 |
|
|
byte grpAC :8;
|
| 8730 |
|
|
} MergedBits;
|
| 8731 |
|
|
} CAN0IDAR1STR;
|
| 8732 |
|
|
extern volatile CAN0IDAR1STR _CAN0IDAR1 @(REG_BASE + 0x00000151);
|
| 8733 |
|
|
#define CAN0IDAR1 _CAN0IDAR1.Byte
|
| 8734 |
|
|
#define CAN0IDAR1_AC0 _CAN0IDAR1.Bits.AC0
|
| 8735 |
|
|
#define CAN0IDAR1_AC1 _CAN0IDAR1.Bits.AC1
|
| 8736 |
|
|
#define CAN0IDAR1_AC2 _CAN0IDAR1.Bits.AC2
|
| 8737 |
|
|
#define CAN0IDAR1_AC3 _CAN0IDAR1.Bits.AC3
|
| 8738 |
|
|
#define CAN0IDAR1_AC4 _CAN0IDAR1.Bits.AC4
|
| 8739 |
|
|
#define CAN0IDAR1_AC5 _CAN0IDAR1.Bits.AC5
|
| 8740 |
|
|
#define CAN0IDAR1_AC6 _CAN0IDAR1.Bits.AC6
|
| 8741 |
|
|
#define CAN0IDAR1_AC7 _CAN0IDAR1.Bits.AC7
|
| 8742 |
|
|
#define CAN0IDAR1_AC _CAN0IDAR1.MergedBits.grpAC
|
| 8743 |
|
|
|
| 8744 |
|
|
|
| 8745 |
|
|
/*** CAN0IDAR2 - MSCAN 0 Identifier Acceptance Register 2; 0x00000152 ***/
|
| 8746 |
|
|
typedef union {
|
| 8747 |
|
|
byte Byte;
|
| 8748 |
|
|
struct {
|
| 8749 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 8750 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 8751 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 8752 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 8753 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 8754 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 8755 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 8756 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 8757 |
|
|
} Bits;
|
| 8758 |
|
|
struct {
|
| 8759 |
|
|
byte grpAC :8;
|
| 8760 |
|
|
} MergedBits;
|
| 8761 |
|
|
} CAN0IDAR2STR;
|
| 8762 |
|
|
extern volatile CAN0IDAR2STR _CAN0IDAR2 @(REG_BASE + 0x00000152);
|
| 8763 |
|
|
#define CAN0IDAR2 _CAN0IDAR2.Byte
|
| 8764 |
|
|
#define CAN0IDAR2_AC0 _CAN0IDAR2.Bits.AC0
|
| 8765 |
|
|
#define CAN0IDAR2_AC1 _CAN0IDAR2.Bits.AC1
|
| 8766 |
|
|
#define CAN0IDAR2_AC2 _CAN0IDAR2.Bits.AC2
|
| 8767 |
|
|
#define CAN0IDAR2_AC3 _CAN0IDAR2.Bits.AC3
|
| 8768 |
|
|
#define CAN0IDAR2_AC4 _CAN0IDAR2.Bits.AC4
|
| 8769 |
|
|
#define CAN0IDAR2_AC5 _CAN0IDAR2.Bits.AC5
|
| 8770 |
|
|
#define CAN0IDAR2_AC6 _CAN0IDAR2.Bits.AC6
|
| 8771 |
|
|
#define CAN0IDAR2_AC7 _CAN0IDAR2.Bits.AC7
|
| 8772 |
|
|
#define CAN0IDAR2_AC _CAN0IDAR2.MergedBits.grpAC
|
| 8773 |
|
|
|
| 8774 |
|
|
|
| 8775 |
|
|
/*** CAN0IDAR3 - MSCAN 0 Identifier Acceptance Register 3; 0x00000153 ***/
|
| 8776 |
|
|
typedef union {
|
| 8777 |
|
|
byte Byte;
|
| 8778 |
|
|
struct {
|
| 8779 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 8780 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 8781 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 8782 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 8783 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 8784 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 8785 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 8786 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 8787 |
|
|
} Bits;
|
| 8788 |
|
|
struct {
|
| 8789 |
|
|
byte grpAC :8;
|
| 8790 |
|
|
} MergedBits;
|
| 8791 |
|
|
} CAN0IDAR3STR;
|
| 8792 |
|
|
extern volatile CAN0IDAR3STR _CAN0IDAR3 @(REG_BASE + 0x00000153);
|
| 8793 |
|
|
#define CAN0IDAR3 _CAN0IDAR3.Byte
|
| 8794 |
|
|
#define CAN0IDAR3_AC0 _CAN0IDAR3.Bits.AC0
|
| 8795 |
|
|
#define CAN0IDAR3_AC1 _CAN0IDAR3.Bits.AC1
|
| 8796 |
|
|
#define CAN0IDAR3_AC2 _CAN0IDAR3.Bits.AC2
|
| 8797 |
|
|
#define CAN0IDAR3_AC3 _CAN0IDAR3.Bits.AC3
|
| 8798 |
|
|
#define CAN0IDAR3_AC4 _CAN0IDAR3.Bits.AC4
|
| 8799 |
|
|
#define CAN0IDAR3_AC5 _CAN0IDAR3.Bits.AC5
|
| 8800 |
|
|
#define CAN0IDAR3_AC6 _CAN0IDAR3.Bits.AC6
|
| 8801 |
|
|
#define CAN0IDAR3_AC7 _CAN0IDAR3.Bits.AC7
|
| 8802 |
|
|
#define CAN0IDAR3_AC _CAN0IDAR3.MergedBits.grpAC
|
| 8803 |
|
|
|
| 8804 |
|
|
|
| 8805 |
|
|
/*** CAN0IDMR0 - MSCAN 0 Identifier Mask Register 0; 0x00000154 ***/
|
| 8806 |
|
|
typedef union {
|
| 8807 |
|
|
byte Byte;
|
| 8808 |
|
|
struct {
|
| 8809 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 8810 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 8811 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 8812 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 8813 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 8814 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 8815 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 8816 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 8817 |
|
|
} Bits;
|
| 8818 |
|
|
struct {
|
| 8819 |
|
|
byte grpAM :8;
|
| 8820 |
|
|
} MergedBits;
|
| 8821 |
|
|
} CAN0IDMR0STR;
|
| 8822 |
|
|
extern volatile CAN0IDMR0STR _CAN0IDMR0 @(REG_BASE + 0x00000154);
|
| 8823 |
|
|
#define CAN0IDMR0 _CAN0IDMR0.Byte
|
| 8824 |
|
|
#define CAN0IDMR0_AM0 _CAN0IDMR0.Bits.AM0
|
| 8825 |
|
|
#define CAN0IDMR0_AM1 _CAN0IDMR0.Bits.AM1
|
| 8826 |
|
|
#define CAN0IDMR0_AM2 _CAN0IDMR0.Bits.AM2
|
| 8827 |
|
|
#define CAN0IDMR0_AM3 _CAN0IDMR0.Bits.AM3
|
| 8828 |
|
|
#define CAN0IDMR0_AM4 _CAN0IDMR0.Bits.AM4
|
| 8829 |
|
|
#define CAN0IDMR0_AM5 _CAN0IDMR0.Bits.AM5
|
| 8830 |
|
|
#define CAN0IDMR0_AM6 _CAN0IDMR0.Bits.AM6
|
| 8831 |
|
|
#define CAN0IDMR0_AM7 _CAN0IDMR0.Bits.AM7
|
| 8832 |
|
|
#define CAN0IDMR0_AM _CAN0IDMR0.MergedBits.grpAM
|
| 8833 |
|
|
|
| 8834 |
|
|
|
| 8835 |
|
|
/*** CAN0IDMR1 - MSCAN 0 Identifier Mask Register 1; 0x00000155 ***/
|
| 8836 |
|
|
typedef union {
|
| 8837 |
|
|
byte Byte;
|
| 8838 |
|
|
struct {
|
| 8839 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 8840 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 8841 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 8842 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 8843 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 8844 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 8845 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 8846 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 8847 |
|
|
} Bits;
|
| 8848 |
|
|
struct {
|
| 8849 |
|
|
byte grpAM :8;
|
| 8850 |
|
|
} MergedBits;
|
| 8851 |
|
|
} CAN0IDMR1STR;
|
| 8852 |
|
|
extern volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155);
|
| 8853 |
|
|
#define CAN0IDMR1 _CAN0IDMR1.Byte
|
| 8854 |
|
|
#define CAN0IDMR1_AM0 _CAN0IDMR1.Bits.AM0
|
| 8855 |
|
|
#define CAN0IDMR1_AM1 _CAN0IDMR1.Bits.AM1
|
| 8856 |
|
|
#define CAN0IDMR1_AM2 _CAN0IDMR1.Bits.AM2
|
| 8857 |
|
|
#define CAN0IDMR1_AM3 _CAN0IDMR1.Bits.AM3
|
| 8858 |
|
|
#define CAN0IDMR1_AM4 _CAN0IDMR1.Bits.AM4
|
| 8859 |
|
|
#define CAN0IDMR1_AM5 _CAN0IDMR1.Bits.AM5
|
| 8860 |
|
|
#define CAN0IDMR1_AM6 _CAN0IDMR1.Bits.AM6
|
| 8861 |
|
|
#define CAN0IDMR1_AM7 _CAN0IDMR1.Bits.AM7
|
| 8862 |
|
|
#define CAN0IDMR1_AM _CAN0IDMR1.MergedBits.grpAM
|
| 8863 |
|
|
|
| 8864 |
|
|
|
| 8865 |
|
|
/*** CAN0IDMR2 - MSCAN 0 Identifier Mask Register 2; 0x00000156 ***/
|
| 8866 |
|
|
typedef union {
|
| 8867 |
|
|
byte Byte;
|
| 8868 |
|
|
struct {
|
| 8869 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 8870 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 8871 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 8872 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 8873 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 8874 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 8875 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 8876 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 8877 |
|
|
} Bits;
|
| 8878 |
|
|
struct {
|
| 8879 |
|
|
byte grpAM :8;
|
| 8880 |
|
|
} MergedBits;
|
| 8881 |
|
|
} CAN0IDMR2STR;
|
| 8882 |
|
|
extern volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156);
|
| 8883 |
|
|
#define CAN0IDMR2 _CAN0IDMR2.Byte
|
| 8884 |
|
|
#define CAN0IDMR2_AM0 _CAN0IDMR2.Bits.AM0
|
| 8885 |
|
|
#define CAN0IDMR2_AM1 _CAN0IDMR2.Bits.AM1
|
| 8886 |
|
|
#define CAN0IDMR2_AM2 _CAN0IDMR2.Bits.AM2
|
| 8887 |
|
|
#define CAN0IDMR2_AM3 _CAN0IDMR2.Bits.AM3
|
| 8888 |
|
|
#define CAN0IDMR2_AM4 _CAN0IDMR2.Bits.AM4
|
| 8889 |
|
|
#define CAN0IDMR2_AM5 _CAN0IDMR2.Bits.AM5
|
| 8890 |
|
|
#define CAN0IDMR2_AM6 _CAN0IDMR2.Bits.AM6
|
| 8891 |
|
|
#define CAN0IDMR2_AM7 _CAN0IDMR2.Bits.AM7
|
| 8892 |
|
|
#define CAN0IDMR2_AM _CAN0IDMR2.MergedBits.grpAM
|
| 8893 |
|
|
|
| 8894 |
|
|
|
| 8895 |
|
|
/*** CAN0IDMR3 - MSCAN 0 Identifier Mask Register 3; 0x00000157 ***/
|
| 8896 |
|
|
typedef union {
|
| 8897 |
|
|
byte Byte;
|
| 8898 |
|
|
struct {
|
| 8899 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 8900 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 8901 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 8902 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 8903 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 8904 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 8905 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 8906 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 8907 |
|
|
} Bits;
|
| 8908 |
|
|
struct {
|
| 8909 |
|
|
byte grpAM :8;
|
| 8910 |
|
|
} MergedBits;
|
| 8911 |
|
|
} CAN0IDMR3STR;
|
| 8912 |
|
|
extern volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157);
|
| 8913 |
|
|
#define CAN0IDMR3 _CAN0IDMR3.Byte
|
| 8914 |
|
|
#define CAN0IDMR3_AM0 _CAN0IDMR3.Bits.AM0
|
| 8915 |
|
|
#define CAN0IDMR3_AM1 _CAN0IDMR3.Bits.AM1
|
| 8916 |
|
|
#define CAN0IDMR3_AM2 _CAN0IDMR3.Bits.AM2
|
| 8917 |
|
|
#define CAN0IDMR3_AM3 _CAN0IDMR3.Bits.AM3
|
| 8918 |
|
|
#define CAN0IDMR3_AM4 _CAN0IDMR3.Bits.AM4
|
| 8919 |
|
|
#define CAN0IDMR3_AM5 _CAN0IDMR3.Bits.AM5
|
| 8920 |
|
|
#define CAN0IDMR3_AM6 _CAN0IDMR3.Bits.AM6
|
| 8921 |
|
|
#define CAN0IDMR3_AM7 _CAN0IDMR3.Bits.AM7
|
| 8922 |
|
|
#define CAN0IDMR3_AM _CAN0IDMR3.MergedBits.grpAM
|
| 8923 |
|
|
|
| 8924 |
|
|
|
| 8925 |
|
|
/*** CAN0IDAR4 - MSCAN 0 Identifier Acceptance Register 4; 0x00000158 ***/
|
| 8926 |
|
|
typedef union {
|
| 8927 |
|
|
byte Byte;
|
| 8928 |
|
|
struct {
|
| 8929 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 8930 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 8931 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 8932 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 8933 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 8934 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 8935 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 8936 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 8937 |
|
|
} Bits;
|
| 8938 |
|
|
struct {
|
| 8939 |
|
|
byte grpAC :8;
|
| 8940 |
|
|
} MergedBits;
|
| 8941 |
|
|
} CAN0IDAR4STR;
|
| 8942 |
|
|
extern volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158);
|
| 8943 |
|
|
#define CAN0IDAR4 _CAN0IDAR4.Byte
|
| 8944 |
|
|
#define CAN0IDAR4_AC0 _CAN0IDAR4.Bits.AC0
|
| 8945 |
|
|
#define CAN0IDAR4_AC1 _CAN0IDAR4.Bits.AC1
|
| 8946 |
|
|
#define CAN0IDAR4_AC2 _CAN0IDAR4.Bits.AC2
|
| 8947 |
|
|
#define CAN0IDAR4_AC3 _CAN0IDAR4.Bits.AC3
|
| 8948 |
|
|
#define CAN0IDAR4_AC4 _CAN0IDAR4.Bits.AC4
|
| 8949 |
|
|
#define CAN0IDAR4_AC5 _CAN0IDAR4.Bits.AC5
|
| 8950 |
|
|
#define CAN0IDAR4_AC6 _CAN0IDAR4.Bits.AC6
|
| 8951 |
|
|
#define CAN0IDAR4_AC7 _CAN0IDAR4.Bits.AC7
|
| 8952 |
|
|
#define CAN0IDAR4_AC _CAN0IDAR4.MergedBits.grpAC
|
| 8953 |
|
|
|
| 8954 |
|
|
|
| 8955 |
|
|
/*** CAN0IDAR5 - MSCAN 0 Identifier Acceptance Register 5; 0x00000159 ***/
|
| 8956 |
|
|
typedef union {
|
| 8957 |
|
|
byte Byte;
|
| 8958 |
|
|
struct {
|
| 8959 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 8960 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 8961 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 8962 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 8963 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 8964 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 8965 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 8966 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 8967 |
|
|
} Bits;
|
| 8968 |
|
|
struct {
|
| 8969 |
|
|
byte grpAC :8;
|
| 8970 |
|
|
} MergedBits;
|
| 8971 |
|
|
} CAN0IDAR5STR;
|
| 8972 |
|
|
extern volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159);
|
| 8973 |
|
|
#define CAN0IDAR5 _CAN0IDAR5.Byte
|
| 8974 |
|
|
#define CAN0IDAR5_AC0 _CAN0IDAR5.Bits.AC0
|
| 8975 |
|
|
#define CAN0IDAR5_AC1 _CAN0IDAR5.Bits.AC1
|
| 8976 |
|
|
#define CAN0IDAR5_AC2 _CAN0IDAR5.Bits.AC2
|
| 8977 |
|
|
#define CAN0IDAR5_AC3 _CAN0IDAR5.Bits.AC3
|
| 8978 |
|
|
#define CAN0IDAR5_AC4 _CAN0IDAR5.Bits.AC4
|
| 8979 |
|
|
#define CAN0IDAR5_AC5 _CAN0IDAR5.Bits.AC5
|
| 8980 |
|
|
#define CAN0IDAR5_AC6 _CAN0IDAR5.Bits.AC6
|
| 8981 |
|
|
#define CAN0IDAR5_AC7 _CAN0IDAR5.Bits.AC7
|
| 8982 |
|
|
#define CAN0IDAR5_AC _CAN0IDAR5.MergedBits.grpAC
|
| 8983 |
|
|
|
| 8984 |
|
|
|
| 8985 |
|
|
/*** CAN0IDAR6 - MSCAN 0 Identifier Acceptance Register 6; 0x0000015A ***/
|
| 8986 |
|
|
typedef union {
|
| 8987 |
|
|
byte Byte;
|
| 8988 |
|
|
struct {
|
| 8989 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 8990 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 8991 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 8992 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 8993 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 8994 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 8995 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 8996 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 8997 |
|
|
} Bits;
|
| 8998 |
|
|
struct {
|
| 8999 |
|
|
byte grpAC :8;
|
| 9000 |
|
|
} MergedBits;
|
| 9001 |
|
|
} CAN0IDAR6STR;
|
| 9002 |
|
|
extern volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015A);
|
| 9003 |
|
|
#define CAN0IDAR6 _CAN0IDAR6.Byte
|
| 9004 |
|
|
#define CAN0IDAR6_AC0 _CAN0IDAR6.Bits.AC0
|
| 9005 |
|
|
#define CAN0IDAR6_AC1 _CAN0IDAR6.Bits.AC1
|
| 9006 |
|
|
#define CAN0IDAR6_AC2 _CAN0IDAR6.Bits.AC2
|
| 9007 |
|
|
#define CAN0IDAR6_AC3 _CAN0IDAR6.Bits.AC3
|
| 9008 |
|
|
#define CAN0IDAR6_AC4 _CAN0IDAR6.Bits.AC4
|
| 9009 |
|
|
#define CAN0IDAR6_AC5 _CAN0IDAR6.Bits.AC5
|
| 9010 |
|
|
#define CAN0IDAR6_AC6 _CAN0IDAR6.Bits.AC6
|
| 9011 |
|
|
#define CAN0IDAR6_AC7 _CAN0IDAR6.Bits.AC7
|
| 9012 |
|
|
#define CAN0IDAR6_AC _CAN0IDAR6.MergedBits.grpAC
|
| 9013 |
|
|
|
| 9014 |
|
|
|
| 9015 |
|
|
/*** CAN0IDAR7 - MSCAN 0 Identifier Acceptance Register 7; 0x0000015B ***/
|
| 9016 |
|
|
typedef union {
|
| 9017 |
|
|
byte Byte;
|
| 9018 |
|
|
struct {
|
| 9019 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 9020 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 9021 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 9022 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 9023 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 9024 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 9025 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 9026 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 9027 |
|
|
} Bits;
|
| 9028 |
|
|
struct {
|
| 9029 |
|
|
byte grpAC :8;
|
| 9030 |
|
|
} MergedBits;
|
| 9031 |
|
|
} CAN0IDAR7STR;
|
| 9032 |
|
|
extern volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015B);
|
| 9033 |
|
|
#define CAN0IDAR7 _CAN0IDAR7.Byte
|
| 9034 |
|
|
#define CAN0IDAR7_AC0 _CAN0IDAR7.Bits.AC0
|
| 9035 |
|
|
#define CAN0IDAR7_AC1 _CAN0IDAR7.Bits.AC1
|
| 9036 |
|
|
#define CAN0IDAR7_AC2 _CAN0IDAR7.Bits.AC2
|
| 9037 |
|
|
#define CAN0IDAR7_AC3 _CAN0IDAR7.Bits.AC3
|
| 9038 |
|
|
#define CAN0IDAR7_AC4 _CAN0IDAR7.Bits.AC4
|
| 9039 |
|
|
#define CAN0IDAR7_AC5 _CAN0IDAR7.Bits.AC5
|
| 9040 |
|
|
#define CAN0IDAR7_AC6 _CAN0IDAR7.Bits.AC6
|
| 9041 |
|
|
#define CAN0IDAR7_AC7 _CAN0IDAR7.Bits.AC7
|
| 9042 |
|
|
#define CAN0IDAR7_AC _CAN0IDAR7.MergedBits.grpAC
|
| 9043 |
|
|
|
| 9044 |
|
|
|
| 9045 |
|
|
/*** CAN0IDMR4 - MSCAN 0 Identifier Mask Register 4; 0x0000015C ***/
|
| 9046 |
|
|
typedef union {
|
| 9047 |
|
|
byte Byte;
|
| 9048 |
|
|
struct {
|
| 9049 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 9050 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 9051 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 9052 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 9053 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 9054 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 9055 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 9056 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 9057 |
|
|
} Bits;
|
| 9058 |
|
|
struct {
|
| 9059 |
|
|
byte grpAM :8;
|
| 9060 |
|
|
} MergedBits;
|
| 9061 |
|
|
} CAN0IDMR4STR;
|
| 9062 |
|
|
extern volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015C);
|
| 9063 |
|
|
#define CAN0IDMR4 _CAN0IDMR4.Byte
|
| 9064 |
|
|
#define CAN0IDMR4_AM0 _CAN0IDMR4.Bits.AM0
|
| 9065 |
|
|
#define CAN0IDMR4_AM1 _CAN0IDMR4.Bits.AM1
|
| 9066 |
|
|
#define CAN0IDMR4_AM2 _CAN0IDMR4.Bits.AM2
|
| 9067 |
|
|
#define CAN0IDMR4_AM3 _CAN0IDMR4.Bits.AM3
|
| 9068 |
|
|
#define CAN0IDMR4_AM4 _CAN0IDMR4.Bits.AM4
|
| 9069 |
|
|
#define CAN0IDMR4_AM5 _CAN0IDMR4.Bits.AM5
|
| 9070 |
|
|
#define CAN0IDMR4_AM6 _CAN0IDMR4.Bits.AM6
|
| 9071 |
|
|
#define CAN0IDMR4_AM7 _CAN0IDMR4.Bits.AM7
|
| 9072 |
|
|
#define CAN0IDMR4_AM _CAN0IDMR4.MergedBits.grpAM
|
| 9073 |
|
|
|
| 9074 |
|
|
|
| 9075 |
|
|
/*** CAN0IDMR5 - MSCAN 0 Identifier Mask Register 5; 0x0000015D ***/
|
| 9076 |
|
|
typedef union {
|
| 9077 |
|
|
byte Byte;
|
| 9078 |
|
|
struct {
|
| 9079 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 9080 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 9081 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 9082 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 9083 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 9084 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 9085 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 9086 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 9087 |
|
|
} Bits;
|
| 9088 |
|
|
struct {
|
| 9089 |
|
|
byte grpAM :8;
|
| 9090 |
|
|
} MergedBits;
|
| 9091 |
|
|
} CAN0IDMR5STR;
|
| 9092 |
|
|
extern volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015D);
|
| 9093 |
|
|
#define CAN0IDMR5 _CAN0IDMR5.Byte
|
| 9094 |
|
|
#define CAN0IDMR5_AM0 _CAN0IDMR5.Bits.AM0
|
| 9095 |
|
|
#define CAN0IDMR5_AM1 _CAN0IDMR5.Bits.AM1
|
| 9096 |
|
|
#define CAN0IDMR5_AM2 _CAN0IDMR5.Bits.AM2
|
| 9097 |
|
|
#define CAN0IDMR5_AM3 _CAN0IDMR5.Bits.AM3
|
| 9098 |
|
|
#define CAN0IDMR5_AM4 _CAN0IDMR5.Bits.AM4
|
| 9099 |
|
|
#define CAN0IDMR5_AM5 _CAN0IDMR5.Bits.AM5
|
| 9100 |
|
|
#define CAN0IDMR5_AM6 _CAN0IDMR5.Bits.AM6
|
| 9101 |
|
|
#define CAN0IDMR5_AM7 _CAN0IDMR5.Bits.AM7
|
| 9102 |
|
|
#define CAN0IDMR5_AM _CAN0IDMR5.MergedBits.grpAM
|
| 9103 |
|
|
|
| 9104 |
|
|
|
| 9105 |
|
|
/*** CAN0IDMR6 - MSCAN 0 Identifier Mask Register 6; 0x0000015E ***/
|
| 9106 |
|
|
typedef union {
|
| 9107 |
|
|
byte Byte;
|
| 9108 |
|
|
struct {
|
| 9109 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 9110 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 9111 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 9112 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 9113 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 9114 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 9115 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 9116 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 9117 |
|
|
} Bits;
|
| 9118 |
|
|
struct {
|
| 9119 |
|
|
byte grpAM :8;
|
| 9120 |
|
|
} MergedBits;
|
| 9121 |
|
|
} CAN0IDMR6STR;
|
| 9122 |
|
|
extern volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015E);
|
| 9123 |
|
|
#define CAN0IDMR6 _CAN0IDMR6.Byte
|
| 9124 |
|
|
#define CAN0IDMR6_AM0 _CAN0IDMR6.Bits.AM0
|
| 9125 |
|
|
#define CAN0IDMR6_AM1 _CAN0IDMR6.Bits.AM1
|
| 9126 |
|
|
#define CAN0IDMR6_AM2 _CAN0IDMR6.Bits.AM2
|
| 9127 |
|
|
#define CAN0IDMR6_AM3 _CAN0IDMR6.Bits.AM3
|
| 9128 |
|
|
#define CAN0IDMR6_AM4 _CAN0IDMR6.Bits.AM4
|
| 9129 |
|
|
#define CAN0IDMR6_AM5 _CAN0IDMR6.Bits.AM5
|
| 9130 |
|
|
#define CAN0IDMR6_AM6 _CAN0IDMR6.Bits.AM6
|
| 9131 |
|
|
#define CAN0IDMR6_AM7 _CAN0IDMR6.Bits.AM7
|
| 9132 |
|
|
#define CAN0IDMR6_AM _CAN0IDMR6.MergedBits.grpAM
|
| 9133 |
|
|
|
| 9134 |
|
|
|
| 9135 |
|
|
/*** CAN0IDMR7 - MSCAN 0 Identifier Mask Register 7; 0x0000015F ***/
|
| 9136 |
|
|
typedef union {
|
| 9137 |
|
|
byte Byte;
|
| 9138 |
|
|
struct {
|
| 9139 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 9140 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 9141 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 9142 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 9143 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 9144 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 9145 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 9146 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 9147 |
|
|
} Bits;
|
| 9148 |
|
|
struct {
|
| 9149 |
|
|
byte grpAM :8;
|
| 9150 |
|
|
} MergedBits;
|
| 9151 |
|
|
} CAN0IDMR7STR;
|
| 9152 |
|
|
extern volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015F);
|
| 9153 |
|
|
#define CAN0IDMR7 _CAN0IDMR7.Byte
|
| 9154 |
|
|
#define CAN0IDMR7_AM0 _CAN0IDMR7.Bits.AM0
|
| 9155 |
|
|
#define CAN0IDMR7_AM1 _CAN0IDMR7.Bits.AM1
|
| 9156 |
|
|
#define CAN0IDMR7_AM2 _CAN0IDMR7.Bits.AM2
|
| 9157 |
|
|
#define CAN0IDMR7_AM3 _CAN0IDMR7.Bits.AM3
|
| 9158 |
|
|
#define CAN0IDMR7_AM4 _CAN0IDMR7.Bits.AM4
|
| 9159 |
|
|
#define CAN0IDMR7_AM5 _CAN0IDMR7.Bits.AM5
|
| 9160 |
|
|
#define CAN0IDMR7_AM6 _CAN0IDMR7.Bits.AM6
|
| 9161 |
|
|
#define CAN0IDMR7_AM7 _CAN0IDMR7.Bits.AM7
|
| 9162 |
|
|
#define CAN0IDMR7_AM _CAN0IDMR7.MergedBits.grpAM
|
| 9163 |
|
|
|
| 9164 |
|
|
|
| 9165 |
|
|
/*** CAN0RXIDR0 - MSCAN 0 Receive Identifier Register 0; 0x00000160 ***/
|
| 9166 |
|
|
typedef union {
|
| 9167 |
|
|
byte Byte;
|
| 9168 |
|
|
struct {
|
| 9169 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 9170 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 9171 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 9172 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 9173 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 9174 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 9175 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 9176 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 9177 |
|
|
} Bits;
|
| 9178 |
|
|
struct {
|
| 9179 |
|
|
byte grpID_21 :8;
|
| 9180 |
|
|
} MergedBits;
|
| 9181 |
|
|
} CAN0RXIDR0STR;
|
| 9182 |
|
|
extern volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160);
|
| 9183 |
|
|
#define CAN0RXIDR0 _CAN0RXIDR0.Byte
|
| 9184 |
|
|
#define CAN0RXIDR0_ID21 _CAN0RXIDR0.Bits.ID21
|
| 9185 |
|
|
#define CAN0RXIDR0_ID22 _CAN0RXIDR0.Bits.ID22
|
| 9186 |
|
|
#define CAN0RXIDR0_ID23 _CAN0RXIDR0.Bits.ID23
|
| 9187 |
|
|
#define CAN0RXIDR0_ID24 _CAN0RXIDR0.Bits.ID24
|
| 9188 |
|
|
#define CAN0RXIDR0_ID25 _CAN0RXIDR0.Bits.ID25
|
| 9189 |
|
|
#define CAN0RXIDR0_ID26 _CAN0RXIDR0.Bits.ID26
|
| 9190 |
|
|
#define CAN0RXIDR0_ID27 _CAN0RXIDR0.Bits.ID27
|
| 9191 |
|
|
#define CAN0RXIDR0_ID28 _CAN0RXIDR0.Bits.ID28
|
| 9192 |
|
|
#define CAN0RXIDR0_ID_21 _CAN0RXIDR0.MergedBits.grpID_21
|
| 9193 |
|
|
#define CAN0RXIDR0_ID CAN0RXIDR0_ID_21
|
| 9194 |
|
|
|
| 9195 |
|
|
|
| 9196 |
|
|
/*** CAN0RXIDR1 - MSCAN 0 Receive Identifier Register 1; 0x00000161 ***/
|
| 9197 |
|
|
typedef union {
|
| 9198 |
|
|
byte Byte;
|
| 9199 |
|
|
struct {
|
| 9200 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 9201 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 9202 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 9203 |
|
|
byte IDE :1; /* ID Extended */
|
| 9204 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 9205 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 9206 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 9207 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 9208 |
|
|
} Bits;
|
| 9209 |
|
|
struct {
|
| 9210 |
|
|
byte grpID_15 :3;
|
| 9211 |
|
|
byte :1;
|
| 9212 |
|
|
byte :1;
|
| 9213 |
|
|
byte grpID_18 :3;
|
| 9214 |
|
|
} MergedBits;
|
| 9215 |
|
|
} CAN0RXIDR1STR;
|
| 9216 |
|
|
extern volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161);
|
| 9217 |
|
|
#define CAN0RXIDR1 _CAN0RXIDR1.Byte
|
| 9218 |
|
|
#define CAN0RXIDR1_ID15 _CAN0RXIDR1.Bits.ID15
|
| 9219 |
|
|
#define CAN0RXIDR1_ID16 _CAN0RXIDR1.Bits.ID16
|
| 9220 |
|
|
#define CAN0RXIDR1_ID17 _CAN0RXIDR1.Bits.ID17
|
| 9221 |
|
|
#define CAN0RXIDR1_IDE _CAN0RXIDR1.Bits.IDE
|
| 9222 |
|
|
#define CAN0RXIDR1_SRR _CAN0RXIDR1.Bits.SRR
|
| 9223 |
|
|
#define CAN0RXIDR1_ID18 _CAN0RXIDR1.Bits.ID18
|
| 9224 |
|
|
#define CAN0RXIDR1_ID19 _CAN0RXIDR1.Bits.ID19
|
| 9225 |
|
|
#define CAN0RXIDR1_ID20 _CAN0RXIDR1.Bits.ID20
|
| 9226 |
|
|
#define CAN0RXIDR1_ID_15 _CAN0RXIDR1.MergedBits.grpID_15
|
| 9227 |
|
|
#define CAN0RXIDR1_ID_18 _CAN0RXIDR1.MergedBits.grpID_18
|
| 9228 |
|
|
#define CAN0RXIDR1_ID CAN0RXIDR1_ID_15
|
| 9229 |
|
|
|
| 9230 |
|
|
|
| 9231 |
|
|
/*** CAN0RXIDR2 - MSCAN 0 Receive Identifier Register 2; 0x00000162 ***/
|
| 9232 |
|
|
typedef union {
|
| 9233 |
|
|
byte Byte;
|
| 9234 |
|
|
struct {
|
| 9235 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 9236 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 9237 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 9238 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 9239 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 9240 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 9241 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 9242 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 9243 |
|
|
} Bits;
|
| 9244 |
|
|
struct {
|
| 9245 |
|
|
byte grpID_7 :8;
|
| 9246 |
|
|
} MergedBits;
|
| 9247 |
|
|
} CAN0RXIDR2STR;
|
| 9248 |
|
|
extern volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162);
|
| 9249 |
|
|
#define CAN0RXIDR2 _CAN0RXIDR2.Byte
|
| 9250 |
|
|
#define CAN0RXIDR2_ID7 _CAN0RXIDR2.Bits.ID7
|
| 9251 |
|
|
#define CAN0RXIDR2_ID8 _CAN0RXIDR2.Bits.ID8
|
| 9252 |
|
|
#define CAN0RXIDR2_ID9 _CAN0RXIDR2.Bits.ID9
|
| 9253 |
|
|
#define CAN0RXIDR2_ID10 _CAN0RXIDR2.Bits.ID10
|
| 9254 |
|
|
#define CAN0RXIDR2_ID11 _CAN0RXIDR2.Bits.ID11
|
| 9255 |
|
|
#define CAN0RXIDR2_ID12 _CAN0RXIDR2.Bits.ID12
|
| 9256 |
|
|
#define CAN0RXIDR2_ID13 _CAN0RXIDR2.Bits.ID13
|
| 9257 |
|
|
#define CAN0RXIDR2_ID14 _CAN0RXIDR2.Bits.ID14
|
| 9258 |
|
|
#define CAN0RXIDR2_ID_7 _CAN0RXIDR2.MergedBits.grpID_7
|
| 9259 |
|
|
#define CAN0RXIDR2_ID CAN0RXIDR2_ID_7
|
| 9260 |
|
|
|
| 9261 |
|
|
|
| 9262 |
|
|
/*** CAN0RXIDR3 - MSCAN 0 Receive Identifier Register 3; 0x00000163 ***/
|
| 9263 |
|
|
typedef union {
|
| 9264 |
|
|
byte Byte;
|
| 9265 |
|
|
struct {
|
| 9266 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 9267 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 9268 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 9269 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 9270 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 9271 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 9272 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 9273 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 9274 |
|
|
} Bits;
|
| 9275 |
|
|
struct {
|
| 9276 |
|
|
byte :1;
|
| 9277 |
|
|
byte grpID :7;
|
| 9278 |
|
|
} MergedBits;
|
| 9279 |
|
|
} CAN0RXIDR3STR;
|
| 9280 |
|
|
extern volatile CAN0RXIDR3STR _CAN0RXIDR3 @(REG_BASE + 0x00000163);
|
| 9281 |
|
|
#define CAN0RXIDR3 _CAN0RXIDR3.Byte
|
| 9282 |
|
|
#define CAN0RXIDR3_RTR _CAN0RXIDR3.Bits.RTR
|
| 9283 |
|
|
#define CAN0RXIDR3_ID0 _CAN0RXIDR3.Bits.ID0
|
| 9284 |
|
|
#define CAN0RXIDR3_ID1 _CAN0RXIDR3.Bits.ID1
|
| 9285 |
|
|
#define CAN0RXIDR3_ID2 _CAN0RXIDR3.Bits.ID2
|
| 9286 |
|
|
#define CAN0RXIDR3_ID3 _CAN0RXIDR3.Bits.ID3
|
| 9287 |
|
|
#define CAN0RXIDR3_ID4 _CAN0RXIDR3.Bits.ID4
|
| 9288 |
|
|
#define CAN0RXIDR3_ID5 _CAN0RXIDR3.Bits.ID5
|
| 9289 |
|
|
#define CAN0RXIDR3_ID6 _CAN0RXIDR3.Bits.ID6
|
| 9290 |
|
|
#define CAN0RXIDR3_ID _CAN0RXIDR3.MergedBits.grpID
|
| 9291 |
|
|
|
| 9292 |
|
|
|
| 9293 |
|
|
/*** CAN0RXDSR0 - MSCAN 0 Receive Data Segment Register 0; 0x00000164 ***/
|
| 9294 |
|
|
typedef union {
|
| 9295 |
|
|
byte Byte;
|
| 9296 |
|
|
struct {
|
| 9297 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9298 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9299 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9300 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9301 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9302 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9303 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9304 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9305 |
|
|
} Bits;
|
| 9306 |
|
|
struct {
|
| 9307 |
|
|
byte grpDB :8;
|
| 9308 |
|
|
} MergedBits;
|
| 9309 |
|
|
} CAN0RXDSR0STR;
|
| 9310 |
|
|
extern volatile CAN0RXDSR0STR _CAN0RXDSR0 @(REG_BASE + 0x00000164);
|
| 9311 |
|
|
#define CAN0RXDSR0 _CAN0RXDSR0.Byte
|
| 9312 |
|
|
#define CAN0RXDSR0_DB0 _CAN0RXDSR0.Bits.DB0
|
| 9313 |
|
|
#define CAN0RXDSR0_DB1 _CAN0RXDSR0.Bits.DB1
|
| 9314 |
|
|
#define CAN0RXDSR0_DB2 _CAN0RXDSR0.Bits.DB2
|
| 9315 |
|
|
#define CAN0RXDSR0_DB3 _CAN0RXDSR0.Bits.DB3
|
| 9316 |
|
|
#define CAN0RXDSR0_DB4 _CAN0RXDSR0.Bits.DB4
|
| 9317 |
|
|
#define CAN0RXDSR0_DB5 _CAN0RXDSR0.Bits.DB5
|
| 9318 |
|
|
#define CAN0RXDSR0_DB6 _CAN0RXDSR0.Bits.DB6
|
| 9319 |
|
|
#define CAN0RXDSR0_DB7 _CAN0RXDSR0.Bits.DB7
|
| 9320 |
|
|
#define CAN0RXDSR0_DB _CAN0RXDSR0.MergedBits.grpDB
|
| 9321 |
|
|
|
| 9322 |
|
|
|
| 9323 |
|
|
/*** CAN0RXDSR1 - MSCAN 0 Receive Data Segment Register 1; 0x00000165 ***/
|
| 9324 |
|
|
typedef union {
|
| 9325 |
|
|
byte Byte;
|
| 9326 |
|
|
struct {
|
| 9327 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9328 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9329 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9330 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9331 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9332 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9333 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9334 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9335 |
|
|
} Bits;
|
| 9336 |
|
|
struct {
|
| 9337 |
|
|
byte grpDB :8;
|
| 9338 |
|
|
} MergedBits;
|
| 9339 |
|
|
} CAN0RXDSR1STR;
|
| 9340 |
|
|
extern volatile CAN0RXDSR1STR _CAN0RXDSR1 @(REG_BASE + 0x00000165);
|
| 9341 |
|
|
#define CAN0RXDSR1 _CAN0RXDSR1.Byte
|
| 9342 |
|
|
#define CAN0RXDSR1_DB0 _CAN0RXDSR1.Bits.DB0
|
| 9343 |
|
|
#define CAN0RXDSR1_DB1 _CAN0RXDSR1.Bits.DB1
|
| 9344 |
|
|
#define CAN0RXDSR1_DB2 _CAN0RXDSR1.Bits.DB2
|
| 9345 |
|
|
#define CAN0RXDSR1_DB3 _CAN0RXDSR1.Bits.DB3
|
| 9346 |
|
|
#define CAN0RXDSR1_DB4 _CAN0RXDSR1.Bits.DB4
|
| 9347 |
|
|
#define CAN0RXDSR1_DB5 _CAN0RXDSR1.Bits.DB5
|
| 9348 |
|
|
#define CAN0RXDSR1_DB6 _CAN0RXDSR1.Bits.DB6
|
| 9349 |
|
|
#define CAN0RXDSR1_DB7 _CAN0RXDSR1.Bits.DB7
|
| 9350 |
|
|
#define CAN0RXDSR1_DB _CAN0RXDSR1.MergedBits.grpDB
|
| 9351 |
|
|
|
| 9352 |
|
|
|
| 9353 |
|
|
/*** CAN0RXDSR2 - MSCAN 0 Receive Data Segment Register 2; 0x00000166 ***/
|
| 9354 |
|
|
typedef union {
|
| 9355 |
|
|
byte Byte;
|
| 9356 |
|
|
struct {
|
| 9357 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9358 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9359 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9360 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9361 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9362 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9363 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9364 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9365 |
|
|
} Bits;
|
| 9366 |
|
|
struct {
|
| 9367 |
|
|
byte grpDB :8;
|
| 9368 |
|
|
} MergedBits;
|
| 9369 |
|
|
} CAN0RXDSR2STR;
|
| 9370 |
|
|
extern volatile CAN0RXDSR2STR _CAN0RXDSR2 @(REG_BASE + 0x00000166);
|
| 9371 |
|
|
#define CAN0RXDSR2 _CAN0RXDSR2.Byte
|
| 9372 |
|
|
#define CAN0RXDSR2_DB0 _CAN0RXDSR2.Bits.DB0
|
| 9373 |
|
|
#define CAN0RXDSR2_DB1 _CAN0RXDSR2.Bits.DB1
|
| 9374 |
|
|
#define CAN0RXDSR2_DB2 _CAN0RXDSR2.Bits.DB2
|
| 9375 |
|
|
#define CAN0RXDSR2_DB3 _CAN0RXDSR2.Bits.DB3
|
| 9376 |
|
|
#define CAN0RXDSR2_DB4 _CAN0RXDSR2.Bits.DB4
|
| 9377 |
|
|
#define CAN0RXDSR2_DB5 _CAN0RXDSR2.Bits.DB5
|
| 9378 |
|
|
#define CAN0RXDSR2_DB6 _CAN0RXDSR2.Bits.DB6
|
| 9379 |
|
|
#define CAN0RXDSR2_DB7 _CAN0RXDSR2.Bits.DB7
|
| 9380 |
|
|
#define CAN0RXDSR2_DB _CAN0RXDSR2.MergedBits.grpDB
|
| 9381 |
|
|
|
| 9382 |
|
|
|
| 9383 |
|
|
/*** CAN0RXDSR3 - MSCAN 0 Receive Data Segment Register 3; 0x00000167 ***/
|
| 9384 |
|
|
typedef union {
|
| 9385 |
|
|
byte Byte;
|
| 9386 |
|
|
struct {
|
| 9387 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9388 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9389 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9390 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9391 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9392 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9393 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9394 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9395 |
|
|
} Bits;
|
| 9396 |
|
|
struct {
|
| 9397 |
|
|
byte grpDB :8;
|
| 9398 |
|
|
} MergedBits;
|
| 9399 |
|
|
} CAN0RXDSR3STR;
|
| 9400 |
|
|
extern volatile CAN0RXDSR3STR _CAN0RXDSR3 @(REG_BASE + 0x00000167);
|
| 9401 |
|
|
#define CAN0RXDSR3 _CAN0RXDSR3.Byte
|
| 9402 |
|
|
#define CAN0RXDSR3_DB0 _CAN0RXDSR3.Bits.DB0
|
| 9403 |
|
|
#define CAN0RXDSR3_DB1 _CAN0RXDSR3.Bits.DB1
|
| 9404 |
|
|
#define CAN0RXDSR3_DB2 _CAN0RXDSR3.Bits.DB2
|
| 9405 |
|
|
#define CAN0RXDSR3_DB3 _CAN0RXDSR3.Bits.DB3
|
| 9406 |
|
|
#define CAN0RXDSR3_DB4 _CAN0RXDSR3.Bits.DB4
|
| 9407 |
|
|
#define CAN0RXDSR3_DB5 _CAN0RXDSR3.Bits.DB5
|
| 9408 |
|
|
#define CAN0RXDSR3_DB6 _CAN0RXDSR3.Bits.DB6
|
| 9409 |
|
|
#define CAN0RXDSR3_DB7 _CAN0RXDSR3.Bits.DB7
|
| 9410 |
|
|
#define CAN0RXDSR3_DB _CAN0RXDSR3.MergedBits.grpDB
|
| 9411 |
|
|
|
| 9412 |
|
|
|
| 9413 |
|
|
/*** CAN0RXDSR4 - MSCAN 0 Receive Data Segment Register 4; 0x00000168 ***/
|
| 9414 |
|
|
typedef union {
|
| 9415 |
|
|
byte Byte;
|
| 9416 |
|
|
struct {
|
| 9417 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9418 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9419 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9420 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9421 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9422 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9423 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9424 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9425 |
|
|
} Bits;
|
| 9426 |
|
|
struct {
|
| 9427 |
|
|
byte grpDB :8;
|
| 9428 |
|
|
} MergedBits;
|
| 9429 |
|
|
} CAN0RXDSR4STR;
|
| 9430 |
|
|
extern volatile CAN0RXDSR4STR _CAN0RXDSR4 @(REG_BASE + 0x00000168);
|
| 9431 |
|
|
#define CAN0RXDSR4 _CAN0RXDSR4.Byte
|
| 9432 |
|
|
#define CAN0RXDSR4_DB0 _CAN0RXDSR4.Bits.DB0
|
| 9433 |
|
|
#define CAN0RXDSR4_DB1 _CAN0RXDSR4.Bits.DB1
|
| 9434 |
|
|
#define CAN0RXDSR4_DB2 _CAN0RXDSR4.Bits.DB2
|
| 9435 |
|
|
#define CAN0RXDSR4_DB3 _CAN0RXDSR4.Bits.DB3
|
| 9436 |
|
|
#define CAN0RXDSR4_DB4 _CAN0RXDSR4.Bits.DB4
|
| 9437 |
|
|
#define CAN0RXDSR4_DB5 _CAN0RXDSR4.Bits.DB5
|
| 9438 |
|
|
#define CAN0RXDSR4_DB6 _CAN0RXDSR4.Bits.DB6
|
| 9439 |
|
|
#define CAN0RXDSR4_DB7 _CAN0RXDSR4.Bits.DB7
|
| 9440 |
|
|
#define CAN0RXDSR4_DB _CAN0RXDSR4.MergedBits.grpDB
|
| 9441 |
|
|
|
| 9442 |
|
|
|
| 9443 |
|
|
/*** CAN0RXDSR5 - MSCAN 0 Receive Data Segment Register 5; 0x00000169 ***/
|
| 9444 |
|
|
typedef union {
|
| 9445 |
|
|
byte Byte;
|
| 9446 |
|
|
struct {
|
| 9447 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9448 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9449 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9450 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9451 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9452 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9453 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9454 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9455 |
|
|
} Bits;
|
| 9456 |
|
|
struct {
|
| 9457 |
|
|
byte grpDB :8;
|
| 9458 |
|
|
} MergedBits;
|
| 9459 |
|
|
} CAN0RXDSR5STR;
|
| 9460 |
|
|
extern volatile CAN0RXDSR5STR _CAN0RXDSR5 @(REG_BASE + 0x00000169);
|
| 9461 |
|
|
#define CAN0RXDSR5 _CAN0RXDSR5.Byte
|
| 9462 |
|
|
#define CAN0RXDSR5_DB0 _CAN0RXDSR5.Bits.DB0
|
| 9463 |
|
|
#define CAN0RXDSR5_DB1 _CAN0RXDSR5.Bits.DB1
|
| 9464 |
|
|
#define CAN0RXDSR5_DB2 _CAN0RXDSR5.Bits.DB2
|
| 9465 |
|
|
#define CAN0RXDSR5_DB3 _CAN0RXDSR5.Bits.DB3
|
| 9466 |
|
|
#define CAN0RXDSR5_DB4 _CAN0RXDSR5.Bits.DB4
|
| 9467 |
|
|
#define CAN0RXDSR5_DB5 _CAN0RXDSR5.Bits.DB5
|
| 9468 |
|
|
#define CAN0RXDSR5_DB6 _CAN0RXDSR5.Bits.DB6
|
| 9469 |
|
|
#define CAN0RXDSR5_DB7 _CAN0RXDSR5.Bits.DB7
|
| 9470 |
|
|
#define CAN0RXDSR5_DB _CAN0RXDSR5.MergedBits.grpDB
|
| 9471 |
|
|
|
| 9472 |
|
|
|
| 9473 |
|
|
/*** CAN0RXDSR6 - MSCAN 0 Receive Data Segment Register 6; 0x0000016A ***/
|
| 9474 |
|
|
typedef union {
|
| 9475 |
|
|
byte Byte;
|
| 9476 |
|
|
struct {
|
| 9477 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9478 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9479 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9480 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9481 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9482 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9483 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9484 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9485 |
|
|
} Bits;
|
| 9486 |
|
|
struct {
|
| 9487 |
|
|
byte grpDB :8;
|
| 9488 |
|
|
} MergedBits;
|
| 9489 |
|
|
} CAN0RXDSR6STR;
|
| 9490 |
|
|
extern volatile CAN0RXDSR6STR _CAN0RXDSR6 @(REG_BASE + 0x0000016A);
|
| 9491 |
|
|
#define CAN0RXDSR6 _CAN0RXDSR6.Byte
|
| 9492 |
|
|
#define CAN0RXDSR6_DB0 _CAN0RXDSR6.Bits.DB0
|
| 9493 |
|
|
#define CAN0RXDSR6_DB1 _CAN0RXDSR6.Bits.DB1
|
| 9494 |
|
|
#define CAN0RXDSR6_DB2 _CAN0RXDSR6.Bits.DB2
|
| 9495 |
|
|
#define CAN0RXDSR6_DB3 _CAN0RXDSR6.Bits.DB3
|
| 9496 |
|
|
#define CAN0RXDSR6_DB4 _CAN0RXDSR6.Bits.DB4
|
| 9497 |
|
|
#define CAN0RXDSR6_DB5 _CAN0RXDSR6.Bits.DB5
|
| 9498 |
|
|
#define CAN0RXDSR6_DB6 _CAN0RXDSR6.Bits.DB6
|
| 9499 |
|
|
#define CAN0RXDSR6_DB7 _CAN0RXDSR6.Bits.DB7
|
| 9500 |
|
|
#define CAN0RXDSR6_DB _CAN0RXDSR6.MergedBits.grpDB
|
| 9501 |
|
|
|
| 9502 |
|
|
|
| 9503 |
|
|
/*** CAN0RXDSR7 - MSCAN 0 Receive Data Segment Register 7; 0x0000016B ***/
|
| 9504 |
|
|
typedef union {
|
| 9505 |
|
|
byte Byte;
|
| 9506 |
|
|
struct {
|
| 9507 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9508 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9509 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9510 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9511 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9512 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9513 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9514 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9515 |
|
|
} Bits;
|
| 9516 |
|
|
struct {
|
| 9517 |
|
|
byte grpDB :8;
|
| 9518 |
|
|
} MergedBits;
|
| 9519 |
|
|
} CAN0RXDSR7STR;
|
| 9520 |
|
|
extern volatile CAN0RXDSR7STR _CAN0RXDSR7 @(REG_BASE + 0x0000016B);
|
| 9521 |
|
|
#define CAN0RXDSR7 _CAN0RXDSR7.Byte
|
| 9522 |
|
|
#define CAN0RXDSR7_DB0 _CAN0RXDSR7.Bits.DB0
|
| 9523 |
|
|
#define CAN0RXDSR7_DB1 _CAN0RXDSR7.Bits.DB1
|
| 9524 |
|
|
#define CAN0RXDSR7_DB2 _CAN0RXDSR7.Bits.DB2
|
| 9525 |
|
|
#define CAN0RXDSR7_DB3 _CAN0RXDSR7.Bits.DB3
|
| 9526 |
|
|
#define CAN0RXDSR7_DB4 _CAN0RXDSR7.Bits.DB4
|
| 9527 |
|
|
#define CAN0RXDSR7_DB5 _CAN0RXDSR7.Bits.DB5
|
| 9528 |
|
|
#define CAN0RXDSR7_DB6 _CAN0RXDSR7.Bits.DB6
|
| 9529 |
|
|
#define CAN0RXDSR7_DB7 _CAN0RXDSR7.Bits.DB7
|
| 9530 |
|
|
#define CAN0RXDSR7_DB _CAN0RXDSR7.MergedBits.grpDB
|
| 9531 |
|
|
|
| 9532 |
|
|
|
| 9533 |
|
|
/*** CAN0RXDLR - MSCAN 0 Receive Data Length Register; 0x0000016C ***/
|
| 9534 |
|
|
typedef union {
|
| 9535 |
|
|
byte Byte;
|
| 9536 |
|
|
struct {
|
| 9537 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 9538 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 9539 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 9540 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 9541 |
|
|
byte :1;
|
| 9542 |
|
|
byte :1;
|
| 9543 |
|
|
byte :1;
|
| 9544 |
|
|
byte :1;
|
| 9545 |
|
|
} Bits;
|
| 9546 |
|
|
struct {
|
| 9547 |
|
|
byte grpDLC :4;
|
| 9548 |
|
|
byte :1;
|
| 9549 |
|
|
byte :1;
|
| 9550 |
|
|
byte :1;
|
| 9551 |
|
|
byte :1;
|
| 9552 |
|
|
} MergedBits;
|
| 9553 |
|
|
} CAN0RXDLRSTR;
|
| 9554 |
|
|
extern volatile CAN0RXDLRSTR _CAN0RXDLR @(REG_BASE + 0x0000016C);
|
| 9555 |
|
|
#define CAN0RXDLR _CAN0RXDLR.Byte
|
| 9556 |
|
|
#define CAN0RXDLR_DLC0 _CAN0RXDLR.Bits.DLC0
|
| 9557 |
|
|
#define CAN0RXDLR_DLC1 _CAN0RXDLR.Bits.DLC1
|
| 9558 |
|
|
#define CAN0RXDLR_DLC2 _CAN0RXDLR.Bits.DLC2
|
| 9559 |
|
|
#define CAN0RXDLR_DLC3 _CAN0RXDLR.Bits.DLC3
|
| 9560 |
|
|
#define CAN0RXDLR_DLC _CAN0RXDLR.MergedBits.grpDLC
|
| 9561 |
|
|
|
| 9562 |
|
|
|
| 9563 |
|
|
/*** CAN0TXIDR0 - MSCAN 0 Transmit Identifier Register 0; 0x00000170 ***/
|
| 9564 |
|
|
typedef union {
|
| 9565 |
|
|
byte Byte;
|
| 9566 |
|
|
struct {
|
| 9567 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 9568 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 9569 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 9570 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 9571 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 9572 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 9573 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 9574 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 9575 |
|
|
} Bits;
|
| 9576 |
|
|
struct {
|
| 9577 |
|
|
byte grpID_21 :8;
|
| 9578 |
|
|
} MergedBits;
|
| 9579 |
|
|
} CAN0TXIDR0STR;
|
| 9580 |
|
|
extern volatile CAN0TXIDR0STR _CAN0TXIDR0 @(REG_BASE + 0x00000170);
|
| 9581 |
|
|
#define CAN0TXIDR0 _CAN0TXIDR0.Byte
|
| 9582 |
|
|
#define CAN0TXIDR0_ID21 _CAN0TXIDR0.Bits.ID21
|
| 9583 |
|
|
#define CAN0TXIDR0_ID22 _CAN0TXIDR0.Bits.ID22
|
| 9584 |
|
|
#define CAN0TXIDR0_ID23 _CAN0TXIDR0.Bits.ID23
|
| 9585 |
|
|
#define CAN0TXIDR0_ID24 _CAN0TXIDR0.Bits.ID24
|
| 9586 |
|
|
#define CAN0TXIDR0_ID25 _CAN0TXIDR0.Bits.ID25
|
| 9587 |
|
|
#define CAN0TXIDR0_ID26 _CAN0TXIDR0.Bits.ID26
|
| 9588 |
|
|
#define CAN0TXIDR0_ID27 _CAN0TXIDR0.Bits.ID27
|
| 9589 |
|
|
#define CAN0TXIDR0_ID28 _CAN0TXIDR0.Bits.ID28
|
| 9590 |
|
|
#define CAN0TXIDR0_ID_21 _CAN0TXIDR0.MergedBits.grpID_21
|
| 9591 |
|
|
#define CAN0TXIDR0_ID CAN0TXIDR0_ID_21
|
| 9592 |
|
|
|
| 9593 |
|
|
|
| 9594 |
|
|
/*** CAN0TXIDR1 - MSCAN 0 Transmit Identifier Register 1; 0x00000171 ***/
|
| 9595 |
|
|
typedef union {
|
| 9596 |
|
|
byte Byte;
|
| 9597 |
|
|
struct {
|
| 9598 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 9599 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 9600 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 9601 |
|
|
byte IDE :1; /* ID Extended */
|
| 9602 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 9603 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 9604 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 9605 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 9606 |
|
|
} Bits;
|
| 9607 |
|
|
struct {
|
| 9608 |
|
|
byte grpID_15 :3;
|
| 9609 |
|
|
byte :1;
|
| 9610 |
|
|
byte :1;
|
| 9611 |
|
|
byte grpID_18 :3;
|
| 9612 |
|
|
} MergedBits;
|
| 9613 |
|
|
} CAN0TXIDR1STR;
|
| 9614 |
|
|
extern volatile CAN0TXIDR1STR _CAN0TXIDR1 @(REG_BASE + 0x00000171);
|
| 9615 |
|
|
#define CAN0TXIDR1 _CAN0TXIDR1.Byte
|
| 9616 |
|
|
#define CAN0TXIDR1_ID15 _CAN0TXIDR1.Bits.ID15
|
| 9617 |
|
|
#define CAN0TXIDR1_ID16 _CAN0TXIDR1.Bits.ID16
|
| 9618 |
|
|
#define CAN0TXIDR1_ID17 _CAN0TXIDR1.Bits.ID17
|
| 9619 |
|
|
#define CAN0TXIDR1_IDE _CAN0TXIDR1.Bits.IDE
|
| 9620 |
|
|
#define CAN0TXIDR1_SRR _CAN0TXIDR1.Bits.SRR
|
| 9621 |
|
|
#define CAN0TXIDR1_ID18 _CAN0TXIDR1.Bits.ID18
|
| 9622 |
|
|
#define CAN0TXIDR1_ID19 _CAN0TXIDR1.Bits.ID19
|
| 9623 |
|
|
#define CAN0TXIDR1_ID20 _CAN0TXIDR1.Bits.ID20
|
| 9624 |
|
|
#define CAN0TXIDR1_ID_15 _CAN0TXIDR1.MergedBits.grpID_15
|
| 9625 |
|
|
#define CAN0TXIDR1_ID_18 _CAN0TXIDR1.MergedBits.grpID_18
|
| 9626 |
|
|
#define CAN0TXIDR1_ID CAN0TXIDR1_ID_15
|
| 9627 |
|
|
|
| 9628 |
|
|
|
| 9629 |
|
|
/*** CAN0TXIDR2 - MSCAN 0 Transmit Identifier Register 2; 0x00000172 ***/
|
| 9630 |
|
|
typedef union {
|
| 9631 |
|
|
byte Byte;
|
| 9632 |
|
|
struct {
|
| 9633 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 9634 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 9635 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 9636 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 9637 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 9638 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 9639 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 9640 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 9641 |
|
|
} Bits;
|
| 9642 |
|
|
struct {
|
| 9643 |
|
|
byte grpID_7 :8;
|
| 9644 |
|
|
} MergedBits;
|
| 9645 |
|
|
} CAN0TXIDR2STR;
|
| 9646 |
|
|
extern volatile CAN0TXIDR2STR _CAN0TXIDR2 @(REG_BASE + 0x00000172);
|
| 9647 |
|
|
#define CAN0TXIDR2 _CAN0TXIDR2.Byte
|
| 9648 |
|
|
#define CAN0TXIDR2_ID7 _CAN0TXIDR2.Bits.ID7
|
| 9649 |
|
|
#define CAN0TXIDR2_ID8 _CAN0TXIDR2.Bits.ID8
|
| 9650 |
|
|
#define CAN0TXIDR2_ID9 _CAN0TXIDR2.Bits.ID9
|
| 9651 |
|
|
#define CAN0TXIDR2_ID10 _CAN0TXIDR2.Bits.ID10
|
| 9652 |
|
|
#define CAN0TXIDR2_ID11 _CAN0TXIDR2.Bits.ID11
|
| 9653 |
|
|
#define CAN0TXIDR2_ID12 _CAN0TXIDR2.Bits.ID12
|
| 9654 |
|
|
#define CAN0TXIDR2_ID13 _CAN0TXIDR2.Bits.ID13
|
| 9655 |
|
|
#define CAN0TXIDR2_ID14 _CAN0TXIDR2.Bits.ID14
|
| 9656 |
|
|
#define CAN0TXIDR2_ID_7 _CAN0TXIDR2.MergedBits.grpID_7
|
| 9657 |
|
|
#define CAN0TXIDR2_ID CAN0TXIDR2_ID_7
|
| 9658 |
|
|
|
| 9659 |
|
|
|
| 9660 |
|
|
/*** CAN0TXIDR3 - MSCAN 0 Transmit Identifier Register 3; 0x00000173 ***/
|
| 9661 |
|
|
typedef union {
|
| 9662 |
|
|
byte Byte;
|
| 9663 |
|
|
struct {
|
| 9664 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 9665 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 9666 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 9667 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 9668 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 9669 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 9670 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 9671 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 9672 |
|
|
} Bits;
|
| 9673 |
|
|
struct {
|
| 9674 |
|
|
byte :1;
|
| 9675 |
|
|
byte grpID :7;
|
| 9676 |
|
|
} MergedBits;
|
| 9677 |
|
|
} CAN0TXIDR3STR;
|
| 9678 |
|
|
extern volatile CAN0TXIDR3STR _CAN0TXIDR3 @(REG_BASE + 0x00000173);
|
| 9679 |
|
|
#define CAN0TXIDR3 _CAN0TXIDR3.Byte
|
| 9680 |
|
|
#define CAN0TXIDR3_RTR _CAN0TXIDR3.Bits.RTR
|
| 9681 |
|
|
#define CAN0TXIDR3_ID0 _CAN0TXIDR3.Bits.ID0
|
| 9682 |
|
|
#define CAN0TXIDR3_ID1 _CAN0TXIDR3.Bits.ID1
|
| 9683 |
|
|
#define CAN0TXIDR3_ID2 _CAN0TXIDR3.Bits.ID2
|
| 9684 |
|
|
#define CAN0TXIDR3_ID3 _CAN0TXIDR3.Bits.ID3
|
| 9685 |
|
|
#define CAN0TXIDR3_ID4 _CAN0TXIDR3.Bits.ID4
|
| 9686 |
|
|
#define CAN0TXIDR3_ID5 _CAN0TXIDR3.Bits.ID5
|
| 9687 |
|
|
#define CAN0TXIDR3_ID6 _CAN0TXIDR3.Bits.ID6
|
| 9688 |
|
|
#define CAN0TXIDR3_ID _CAN0TXIDR3.MergedBits.grpID
|
| 9689 |
|
|
|
| 9690 |
|
|
|
| 9691 |
|
|
/*** CAN0TXDSR0 - MSCAN 0 Transmit Data Segment Register 0; 0x00000174 ***/
|
| 9692 |
|
|
typedef union {
|
| 9693 |
|
|
byte Byte;
|
| 9694 |
|
|
struct {
|
| 9695 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9696 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9697 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9698 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9699 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9700 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9701 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9702 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9703 |
|
|
} Bits;
|
| 9704 |
|
|
struct {
|
| 9705 |
|
|
byte grpDB :8;
|
| 9706 |
|
|
} MergedBits;
|
| 9707 |
|
|
} CAN0TXDSR0STR;
|
| 9708 |
|
|
extern volatile CAN0TXDSR0STR _CAN0TXDSR0 @(REG_BASE + 0x00000174);
|
| 9709 |
|
|
#define CAN0TXDSR0 _CAN0TXDSR0.Byte
|
| 9710 |
|
|
#define CAN0TXDSR0_DB0 _CAN0TXDSR0.Bits.DB0
|
| 9711 |
|
|
#define CAN0TXDSR0_DB1 _CAN0TXDSR0.Bits.DB1
|
| 9712 |
|
|
#define CAN0TXDSR0_DB2 _CAN0TXDSR0.Bits.DB2
|
| 9713 |
|
|
#define CAN0TXDSR0_DB3 _CAN0TXDSR0.Bits.DB3
|
| 9714 |
|
|
#define CAN0TXDSR0_DB4 _CAN0TXDSR0.Bits.DB4
|
| 9715 |
|
|
#define CAN0TXDSR0_DB5 _CAN0TXDSR0.Bits.DB5
|
| 9716 |
|
|
#define CAN0TXDSR0_DB6 _CAN0TXDSR0.Bits.DB6
|
| 9717 |
|
|
#define CAN0TXDSR0_DB7 _CAN0TXDSR0.Bits.DB7
|
| 9718 |
|
|
#define CAN0TXDSR0_DB _CAN0TXDSR0.MergedBits.grpDB
|
| 9719 |
|
|
|
| 9720 |
|
|
|
| 9721 |
|
|
/*** CAN0TXDSR1 - MSCAN 0 Transmit Data Segment Register 1; 0x00000175 ***/
|
| 9722 |
|
|
typedef union {
|
| 9723 |
|
|
byte Byte;
|
| 9724 |
|
|
struct {
|
| 9725 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9726 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9727 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9728 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9729 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9730 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9731 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9732 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9733 |
|
|
} Bits;
|
| 9734 |
|
|
struct {
|
| 9735 |
|
|
byte grpDB :8;
|
| 9736 |
|
|
} MergedBits;
|
| 9737 |
|
|
} CAN0TXDSR1STR;
|
| 9738 |
|
|
extern volatile CAN0TXDSR1STR _CAN0TXDSR1 @(REG_BASE + 0x00000175);
|
| 9739 |
|
|
#define CAN0TXDSR1 _CAN0TXDSR1.Byte
|
| 9740 |
|
|
#define CAN0TXDSR1_DB0 _CAN0TXDSR1.Bits.DB0
|
| 9741 |
|
|
#define CAN0TXDSR1_DB1 _CAN0TXDSR1.Bits.DB1
|
| 9742 |
|
|
#define CAN0TXDSR1_DB2 _CAN0TXDSR1.Bits.DB2
|
| 9743 |
|
|
#define CAN0TXDSR1_DB3 _CAN0TXDSR1.Bits.DB3
|
| 9744 |
|
|
#define CAN0TXDSR1_DB4 _CAN0TXDSR1.Bits.DB4
|
| 9745 |
|
|
#define CAN0TXDSR1_DB5 _CAN0TXDSR1.Bits.DB5
|
| 9746 |
|
|
#define CAN0TXDSR1_DB6 _CAN0TXDSR1.Bits.DB6
|
| 9747 |
|
|
#define CAN0TXDSR1_DB7 _CAN0TXDSR1.Bits.DB7
|
| 9748 |
|
|
#define CAN0TXDSR1_DB _CAN0TXDSR1.MergedBits.grpDB
|
| 9749 |
|
|
|
| 9750 |
|
|
|
| 9751 |
|
|
/*** CAN0TXDSR2 - MSCAN 0 Transmit Data Segment Register 2; 0x00000176 ***/
|
| 9752 |
|
|
typedef union {
|
| 9753 |
|
|
byte Byte;
|
| 9754 |
|
|
struct {
|
| 9755 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9756 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9757 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9758 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9759 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9760 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9761 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9762 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9763 |
|
|
} Bits;
|
| 9764 |
|
|
struct {
|
| 9765 |
|
|
byte grpDB :8;
|
| 9766 |
|
|
} MergedBits;
|
| 9767 |
|
|
} CAN0TXDSR2STR;
|
| 9768 |
|
|
extern volatile CAN0TXDSR2STR _CAN0TXDSR2 @(REG_BASE + 0x00000176);
|
| 9769 |
|
|
#define CAN0TXDSR2 _CAN0TXDSR2.Byte
|
| 9770 |
|
|
#define CAN0TXDSR2_DB0 _CAN0TXDSR2.Bits.DB0
|
| 9771 |
|
|
#define CAN0TXDSR2_DB1 _CAN0TXDSR2.Bits.DB1
|
| 9772 |
|
|
#define CAN0TXDSR2_DB2 _CAN0TXDSR2.Bits.DB2
|
| 9773 |
|
|
#define CAN0TXDSR2_DB3 _CAN0TXDSR2.Bits.DB3
|
| 9774 |
|
|
#define CAN0TXDSR2_DB4 _CAN0TXDSR2.Bits.DB4
|
| 9775 |
|
|
#define CAN0TXDSR2_DB5 _CAN0TXDSR2.Bits.DB5
|
| 9776 |
|
|
#define CAN0TXDSR2_DB6 _CAN0TXDSR2.Bits.DB6
|
| 9777 |
|
|
#define CAN0TXDSR2_DB7 _CAN0TXDSR2.Bits.DB7
|
| 9778 |
|
|
#define CAN0TXDSR2_DB _CAN0TXDSR2.MergedBits.grpDB
|
| 9779 |
|
|
|
| 9780 |
|
|
|
| 9781 |
|
|
/*** CAN0TXDSR3 - MSCAN 0 Transmit Data Segment Register 3; 0x00000177 ***/
|
| 9782 |
|
|
typedef union {
|
| 9783 |
|
|
byte Byte;
|
| 9784 |
|
|
struct {
|
| 9785 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9786 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9787 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9788 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9789 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9790 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9791 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9792 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9793 |
|
|
} Bits;
|
| 9794 |
|
|
struct {
|
| 9795 |
|
|
byte grpDB :8;
|
| 9796 |
|
|
} MergedBits;
|
| 9797 |
|
|
} CAN0TXDSR3STR;
|
| 9798 |
|
|
extern volatile CAN0TXDSR3STR _CAN0TXDSR3 @(REG_BASE + 0x00000177);
|
| 9799 |
|
|
#define CAN0TXDSR3 _CAN0TXDSR3.Byte
|
| 9800 |
|
|
#define CAN0TXDSR3_DB0 _CAN0TXDSR3.Bits.DB0
|
| 9801 |
|
|
#define CAN0TXDSR3_DB1 _CAN0TXDSR3.Bits.DB1
|
| 9802 |
|
|
#define CAN0TXDSR3_DB2 _CAN0TXDSR3.Bits.DB2
|
| 9803 |
|
|
#define CAN0TXDSR3_DB3 _CAN0TXDSR3.Bits.DB3
|
| 9804 |
|
|
#define CAN0TXDSR3_DB4 _CAN0TXDSR3.Bits.DB4
|
| 9805 |
|
|
#define CAN0TXDSR3_DB5 _CAN0TXDSR3.Bits.DB5
|
| 9806 |
|
|
#define CAN0TXDSR3_DB6 _CAN0TXDSR3.Bits.DB6
|
| 9807 |
|
|
#define CAN0TXDSR3_DB7 _CAN0TXDSR3.Bits.DB7
|
| 9808 |
|
|
#define CAN0TXDSR3_DB _CAN0TXDSR3.MergedBits.grpDB
|
| 9809 |
|
|
|
| 9810 |
|
|
|
| 9811 |
|
|
/*** CAN0TXDSR4 - MSCAN 0 Transmit Data Segment Register 4; 0x00000178 ***/
|
| 9812 |
|
|
typedef union {
|
| 9813 |
|
|
byte Byte;
|
| 9814 |
|
|
struct {
|
| 9815 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9816 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9817 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9818 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9819 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9820 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9821 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9822 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9823 |
|
|
} Bits;
|
| 9824 |
|
|
struct {
|
| 9825 |
|
|
byte grpDB :8;
|
| 9826 |
|
|
} MergedBits;
|
| 9827 |
|
|
} CAN0TXDSR4STR;
|
| 9828 |
|
|
extern volatile CAN0TXDSR4STR _CAN0TXDSR4 @(REG_BASE + 0x00000178);
|
| 9829 |
|
|
#define CAN0TXDSR4 _CAN0TXDSR4.Byte
|
| 9830 |
|
|
#define CAN0TXDSR4_DB0 _CAN0TXDSR4.Bits.DB0
|
| 9831 |
|
|
#define CAN0TXDSR4_DB1 _CAN0TXDSR4.Bits.DB1
|
| 9832 |
|
|
#define CAN0TXDSR4_DB2 _CAN0TXDSR4.Bits.DB2
|
| 9833 |
|
|
#define CAN0TXDSR4_DB3 _CAN0TXDSR4.Bits.DB3
|
| 9834 |
|
|
#define CAN0TXDSR4_DB4 _CAN0TXDSR4.Bits.DB4
|
| 9835 |
|
|
#define CAN0TXDSR4_DB5 _CAN0TXDSR4.Bits.DB5
|
| 9836 |
|
|
#define CAN0TXDSR4_DB6 _CAN0TXDSR4.Bits.DB6
|
| 9837 |
|
|
#define CAN0TXDSR4_DB7 _CAN0TXDSR4.Bits.DB7
|
| 9838 |
|
|
#define CAN0TXDSR4_DB _CAN0TXDSR4.MergedBits.grpDB
|
| 9839 |
|
|
|
| 9840 |
|
|
|
| 9841 |
|
|
/*** CAN0TXDSR5 - MSCAN 0 Transmit Data Segment Register 5; 0x00000179 ***/
|
| 9842 |
|
|
typedef union {
|
| 9843 |
|
|
byte Byte;
|
| 9844 |
|
|
struct {
|
| 9845 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9846 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9847 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9848 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9849 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9850 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9851 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9852 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9853 |
|
|
} Bits;
|
| 9854 |
|
|
struct {
|
| 9855 |
|
|
byte grpDB :8;
|
| 9856 |
|
|
} MergedBits;
|
| 9857 |
|
|
} CAN0TXDSR5STR;
|
| 9858 |
|
|
extern volatile CAN0TXDSR5STR _CAN0TXDSR5 @(REG_BASE + 0x00000179);
|
| 9859 |
|
|
#define CAN0TXDSR5 _CAN0TXDSR5.Byte
|
| 9860 |
|
|
#define CAN0TXDSR5_DB0 _CAN0TXDSR5.Bits.DB0
|
| 9861 |
|
|
#define CAN0TXDSR5_DB1 _CAN0TXDSR5.Bits.DB1
|
| 9862 |
|
|
#define CAN0TXDSR5_DB2 _CAN0TXDSR5.Bits.DB2
|
| 9863 |
|
|
#define CAN0TXDSR5_DB3 _CAN0TXDSR5.Bits.DB3
|
| 9864 |
|
|
#define CAN0TXDSR5_DB4 _CAN0TXDSR5.Bits.DB4
|
| 9865 |
|
|
#define CAN0TXDSR5_DB5 _CAN0TXDSR5.Bits.DB5
|
| 9866 |
|
|
#define CAN0TXDSR5_DB6 _CAN0TXDSR5.Bits.DB6
|
| 9867 |
|
|
#define CAN0TXDSR5_DB7 _CAN0TXDSR5.Bits.DB7
|
| 9868 |
|
|
#define CAN0TXDSR5_DB _CAN0TXDSR5.MergedBits.grpDB
|
| 9869 |
|
|
|
| 9870 |
|
|
|
| 9871 |
|
|
/*** CAN0TXDSR6 - MSCAN 0 Transmit Data Segment Register 6; 0x0000017A ***/
|
| 9872 |
|
|
typedef union {
|
| 9873 |
|
|
byte Byte;
|
| 9874 |
|
|
struct {
|
| 9875 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9876 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9877 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9878 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9879 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9880 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9881 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9882 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9883 |
|
|
} Bits;
|
| 9884 |
|
|
struct {
|
| 9885 |
|
|
byte grpDB :8;
|
| 9886 |
|
|
} MergedBits;
|
| 9887 |
|
|
} CAN0TXDSR6STR;
|
| 9888 |
|
|
extern volatile CAN0TXDSR6STR _CAN0TXDSR6 @(REG_BASE + 0x0000017A);
|
| 9889 |
|
|
#define CAN0TXDSR6 _CAN0TXDSR6.Byte
|
| 9890 |
|
|
#define CAN0TXDSR6_DB0 _CAN0TXDSR6.Bits.DB0
|
| 9891 |
|
|
#define CAN0TXDSR6_DB1 _CAN0TXDSR6.Bits.DB1
|
| 9892 |
|
|
#define CAN0TXDSR6_DB2 _CAN0TXDSR6.Bits.DB2
|
| 9893 |
|
|
#define CAN0TXDSR6_DB3 _CAN0TXDSR6.Bits.DB3
|
| 9894 |
|
|
#define CAN0TXDSR6_DB4 _CAN0TXDSR6.Bits.DB4
|
| 9895 |
|
|
#define CAN0TXDSR6_DB5 _CAN0TXDSR6.Bits.DB5
|
| 9896 |
|
|
#define CAN0TXDSR6_DB6 _CAN0TXDSR6.Bits.DB6
|
| 9897 |
|
|
#define CAN0TXDSR6_DB7 _CAN0TXDSR6.Bits.DB7
|
| 9898 |
|
|
#define CAN0TXDSR6_DB _CAN0TXDSR6.MergedBits.grpDB
|
| 9899 |
|
|
|
| 9900 |
|
|
|
| 9901 |
|
|
/*** CAN0TXDSR7 - MSCAN 0 Transmit Data Segment Register 7; 0x0000017B ***/
|
| 9902 |
|
|
typedef union {
|
| 9903 |
|
|
byte Byte;
|
| 9904 |
|
|
struct {
|
| 9905 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 9906 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 9907 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 9908 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 9909 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 9910 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 9911 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 9912 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 9913 |
|
|
} Bits;
|
| 9914 |
|
|
struct {
|
| 9915 |
|
|
byte grpDB :8;
|
| 9916 |
|
|
} MergedBits;
|
| 9917 |
|
|
} CAN0TXDSR7STR;
|
| 9918 |
|
|
extern volatile CAN0TXDSR7STR _CAN0TXDSR7 @(REG_BASE + 0x0000017B);
|
| 9919 |
|
|
#define CAN0TXDSR7 _CAN0TXDSR7.Byte
|
| 9920 |
|
|
#define CAN0TXDSR7_DB0 _CAN0TXDSR7.Bits.DB0
|
| 9921 |
|
|
#define CAN0TXDSR7_DB1 _CAN0TXDSR7.Bits.DB1
|
| 9922 |
|
|
#define CAN0TXDSR7_DB2 _CAN0TXDSR7.Bits.DB2
|
| 9923 |
|
|
#define CAN0TXDSR7_DB3 _CAN0TXDSR7.Bits.DB3
|
| 9924 |
|
|
#define CAN0TXDSR7_DB4 _CAN0TXDSR7.Bits.DB4
|
| 9925 |
|
|
#define CAN0TXDSR7_DB5 _CAN0TXDSR7.Bits.DB5
|
| 9926 |
|
|
#define CAN0TXDSR7_DB6 _CAN0TXDSR7.Bits.DB6
|
| 9927 |
|
|
#define CAN0TXDSR7_DB7 _CAN0TXDSR7.Bits.DB7
|
| 9928 |
|
|
#define CAN0TXDSR7_DB _CAN0TXDSR7.MergedBits.grpDB
|
| 9929 |
|
|
|
| 9930 |
|
|
|
| 9931 |
|
|
/*** CAN0TXDLR - MSCAN 0 Transmit Data Length Register; 0x0000017C ***/
|
| 9932 |
|
|
typedef union {
|
| 9933 |
|
|
byte Byte;
|
| 9934 |
|
|
struct {
|
| 9935 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 9936 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 9937 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 9938 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 9939 |
|
|
byte :1;
|
| 9940 |
|
|
byte :1;
|
| 9941 |
|
|
byte :1;
|
| 9942 |
|
|
byte :1;
|
| 9943 |
|
|
} Bits;
|
| 9944 |
|
|
struct {
|
| 9945 |
|
|
byte grpDLC :4;
|
| 9946 |
|
|
byte :1;
|
| 9947 |
|
|
byte :1;
|
| 9948 |
|
|
byte :1;
|
| 9949 |
|
|
byte :1;
|
| 9950 |
|
|
} MergedBits;
|
| 9951 |
|
|
} CAN0TXDLRSTR;
|
| 9952 |
|
|
extern volatile CAN0TXDLRSTR _CAN0TXDLR @(REG_BASE + 0x0000017C);
|
| 9953 |
|
|
#define CAN0TXDLR _CAN0TXDLR.Byte
|
| 9954 |
|
|
#define CAN0TXDLR_DLC0 _CAN0TXDLR.Bits.DLC0
|
| 9955 |
|
|
#define CAN0TXDLR_DLC1 _CAN0TXDLR.Bits.DLC1
|
| 9956 |
|
|
#define CAN0TXDLR_DLC2 _CAN0TXDLR.Bits.DLC2
|
| 9957 |
|
|
#define CAN0TXDLR_DLC3 _CAN0TXDLR.Bits.DLC3
|
| 9958 |
|
|
#define CAN0TXDLR_DLC _CAN0TXDLR.MergedBits.grpDLC
|
| 9959 |
|
|
|
| 9960 |
|
|
|
| 9961 |
|
|
/*** CAN0TXTBPR - MSCAN 0 Transmit Buffer Priority; 0x0000017F ***/
|
| 9962 |
|
|
typedef union {
|
| 9963 |
|
|
byte Byte;
|
| 9964 |
|
|
struct {
|
| 9965 |
|
|
byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
|
| 9966 |
|
|
byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
|
| 9967 |
|
|
byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
|
| 9968 |
|
|
byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
|
| 9969 |
|
|
byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
|
| 9970 |
|
|
byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
|
| 9971 |
|
|
byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
|
| 9972 |
|
|
byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
|
| 9973 |
|
|
} Bits;
|
| 9974 |
|
|
struct {
|
| 9975 |
|
|
byte grpPRIO :8;
|
| 9976 |
|
|
} MergedBits;
|
| 9977 |
|
|
} CAN0TXTBPRSTR;
|
| 9978 |
|
|
extern volatile CAN0TXTBPRSTR _CAN0TXTBPR @(REG_BASE + 0x0000017F);
|
| 9979 |
|
|
#define CAN0TXTBPR _CAN0TXTBPR.Byte
|
| 9980 |
|
|
#define CAN0TXTBPR_PRIO0 _CAN0TXTBPR.Bits.PRIO0
|
| 9981 |
|
|
#define CAN0TXTBPR_PRIO1 _CAN0TXTBPR.Bits.PRIO1
|
| 9982 |
|
|
#define CAN0TXTBPR_PRIO2 _CAN0TXTBPR.Bits.PRIO2
|
| 9983 |
|
|
#define CAN0TXTBPR_PRIO3 _CAN0TXTBPR.Bits.PRIO3
|
| 9984 |
|
|
#define CAN0TXTBPR_PRIO4 _CAN0TXTBPR.Bits.PRIO4
|
| 9985 |
|
|
#define CAN0TXTBPR_PRIO5 _CAN0TXTBPR.Bits.PRIO5
|
| 9986 |
|
|
#define CAN0TXTBPR_PRIO6 _CAN0TXTBPR.Bits.PRIO6
|
| 9987 |
|
|
#define CAN0TXTBPR_PRIO7 _CAN0TXTBPR.Bits.PRIO7
|
| 9988 |
|
|
#define CAN0TXTBPR_PRIO _CAN0TXTBPR.MergedBits.grpPRIO
|
| 9989 |
|
|
|
| 9990 |
|
|
|
| 9991 |
|
|
/*** CAN1CTL0 - MSCAN 1 Control 0 Register; 0x00000180 ***/
|
| 9992 |
|
|
typedef union {
|
| 9993 |
|
|
byte Byte;
|
| 9994 |
|
|
struct {
|
| 9995 |
|
|
byte INITRQ :1; /* Initialization Mode Request */
|
| 9996 |
|
|
byte SLPRQ :1; /* Sleep Mode Request */
|
| 9997 |
|
|
byte WUPE :1; /* Wake-Up Enable */
|
| 9998 |
|
|
byte TIME :1; /* Timer Enable */
|
| 9999 |
|
|
byte SYNCH :1; /* Synchronized Status */
|
| 10000 |
|
|
byte CSWAI :1; /* CAN Stops in Wait Mode */
|
| 10001 |
|
|
byte RXACT :1; /* Receiver Active Status */
|
| 10002 |
|
|
byte RXFRM :1; /* Received Frame Flag */
|
| 10003 |
|
|
} Bits;
|
| 10004 |
|
|
} CAN1CTL0STR;
|
| 10005 |
|
|
extern volatile CAN1CTL0STR _CAN1CTL0 @(REG_BASE + 0x00000180);
|
| 10006 |
|
|
#define CAN1CTL0 _CAN1CTL0.Byte
|
| 10007 |
|
|
#define CAN1CTL0_INITRQ _CAN1CTL0.Bits.INITRQ
|
| 10008 |
|
|
#define CAN1CTL0_SLPRQ _CAN1CTL0.Bits.SLPRQ
|
| 10009 |
|
|
#define CAN1CTL0_WUPE _CAN1CTL0.Bits.WUPE
|
| 10010 |
|
|
#define CAN1CTL0_TIME _CAN1CTL0.Bits.TIME
|
| 10011 |
|
|
#define CAN1CTL0_SYNCH _CAN1CTL0.Bits.SYNCH
|
| 10012 |
|
|
#define CAN1CTL0_CSWAI _CAN1CTL0.Bits.CSWAI
|
| 10013 |
|
|
#define CAN1CTL0_RXACT _CAN1CTL0.Bits.RXACT
|
| 10014 |
|
|
#define CAN1CTL0_RXFRM _CAN1CTL0.Bits.RXFRM
|
| 10015 |
|
|
|
| 10016 |
|
|
|
| 10017 |
|
|
/*** CAN1CTL1 - MSCAN 1 Control 1 Register; 0x00000181 ***/
|
| 10018 |
|
|
typedef union {
|
| 10019 |
|
|
byte Byte;
|
| 10020 |
|
|
struct {
|
| 10021 |
|
|
byte INITAK :1; /* Initialization Mode Acknowledge */
|
| 10022 |
|
|
byte SLPAK :1; /* Sleep Mode Acknowledge */
|
| 10023 |
|
|
byte WUPM :1; /* Wake-Up Mode */
|
| 10024 |
|
|
byte :1;
|
| 10025 |
|
|
byte LISTEN :1; /* Listen Only Mode */
|
| 10026 |
|
|
byte LOOPB :1; /* Loop Back Self Test Mode */
|
| 10027 |
|
|
byte CLKSRC :1; /* MSCAN 1 Clock Source */
|
| 10028 |
|
|
byte CANE :1; /* MSCAN 1 Enable */
|
| 10029 |
|
|
} Bits;
|
| 10030 |
|
|
} CAN1CTL1STR;
|
| 10031 |
|
|
extern volatile CAN1CTL1STR _CAN1CTL1 @(REG_BASE + 0x00000181);
|
| 10032 |
|
|
#define CAN1CTL1 _CAN1CTL1.Byte
|
| 10033 |
|
|
#define CAN1CTL1_INITAK _CAN1CTL1.Bits.INITAK
|
| 10034 |
|
|
#define CAN1CTL1_SLPAK _CAN1CTL1.Bits.SLPAK
|
| 10035 |
|
|
#define CAN1CTL1_WUPM _CAN1CTL1.Bits.WUPM
|
| 10036 |
|
|
#define CAN1CTL1_LISTEN _CAN1CTL1.Bits.LISTEN
|
| 10037 |
|
|
#define CAN1CTL1_LOOPB _CAN1CTL1.Bits.LOOPB
|
| 10038 |
|
|
#define CAN1CTL1_CLKSRC _CAN1CTL1.Bits.CLKSRC
|
| 10039 |
|
|
#define CAN1CTL1_CANE _CAN1CTL1.Bits.CANE
|
| 10040 |
|
|
|
| 10041 |
|
|
|
| 10042 |
|
|
/*** CAN1BTR0 - MSCAN 1 Bus Timing Register 0; 0x00000182 ***/
|
| 10043 |
|
|
typedef union {
|
| 10044 |
|
|
byte Byte;
|
| 10045 |
|
|
struct {
|
| 10046 |
|
|
byte BRP0 :1; /* Baud Rate Prescaler 0 */
|
| 10047 |
|
|
byte BRP1 :1; /* Baud Rate Prescaler 1 */
|
| 10048 |
|
|
byte BRP2 :1; /* Baud Rate Prescaler 2 */
|
| 10049 |
|
|
byte BRP3 :1; /* Baud Rate Prescaler 3 */
|
| 10050 |
|
|
byte BRP4 :1; /* Baud Rate Prescaler 4 */
|
| 10051 |
|
|
byte BRP5 :1; /* Baud Rate Prescaler 5 */
|
| 10052 |
|
|
byte SJW0 :1; /* Synchronization Jump Width 0 */
|
| 10053 |
|
|
byte SJW1 :1; /* Synchronization Jump Width 1 */
|
| 10054 |
|
|
} Bits;
|
| 10055 |
|
|
struct {
|
| 10056 |
|
|
byte grpBRP :6;
|
| 10057 |
|
|
byte grpSJW :2;
|
| 10058 |
|
|
} MergedBits;
|
| 10059 |
|
|
} CAN1BTR0STR;
|
| 10060 |
|
|
extern volatile CAN1BTR0STR _CAN1BTR0 @(REG_BASE + 0x00000182);
|
| 10061 |
|
|
#define CAN1BTR0 _CAN1BTR0.Byte
|
| 10062 |
|
|
#define CAN1BTR0_BRP0 _CAN1BTR0.Bits.BRP0
|
| 10063 |
|
|
#define CAN1BTR0_BRP1 _CAN1BTR0.Bits.BRP1
|
| 10064 |
|
|
#define CAN1BTR0_BRP2 _CAN1BTR0.Bits.BRP2
|
| 10065 |
|
|
#define CAN1BTR0_BRP3 _CAN1BTR0.Bits.BRP3
|
| 10066 |
|
|
#define CAN1BTR0_BRP4 _CAN1BTR0.Bits.BRP4
|
| 10067 |
|
|
#define CAN1BTR0_BRP5 _CAN1BTR0.Bits.BRP5
|
| 10068 |
|
|
#define CAN1BTR0_SJW0 _CAN1BTR0.Bits.SJW0
|
| 10069 |
|
|
#define CAN1BTR0_SJW1 _CAN1BTR0.Bits.SJW1
|
| 10070 |
|
|
#define CAN1BTR0_BRP _CAN1BTR0.MergedBits.grpBRP
|
| 10071 |
|
|
#define CAN1BTR0_SJW _CAN1BTR0.MergedBits.grpSJW
|
| 10072 |
|
|
|
| 10073 |
|
|
|
| 10074 |
|
|
/*** CAN1BTR1 - MSCAN 1 Bus Timing Register 1; 0x00000183 ***/
|
| 10075 |
|
|
typedef union {
|
| 10076 |
|
|
byte Byte;
|
| 10077 |
|
|
struct {
|
| 10078 |
|
|
byte TSEG10 :1; /* Time Segment 1 */
|
| 10079 |
|
|
byte TSEG11 :1; /* Time Segment 1 */
|
| 10080 |
|
|
byte TSEG12 :1; /* Time Segment 1 */
|
| 10081 |
|
|
byte TSEG13 :1; /* Time Segment 1 */
|
| 10082 |
|
|
byte TSEG20 :1; /* Time Segment 2 */
|
| 10083 |
|
|
byte TSEG21 :1; /* Time Segment 2 */
|
| 10084 |
|
|
byte TSEG22 :1; /* Time Segment 2 */
|
| 10085 |
|
|
byte SAMP :1; /* Sampling */
|
| 10086 |
|
|
} Bits;
|
| 10087 |
|
|
struct {
|
| 10088 |
|
|
byte grpTSEG_10 :4;
|
| 10089 |
|
|
byte grpTSEG_20 :3;
|
| 10090 |
|
|
byte :1;
|
| 10091 |
|
|
} MergedBits;
|
| 10092 |
|
|
} CAN1BTR1STR;
|
| 10093 |
|
|
extern volatile CAN1BTR1STR _CAN1BTR1 @(REG_BASE + 0x00000183);
|
| 10094 |
|
|
#define CAN1BTR1 _CAN1BTR1.Byte
|
| 10095 |
|
|
#define CAN1BTR1_TSEG10 _CAN1BTR1.Bits.TSEG10
|
| 10096 |
|
|
#define CAN1BTR1_TSEG11 _CAN1BTR1.Bits.TSEG11
|
| 10097 |
|
|
#define CAN1BTR1_TSEG12 _CAN1BTR1.Bits.TSEG12
|
| 10098 |
|
|
#define CAN1BTR1_TSEG13 _CAN1BTR1.Bits.TSEG13
|
| 10099 |
|
|
#define CAN1BTR1_TSEG20 _CAN1BTR1.Bits.TSEG20
|
| 10100 |
|
|
#define CAN1BTR1_TSEG21 _CAN1BTR1.Bits.TSEG21
|
| 10101 |
|
|
#define CAN1BTR1_TSEG22 _CAN1BTR1.Bits.TSEG22
|
| 10102 |
|
|
#define CAN1BTR1_SAMP _CAN1BTR1.Bits.SAMP
|
| 10103 |
|
|
#define CAN1BTR1_TSEG_10 _CAN1BTR1.MergedBits.grpTSEG_10
|
| 10104 |
|
|
#define CAN1BTR1_TSEG_20 _CAN1BTR1.MergedBits.grpTSEG_20
|
| 10105 |
|
|
#define CAN1BTR1_TSEG CAN1BTR1_TSEG_10
|
| 10106 |
|
|
|
| 10107 |
|
|
|
| 10108 |
|
|
/*** CAN1RFLG - MSCAN 1 Receiver Flag Register; 0x00000184 ***/
|
| 10109 |
|
|
typedef union {
|
| 10110 |
|
|
byte Byte;
|
| 10111 |
|
|
struct {
|
| 10112 |
|
|
byte RXF :1; /* Receive Buffer Full */
|
| 10113 |
|
|
byte OVRIF :1; /* Overrun Interrupt Flag */
|
| 10114 |
|
|
byte TSTAT0 :1; /* Transmitter Status Bit 0 */
|
| 10115 |
|
|
byte TSTAT1 :1; /* Transmitter Status Bit 1 */
|
| 10116 |
|
|
byte RSTAT0 :1; /* Receiver Status Bit 0 */
|
| 10117 |
|
|
byte RSTAT1 :1; /* Receiver Status Bit 1 */
|
| 10118 |
|
|
byte CSCIF :1; /* CAN Status Change Interrupt Flag */
|
| 10119 |
|
|
byte WUPIF :1; /* Wake-up Interrupt Flag */
|
| 10120 |
|
|
} Bits;
|
| 10121 |
|
|
struct {
|
| 10122 |
|
|
byte :1;
|
| 10123 |
|
|
byte :1;
|
| 10124 |
|
|
byte grpTSTAT :2;
|
| 10125 |
|
|
byte grpRSTAT :2;
|
| 10126 |
|
|
byte :1;
|
| 10127 |
|
|
byte :1;
|
| 10128 |
|
|
} MergedBits;
|
| 10129 |
|
|
} CAN1RFLGSTR;
|
| 10130 |
|
|
extern volatile CAN1RFLGSTR _CAN1RFLG @(REG_BASE + 0x00000184);
|
| 10131 |
|
|
#define CAN1RFLG _CAN1RFLG.Byte
|
| 10132 |
|
|
#define CAN1RFLG_RXF _CAN1RFLG.Bits.RXF
|
| 10133 |
|
|
#define CAN1RFLG_OVRIF _CAN1RFLG.Bits.OVRIF
|
| 10134 |
|
|
#define CAN1RFLG_TSTAT0 _CAN1RFLG.Bits.TSTAT0
|
| 10135 |
|
|
#define CAN1RFLG_TSTAT1 _CAN1RFLG.Bits.TSTAT1
|
| 10136 |
|
|
#define CAN1RFLG_RSTAT0 _CAN1RFLG.Bits.RSTAT0
|
| 10137 |
|
|
#define CAN1RFLG_RSTAT1 _CAN1RFLG.Bits.RSTAT1
|
| 10138 |
|
|
#define CAN1RFLG_CSCIF _CAN1RFLG.Bits.CSCIF
|
| 10139 |
|
|
#define CAN1RFLG_WUPIF _CAN1RFLG.Bits.WUPIF
|
| 10140 |
|
|
#define CAN1RFLG_TSTAT _CAN1RFLG.MergedBits.grpTSTAT
|
| 10141 |
|
|
#define CAN1RFLG_RSTAT _CAN1RFLG.MergedBits.grpRSTAT
|
| 10142 |
|
|
|
| 10143 |
|
|
|
| 10144 |
|
|
/*** CAN1RIER - MSCAN 1 Receiver Interrupt Enable Register; 0x00000185 ***/
|
| 10145 |
|
|
typedef union {
|
| 10146 |
|
|
byte Byte;
|
| 10147 |
|
|
struct {
|
| 10148 |
|
|
byte RXFIE :1; /* Receiver Full Interrupt Enable */
|
| 10149 |
|
|
byte OVRIE :1; /* Overrun Interrupt Enable */
|
| 10150 |
|
|
byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
|
| 10151 |
|
|
byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
|
| 10152 |
|
|
byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
|
| 10153 |
|
|
byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
|
| 10154 |
|
|
byte CSCIE :1; /* CAN Status Change Interrupt Enable */
|
| 10155 |
|
|
byte WUPIE :1; /* Wake-up Interrupt Enable */
|
| 10156 |
|
|
} Bits;
|
| 10157 |
|
|
struct {
|
| 10158 |
|
|
byte :1;
|
| 10159 |
|
|
byte :1;
|
| 10160 |
|
|
byte grpTSTATE :2;
|
| 10161 |
|
|
byte grpRSTATE :2;
|
| 10162 |
|
|
byte :1;
|
| 10163 |
|
|
byte :1;
|
| 10164 |
|
|
} MergedBits;
|
| 10165 |
|
|
} CAN1RIERSTR;
|
| 10166 |
|
|
extern volatile CAN1RIERSTR _CAN1RIER @(REG_BASE + 0x00000185);
|
| 10167 |
|
|
#define CAN1RIER _CAN1RIER.Byte
|
| 10168 |
|
|
#define CAN1RIER_RXFIE _CAN1RIER.Bits.RXFIE
|
| 10169 |
|
|
#define CAN1RIER_OVRIE _CAN1RIER.Bits.OVRIE
|
| 10170 |
|
|
#define CAN1RIER_TSTATE0 _CAN1RIER.Bits.TSTATE0
|
| 10171 |
|
|
#define CAN1RIER_TSTATE1 _CAN1RIER.Bits.TSTATE1
|
| 10172 |
|
|
#define CAN1RIER_RSTATE0 _CAN1RIER.Bits.RSTATE0
|
| 10173 |
|
|
#define CAN1RIER_RSTATE1 _CAN1RIER.Bits.RSTATE1
|
| 10174 |
|
|
#define CAN1RIER_CSCIE _CAN1RIER.Bits.CSCIE
|
| 10175 |
|
|
#define CAN1RIER_WUPIE _CAN1RIER.Bits.WUPIE
|
| 10176 |
|
|
#define CAN1RIER_TSTATE _CAN1RIER.MergedBits.grpTSTATE
|
| 10177 |
|
|
#define CAN1RIER_RSTATE _CAN1RIER.MergedBits.grpRSTATE
|
| 10178 |
|
|
|
| 10179 |
|
|
|
| 10180 |
|
|
/*** CAN1TFLG - MSCAN 1 Transmitter Flag Register; 0x00000186 ***/
|
| 10181 |
|
|
typedef union {
|
| 10182 |
|
|
byte Byte;
|
| 10183 |
|
|
struct {
|
| 10184 |
|
|
byte TXE0 :1; /* Transmitter Buffer Empty 0 */
|
| 10185 |
|
|
byte TXE1 :1; /* Transmitter Buffer Empty 1 */
|
| 10186 |
|
|
byte TXE2 :1; /* Transmitter Buffer Empty 2 */
|
| 10187 |
|
|
byte :1;
|
| 10188 |
|
|
byte :1;
|
| 10189 |
|
|
byte :1;
|
| 10190 |
|
|
byte :1;
|
| 10191 |
|
|
byte :1;
|
| 10192 |
|
|
} Bits;
|
| 10193 |
|
|
struct {
|
| 10194 |
|
|
byte grpTXE :3;
|
| 10195 |
|
|
byte :1;
|
| 10196 |
|
|
byte :1;
|
| 10197 |
|
|
byte :1;
|
| 10198 |
|
|
byte :1;
|
| 10199 |
|
|
byte :1;
|
| 10200 |
|
|
} MergedBits;
|
| 10201 |
|
|
} CAN1TFLGSTR;
|
| 10202 |
|
|
extern volatile CAN1TFLGSTR _CAN1TFLG @(REG_BASE + 0x00000186);
|
| 10203 |
|
|
#define CAN1TFLG _CAN1TFLG.Byte
|
| 10204 |
|
|
#define CAN1TFLG_TXE0 _CAN1TFLG.Bits.TXE0
|
| 10205 |
|
|
#define CAN1TFLG_TXE1 _CAN1TFLG.Bits.TXE1
|
| 10206 |
|
|
#define CAN1TFLG_TXE2 _CAN1TFLG.Bits.TXE2
|
| 10207 |
|
|
#define CAN1TFLG_TXE _CAN1TFLG.MergedBits.grpTXE
|
| 10208 |
|
|
|
| 10209 |
|
|
|
| 10210 |
|
|
/*** CAN1TIER - MSCAN 1 Transmitter Interrupt Enable Register; 0x00000187 ***/
|
| 10211 |
|
|
typedef union {
|
| 10212 |
|
|
byte Byte;
|
| 10213 |
|
|
struct {
|
| 10214 |
|
|
byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
|
| 10215 |
|
|
byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
|
| 10216 |
|
|
byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
|
| 10217 |
|
|
byte :1;
|
| 10218 |
|
|
byte :1;
|
| 10219 |
|
|
byte :1;
|
| 10220 |
|
|
byte :1;
|
| 10221 |
|
|
byte :1;
|
| 10222 |
|
|
} Bits;
|
| 10223 |
|
|
struct {
|
| 10224 |
|
|
byte grpTXEIE :3;
|
| 10225 |
|
|
byte :1;
|
| 10226 |
|
|
byte :1;
|
| 10227 |
|
|
byte :1;
|
| 10228 |
|
|
byte :1;
|
| 10229 |
|
|
byte :1;
|
| 10230 |
|
|
} MergedBits;
|
| 10231 |
|
|
} CAN1TIERSTR;
|
| 10232 |
|
|
extern volatile CAN1TIERSTR _CAN1TIER @(REG_BASE + 0x00000187);
|
| 10233 |
|
|
#define CAN1TIER _CAN1TIER.Byte
|
| 10234 |
|
|
#define CAN1TIER_TXEIE0 _CAN1TIER.Bits.TXEIE0
|
| 10235 |
|
|
#define CAN1TIER_TXEIE1 _CAN1TIER.Bits.TXEIE1
|
| 10236 |
|
|
#define CAN1TIER_TXEIE2 _CAN1TIER.Bits.TXEIE2
|
| 10237 |
|
|
#define CAN1TIER_TXEIE _CAN1TIER.MergedBits.grpTXEIE
|
| 10238 |
|
|
|
| 10239 |
|
|
|
| 10240 |
|
|
/*** CAN1TARQ - MSCAN 1 Transmitter Message Abort Request; 0x00000188 ***/
|
| 10241 |
|
|
typedef union {
|
| 10242 |
|
|
byte Byte;
|
| 10243 |
|
|
struct {
|
| 10244 |
|
|
byte ABTRQ0 :1; /* Abort Request 0 */
|
| 10245 |
|
|
byte ABTRQ1 :1; /* Abort Request 1 */
|
| 10246 |
|
|
byte ABTRQ2 :1; /* Abort Request 2 */
|
| 10247 |
|
|
byte :1;
|
| 10248 |
|
|
byte :1;
|
| 10249 |
|
|
byte :1;
|
| 10250 |
|
|
byte :1;
|
| 10251 |
|
|
byte :1;
|
| 10252 |
|
|
} Bits;
|
| 10253 |
|
|
struct {
|
| 10254 |
|
|
byte grpABTRQ :3;
|
| 10255 |
|
|
byte :1;
|
| 10256 |
|
|
byte :1;
|
| 10257 |
|
|
byte :1;
|
| 10258 |
|
|
byte :1;
|
| 10259 |
|
|
byte :1;
|
| 10260 |
|
|
} MergedBits;
|
| 10261 |
|
|
} CAN1TARQSTR;
|
| 10262 |
|
|
extern volatile CAN1TARQSTR _CAN1TARQ @(REG_BASE + 0x00000188);
|
| 10263 |
|
|
#define CAN1TARQ _CAN1TARQ.Byte
|
| 10264 |
|
|
#define CAN1TARQ_ABTRQ0 _CAN1TARQ.Bits.ABTRQ0
|
| 10265 |
|
|
#define CAN1TARQ_ABTRQ1 _CAN1TARQ.Bits.ABTRQ1
|
| 10266 |
|
|
#define CAN1TARQ_ABTRQ2 _CAN1TARQ.Bits.ABTRQ2
|
| 10267 |
|
|
#define CAN1TARQ_ABTRQ _CAN1TARQ.MergedBits.grpABTRQ
|
| 10268 |
|
|
|
| 10269 |
|
|
|
| 10270 |
|
|
/*** CAN1TAAK - MSCAN 1 Transmitter Message Abort Control; 0x00000189 ***/
|
| 10271 |
|
|
typedef union {
|
| 10272 |
|
|
byte Byte;
|
| 10273 |
|
|
struct {
|
| 10274 |
|
|
byte ABTAK0 :1; /* Abort Acknowledge 0 */
|
| 10275 |
|
|
byte ABTAK1 :1; /* Abort Acknowledge 1 */
|
| 10276 |
|
|
byte ABTAK2 :1; /* Abort Acknowledge 2 */
|
| 10277 |
|
|
byte :1;
|
| 10278 |
|
|
byte :1;
|
| 10279 |
|
|
byte :1;
|
| 10280 |
|
|
byte :1;
|
| 10281 |
|
|
byte :1;
|
| 10282 |
|
|
} Bits;
|
| 10283 |
|
|
struct {
|
| 10284 |
|
|
byte grpABTAK :3;
|
| 10285 |
|
|
byte :1;
|
| 10286 |
|
|
byte :1;
|
| 10287 |
|
|
byte :1;
|
| 10288 |
|
|
byte :1;
|
| 10289 |
|
|
byte :1;
|
| 10290 |
|
|
} MergedBits;
|
| 10291 |
|
|
} CAN1TAAKSTR;
|
| 10292 |
|
|
extern volatile CAN1TAAKSTR _CAN1TAAK @(REG_BASE + 0x00000189);
|
| 10293 |
|
|
#define CAN1TAAK _CAN1TAAK.Byte
|
| 10294 |
|
|
#define CAN1TAAK_ABTAK0 _CAN1TAAK.Bits.ABTAK0
|
| 10295 |
|
|
#define CAN1TAAK_ABTAK1 _CAN1TAAK.Bits.ABTAK1
|
| 10296 |
|
|
#define CAN1TAAK_ABTAK2 _CAN1TAAK.Bits.ABTAK2
|
| 10297 |
|
|
#define CAN1TAAK_ABTAK _CAN1TAAK.MergedBits.grpABTAK
|
| 10298 |
|
|
|
| 10299 |
|
|
|
| 10300 |
|
|
/*** CAN1TBSEL - MSCAN 1 Transmit Buffer Selection; 0x0000018A ***/
|
| 10301 |
|
|
typedef union {
|
| 10302 |
|
|
byte Byte;
|
| 10303 |
|
|
struct {
|
| 10304 |
|
|
byte TX0 :1; /* Transmit Buffer Select 0 */
|
| 10305 |
|
|
byte TX1 :1; /* Transmit Buffer Select 1 */
|
| 10306 |
|
|
byte TX2 :1; /* Transmit Buffer Select 2 */
|
| 10307 |
|
|
byte :1;
|
| 10308 |
|
|
byte :1;
|
| 10309 |
|
|
byte :1;
|
| 10310 |
|
|
byte :1;
|
| 10311 |
|
|
byte :1;
|
| 10312 |
|
|
} Bits;
|
| 10313 |
|
|
struct {
|
| 10314 |
|
|
byte grpTX :3;
|
| 10315 |
|
|
byte :1;
|
| 10316 |
|
|
byte :1;
|
| 10317 |
|
|
byte :1;
|
| 10318 |
|
|
byte :1;
|
| 10319 |
|
|
byte :1;
|
| 10320 |
|
|
} MergedBits;
|
| 10321 |
|
|
} CAN1TBSELSTR;
|
| 10322 |
|
|
extern volatile CAN1TBSELSTR _CAN1TBSEL @(REG_BASE + 0x0000018A);
|
| 10323 |
|
|
#define CAN1TBSEL _CAN1TBSEL.Byte
|
| 10324 |
|
|
#define CAN1TBSEL_TX0 _CAN1TBSEL.Bits.TX0
|
| 10325 |
|
|
#define CAN1TBSEL_TX1 _CAN1TBSEL.Bits.TX1
|
| 10326 |
|
|
#define CAN1TBSEL_TX2 _CAN1TBSEL.Bits.TX2
|
| 10327 |
|
|
#define CAN1TBSEL_TX _CAN1TBSEL.MergedBits.grpTX
|
| 10328 |
|
|
|
| 10329 |
|
|
|
| 10330 |
|
|
/*** CAN1IDAC - MSCAN 1 Identifier Acceptance Control Register; 0x0000018B ***/
|
| 10331 |
|
|
typedef union {
|
| 10332 |
|
|
byte Byte;
|
| 10333 |
|
|
struct {
|
| 10334 |
|
|
byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
|
| 10335 |
|
|
byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
|
| 10336 |
|
|
byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
|
| 10337 |
|
|
byte :1;
|
| 10338 |
|
|
byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
|
| 10339 |
|
|
byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
|
| 10340 |
|
|
byte :1;
|
| 10341 |
|
|
byte :1;
|
| 10342 |
|
|
} Bits;
|
| 10343 |
|
|
struct {
|
| 10344 |
|
|
byte grpIDHIT :3;
|
| 10345 |
|
|
byte :1;
|
| 10346 |
|
|
byte grpIDAM :2;
|
| 10347 |
|
|
byte :1;
|
| 10348 |
|
|
byte :1;
|
| 10349 |
|
|
} MergedBits;
|
| 10350 |
|
|
} CAN1IDACSTR;
|
| 10351 |
|
|
extern volatile CAN1IDACSTR _CAN1IDAC @(REG_BASE + 0x0000018B);
|
| 10352 |
|
|
#define CAN1IDAC _CAN1IDAC.Byte
|
| 10353 |
|
|
#define CAN1IDAC_IDHIT0 _CAN1IDAC.Bits.IDHIT0
|
| 10354 |
|
|
#define CAN1IDAC_IDHIT1 _CAN1IDAC.Bits.IDHIT1
|
| 10355 |
|
|
#define CAN1IDAC_IDHIT2 _CAN1IDAC.Bits.IDHIT2
|
| 10356 |
|
|
#define CAN1IDAC_IDAM0 _CAN1IDAC.Bits.IDAM0
|
| 10357 |
|
|
#define CAN1IDAC_IDAM1 _CAN1IDAC.Bits.IDAM1
|
| 10358 |
|
|
#define CAN1IDAC_IDHIT _CAN1IDAC.MergedBits.grpIDHIT
|
| 10359 |
|
|
#define CAN1IDAC_IDAM _CAN1IDAC.MergedBits.grpIDAM
|
| 10360 |
|
|
|
| 10361 |
|
|
|
| 10362 |
|
|
/*** CAN1RXERR - MSCAN 1 Receive Error Counter Register; 0x0000018E ***/
|
| 10363 |
|
|
typedef union {
|
| 10364 |
|
|
byte Byte;
|
| 10365 |
|
|
struct {
|
| 10366 |
|
|
byte RXERR0 :1; /* Bit 0 */
|
| 10367 |
|
|
byte RXERR1 :1; /* Bit 1 */
|
| 10368 |
|
|
byte RXERR2 :1; /* Bit 2 */
|
| 10369 |
|
|
byte RXERR3 :1; /* Bit 3 */
|
| 10370 |
|
|
byte RXERR4 :1; /* Bit 4 */
|
| 10371 |
|
|
byte RXERR5 :1; /* Bit 5 */
|
| 10372 |
|
|
byte RXERR6 :1; /* Bit 6 */
|
| 10373 |
|
|
byte RXERR7 :1; /* Bit 7 */
|
| 10374 |
|
|
} Bits;
|
| 10375 |
|
|
struct {
|
| 10376 |
|
|
byte grpRXERR :8;
|
| 10377 |
|
|
} MergedBits;
|
| 10378 |
|
|
} CAN1RXERRSTR;
|
| 10379 |
|
|
extern volatile CAN1RXERRSTR _CAN1RXERR @(REG_BASE + 0x0000018E);
|
| 10380 |
|
|
#define CAN1RXERR _CAN1RXERR.Byte
|
| 10381 |
|
|
#define CAN1RXERR_RXERR0 _CAN1RXERR.Bits.RXERR0
|
| 10382 |
|
|
#define CAN1RXERR_RXERR1 _CAN1RXERR.Bits.RXERR1
|
| 10383 |
|
|
#define CAN1RXERR_RXERR2 _CAN1RXERR.Bits.RXERR2
|
| 10384 |
|
|
#define CAN1RXERR_RXERR3 _CAN1RXERR.Bits.RXERR3
|
| 10385 |
|
|
#define CAN1RXERR_RXERR4 _CAN1RXERR.Bits.RXERR4
|
| 10386 |
|
|
#define CAN1RXERR_RXERR5 _CAN1RXERR.Bits.RXERR5
|
| 10387 |
|
|
#define CAN1RXERR_RXERR6 _CAN1RXERR.Bits.RXERR6
|
| 10388 |
|
|
#define CAN1RXERR_RXERR7 _CAN1RXERR.Bits.RXERR7
|
| 10389 |
|
|
#define CAN1RXERR_RXERR _CAN1RXERR.MergedBits.grpRXERR
|
| 10390 |
|
|
|
| 10391 |
|
|
|
| 10392 |
|
|
/*** CAN1TXERR - MSCAN 1 Transmit Error Counter Register; 0x0000018F ***/
|
| 10393 |
|
|
typedef union {
|
| 10394 |
|
|
byte Byte;
|
| 10395 |
|
|
struct {
|
| 10396 |
|
|
byte TXERR0 :1; /* Bit 0 */
|
| 10397 |
|
|
byte TXERR1 :1; /* Bit 1 */
|
| 10398 |
|
|
byte TXERR2 :1; /* Bit 2 */
|
| 10399 |
|
|
byte TXERR3 :1; /* Bit 3 */
|
| 10400 |
|
|
byte TXERR4 :1; /* Bit 4 */
|
| 10401 |
|
|
byte TXERR5 :1; /* Bit 5 */
|
| 10402 |
|
|
byte TXERR6 :1; /* Bit 6 */
|
| 10403 |
|
|
byte TXERR7 :1; /* Bit 7 */
|
| 10404 |
|
|
} Bits;
|
| 10405 |
|
|
struct {
|
| 10406 |
|
|
byte grpTXERR :8;
|
| 10407 |
|
|
} MergedBits;
|
| 10408 |
|
|
} CAN1TXERRSTR;
|
| 10409 |
|
|
extern volatile CAN1TXERRSTR _CAN1TXERR @(REG_BASE + 0x0000018F);
|
| 10410 |
|
|
#define CAN1TXERR _CAN1TXERR.Byte
|
| 10411 |
|
|
#define CAN1TXERR_TXERR0 _CAN1TXERR.Bits.TXERR0
|
| 10412 |
|
|
#define CAN1TXERR_TXERR1 _CAN1TXERR.Bits.TXERR1
|
| 10413 |
|
|
#define CAN1TXERR_TXERR2 _CAN1TXERR.Bits.TXERR2
|
| 10414 |
|
|
#define CAN1TXERR_TXERR3 _CAN1TXERR.Bits.TXERR3
|
| 10415 |
|
|
#define CAN1TXERR_TXERR4 _CAN1TXERR.Bits.TXERR4
|
| 10416 |
|
|
#define CAN1TXERR_TXERR5 _CAN1TXERR.Bits.TXERR5
|
| 10417 |
|
|
#define CAN1TXERR_TXERR6 _CAN1TXERR.Bits.TXERR6
|
| 10418 |
|
|
#define CAN1TXERR_TXERR7 _CAN1TXERR.Bits.TXERR7
|
| 10419 |
|
|
#define CAN1TXERR_TXERR _CAN1TXERR.MergedBits.grpTXERR
|
| 10420 |
|
|
|
| 10421 |
|
|
|
| 10422 |
|
|
/*** CAN1IDAR0 - MSCAN 1 Identifier Acceptance Register 0; 0x00000190 ***/
|
| 10423 |
|
|
typedef union {
|
| 10424 |
|
|
byte Byte;
|
| 10425 |
|
|
struct {
|
| 10426 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 10427 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 10428 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 10429 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 10430 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 10431 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 10432 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 10433 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 10434 |
|
|
} Bits;
|
| 10435 |
|
|
struct {
|
| 10436 |
|
|
byte grpAC :8;
|
| 10437 |
|
|
} MergedBits;
|
| 10438 |
|
|
} CAN1IDAR0STR;
|
| 10439 |
|
|
extern volatile CAN1IDAR0STR _CAN1IDAR0 @(REG_BASE + 0x00000190);
|
| 10440 |
|
|
#define CAN1IDAR0 _CAN1IDAR0.Byte
|
| 10441 |
|
|
#define CAN1IDAR0_AC0 _CAN1IDAR0.Bits.AC0
|
| 10442 |
|
|
#define CAN1IDAR0_AC1 _CAN1IDAR0.Bits.AC1
|
| 10443 |
|
|
#define CAN1IDAR0_AC2 _CAN1IDAR0.Bits.AC2
|
| 10444 |
|
|
#define CAN1IDAR0_AC3 _CAN1IDAR0.Bits.AC3
|
| 10445 |
|
|
#define CAN1IDAR0_AC4 _CAN1IDAR0.Bits.AC4
|
| 10446 |
|
|
#define CAN1IDAR0_AC5 _CAN1IDAR0.Bits.AC5
|
| 10447 |
|
|
#define CAN1IDAR0_AC6 _CAN1IDAR0.Bits.AC6
|
| 10448 |
|
|
#define CAN1IDAR0_AC7 _CAN1IDAR0.Bits.AC7
|
| 10449 |
|
|
#define CAN1IDAR0_AC _CAN1IDAR0.MergedBits.grpAC
|
| 10450 |
|
|
|
| 10451 |
|
|
|
| 10452 |
|
|
/*** CAN1IDAR1 - MSCAN 1 Identifier Acceptance Register 1; 0x00000191 ***/
|
| 10453 |
|
|
typedef union {
|
| 10454 |
|
|
byte Byte;
|
| 10455 |
|
|
struct {
|
| 10456 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 10457 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 10458 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 10459 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 10460 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 10461 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 10462 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 10463 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 10464 |
|
|
} Bits;
|
| 10465 |
|
|
struct {
|
| 10466 |
|
|
byte grpAC :8;
|
| 10467 |
|
|
} MergedBits;
|
| 10468 |
|
|
} CAN1IDAR1STR;
|
| 10469 |
|
|
extern volatile CAN1IDAR1STR _CAN1IDAR1 @(REG_BASE + 0x00000191);
|
| 10470 |
|
|
#define CAN1IDAR1 _CAN1IDAR1.Byte
|
| 10471 |
|
|
#define CAN1IDAR1_AC0 _CAN1IDAR1.Bits.AC0
|
| 10472 |
|
|
#define CAN1IDAR1_AC1 _CAN1IDAR1.Bits.AC1
|
| 10473 |
|
|
#define CAN1IDAR1_AC2 _CAN1IDAR1.Bits.AC2
|
| 10474 |
|
|
#define CAN1IDAR1_AC3 _CAN1IDAR1.Bits.AC3
|
| 10475 |
|
|
#define CAN1IDAR1_AC4 _CAN1IDAR1.Bits.AC4
|
| 10476 |
|
|
#define CAN1IDAR1_AC5 _CAN1IDAR1.Bits.AC5
|
| 10477 |
|
|
#define CAN1IDAR1_AC6 _CAN1IDAR1.Bits.AC6
|
| 10478 |
|
|
#define CAN1IDAR1_AC7 _CAN1IDAR1.Bits.AC7
|
| 10479 |
|
|
#define CAN1IDAR1_AC _CAN1IDAR1.MergedBits.grpAC
|
| 10480 |
|
|
|
| 10481 |
|
|
|
| 10482 |
|
|
/*** CAN1IDAR2 - MSCAN 1 Identifier Acceptance Register 2; 0x00000192 ***/
|
| 10483 |
|
|
typedef union {
|
| 10484 |
|
|
byte Byte;
|
| 10485 |
|
|
struct {
|
| 10486 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 10487 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 10488 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 10489 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 10490 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 10491 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 10492 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 10493 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 10494 |
|
|
} Bits;
|
| 10495 |
|
|
struct {
|
| 10496 |
|
|
byte grpAC :8;
|
| 10497 |
|
|
} MergedBits;
|
| 10498 |
|
|
} CAN1IDAR2STR;
|
| 10499 |
|
|
extern volatile CAN1IDAR2STR _CAN1IDAR2 @(REG_BASE + 0x00000192);
|
| 10500 |
|
|
#define CAN1IDAR2 _CAN1IDAR2.Byte
|
| 10501 |
|
|
#define CAN1IDAR2_AC0 _CAN1IDAR2.Bits.AC0
|
| 10502 |
|
|
#define CAN1IDAR2_AC1 _CAN1IDAR2.Bits.AC1
|
| 10503 |
|
|
#define CAN1IDAR2_AC2 _CAN1IDAR2.Bits.AC2
|
| 10504 |
|
|
#define CAN1IDAR2_AC3 _CAN1IDAR2.Bits.AC3
|
| 10505 |
|
|
#define CAN1IDAR2_AC4 _CAN1IDAR2.Bits.AC4
|
| 10506 |
|
|
#define CAN1IDAR2_AC5 _CAN1IDAR2.Bits.AC5
|
| 10507 |
|
|
#define CAN1IDAR2_AC6 _CAN1IDAR2.Bits.AC6
|
| 10508 |
|
|
#define CAN1IDAR2_AC7 _CAN1IDAR2.Bits.AC7
|
| 10509 |
|
|
#define CAN1IDAR2_AC _CAN1IDAR2.MergedBits.grpAC
|
| 10510 |
|
|
|
| 10511 |
|
|
|
| 10512 |
|
|
/*** CAN1IDAR3 - MSCAN 1 Identifier Acceptance Register 3; 0x00000193 ***/
|
| 10513 |
|
|
typedef union {
|
| 10514 |
|
|
byte Byte;
|
| 10515 |
|
|
struct {
|
| 10516 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 10517 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 10518 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 10519 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 10520 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 10521 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 10522 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 10523 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 10524 |
|
|
} Bits;
|
| 10525 |
|
|
struct {
|
| 10526 |
|
|
byte grpAC :8;
|
| 10527 |
|
|
} MergedBits;
|
| 10528 |
|
|
} CAN1IDAR3STR;
|
| 10529 |
|
|
extern volatile CAN1IDAR3STR _CAN1IDAR3 @(REG_BASE + 0x00000193);
|
| 10530 |
|
|
#define CAN1IDAR3 _CAN1IDAR3.Byte
|
| 10531 |
|
|
#define CAN1IDAR3_AC0 _CAN1IDAR3.Bits.AC0
|
| 10532 |
|
|
#define CAN1IDAR3_AC1 _CAN1IDAR3.Bits.AC1
|
| 10533 |
|
|
#define CAN1IDAR3_AC2 _CAN1IDAR3.Bits.AC2
|
| 10534 |
|
|
#define CAN1IDAR3_AC3 _CAN1IDAR3.Bits.AC3
|
| 10535 |
|
|
#define CAN1IDAR3_AC4 _CAN1IDAR3.Bits.AC4
|
| 10536 |
|
|
#define CAN1IDAR3_AC5 _CAN1IDAR3.Bits.AC5
|
| 10537 |
|
|
#define CAN1IDAR3_AC6 _CAN1IDAR3.Bits.AC6
|
| 10538 |
|
|
#define CAN1IDAR3_AC7 _CAN1IDAR3.Bits.AC7
|
| 10539 |
|
|
#define CAN1IDAR3_AC _CAN1IDAR3.MergedBits.grpAC
|
| 10540 |
|
|
|
| 10541 |
|
|
|
| 10542 |
|
|
/*** CAN1IDMR0 - MSCAN 1 Identifier Mask Register 0; 0x00000194 ***/
|
| 10543 |
|
|
typedef union {
|
| 10544 |
|
|
byte Byte;
|
| 10545 |
|
|
struct {
|
| 10546 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 10547 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 10548 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 10549 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 10550 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 10551 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 10552 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 10553 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 10554 |
|
|
} Bits;
|
| 10555 |
|
|
struct {
|
| 10556 |
|
|
byte grpAM :8;
|
| 10557 |
|
|
} MergedBits;
|
| 10558 |
|
|
} CAN1IDMR0STR;
|
| 10559 |
|
|
extern volatile CAN1IDMR0STR _CAN1IDMR0 @(REG_BASE + 0x00000194);
|
| 10560 |
|
|
#define CAN1IDMR0 _CAN1IDMR0.Byte
|
| 10561 |
|
|
#define CAN1IDMR0_AM0 _CAN1IDMR0.Bits.AM0
|
| 10562 |
|
|
#define CAN1IDMR0_AM1 _CAN1IDMR0.Bits.AM1
|
| 10563 |
|
|
#define CAN1IDMR0_AM2 _CAN1IDMR0.Bits.AM2
|
| 10564 |
|
|
#define CAN1IDMR0_AM3 _CAN1IDMR0.Bits.AM3
|
| 10565 |
|
|
#define CAN1IDMR0_AM4 _CAN1IDMR0.Bits.AM4
|
| 10566 |
|
|
#define CAN1IDMR0_AM5 _CAN1IDMR0.Bits.AM5
|
| 10567 |
|
|
#define CAN1IDMR0_AM6 _CAN1IDMR0.Bits.AM6
|
| 10568 |
|
|
#define CAN1IDMR0_AM7 _CAN1IDMR0.Bits.AM7
|
| 10569 |
|
|
#define CAN1IDMR0_AM _CAN1IDMR0.MergedBits.grpAM
|
| 10570 |
|
|
|
| 10571 |
|
|
|
| 10572 |
|
|
/*** CAN1IDMR1 - MSCAN 1 Identifier Mask Register 1; 0x00000195 ***/
|
| 10573 |
|
|
typedef union {
|
| 10574 |
|
|
byte Byte;
|
| 10575 |
|
|
struct {
|
| 10576 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 10577 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 10578 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 10579 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 10580 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 10581 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 10582 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 10583 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 10584 |
|
|
} Bits;
|
| 10585 |
|
|
struct {
|
| 10586 |
|
|
byte grpAM :8;
|
| 10587 |
|
|
} MergedBits;
|
| 10588 |
|
|
} CAN1IDMR1STR;
|
| 10589 |
|
|
extern volatile CAN1IDMR1STR _CAN1IDMR1 @(REG_BASE + 0x00000195);
|
| 10590 |
|
|
#define CAN1IDMR1 _CAN1IDMR1.Byte
|
| 10591 |
|
|
#define CAN1IDMR1_AM0 _CAN1IDMR1.Bits.AM0
|
| 10592 |
|
|
#define CAN1IDMR1_AM1 _CAN1IDMR1.Bits.AM1
|
| 10593 |
|
|
#define CAN1IDMR1_AM2 _CAN1IDMR1.Bits.AM2
|
| 10594 |
|
|
#define CAN1IDMR1_AM3 _CAN1IDMR1.Bits.AM3
|
| 10595 |
|
|
#define CAN1IDMR1_AM4 _CAN1IDMR1.Bits.AM4
|
| 10596 |
|
|
#define CAN1IDMR1_AM5 _CAN1IDMR1.Bits.AM5
|
| 10597 |
|
|
#define CAN1IDMR1_AM6 _CAN1IDMR1.Bits.AM6
|
| 10598 |
|
|
#define CAN1IDMR1_AM7 _CAN1IDMR1.Bits.AM7
|
| 10599 |
|
|
#define CAN1IDMR1_AM _CAN1IDMR1.MergedBits.grpAM
|
| 10600 |
|
|
|
| 10601 |
|
|
|
| 10602 |
|
|
/*** CAN1IDMR2 - MSCAN 1 Identifier Mask Register 2; 0x00000196 ***/
|
| 10603 |
|
|
typedef union {
|
| 10604 |
|
|
byte Byte;
|
| 10605 |
|
|
struct {
|
| 10606 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 10607 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 10608 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 10609 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 10610 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 10611 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 10612 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 10613 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 10614 |
|
|
} Bits;
|
| 10615 |
|
|
struct {
|
| 10616 |
|
|
byte grpAM :8;
|
| 10617 |
|
|
} MergedBits;
|
| 10618 |
|
|
} CAN1IDMR2STR;
|
| 10619 |
|
|
extern volatile CAN1IDMR2STR _CAN1IDMR2 @(REG_BASE + 0x00000196);
|
| 10620 |
|
|
#define CAN1IDMR2 _CAN1IDMR2.Byte
|
| 10621 |
|
|
#define CAN1IDMR2_AM0 _CAN1IDMR2.Bits.AM0
|
| 10622 |
|
|
#define CAN1IDMR2_AM1 _CAN1IDMR2.Bits.AM1
|
| 10623 |
|
|
#define CAN1IDMR2_AM2 _CAN1IDMR2.Bits.AM2
|
| 10624 |
|
|
#define CAN1IDMR2_AM3 _CAN1IDMR2.Bits.AM3
|
| 10625 |
|
|
#define CAN1IDMR2_AM4 _CAN1IDMR2.Bits.AM4
|
| 10626 |
|
|
#define CAN1IDMR2_AM5 _CAN1IDMR2.Bits.AM5
|
| 10627 |
|
|
#define CAN1IDMR2_AM6 _CAN1IDMR2.Bits.AM6
|
| 10628 |
|
|
#define CAN1IDMR2_AM7 _CAN1IDMR2.Bits.AM7
|
| 10629 |
|
|
#define CAN1IDMR2_AM _CAN1IDMR2.MergedBits.grpAM
|
| 10630 |
|
|
|
| 10631 |
|
|
|
| 10632 |
|
|
/*** CAN1IDMR3 - MSCAN 1 Identifier Mask Register 3; 0x00000197 ***/
|
| 10633 |
|
|
typedef union {
|
| 10634 |
|
|
byte Byte;
|
| 10635 |
|
|
struct {
|
| 10636 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 10637 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 10638 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 10639 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 10640 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 10641 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 10642 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 10643 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 10644 |
|
|
} Bits;
|
| 10645 |
|
|
struct {
|
| 10646 |
|
|
byte grpAM :8;
|
| 10647 |
|
|
} MergedBits;
|
| 10648 |
|
|
} CAN1IDMR3STR;
|
| 10649 |
|
|
extern volatile CAN1IDMR3STR _CAN1IDMR3 @(REG_BASE + 0x00000197);
|
| 10650 |
|
|
#define CAN1IDMR3 _CAN1IDMR3.Byte
|
| 10651 |
|
|
#define CAN1IDMR3_AM0 _CAN1IDMR3.Bits.AM0
|
| 10652 |
|
|
#define CAN1IDMR3_AM1 _CAN1IDMR3.Bits.AM1
|
| 10653 |
|
|
#define CAN1IDMR3_AM2 _CAN1IDMR3.Bits.AM2
|
| 10654 |
|
|
#define CAN1IDMR3_AM3 _CAN1IDMR3.Bits.AM3
|
| 10655 |
|
|
#define CAN1IDMR3_AM4 _CAN1IDMR3.Bits.AM4
|
| 10656 |
|
|
#define CAN1IDMR3_AM5 _CAN1IDMR3.Bits.AM5
|
| 10657 |
|
|
#define CAN1IDMR3_AM6 _CAN1IDMR3.Bits.AM6
|
| 10658 |
|
|
#define CAN1IDMR3_AM7 _CAN1IDMR3.Bits.AM7
|
| 10659 |
|
|
#define CAN1IDMR3_AM _CAN1IDMR3.MergedBits.grpAM
|
| 10660 |
|
|
|
| 10661 |
|
|
|
| 10662 |
|
|
/*** CAN1IDAR4 - MSCAN 1 Identifier Acceptance Register 4; 0x00000198 ***/
|
| 10663 |
|
|
typedef union {
|
| 10664 |
|
|
byte Byte;
|
| 10665 |
|
|
struct {
|
| 10666 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 10667 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 10668 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 10669 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 10670 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 10671 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 10672 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 10673 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 10674 |
|
|
} Bits;
|
| 10675 |
|
|
struct {
|
| 10676 |
|
|
byte grpAC :8;
|
| 10677 |
|
|
} MergedBits;
|
| 10678 |
|
|
} CAN1IDAR4STR;
|
| 10679 |
|
|
extern volatile CAN1IDAR4STR _CAN1IDAR4 @(REG_BASE + 0x00000198);
|
| 10680 |
|
|
#define CAN1IDAR4 _CAN1IDAR4.Byte
|
| 10681 |
|
|
#define CAN1IDAR4_AC0 _CAN1IDAR4.Bits.AC0
|
| 10682 |
|
|
#define CAN1IDAR4_AC1 _CAN1IDAR4.Bits.AC1
|
| 10683 |
|
|
#define CAN1IDAR4_AC2 _CAN1IDAR4.Bits.AC2
|
| 10684 |
|
|
#define CAN1IDAR4_AC3 _CAN1IDAR4.Bits.AC3
|
| 10685 |
|
|
#define CAN1IDAR4_AC4 _CAN1IDAR4.Bits.AC4
|
| 10686 |
|
|
#define CAN1IDAR4_AC5 _CAN1IDAR4.Bits.AC5
|
| 10687 |
|
|
#define CAN1IDAR4_AC6 _CAN1IDAR4.Bits.AC6
|
| 10688 |
|
|
#define CAN1IDAR4_AC7 _CAN1IDAR4.Bits.AC7
|
| 10689 |
|
|
#define CAN1IDAR4_AC _CAN1IDAR4.MergedBits.grpAC
|
| 10690 |
|
|
|
| 10691 |
|
|
|
| 10692 |
|
|
/*** CAN1IDAR5 - MSCAN 1 Identifier Acceptance Register 5; 0x00000199 ***/
|
| 10693 |
|
|
typedef union {
|
| 10694 |
|
|
byte Byte;
|
| 10695 |
|
|
struct {
|
| 10696 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 10697 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 10698 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 10699 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 10700 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 10701 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 10702 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 10703 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 10704 |
|
|
} Bits;
|
| 10705 |
|
|
struct {
|
| 10706 |
|
|
byte grpAC :8;
|
| 10707 |
|
|
} MergedBits;
|
| 10708 |
|
|
} CAN1IDAR5STR;
|
| 10709 |
|
|
extern volatile CAN1IDAR5STR _CAN1IDAR5 @(REG_BASE + 0x00000199);
|
| 10710 |
|
|
#define CAN1IDAR5 _CAN1IDAR5.Byte
|
| 10711 |
|
|
#define CAN1IDAR5_AC0 _CAN1IDAR5.Bits.AC0
|
| 10712 |
|
|
#define CAN1IDAR5_AC1 _CAN1IDAR5.Bits.AC1
|
| 10713 |
|
|
#define CAN1IDAR5_AC2 _CAN1IDAR5.Bits.AC2
|
| 10714 |
|
|
#define CAN1IDAR5_AC3 _CAN1IDAR5.Bits.AC3
|
| 10715 |
|
|
#define CAN1IDAR5_AC4 _CAN1IDAR5.Bits.AC4
|
| 10716 |
|
|
#define CAN1IDAR5_AC5 _CAN1IDAR5.Bits.AC5
|
| 10717 |
|
|
#define CAN1IDAR5_AC6 _CAN1IDAR5.Bits.AC6
|
| 10718 |
|
|
#define CAN1IDAR5_AC7 _CAN1IDAR5.Bits.AC7
|
| 10719 |
|
|
#define CAN1IDAR5_AC _CAN1IDAR5.MergedBits.grpAC
|
| 10720 |
|
|
|
| 10721 |
|
|
|
| 10722 |
|
|
/*** CAN1IDAR6 - MSCAN 1 Identifier Acceptance Register 6; 0x0000019A ***/
|
| 10723 |
|
|
typedef union {
|
| 10724 |
|
|
byte Byte;
|
| 10725 |
|
|
struct {
|
| 10726 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 10727 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 10728 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 10729 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 10730 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 10731 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 10732 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 10733 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 10734 |
|
|
} Bits;
|
| 10735 |
|
|
struct {
|
| 10736 |
|
|
byte grpAC :8;
|
| 10737 |
|
|
} MergedBits;
|
| 10738 |
|
|
} CAN1IDAR6STR;
|
| 10739 |
|
|
extern volatile CAN1IDAR6STR _CAN1IDAR6 @(REG_BASE + 0x0000019A);
|
| 10740 |
|
|
#define CAN1IDAR6 _CAN1IDAR6.Byte
|
| 10741 |
|
|
#define CAN1IDAR6_AC0 _CAN1IDAR6.Bits.AC0
|
| 10742 |
|
|
#define CAN1IDAR6_AC1 _CAN1IDAR6.Bits.AC1
|
| 10743 |
|
|
#define CAN1IDAR6_AC2 _CAN1IDAR6.Bits.AC2
|
| 10744 |
|
|
#define CAN1IDAR6_AC3 _CAN1IDAR6.Bits.AC3
|
| 10745 |
|
|
#define CAN1IDAR6_AC4 _CAN1IDAR6.Bits.AC4
|
| 10746 |
|
|
#define CAN1IDAR6_AC5 _CAN1IDAR6.Bits.AC5
|
| 10747 |
|
|
#define CAN1IDAR6_AC6 _CAN1IDAR6.Bits.AC6
|
| 10748 |
|
|
#define CAN1IDAR6_AC7 _CAN1IDAR6.Bits.AC7
|
| 10749 |
|
|
#define CAN1IDAR6_AC _CAN1IDAR6.MergedBits.grpAC
|
| 10750 |
|
|
|
| 10751 |
|
|
|
| 10752 |
|
|
/*** CAN1IDAR7 - MSCAN 1 Identifier Acceptance Register 7; 0x0000019B ***/
|
| 10753 |
|
|
typedef union {
|
| 10754 |
|
|
byte Byte;
|
| 10755 |
|
|
struct {
|
| 10756 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 10757 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 10758 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 10759 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 10760 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 10761 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 10762 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 10763 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 10764 |
|
|
} Bits;
|
| 10765 |
|
|
struct {
|
| 10766 |
|
|
byte grpAC :8;
|
| 10767 |
|
|
} MergedBits;
|
| 10768 |
|
|
} CAN1IDAR7STR;
|
| 10769 |
|
|
extern volatile CAN1IDAR7STR _CAN1IDAR7 @(REG_BASE + 0x0000019B);
|
| 10770 |
|
|
#define CAN1IDAR7 _CAN1IDAR7.Byte
|
| 10771 |
|
|
#define CAN1IDAR7_AC0 _CAN1IDAR7.Bits.AC0
|
| 10772 |
|
|
#define CAN1IDAR7_AC1 _CAN1IDAR7.Bits.AC1
|
| 10773 |
|
|
#define CAN1IDAR7_AC2 _CAN1IDAR7.Bits.AC2
|
| 10774 |
|
|
#define CAN1IDAR7_AC3 _CAN1IDAR7.Bits.AC3
|
| 10775 |
|
|
#define CAN1IDAR7_AC4 _CAN1IDAR7.Bits.AC4
|
| 10776 |
|
|
#define CAN1IDAR7_AC5 _CAN1IDAR7.Bits.AC5
|
| 10777 |
|
|
#define CAN1IDAR7_AC6 _CAN1IDAR7.Bits.AC6
|
| 10778 |
|
|
#define CAN1IDAR7_AC7 _CAN1IDAR7.Bits.AC7
|
| 10779 |
|
|
#define CAN1IDAR7_AC _CAN1IDAR7.MergedBits.grpAC
|
| 10780 |
|
|
|
| 10781 |
|
|
|
| 10782 |
|
|
/*** CAN1IDMR4 - MSCAN 1 Identifier Mask Register 4; 0x0000019C ***/
|
| 10783 |
|
|
typedef union {
|
| 10784 |
|
|
byte Byte;
|
| 10785 |
|
|
struct {
|
| 10786 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 10787 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 10788 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 10789 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 10790 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 10791 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 10792 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 10793 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 10794 |
|
|
} Bits;
|
| 10795 |
|
|
struct {
|
| 10796 |
|
|
byte grpAM :8;
|
| 10797 |
|
|
} MergedBits;
|
| 10798 |
|
|
} CAN1IDMR4STR;
|
| 10799 |
|
|
extern volatile CAN1IDMR4STR _CAN1IDMR4 @(REG_BASE + 0x0000019C);
|
| 10800 |
|
|
#define CAN1IDMR4 _CAN1IDMR4.Byte
|
| 10801 |
|
|
#define CAN1IDMR4_AM0 _CAN1IDMR4.Bits.AM0
|
| 10802 |
|
|
#define CAN1IDMR4_AM1 _CAN1IDMR4.Bits.AM1
|
| 10803 |
|
|
#define CAN1IDMR4_AM2 _CAN1IDMR4.Bits.AM2
|
| 10804 |
|
|
#define CAN1IDMR4_AM3 _CAN1IDMR4.Bits.AM3
|
| 10805 |
|
|
#define CAN1IDMR4_AM4 _CAN1IDMR4.Bits.AM4
|
| 10806 |
|
|
#define CAN1IDMR4_AM5 _CAN1IDMR4.Bits.AM5
|
| 10807 |
|
|
#define CAN1IDMR4_AM6 _CAN1IDMR4.Bits.AM6
|
| 10808 |
|
|
#define CAN1IDMR4_AM7 _CAN1IDMR4.Bits.AM7
|
| 10809 |
|
|
#define CAN1IDMR4_AM _CAN1IDMR4.MergedBits.grpAM
|
| 10810 |
|
|
|
| 10811 |
|
|
|
| 10812 |
|
|
/*** CAN1IDMR5 - MSCAN 1 Identifier Mask Register 5; 0x0000019D ***/
|
| 10813 |
|
|
typedef union {
|
| 10814 |
|
|
byte Byte;
|
| 10815 |
|
|
struct {
|
| 10816 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 10817 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 10818 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 10819 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 10820 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 10821 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 10822 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 10823 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 10824 |
|
|
} Bits;
|
| 10825 |
|
|
struct {
|
| 10826 |
|
|
byte grpAM :8;
|
| 10827 |
|
|
} MergedBits;
|
| 10828 |
|
|
} CAN1IDMR5STR;
|
| 10829 |
|
|
extern volatile CAN1IDMR5STR _CAN1IDMR5 @(REG_BASE + 0x0000019D);
|
| 10830 |
|
|
#define CAN1IDMR5 _CAN1IDMR5.Byte
|
| 10831 |
|
|
#define CAN1IDMR5_AM0 _CAN1IDMR5.Bits.AM0
|
| 10832 |
|
|
#define CAN1IDMR5_AM1 _CAN1IDMR5.Bits.AM1
|
| 10833 |
|
|
#define CAN1IDMR5_AM2 _CAN1IDMR5.Bits.AM2
|
| 10834 |
|
|
#define CAN1IDMR5_AM3 _CAN1IDMR5.Bits.AM3
|
| 10835 |
|
|
#define CAN1IDMR5_AM4 _CAN1IDMR5.Bits.AM4
|
| 10836 |
|
|
#define CAN1IDMR5_AM5 _CAN1IDMR5.Bits.AM5
|
| 10837 |
|
|
#define CAN1IDMR5_AM6 _CAN1IDMR5.Bits.AM6
|
| 10838 |
|
|
#define CAN1IDMR5_AM7 _CAN1IDMR5.Bits.AM7
|
| 10839 |
|
|
#define CAN1IDMR5_AM _CAN1IDMR5.MergedBits.grpAM
|
| 10840 |
|
|
|
| 10841 |
|
|
|
| 10842 |
|
|
/*** CAN1IDMR6 - MSCAN 1 Identifier Mask Register 6; 0x0000019E ***/
|
| 10843 |
|
|
typedef union {
|
| 10844 |
|
|
byte Byte;
|
| 10845 |
|
|
struct {
|
| 10846 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 10847 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 10848 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 10849 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 10850 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 10851 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 10852 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 10853 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 10854 |
|
|
} Bits;
|
| 10855 |
|
|
struct {
|
| 10856 |
|
|
byte grpAM :8;
|
| 10857 |
|
|
} MergedBits;
|
| 10858 |
|
|
} CAN1IDMR6STR;
|
| 10859 |
|
|
extern volatile CAN1IDMR6STR _CAN1IDMR6 @(REG_BASE + 0x0000019E);
|
| 10860 |
|
|
#define CAN1IDMR6 _CAN1IDMR6.Byte
|
| 10861 |
|
|
#define CAN1IDMR6_AM0 _CAN1IDMR6.Bits.AM0
|
| 10862 |
|
|
#define CAN1IDMR6_AM1 _CAN1IDMR6.Bits.AM1
|
| 10863 |
|
|
#define CAN1IDMR6_AM2 _CAN1IDMR6.Bits.AM2
|
| 10864 |
|
|
#define CAN1IDMR6_AM3 _CAN1IDMR6.Bits.AM3
|
| 10865 |
|
|
#define CAN1IDMR6_AM4 _CAN1IDMR6.Bits.AM4
|
| 10866 |
|
|
#define CAN1IDMR6_AM5 _CAN1IDMR6.Bits.AM5
|
| 10867 |
|
|
#define CAN1IDMR6_AM6 _CAN1IDMR6.Bits.AM6
|
| 10868 |
|
|
#define CAN1IDMR6_AM7 _CAN1IDMR6.Bits.AM7
|
| 10869 |
|
|
#define CAN1IDMR6_AM _CAN1IDMR6.MergedBits.grpAM
|
| 10870 |
|
|
|
| 10871 |
|
|
|
| 10872 |
|
|
/*** CAN1IDMR7 - MSCAN 1 Identifier Mask Register 7; 0x0000019F ***/
|
| 10873 |
|
|
typedef union {
|
| 10874 |
|
|
byte Byte;
|
| 10875 |
|
|
struct {
|
| 10876 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 10877 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 10878 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 10879 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 10880 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 10881 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 10882 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 10883 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 10884 |
|
|
} Bits;
|
| 10885 |
|
|
struct {
|
| 10886 |
|
|
byte grpAM :8;
|
| 10887 |
|
|
} MergedBits;
|
| 10888 |
|
|
} CAN1IDMR7STR;
|
| 10889 |
|
|
extern volatile CAN1IDMR7STR _CAN1IDMR7 @(REG_BASE + 0x0000019F);
|
| 10890 |
|
|
#define CAN1IDMR7 _CAN1IDMR7.Byte
|
| 10891 |
|
|
#define CAN1IDMR7_AM0 _CAN1IDMR7.Bits.AM0
|
| 10892 |
|
|
#define CAN1IDMR7_AM1 _CAN1IDMR7.Bits.AM1
|
| 10893 |
|
|
#define CAN1IDMR7_AM2 _CAN1IDMR7.Bits.AM2
|
| 10894 |
|
|
#define CAN1IDMR7_AM3 _CAN1IDMR7.Bits.AM3
|
| 10895 |
|
|
#define CAN1IDMR7_AM4 _CAN1IDMR7.Bits.AM4
|
| 10896 |
|
|
#define CAN1IDMR7_AM5 _CAN1IDMR7.Bits.AM5
|
| 10897 |
|
|
#define CAN1IDMR7_AM6 _CAN1IDMR7.Bits.AM6
|
| 10898 |
|
|
#define CAN1IDMR7_AM7 _CAN1IDMR7.Bits.AM7
|
| 10899 |
|
|
#define CAN1IDMR7_AM _CAN1IDMR7.MergedBits.grpAM
|
| 10900 |
|
|
|
| 10901 |
|
|
|
| 10902 |
|
|
/*** CAN1RXIDR0 - MSCAN 1 Receive Identifier Register 0; 0x000001A0 ***/
|
| 10903 |
|
|
typedef union {
|
| 10904 |
|
|
byte Byte;
|
| 10905 |
|
|
struct {
|
| 10906 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 10907 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 10908 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 10909 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 10910 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 10911 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 10912 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 10913 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 10914 |
|
|
} Bits;
|
| 10915 |
|
|
struct {
|
| 10916 |
|
|
byte grpID_21 :8;
|
| 10917 |
|
|
} MergedBits;
|
| 10918 |
|
|
} CAN1RXIDR0STR;
|
| 10919 |
|
|
extern volatile CAN1RXIDR0STR _CAN1RXIDR0 @(REG_BASE + 0x000001A0);
|
| 10920 |
|
|
#define CAN1RXIDR0 _CAN1RXIDR0.Byte
|
| 10921 |
|
|
#define CAN1RXIDR0_ID21 _CAN1RXIDR0.Bits.ID21
|
| 10922 |
|
|
#define CAN1RXIDR0_ID22 _CAN1RXIDR0.Bits.ID22
|
| 10923 |
|
|
#define CAN1RXIDR0_ID23 _CAN1RXIDR0.Bits.ID23
|
| 10924 |
|
|
#define CAN1RXIDR0_ID24 _CAN1RXIDR0.Bits.ID24
|
| 10925 |
|
|
#define CAN1RXIDR0_ID25 _CAN1RXIDR0.Bits.ID25
|
| 10926 |
|
|
#define CAN1RXIDR0_ID26 _CAN1RXIDR0.Bits.ID26
|
| 10927 |
|
|
#define CAN1RXIDR0_ID27 _CAN1RXIDR0.Bits.ID27
|
| 10928 |
|
|
#define CAN1RXIDR0_ID28 _CAN1RXIDR0.Bits.ID28
|
| 10929 |
|
|
#define CAN1RXIDR0_ID_21 _CAN1RXIDR0.MergedBits.grpID_21
|
| 10930 |
|
|
#define CAN1RXIDR0_ID CAN1RXIDR0_ID_21
|
| 10931 |
|
|
|
| 10932 |
|
|
|
| 10933 |
|
|
/*** CAN1RXIDR1 - MSCAN 1 Receive Identifier Register 1; 0x000001A1 ***/
|
| 10934 |
|
|
typedef union {
|
| 10935 |
|
|
byte Byte;
|
| 10936 |
|
|
struct {
|
| 10937 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 10938 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 10939 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 10940 |
|
|
byte IDE :1; /* ID Extended */
|
| 10941 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 10942 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 10943 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 10944 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 10945 |
|
|
} Bits;
|
| 10946 |
|
|
struct {
|
| 10947 |
|
|
byte grpID_15 :3;
|
| 10948 |
|
|
byte :1;
|
| 10949 |
|
|
byte :1;
|
| 10950 |
|
|
byte grpID_18 :3;
|
| 10951 |
|
|
} MergedBits;
|
| 10952 |
|
|
} CAN1RXIDR1STR;
|
| 10953 |
|
|
extern volatile CAN1RXIDR1STR _CAN1RXIDR1 @(REG_BASE + 0x000001A1);
|
| 10954 |
|
|
#define CAN1RXIDR1 _CAN1RXIDR1.Byte
|
| 10955 |
|
|
#define CAN1RXIDR1_ID15 _CAN1RXIDR1.Bits.ID15
|
| 10956 |
|
|
#define CAN1RXIDR1_ID16 _CAN1RXIDR1.Bits.ID16
|
| 10957 |
|
|
#define CAN1RXIDR1_ID17 _CAN1RXIDR1.Bits.ID17
|
| 10958 |
|
|
#define CAN1RXIDR1_IDE _CAN1RXIDR1.Bits.IDE
|
| 10959 |
|
|
#define CAN1RXIDR1_SRR _CAN1RXIDR1.Bits.SRR
|
| 10960 |
|
|
#define CAN1RXIDR1_ID18 _CAN1RXIDR1.Bits.ID18
|
| 10961 |
|
|
#define CAN1RXIDR1_ID19 _CAN1RXIDR1.Bits.ID19
|
| 10962 |
|
|
#define CAN1RXIDR1_ID20 _CAN1RXIDR1.Bits.ID20
|
| 10963 |
|
|
#define CAN1RXIDR1_ID_15 _CAN1RXIDR1.MergedBits.grpID_15
|
| 10964 |
|
|
#define CAN1RXIDR1_ID_18 _CAN1RXIDR1.MergedBits.grpID_18
|
| 10965 |
|
|
#define CAN1RXIDR1_ID CAN1RXIDR1_ID_15
|
| 10966 |
|
|
|
| 10967 |
|
|
|
| 10968 |
|
|
/*** CAN1RXIDR2 - MSCAN 1 Receive Identifier Register 2; 0x000001A2 ***/
|
| 10969 |
|
|
typedef union {
|
| 10970 |
|
|
byte Byte;
|
| 10971 |
|
|
struct {
|
| 10972 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 10973 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 10974 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 10975 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 10976 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 10977 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 10978 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 10979 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 10980 |
|
|
} Bits;
|
| 10981 |
|
|
struct {
|
| 10982 |
|
|
byte grpID_7 :8;
|
| 10983 |
|
|
} MergedBits;
|
| 10984 |
|
|
} CAN1RXIDR2STR;
|
| 10985 |
|
|
extern volatile CAN1RXIDR2STR _CAN1RXIDR2 @(REG_BASE + 0x000001A2);
|
| 10986 |
|
|
#define CAN1RXIDR2 _CAN1RXIDR2.Byte
|
| 10987 |
|
|
#define CAN1RXIDR2_ID7 _CAN1RXIDR2.Bits.ID7
|
| 10988 |
|
|
#define CAN1RXIDR2_ID8 _CAN1RXIDR2.Bits.ID8
|
| 10989 |
|
|
#define CAN1RXIDR2_ID9 _CAN1RXIDR2.Bits.ID9
|
| 10990 |
|
|
#define CAN1RXIDR2_ID10 _CAN1RXIDR2.Bits.ID10
|
| 10991 |
|
|
#define CAN1RXIDR2_ID11 _CAN1RXIDR2.Bits.ID11
|
| 10992 |
|
|
#define CAN1RXIDR2_ID12 _CAN1RXIDR2.Bits.ID12
|
| 10993 |
|
|
#define CAN1RXIDR2_ID13 _CAN1RXIDR2.Bits.ID13
|
| 10994 |
|
|
#define CAN1RXIDR2_ID14 _CAN1RXIDR2.Bits.ID14
|
| 10995 |
|
|
#define CAN1RXIDR2_ID_7 _CAN1RXIDR2.MergedBits.grpID_7
|
| 10996 |
|
|
#define CAN1RXIDR2_ID CAN1RXIDR2_ID_7
|
| 10997 |
|
|
|
| 10998 |
|
|
|
| 10999 |
|
|
/*** CAN1RXIDR3 - MSCAN 1 Receive Identifier Register 3; 0x000001A3 ***/
|
| 11000 |
|
|
typedef union {
|
| 11001 |
|
|
byte Byte;
|
| 11002 |
|
|
struct {
|
| 11003 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 11004 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 11005 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 11006 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 11007 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 11008 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 11009 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 11010 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 11011 |
|
|
} Bits;
|
| 11012 |
|
|
struct {
|
| 11013 |
|
|
byte :1;
|
| 11014 |
|
|
byte grpID :7;
|
| 11015 |
|
|
} MergedBits;
|
| 11016 |
|
|
} CAN1RXIDR3STR;
|
| 11017 |
|
|
extern volatile CAN1RXIDR3STR _CAN1RXIDR3 @(REG_BASE + 0x000001A3);
|
| 11018 |
|
|
#define CAN1RXIDR3 _CAN1RXIDR3.Byte
|
| 11019 |
|
|
#define CAN1RXIDR3_RTR _CAN1RXIDR3.Bits.RTR
|
| 11020 |
|
|
#define CAN1RXIDR3_ID0 _CAN1RXIDR3.Bits.ID0
|
| 11021 |
|
|
#define CAN1RXIDR3_ID1 _CAN1RXIDR3.Bits.ID1
|
| 11022 |
|
|
#define CAN1RXIDR3_ID2 _CAN1RXIDR3.Bits.ID2
|
| 11023 |
|
|
#define CAN1RXIDR3_ID3 _CAN1RXIDR3.Bits.ID3
|
| 11024 |
|
|
#define CAN1RXIDR3_ID4 _CAN1RXIDR3.Bits.ID4
|
| 11025 |
|
|
#define CAN1RXIDR3_ID5 _CAN1RXIDR3.Bits.ID5
|
| 11026 |
|
|
#define CAN1RXIDR3_ID6 _CAN1RXIDR3.Bits.ID6
|
| 11027 |
|
|
#define CAN1RXIDR3_ID _CAN1RXIDR3.MergedBits.grpID
|
| 11028 |
|
|
|
| 11029 |
|
|
|
| 11030 |
|
|
/*** CAN1RXDSR0 - MSCAN 1 Receive Data Segment Register 0; 0x000001A4 ***/
|
| 11031 |
|
|
typedef union {
|
| 11032 |
|
|
byte Byte;
|
| 11033 |
|
|
struct {
|
| 11034 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11035 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11036 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11037 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11038 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11039 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11040 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11041 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11042 |
|
|
} Bits;
|
| 11043 |
|
|
struct {
|
| 11044 |
|
|
byte grpDB :8;
|
| 11045 |
|
|
} MergedBits;
|
| 11046 |
|
|
} CAN1RXDSR0STR;
|
| 11047 |
|
|
extern volatile CAN1RXDSR0STR _CAN1RXDSR0 @(REG_BASE + 0x000001A4);
|
| 11048 |
|
|
#define CAN1RXDSR0 _CAN1RXDSR0.Byte
|
| 11049 |
|
|
#define CAN1RXDSR0_DB0 _CAN1RXDSR0.Bits.DB0
|
| 11050 |
|
|
#define CAN1RXDSR0_DB1 _CAN1RXDSR0.Bits.DB1
|
| 11051 |
|
|
#define CAN1RXDSR0_DB2 _CAN1RXDSR0.Bits.DB2
|
| 11052 |
|
|
#define CAN1RXDSR0_DB3 _CAN1RXDSR0.Bits.DB3
|
| 11053 |
|
|
#define CAN1RXDSR0_DB4 _CAN1RXDSR0.Bits.DB4
|
| 11054 |
|
|
#define CAN1RXDSR0_DB5 _CAN1RXDSR0.Bits.DB5
|
| 11055 |
|
|
#define CAN1RXDSR0_DB6 _CAN1RXDSR0.Bits.DB6
|
| 11056 |
|
|
#define CAN1RXDSR0_DB7 _CAN1RXDSR0.Bits.DB7
|
| 11057 |
|
|
#define CAN1RXDSR0_DB _CAN1RXDSR0.MergedBits.grpDB
|
| 11058 |
|
|
|
| 11059 |
|
|
|
| 11060 |
|
|
/*** CAN1RXDSR1 - MSCAN 1 Receive Data Segment Register 1; 0x000001A5 ***/
|
| 11061 |
|
|
typedef union {
|
| 11062 |
|
|
byte Byte;
|
| 11063 |
|
|
struct {
|
| 11064 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11065 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11066 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11067 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11068 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11069 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11070 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11071 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11072 |
|
|
} Bits;
|
| 11073 |
|
|
struct {
|
| 11074 |
|
|
byte grpDB :8;
|
| 11075 |
|
|
} MergedBits;
|
| 11076 |
|
|
} CAN1RXDSR1STR;
|
| 11077 |
|
|
extern volatile CAN1RXDSR1STR _CAN1RXDSR1 @(REG_BASE + 0x000001A5);
|
| 11078 |
|
|
#define CAN1RXDSR1 _CAN1RXDSR1.Byte
|
| 11079 |
|
|
#define CAN1RXDSR1_DB0 _CAN1RXDSR1.Bits.DB0
|
| 11080 |
|
|
#define CAN1RXDSR1_DB1 _CAN1RXDSR1.Bits.DB1
|
| 11081 |
|
|
#define CAN1RXDSR1_DB2 _CAN1RXDSR1.Bits.DB2
|
| 11082 |
|
|
#define CAN1RXDSR1_DB3 _CAN1RXDSR1.Bits.DB3
|
| 11083 |
|
|
#define CAN1RXDSR1_DB4 _CAN1RXDSR1.Bits.DB4
|
| 11084 |
|
|
#define CAN1RXDSR1_DB5 _CAN1RXDSR1.Bits.DB5
|
| 11085 |
|
|
#define CAN1RXDSR1_DB6 _CAN1RXDSR1.Bits.DB6
|
| 11086 |
|
|
#define CAN1RXDSR1_DB7 _CAN1RXDSR1.Bits.DB7
|
| 11087 |
|
|
#define CAN1RXDSR1_DB _CAN1RXDSR1.MergedBits.grpDB
|
| 11088 |
|
|
|
| 11089 |
|
|
|
| 11090 |
|
|
/*** CAN1RXDSR2 - MSCAN 1 Receive Data Segment Register 2; 0x000001A6 ***/
|
| 11091 |
|
|
typedef union {
|
| 11092 |
|
|
byte Byte;
|
| 11093 |
|
|
struct {
|
| 11094 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11095 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11096 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11097 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11098 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11099 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11100 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11101 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11102 |
|
|
} Bits;
|
| 11103 |
|
|
struct {
|
| 11104 |
|
|
byte grpDB :8;
|
| 11105 |
|
|
} MergedBits;
|
| 11106 |
|
|
} CAN1RXDSR2STR;
|
| 11107 |
|
|
extern volatile CAN1RXDSR2STR _CAN1RXDSR2 @(REG_BASE + 0x000001A6);
|
| 11108 |
|
|
#define CAN1RXDSR2 _CAN1RXDSR2.Byte
|
| 11109 |
|
|
#define CAN1RXDSR2_DB0 _CAN1RXDSR2.Bits.DB0
|
| 11110 |
|
|
#define CAN1RXDSR2_DB1 _CAN1RXDSR2.Bits.DB1
|
| 11111 |
|
|
#define CAN1RXDSR2_DB2 _CAN1RXDSR2.Bits.DB2
|
| 11112 |
|
|
#define CAN1RXDSR2_DB3 _CAN1RXDSR2.Bits.DB3
|
| 11113 |
|
|
#define CAN1RXDSR2_DB4 _CAN1RXDSR2.Bits.DB4
|
| 11114 |
|
|
#define CAN1RXDSR2_DB5 _CAN1RXDSR2.Bits.DB5
|
| 11115 |
|
|
#define CAN1RXDSR2_DB6 _CAN1RXDSR2.Bits.DB6
|
| 11116 |
|
|
#define CAN1RXDSR2_DB7 _CAN1RXDSR2.Bits.DB7
|
| 11117 |
|
|
#define CAN1RXDSR2_DB _CAN1RXDSR2.MergedBits.grpDB
|
| 11118 |
|
|
|
| 11119 |
|
|
|
| 11120 |
|
|
/*** CAN1RXDSR3 - MSCAN 1 Receive Data Segment Register 3; 0x000001A7 ***/
|
| 11121 |
|
|
typedef union {
|
| 11122 |
|
|
byte Byte;
|
| 11123 |
|
|
struct {
|
| 11124 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11125 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11126 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11127 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11128 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11129 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11130 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11131 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11132 |
|
|
} Bits;
|
| 11133 |
|
|
struct {
|
| 11134 |
|
|
byte grpDB :8;
|
| 11135 |
|
|
} MergedBits;
|
| 11136 |
|
|
} CAN1RXDSR3STR;
|
| 11137 |
|
|
extern volatile CAN1RXDSR3STR _CAN1RXDSR3 @(REG_BASE + 0x000001A7);
|
| 11138 |
|
|
#define CAN1RXDSR3 _CAN1RXDSR3.Byte
|
| 11139 |
|
|
#define CAN1RXDSR3_DB0 _CAN1RXDSR3.Bits.DB0
|
| 11140 |
|
|
#define CAN1RXDSR3_DB1 _CAN1RXDSR3.Bits.DB1
|
| 11141 |
|
|
#define CAN1RXDSR3_DB2 _CAN1RXDSR3.Bits.DB2
|
| 11142 |
|
|
#define CAN1RXDSR3_DB3 _CAN1RXDSR3.Bits.DB3
|
| 11143 |
|
|
#define CAN1RXDSR3_DB4 _CAN1RXDSR3.Bits.DB4
|
| 11144 |
|
|
#define CAN1RXDSR3_DB5 _CAN1RXDSR3.Bits.DB5
|
| 11145 |
|
|
#define CAN1RXDSR3_DB6 _CAN1RXDSR3.Bits.DB6
|
| 11146 |
|
|
#define CAN1RXDSR3_DB7 _CAN1RXDSR3.Bits.DB7
|
| 11147 |
|
|
#define CAN1RXDSR3_DB _CAN1RXDSR3.MergedBits.grpDB
|
| 11148 |
|
|
|
| 11149 |
|
|
|
| 11150 |
|
|
/*** CAN1RXDSR4 - MSCAN 1 Receive Data Segment Register 4; 0x000001A8 ***/
|
| 11151 |
|
|
typedef union {
|
| 11152 |
|
|
byte Byte;
|
| 11153 |
|
|
struct {
|
| 11154 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11155 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11156 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11157 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11158 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11159 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11160 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11161 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11162 |
|
|
} Bits;
|
| 11163 |
|
|
struct {
|
| 11164 |
|
|
byte grpDB :8;
|
| 11165 |
|
|
} MergedBits;
|
| 11166 |
|
|
} CAN1RXDSR4STR;
|
| 11167 |
|
|
extern volatile CAN1RXDSR4STR _CAN1RXDSR4 @(REG_BASE + 0x000001A8);
|
| 11168 |
|
|
#define CAN1RXDSR4 _CAN1RXDSR4.Byte
|
| 11169 |
|
|
#define CAN1RXDSR4_DB0 _CAN1RXDSR4.Bits.DB0
|
| 11170 |
|
|
#define CAN1RXDSR4_DB1 _CAN1RXDSR4.Bits.DB1
|
| 11171 |
|
|
#define CAN1RXDSR4_DB2 _CAN1RXDSR4.Bits.DB2
|
| 11172 |
|
|
#define CAN1RXDSR4_DB3 _CAN1RXDSR4.Bits.DB3
|
| 11173 |
|
|
#define CAN1RXDSR4_DB4 _CAN1RXDSR4.Bits.DB4
|
| 11174 |
|
|
#define CAN1RXDSR4_DB5 _CAN1RXDSR4.Bits.DB5
|
| 11175 |
|
|
#define CAN1RXDSR4_DB6 _CAN1RXDSR4.Bits.DB6
|
| 11176 |
|
|
#define CAN1RXDSR4_DB7 _CAN1RXDSR4.Bits.DB7
|
| 11177 |
|
|
#define CAN1RXDSR4_DB _CAN1RXDSR4.MergedBits.grpDB
|
| 11178 |
|
|
|
| 11179 |
|
|
|
| 11180 |
|
|
/*** CAN1RXDSR5 - MSCAN 1 Receive Data Segment Register 5; 0x000001A9 ***/
|
| 11181 |
|
|
typedef union {
|
| 11182 |
|
|
byte Byte;
|
| 11183 |
|
|
struct {
|
| 11184 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11185 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11186 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11187 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11188 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11189 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11190 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11191 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11192 |
|
|
} Bits;
|
| 11193 |
|
|
struct {
|
| 11194 |
|
|
byte grpDB :8;
|
| 11195 |
|
|
} MergedBits;
|
| 11196 |
|
|
} CAN1RXDSR5STR;
|
| 11197 |
|
|
extern volatile CAN1RXDSR5STR _CAN1RXDSR5 @(REG_BASE + 0x000001A9);
|
| 11198 |
|
|
#define CAN1RXDSR5 _CAN1RXDSR5.Byte
|
| 11199 |
|
|
#define CAN1RXDSR5_DB0 _CAN1RXDSR5.Bits.DB0
|
| 11200 |
|
|
#define CAN1RXDSR5_DB1 _CAN1RXDSR5.Bits.DB1
|
| 11201 |
|
|
#define CAN1RXDSR5_DB2 _CAN1RXDSR5.Bits.DB2
|
| 11202 |
|
|
#define CAN1RXDSR5_DB3 _CAN1RXDSR5.Bits.DB3
|
| 11203 |
|
|
#define CAN1RXDSR5_DB4 _CAN1RXDSR5.Bits.DB4
|
| 11204 |
|
|
#define CAN1RXDSR5_DB5 _CAN1RXDSR5.Bits.DB5
|
| 11205 |
|
|
#define CAN1RXDSR5_DB6 _CAN1RXDSR5.Bits.DB6
|
| 11206 |
|
|
#define CAN1RXDSR5_DB7 _CAN1RXDSR5.Bits.DB7
|
| 11207 |
|
|
#define CAN1RXDSR5_DB _CAN1RXDSR5.MergedBits.grpDB
|
| 11208 |
|
|
|
| 11209 |
|
|
|
| 11210 |
|
|
/*** CAN1RXDSR6 - MSCAN 1 Receive Data Segment Register 6; 0x000001AA ***/
|
| 11211 |
|
|
typedef union {
|
| 11212 |
|
|
byte Byte;
|
| 11213 |
|
|
struct {
|
| 11214 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11215 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11216 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11217 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11218 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11219 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11220 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11221 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11222 |
|
|
} Bits;
|
| 11223 |
|
|
struct {
|
| 11224 |
|
|
byte grpDB :8;
|
| 11225 |
|
|
} MergedBits;
|
| 11226 |
|
|
} CAN1RXDSR6STR;
|
| 11227 |
|
|
extern volatile CAN1RXDSR6STR _CAN1RXDSR6 @(REG_BASE + 0x000001AA);
|
| 11228 |
|
|
#define CAN1RXDSR6 _CAN1RXDSR6.Byte
|
| 11229 |
|
|
#define CAN1RXDSR6_DB0 _CAN1RXDSR6.Bits.DB0
|
| 11230 |
|
|
#define CAN1RXDSR6_DB1 _CAN1RXDSR6.Bits.DB1
|
| 11231 |
|
|
#define CAN1RXDSR6_DB2 _CAN1RXDSR6.Bits.DB2
|
| 11232 |
|
|
#define CAN1RXDSR6_DB3 _CAN1RXDSR6.Bits.DB3
|
| 11233 |
|
|
#define CAN1RXDSR6_DB4 _CAN1RXDSR6.Bits.DB4
|
| 11234 |
|
|
#define CAN1RXDSR6_DB5 _CAN1RXDSR6.Bits.DB5
|
| 11235 |
|
|
#define CAN1RXDSR6_DB6 _CAN1RXDSR6.Bits.DB6
|
| 11236 |
|
|
#define CAN1RXDSR6_DB7 _CAN1RXDSR6.Bits.DB7
|
| 11237 |
|
|
#define CAN1RXDSR6_DB _CAN1RXDSR6.MergedBits.grpDB
|
| 11238 |
|
|
|
| 11239 |
|
|
|
| 11240 |
|
|
/*** CAN1RXDSR7 - MSCAN 1 Receive Data Segment Register 7; 0x000001AB ***/
|
| 11241 |
|
|
typedef union {
|
| 11242 |
|
|
byte Byte;
|
| 11243 |
|
|
struct {
|
| 11244 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11245 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11246 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11247 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11248 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11249 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11250 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11251 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11252 |
|
|
} Bits;
|
| 11253 |
|
|
struct {
|
| 11254 |
|
|
byte grpDB :8;
|
| 11255 |
|
|
} MergedBits;
|
| 11256 |
|
|
} CAN1RXDSR7STR;
|
| 11257 |
|
|
extern volatile CAN1RXDSR7STR _CAN1RXDSR7 @(REG_BASE + 0x000001AB);
|
| 11258 |
|
|
#define CAN1RXDSR7 _CAN1RXDSR7.Byte
|
| 11259 |
|
|
#define CAN1RXDSR7_DB0 _CAN1RXDSR7.Bits.DB0
|
| 11260 |
|
|
#define CAN1RXDSR7_DB1 _CAN1RXDSR7.Bits.DB1
|
| 11261 |
|
|
#define CAN1RXDSR7_DB2 _CAN1RXDSR7.Bits.DB2
|
| 11262 |
|
|
#define CAN1RXDSR7_DB3 _CAN1RXDSR7.Bits.DB3
|
| 11263 |
|
|
#define CAN1RXDSR7_DB4 _CAN1RXDSR7.Bits.DB4
|
| 11264 |
|
|
#define CAN1RXDSR7_DB5 _CAN1RXDSR7.Bits.DB5
|
| 11265 |
|
|
#define CAN1RXDSR7_DB6 _CAN1RXDSR7.Bits.DB6
|
| 11266 |
|
|
#define CAN1RXDSR7_DB7 _CAN1RXDSR7.Bits.DB7
|
| 11267 |
|
|
#define CAN1RXDSR7_DB _CAN1RXDSR7.MergedBits.grpDB
|
| 11268 |
|
|
|
| 11269 |
|
|
|
| 11270 |
|
|
/*** CAN1RXDLR - MSCAN 1 Receive Data Length Register; 0x000001AC ***/
|
| 11271 |
|
|
typedef union {
|
| 11272 |
|
|
byte Byte;
|
| 11273 |
|
|
struct {
|
| 11274 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 11275 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 11276 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 11277 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 11278 |
|
|
byte :1;
|
| 11279 |
|
|
byte :1;
|
| 11280 |
|
|
byte :1;
|
| 11281 |
|
|
byte :1;
|
| 11282 |
|
|
} Bits;
|
| 11283 |
|
|
struct {
|
| 11284 |
|
|
byte grpDLC :4;
|
| 11285 |
|
|
byte :1;
|
| 11286 |
|
|
byte :1;
|
| 11287 |
|
|
byte :1;
|
| 11288 |
|
|
byte :1;
|
| 11289 |
|
|
} MergedBits;
|
| 11290 |
|
|
} CAN1RXDLRSTR;
|
| 11291 |
|
|
extern volatile CAN1RXDLRSTR _CAN1RXDLR @(REG_BASE + 0x000001AC);
|
| 11292 |
|
|
#define CAN1RXDLR _CAN1RXDLR.Byte
|
| 11293 |
|
|
#define CAN1RXDLR_DLC0 _CAN1RXDLR.Bits.DLC0
|
| 11294 |
|
|
#define CAN1RXDLR_DLC1 _CAN1RXDLR.Bits.DLC1
|
| 11295 |
|
|
#define CAN1RXDLR_DLC2 _CAN1RXDLR.Bits.DLC2
|
| 11296 |
|
|
#define CAN1RXDLR_DLC3 _CAN1RXDLR.Bits.DLC3
|
| 11297 |
|
|
#define CAN1RXDLR_DLC _CAN1RXDLR.MergedBits.grpDLC
|
| 11298 |
|
|
|
| 11299 |
|
|
|
| 11300 |
|
|
/*** CAN1TXIDR0 - MSCAN 1 Transmit Identifier Register 0; 0x000001B0 ***/
|
| 11301 |
|
|
typedef union {
|
| 11302 |
|
|
byte Byte;
|
| 11303 |
|
|
struct {
|
| 11304 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 11305 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 11306 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 11307 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 11308 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 11309 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 11310 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 11311 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 11312 |
|
|
} Bits;
|
| 11313 |
|
|
struct {
|
| 11314 |
|
|
byte grpID_21 :8;
|
| 11315 |
|
|
} MergedBits;
|
| 11316 |
|
|
} CAN1TXIDR0STR;
|
| 11317 |
|
|
extern volatile CAN1TXIDR0STR _CAN1TXIDR0 @(REG_BASE + 0x000001B0);
|
| 11318 |
|
|
#define CAN1TXIDR0 _CAN1TXIDR0.Byte
|
| 11319 |
|
|
#define CAN1TXIDR0_ID21 _CAN1TXIDR0.Bits.ID21
|
| 11320 |
|
|
#define CAN1TXIDR0_ID22 _CAN1TXIDR0.Bits.ID22
|
| 11321 |
|
|
#define CAN1TXIDR0_ID23 _CAN1TXIDR0.Bits.ID23
|
| 11322 |
|
|
#define CAN1TXIDR0_ID24 _CAN1TXIDR0.Bits.ID24
|
| 11323 |
|
|
#define CAN1TXIDR0_ID25 _CAN1TXIDR0.Bits.ID25
|
| 11324 |
|
|
#define CAN1TXIDR0_ID26 _CAN1TXIDR0.Bits.ID26
|
| 11325 |
|
|
#define CAN1TXIDR0_ID27 _CAN1TXIDR0.Bits.ID27
|
| 11326 |
|
|
#define CAN1TXIDR0_ID28 _CAN1TXIDR0.Bits.ID28
|
| 11327 |
|
|
#define CAN1TXIDR0_ID_21 _CAN1TXIDR0.MergedBits.grpID_21
|
| 11328 |
|
|
#define CAN1TXIDR0_ID CAN1TXIDR0_ID_21
|
| 11329 |
|
|
|
| 11330 |
|
|
|
| 11331 |
|
|
/*** CAN1TXIDR1 - MSCAN 1 Transmit Identifier Register 1; 0x000001B1 ***/
|
| 11332 |
|
|
typedef union {
|
| 11333 |
|
|
byte Byte;
|
| 11334 |
|
|
struct {
|
| 11335 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 11336 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 11337 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 11338 |
|
|
byte IDE :1; /* ID Extended */
|
| 11339 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 11340 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 11341 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 11342 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 11343 |
|
|
} Bits;
|
| 11344 |
|
|
struct {
|
| 11345 |
|
|
byte grpID_15 :3;
|
| 11346 |
|
|
byte :1;
|
| 11347 |
|
|
byte :1;
|
| 11348 |
|
|
byte grpID_18 :3;
|
| 11349 |
|
|
} MergedBits;
|
| 11350 |
|
|
} CAN1TXIDR1STR;
|
| 11351 |
|
|
extern volatile CAN1TXIDR1STR _CAN1TXIDR1 @(REG_BASE + 0x000001B1);
|
| 11352 |
|
|
#define CAN1TXIDR1 _CAN1TXIDR1.Byte
|
| 11353 |
|
|
#define CAN1TXIDR1_ID15 _CAN1TXIDR1.Bits.ID15
|
| 11354 |
|
|
#define CAN1TXIDR1_ID16 _CAN1TXIDR1.Bits.ID16
|
| 11355 |
|
|
#define CAN1TXIDR1_ID17 _CAN1TXIDR1.Bits.ID17
|
| 11356 |
|
|
#define CAN1TXIDR1_IDE _CAN1TXIDR1.Bits.IDE
|
| 11357 |
|
|
#define CAN1TXIDR1_SRR _CAN1TXIDR1.Bits.SRR
|
| 11358 |
|
|
#define CAN1TXIDR1_ID18 _CAN1TXIDR1.Bits.ID18
|
| 11359 |
|
|
#define CAN1TXIDR1_ID19 _CAN1TXIDR1.Bits.ID19
|
| 11360 |
|
|
#define CAN1TXIDR1_ID20 _CAN1TXIDR1.Bits.ID20
|
| 11361 |
|
|
#define CAN1TXIDR1_ID_15 _CAN1TXIDR1.MergedBits.grpID_15
|
| 11362 |
|
|
#define CAN1TXIDR1_ID_18 _CAN1TXIDR1.MergedBits.grpID_18
|
| 11363 |
|
|
#define CAN1TXIDR1_ID CAN1TXIDR1_ID_15
|
| 11364 |
|
|
|
| 11365 |
|
|
|
| 11366 |
|
|
/*** CAN1TXIDR2 - MSCAN 1 Transmit Identifier Register 2; 0x000001B2 ***/
|
| 11367 |
|
|
typedef union {
|
| 11368 |
|
|
byte Byte;
|
| 11369 |
|
|
struct {
|
| 11370 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 11371 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 11372 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 11373 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 11374 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 11375 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 11376 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 11377 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 11378 |
|
|
} Bits;
|
| 11379 |
|
|
struct {
|
| 11380 |
|
|
byte grpID_7 :8;
|
| 11381 |
|
|
} MergedBits;
|
| 11382 |
|
|
} CAN1TXIDR2STR;
|
| 11383 |
|
|
extern volatile CAN1TXIDR2STR _CAN1TXIDR2 @(REG_BASE + 0x000001B2);
|
| 11384 |
|
|
#define CAN1TXIDR2 _CAN1TXIDR2.Byte
|
| 11385 |
|
|
#define CAN1TXIDR2_ID7 _CAN1TXIDR2.Bits.ID7
|
| 11386 |
|
|
#define CAN1TXIDR2_ID8 _CAN1TXIDR2.Bits.ID8
|
| 11387 |
|
|
#define CAN1TXIDR2_ID9 _CAN1TXIDR2.Bits.ID9
|
| 11388 |
|
|
#define CAN1TXIDR2_ID10 _CAN1TXIDR2.Bits.ID10
|
| 11389 |
|
|
#define CAN1TXIDR2_ID11 _CAN1TXIDR2.Bits.ID11
|
| 11390 |
|
|
#define CAN1TXIDR2_ID12 _CAN1TXIDR2.Bits.ID12
|
| 11391 |
|
|
#define CAN1TXIDR2_ID13 _CAN1TXIDR2.Bits.ID13
|
| 11392 |
|
|
#define CAN1TXIDR2_ID14 _CAN1TXIDR2.Bits.ID14
|
| 11393 |
|
|
#define CAN1TXIDR2_ID_7 _CAN1TXIDR2.MergedBits.grpID_7
|
| 11394 |
|
|
#define CAN1TXIDR2_ID CAN1TXIDR2_ID_7
|
| 11395 |
|
|
|
| 11396 |
|
|
|
| 11397 |
|
|
/*** CAN1TXIDR3 - MSCAN 1 Transmit Identifier Register 3; 0x000001B3 ***/
|
| 11398 |
|
|
typedef union {
|
| 11399 |
|
|
byte Byte;
|
| 11400 |
|
|
struct {
|
| 11401 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 11402 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 11403 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 11404 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 11405 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 11406 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 11407 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 11408 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 11409 |
|
|
} Bits;
|
| 11410 |
|
|
struct {
|
| 11411 |
|
|
byte :1;
|
| 11412 |
|
|
byte grpID :7;
|
| 11413 |
|
|
} MergedBits;
|
| 11414 |
|
|
} CAN1TXIDR3STR;
|
| 11415 |
|
|
extern volatile CAN1TXIDR3STR _CAN1TXIDR3 @(REG_BASE + 0x000001B3);
|
| 11416 |
|
|
#define CAN1TXIDR3 _CAN1TXIDR3.Byte
|
| 11417 |
|
|
#define CAN1TXIDR3_RTR _CAN1TXIDR3.Bits.RTR
|
| 11418 |
|
|
#define CAN1TXIDR3_ID0 _CAN1TXIDR3.Bits.ID0
|
| 11419 |
|
|
#define CAN1TXIDR3_ID1 _CAN1TXIDR3.Bits.ID1
|
| 11420 |
|
|
#define CAN1TXIDR3_ID2 _CAN1TXIDR3.Bits.ID2
|
| 11421 |
|
|
#define CAN1TXIDR3_ID3 _CAN1TXIDR3.Bits.ID3
|
| 11422 |
|
|
#define CAN1TXIDR3_ID4 _CAN1TXIDR3.Bits.ID4
|
| 11423 |
|
|
#define CAN1TXIDR3_ID5 _CAN1TXIDR3.Bits.ID5
|
| 11424 |
|
|
#define CAN1TXIDR3_ID6 _CAN1TXIDR3.Bits.ID6
|
| 11425 |
|
|
#define CAN1TXIDR3_ID _CAN1TXIDR3.MergedBits.grpID
|
| 11426 |
|
|
|
| 11427 |
|
|
|
| 11428 |
|
|
/*** CAN1TXDSR0 - MSCAN 1 Transmit Data Segment Register 0; 0x000001B4 ***/
|
| 11429 |
|
|
typedef union {
|
| 11430 |
|
|
byte Byte;
|
| 11431 |
|
|
struct {
|
| 11432 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11433 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11434 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11435 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11436 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11437 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11438 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11439 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11440 |
|
|
} Bits;
|
| 11441 |
|
|
struct {
|
| 11442 |
|
|
byte grpDB :8;
|
| 11443 |
|
|
} MergedBits;
|
| 11444 |
|
|
} CAN1TXDSR0STR;
|
| 11445 |
|
|
extern volatile CAN1TXDSR0STR _CAN1TXDSR0 @(REG_BASE + 0x000001B4);
|
| 11446 |
|
|
#define CAN1TXDSR0 _CAN1TXDSR0.Byte
|
| 11447 |
|
|
#define CAN1TXDSR0_DB0 _CAN1TXDSR0.Bits.DB0
|
| 11448 |
|
|
#define CAN1TXDSR0_DB1 _CAN1TXDSR0.Bits.DB1
|
| 11449 |
|
|
#define CAN1TXDSR0_DB2 _CAN1TXDSR0.Bits.DB2
|
| 11450 |
|
|
#define CAN1TXDSR0_DB3 _CAN1TXDSR0.Bits.DB3
|
| 11451 |
|
|
#define CAN1TXDSR0_DB4 _CAN1TXDSR0.Bits.DB4
|
| 11452 |
|
|
#define CAN1TXDSR0_DB5 _CAN1TXDSR0.Bits.DB5
|
| 11453 |
|
|
#define CAN1TXDSR0_DB6 _CAN1TXDSR0.Bits.DB6
|
| 11454 |
|
|
#define CAN1TXDSR0_DB7 _CAN1TXDSR0.Bits.DB7
|
| 11455 |
|
|
#define CAN1TXDSR0_DB _CAN1TXDSR0.MergedBits.grpDB
|
| 11456 |
|
|
|
| 11457 |
|
|
|
| 11458 |
|
|
/*** CAN1TXDSR1 - MSCAN 1 Transmit Data Segment Register 1; 0x000001B5 ***/
|
| 11459 |
|
|
typedef union {
|
| 11460 |
|
|
byte Byte;
|
| 11461 |
|
|
struct {
|
| 11462 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11463 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11464 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11465 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11466 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11467 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11468 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11469 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11470 |
|
|
} Bits;
|
| 11471 |
|
|
struct {
|
| 11472 |
|
|
byte grpDB :8;
|
| 11473 |
|
|
} MergedBits;
|
| 11474 |
|
|
} CAN1TXDSR1STR;
|
| 11475 |
|
|
extern volatile CAN1TXDSR1STR _CAN1TXDSR1 @(REG_BASE + 0x000001B5);
|
| 11476 |
|
|
#define CAN1TXDSR1 _CAN1TXDSR1.Byte
|
| 11477 |
|
|
#define CAN1TXDSR1_DB0 _CAN1TXDSR1.Bits.DB0
|
| 11478 |
|
|
#define CAN1TXDSR1_DB1 _CAN1TXDSR1.Bits.DB1
|
| 11479 |
|
|
#define CAN1TXDSR1_DB2 _CAN1TXDSR1.Bits.DB2
|
| 11480 |
|
|
#define CAN1TXDSR1_DB3 _CAN1TXDSR1.Bits.DB3
|
| 11481 |
|
|
#define CAN1TXDSR1_DB4 _CAN1TXDSR1.Bits.DB4
|
| 11482 |
|
|
#define CAN1TXDSR1_DB5 _CAN1TXDSR1.Bits.DB5
|
| 11483 |
|
|
#define CAN1TXDSR1_DB6 _CAN1TXDSR1.Bits.DB6
|
| 11484 |
|
|
#define CAN1TXDSR1_DB7 _CAN1TXDSR1.Bits.DB7
|
| 11485 |
|
|
#define CAN1TXDSR1_DB _CAN1TXDSR1.MergedBits.grpDB
|
| 11486 |
|
|
|
| 11487 |
|
|
|
| 11488 |
|
|
/*** CAN1TXDSR2 - MSCAN 1 Transmit Data Segment Register 2; 0x000001B6 ***/
|
| 11489 |
|
|
typedef union {
|
| 11490 |
|
|
byte Byte;
|
| 11491 |
|
|
struct {
|
| 11492 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11493 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11494 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11495 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11496 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11497 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11498 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11499 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11500 |
|
|
} Bits;
|
| 11501 |
|
|
struct {
|
| 11502 |
|
|
byte grpDB :8;
|
| 11503 |
|
|
} MergedBits;
|
| 11504 |
|
|
} CAN1TXDSR2STR;
|
| 11505 |
|
|
extern volatile CAN1TXDSR2STR _CAN1TXDSR2 @(REG_BASE + 0x000001B6);
|
| 11506 |
|
|
#define CAN1TXDSR2 _CAN1TXDSR2.Byte
|
| 11507 |
|
|
#define CAN1TXDSR2_DB0 _CAN1TXDSR2.Bits.DB0
|
| 11508 |
|
|
#define CAN1TXDSR2_DB1 _CAN1TXDSR2.Bits.DB1
|
| 11509 |
|
|
#define CAN1TXDSR2_DB2 _CAN1TXDSR2.Bits.DB2
|
| 11510 |
|
|
#define CAN1TXDSR2_DB3 _CAN1TXDSR2.Bits.DB3
|
| 11511 |
|
|
#define CAN1TXDSR2_DB4 _CAN1TXDSR2.Bits.DB4
|
| 11512 |
|
|
#define CAN1TXDSR2_DB5 _CAN1TXDSR2.Bits.DB5
|
| 11513 |
|
|
#define CAN1TXDSR2_DB6 _CAN1TXDSR2.Bits.DB6
|
| 11514 |
|
|
#define CAN1TXDSR2_DB7 _CAN1TXDSR2.Bits.DB7
|
| 11515 |
|
|
#define CAN1TXDSR2_DB _CAN1TXDSR2.MergedBits.grpDB
|
| 11516 |
|
|
|
| 11517 |
|
|
|
| 11518 |
|
|
/*** CAN1TXDSR3 - MSCAN 1 Transmit Data Segment Register 3; 0x000001B7 ***/
|
| 11519 |
|
|
typedef union {
|
| 11520 |
|
|
byte Byte;
|
| 11521 |
|
|
struct {
|
| 11522 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11523 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11524 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11525 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11526 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11527 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11528 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11529 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11530 |
|
|
} Bits;
|
| 11531 |
|
|
struct {
|
| 11532 |
|
|
byte grpDB :8;
|
| 11533 |
|
|
} MergedBits;
|
| 11534 |
|
|
} CAN1TXDSR3STR;
|
| 11535 |
|
|
extern volatile CAN1TXDSR3STR _CAN1TXDSR3 @(REG_BASE + 0x000001B7);
|
| 11536 |
|
|
#define CAN1TXDSR3 _CAN1TXDSR3.Byte
|
| 11537 |
|
|
#define CAN1TXDSR3_DB0 _CAN1TXDSR3.Bits.DB0
|
| 11538 |
|
|
#define CAN1TXDSR3_DB1 _CAN1TXDSR3.Bits.DB1
|
| 11539 |
|
|
#define CAN1TXDSR3_DB2 _CAN1TXDSR3.Bits.DB2
|
| 11540 |
|
|
#define CAN1TXDSR3_DB3 _CAN1TXDSR3.Bits.DB3
|
| 11541 |
|
|
#define CAN1TXDSR3_DB4 _CAN1TXDSR3.Bits.DB4
|
| 11542 |
|
|
#define CAN1TXDSR3_DB5 _CAN1TXDSR3.Bits.DB5
|
| 11543 |
|
|
#define CAN1TXDSR3_DB6 _CAN1TXDSR3.Bits.DB6
|
| 11544 |
|
|
#define CAN1TXDSR3_DB7 _CAN1TXDSR3.Bits.DB7
|
| 11545 |
|
|
#define CAN1TXDSR3_DB _CAN1TXDSR3.MergedBits.grpDB
|
| 11546 |
|
|
|
| 11547 |
|
|
|
| 11548 |
|
|
/*** CAN1TXDSR4 - MSCAN 1 Transmit Data Segment Register 4; 0x000001B8 ***/
|
| 11549 |
|
|
typedef union {
|
| 11550 |
|
|
byte Byte;
|
| 11551 |
|
|
struct {
|
| 11552 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11553 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11554 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11555 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11556 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11557 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11558 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11559 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11560 |
|
|
} Bits;
|
| 11561 |
|
|
struct {
|
| 11562 |
|
|
byte grpDB :8;
|
| 11563 |
|
|
} MergedBits;
|
| 11564 |
|
|
} CAN1TXDSR4STR;
|
| 11565 |
|
|
extern volatile CAN1TXDSR4STR _CAN1TXDSR4 @(REG_BASE + 0x000001B8);
|
| 11566 |
|
|
#define CAN1TXDSR4 _CAN1TXDSR4.Byte
|
| 11567 |
|
|
#define CAN1TXDSR4_DB0 _CAN1TXDSR4.Bits.DB0
|
| 11568 |
|
|
#define CAN1TXDSR4_DB1 _CAN1TXDSR4.Bits.DB1
|
| 11569 |
|
|
#define CAN1TXDSR4_DB2 _CAN1TXDSR4.Bits.DB2
|
| 11570 |
|
|
#define CAN1TXDSR4_DB3 _CAN1TXDSR4.Bits.DB3
|
| 11571 |
|
|
#define CAN1TXDSR4_DB4 _CAN1TXDSR4.Bits.DB4
|
| 11572 |
|
|
#define CAN1TXDSR4_DB5 _CAN1TXDSR4.Bits.DB5
|
| 11573 |
|
|
#define CAN1TXDSR4_DB6 _CAN1TXDSR4.Bits.DB6
|
| 11574 |
|
|
#define CAN1TXDSR4_DB7 _CAN1TXDSR4.Bits.DB7
|
| 11575 |
|
|
#define CAN1TXDSR4_DB _CAN1TXDSR4.MergedBits.grpDB
|
| 11576 |
|
|
|
| 11577 |
|
|
|
| 11578 |
|
|
/*** CAN1TXDSR5 - MSCAN 1 Transmit Data Segment Register 5; 0x000001B9 ***/
|
| 11579 |
|
|
typedef union {
|
| 11580 |
|
|
byte Byte;
|
| 11581 |
|
|
struct {
|
| 11582 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11583 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11584 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11585 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11586 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11587 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11588 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11589 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11590 |
|
|
} Bits;
|
| 11591 |
|
|
struct {
|
| 11592 |
|
|
byte grpDB :8;
|
| 11593 |
|
|
} MergedBits;
|
| 11594 |
|
|
} CAN1TXDSR5STR;
|
| 11595 |
|
|
extern volatile CAN1TXDSR5STR _CAN1TXDSR5 @(REG_BASE + 0x000001B9);
|
| 11596 |
|
|
#define CAN1TXDSR5 _CAN1TXDSR5.Byte
|
| 11597 |
|
|
#define CAN1TXDSR5_DB0 _CAN1TXDSR5.Bits.DB0
|
| 11598 |
|
|
#define CAN1TXDSR5_DB1 _CAN1TXDSR5.Bits.DB1
|
| 11599 |
|
|
#define CAN1TXDSR5_DB2 _CAN1TXDSR5.Bits.DB2
|
| 11600 |
|
|
#define CAN1TXDSR5_DB3 _CAN1TXDSR5.Bits.DB3
|
| 11601 |
|
|
#define CAN1TXDSR5_DB4 _CAN1TXDSR5.Bits.DB4
|
| 11602 |
|
|
#define CAN1TXDSR5_DB5 _CAN1TXDSR5.Bits.DB5
|
| 11603 |
|
|
#define CAN1TXDSR5_DB6 _CAN1TXDSR5.Bits.DB6
|
| 11604 |
|
|
#define CAN1TXDSR5_DB7 _CAN1TXDSR5.Bits.DB7
|
| 11605 |
|
|
#define CAN1TXDSR5_DB _CAN1TXDSR5.MergedBits.grpDB
|
| 11606 |
|
|
|
| 11607 |
|
|
|
| 11608 |
|
|
/*** CAN1TXDSR6 - MSCAN 1 Transmit Data Segment Register 6; 0x000001BA ***/
|
| 11609 |
|
|
typedef union {
|
| 11610 |
|
|
byte Byte;
|
| 11611 |
|
|
struct {
|
| 11612 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11613 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11614 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11615 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11616 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11617 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11618 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11619 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11620 |
|
|
} Bits;
|
| 11621 |
|
|
struct {
|
| 11622 |
|
|
byte grpDB :8;
|
| 11623 |
|
|
} MergedBits;
|
| 11624 |
|
|
} CAN1TXDSR6STR;
|
| 11625 |
|
|
extern volatile CAN1TXDSR6STR _CAN1TXDSR6 @(REG_BASE + 0x000001BA);
|
| 11626 |
|
|
#define CAN1TXDSR6 _CAN1TXDSR6.Byte
|
| 11627 |
|
|
#define CAN1TXDSR6_DB0 _CAN1TXDSR6.Bits.DB0
|
| 11628 |
|
|
#define CAN1TXDSR6_DB1 _CAN1TXDSR6.Bits.DB1
|
| 11629 |
|
|
#define CAN1TXDSR6_DB2 _CAN1TXDSR6.Bits.DB2
|
| 11630 |
|
|
#define CAN1TXDSR6_DB3 _CAN1TXDSR6.Bits.DB3
|
| 11631 |
|
|
#define CAN1TXDSR6_DB4 _CAN1TXDSR6.Bits.DB4
|
| 11632 |
|
|
#define CAN1TXDSR6_DB5 _CAN1TXDSR6.Bits.DB5
|
| 11633 |
|
|
#define CAN1TXDSR6_DB6 _CAN1TXDSR6.Bits.DB6
|
| 11634 |
|
|
#define CAN1TXDSR6_DB7 _CAN1TXDSR6.Bits.DB7
|
| 11635 |
|
|
#define CAN1TXDSR6_DB _CAN1TXDSR6.MergedBits.grpDB
|
| 11636 |
|
|
|
| 11637 |
|
|
|
| 11638 |
|
|
/*** CAN1TXDSR7 - MSCAN 1 Transmit Data Segment Register 7; 0x000001BB ***/
|
| 11639 |
|
|
typedef union {
|
| 11640 |
|
|
byte Byte;
|
| 11641 |
|
|
struct {
|
| 11642 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 11643 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 11644 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 11645 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 11646 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 11647 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 11648 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 11649 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 11650 |
|
|
} Bits;
|
| 11651 |
|
|
struct {
|
| 11652 |
|
|
byte grpDB :8;
|
| 11653 |
|
|
} MergedBits;
|
| 11654 |
|
|
} CAN1TXDSR7STR;
|
| 11655 |
|
|
extern volatile CAN1TXDSR7STR _CAN1TXDSR7 @(REG_BASE + 0x000001BB);
|
| 11656 |
|
|
#define CAN1TXDSR7 _CAN1TXDSR7.Byte
|
| 11657 |
|
|
#define CAN1TXDSR7_DB0 _CAN1TXDSR7.Bits.DB0
|
| 11658 |
|
|
#define CAN1TXDSR7_DB1 _CAN1TXDSR7.Bits.DB1
|
| 11659 |
|
|
#define CAN1TXDSR7_DB2 _CAN1TXDSR7.Bits.DB2
|
| 11660 |
|
|
#define CAN1TXDSR7_DB3 _CAN1TXDSR7.Bits.DB3
|
| 11661 |
|
|
#define CAN1TXDSR7_DB4 _CAN1TXDSR7.Bits.DB4
|
| 11662 |
|
|
#define CAN1TXDSR7_DB5 _CAN1TXDSR7.Bits.DB5
|
| 11663 |
|
|
#define CAN1TXDSR7_DB6 _CAN1TXDSR7.Bits.DB6
|
| 11664 |
|
|
#define CAN1TXDSR7_DB7 _CAN1TXDSR7.Bits.DB7
|
| 11665 |
|
|
#define CAN1TXDSR7_DB _CAN1TXDSR7.MergedBits.grpDB
|
| 11666 |
|
|
|
| 11667 |
|
|
|
| 11668 |
|
|
/*** CAN1TXDLR - MSCAN 1 Transmit Data Length Register; 0x000001BC ***/
|
| 11669 |
|
|
typedef union {
|
| 11670 |
|
|
byte Byte;
|
| 11671 |
|
|
struct {
|
| 11672 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 11673 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 11674 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 11675 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 11676 |
|
|
byte :1;
|
| 11677 |
|
|
byte :1;
|
| 11678 |
|
|
byte :1;
|
| 11679 |
|
|
byte :1;
|
| 11680 |
|
|
} Bits;
|
| 11681 |
|
|
struct {
|
| 11682 |
|
|
byte grpDLC :4;
|
| 11683 |
|
|
byte :1;
|
| 11684 |
|
|
byte :1;
|
| 11685 |
|
|
byte :1;
|
| 11686 |
|
|
byte :1;
|
| 11687 |
|
|
} MergedBits;
|
| 11688 |
|
|
} CAN1TXDLRSTR;
|
| 11689 |
|
|
extern volatile CAN1TXDLRSTR _CAN1TXDLR @(REG_BASE + 0x000001BC);
|
| 11690 |
|
|
#define CAN1TXDLR _CAN1TXDLR.Byte
|
| 11691 |
|
|
#define CAN1TXDLR_DLC0 _CAN1TXDLR.Bits.DLC0
|
| 11692 |
|
|
#define CAN1TXDLR_DLC1 _CAN1TXDLR.Bits.DLC1
|
| 11693 |
|
|
#define CAN1TXDLR_DLC2 _CAN1TXDLR.Bits.DLC2
|
| 11694 |
|
|
#define CAN1TXDLR_DLC3 _CAN1TXDLR.Bits.DLC3
|
| 11695 |
|
|
#define CAN1TXDLR_DLC _CAN1TXDLR.MergedBits.grpDLC
|
| 11696 |
|
|
|
| 11697 |
|
|
|
| 11698 |
|
|
/*** CAN1TXTBPR - MSCAN 1 Transmit Buffer Priority; 0x000001BF ***/
|
| 11699 |
|
|
typedef union {
|
| 11700 |
|
|
byte Byte;
|
| 11701 |
|
|
struct {
|
| 11702 |
|
|
byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
|
| 11703 |
|
|
byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
|
| 11704 |
|
|
byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
|
| 11705 |
|
|
byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
|
| 11706 |
|
|
byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
|
| 11707 |
|
|
byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
|
| 11708 |
|
|
byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
|
| 11709 |
|
|
byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
|
| 11710 |
|
|
} Bits;
|
| 11711 |
|
|
struct {
|
| 11712 |
|
|
byte grpPRIO :8;
|
| 11713 |
|
|
} MergedBits;
|
| 11714 |
|
|
} CAN1TXTBPRSTR;
|
| 11715 |
|
|
extern volatile CAN1TXTBPRSTR _CAN1TXTBPR @(REG_BASE + 0x000001BF);
|
| 11716 |
|
|
#define CAN1TXTBPR _CAN1TXTBPR.Byte
|
| 11717 |
|
|
#define CAN1TXTBPR_PRIO0 _CAN1TXTBPR.Bits.PRIO0
|
| 11718 |
|
|
#define CAN1TXTBPR_PRIO1 _CAN1TXTBPR.Bits.PRIO1
|
| 11719 |
|
|
#define CAN1TXTBPR_PRIO2 _CAN1TXTBPR.Bits.PRIO2
|
| 11720 |
|
|
#define CAN1TXTBPR_PRIO3 _CAN1TXTBPR.Bits.PRIO3
|
| 11721 |
|
|
#define CAN1TXTBPR_PRIO4 _CAN1TXTBPR.Bits.PRIO4
|
| 11722 |
|
|
#define CAN1TXTBPR_PRIO5 _CAN1TXTBPR.Bits.PRIO5
|
| 11723 |
|
|
#define CAN1TXTBPR_PRIO6 _CAN1TXTBPR.Bits.PRIO6
|
| 11724 |
|
|
#define CAN1TXTBPR_PRIO7 _CAN1TXTBPR.Bits.PRIO7
|
| 11725 |
|
|
#define CAN1TXTBPR_PRIO _CAN1TXTBPR.MergedBits.grpPRIO
|
| 11726 |
|
|
|
| 11727 |
|
|
|
| 11728 |
|
|
/*** CAN2CTL0 - MSCAN 2 Control 0 Register; 0x000001C0 ***/
|
| 11729 |
|
|
typedef union {
|
| 11730 |
|
|
byte Byte;
|
| 11731 |
|
|
struct {
|
| 11732 |
|
|
byte INITRQ :1; /* Initialization Mode Request */
|
| 11733 |
|
|
byte SLPRQ :1; /* Sleep Mode Request */
|
| 11734 |
|
|
byte WUPE :1; /* Wake-Up Enable */
|
| 11735 |
|
|
byte TIME :1; /* Timer Enable */
|
| 11736 |
|
|
byte SYNCH :1; /* Synchronized Status */
|
| 11737 |
|
|
byte CSWAI :1; /* CAN Stops in Wait Mode */
|
| 11738 |
|
|
byte RXACT :1; /* Receiver Active Status */
|
| 11739 |
|
|
byte RXFRM :1; /* Received Frame Flag */
|
| 11740 |
|
|
} Bits;
|
| 11741 |
|
|
} CAN2CTL0STR;
|
| 11742 |
|
|
extern volatile CAN2CTL0STR _CAN2CTL0 @(REG_BASE + 0x000001C0);
|
| 11743 |
|
|
#define CAN2CTL0 _CAN2CTL0.Byte
|
| 11744 |
|
|
#define CAN2CTL0_INITRQ _CAN2CTL0.Bits.INITRQ
|
| 11745 |
|
|
#define CAN2CTL0_SLPRQ _CAN2CTL0.Bits.SLPRQ
|
| 11746 |
|
|
#define CAN2CTL0_WUPE _CAN2CTL0.Bits.WUPE
|
| 11747 |
|
|
#define CAN2CTL0_TIME _CAN2CTL0.Bits.TIME
|
| 11748 |
|
|
#define CAN2CTL0_SYNCH _CAN2CTL0.Bits.SYNCH
|
| 11749 |
|
|
#define CAN2CTL0_CSWAI _CAN2CTL0.Bits.CSWAI
|
| 11750 |
|
|
#define CAN2CTL0_RXACT _CAN2CTL0.Bits.RXACT
|
| 11751 |
|
|
#define CAN2CTL0_RXFRM _CAN2CTL0.Bits.RXFRM
|
| 11752 |
|
|
|
| 11753 |
|
|
|
| 11754 |
|
|
/*** CAN2CTL1 - MSCAN 2 Control 1 Register; 0x000001C1 ***/
|
| 11755 |
|
|
typedef union {
|
| 11756 |
|
|
byte Byte;
|
| 11757 |
|
|
struct {
|
| 11758 |
|
|
byte INITAK :1; /* Initialization Mode Acknowledge */
|
| 11759 |
|
|
byte SLPAK :1; /* Sleep Mode Acknowledge */
|
| 11760 |
|
|
byte WUPM :1; /* Wake-Up Mode */
|
| 11761 |
|
|
byte :1;
|
| 11762 |
|
|
byte LISTEN :1; /* Listen Only Mode */
|
| 11763 |
|
|
byte LOOPB :1; /* Loop Back Self Test Mode */
|
| 11764 |
|
|
byte CLKSRC :1; /* MSCAN 2 Clock Source */
|
| 11765 |
|
|
byte CANE :1; /* MSCAN 2 Enable */
|
| 11766 |
|
|
} Bits;
|
| 11767 |
|
|
} CAN2CTL1STR;
|
| 11768 |
|
|
extern volatile CAN2CTL1STR _CAN2CTL1 @(REG_BASE + 0x000001C1);
|
| 11769 |
|
|
#define CAN2CTL1 _CAN2CTL1.Byte
|
| 11770 |
|
|
#define CAN2CTL1_INITAK _CAN2CTL1.Bits.INITAK
|
| 11771 |
|
|
#define CAN2CTL1_SLPAK _CAN2CTL1.Bits.SLPAK
|
| 11772 |
|
|
#define CAN2CTL1_WUPM _CAN2CTL1.Bits.WUPM
|
| 11773 |
|
|
#define CAN2CTL1_LISTEN _CAN2CTL1.Bits.LISTEN
|
| 11774 |
|
|
#define CAN2CTL1_LOOPB _CAN2CTL1.Bits.LOOPB
|
| 11775 |
|
|
#define CAN2CTL1_CLKSRC _CAN2CTL1.Bits.CLKSRC
|
| 11776 |
|
|
#define CAN2CTL1_CANE _CAN2CTL1.Bits.CANE
|
| 11777 |
|
|
|
| 11778 |
|
|
|
| 11779 |
|
|
/*** CAN2BTR0 - MSCAN 2 Bus Timing Register 0; 0x000001C2 ***/
|
| 11780 |
|
|
typedef union {
|
| 11781 |
|
|
byte Byte;
|
| 11782 |
|
|
struct {
|
| 11783 |
|
|
byte BRP0 :1; /* Baud Rate Prescaler 0 */
|
| 11784 |
|
|
byte BRP1 :1; /* Baud Rate Prescaler 1 */
|
| 11785 |
|
|
byte BRP2 :1; /* Baud Rate Prescaler 2 */
|
| 11786 |
|
|
byte BRP3 :1; /* Baud Rate Prescaler 3 */
|
| 11787 |
|
|
byte BRP4 :1; /* Baud Rate Prescaler 4 */
|
| 11788 |
|
|
byte BRP5 :1; /* Baud Rate Prescaler 5 */
|
| 11789 |
|
|
byte SJW0 :1; /* Synchronization Jump Width 0 */
|
| 11790 |
|
|
byte SJW1 :1; /* Synchronization Jump Width 1 */
|
| 11791 |
|
|
} Bits;
|
| 11792 |
|
|
struct {
|
| 11793 |
|
|
byte grpBRP :6;
|
| 11794 |
|
|
byte grpSJW :2;
|
| 11795 |
|
|
} MergedBits;
|
| 11796 |
|
|
} CAN2BTR0STR;
|
| 11797 |
|
|
extern volatile CAN2BTR0STR _CAN2BTR0 @(REG_BASE + 0x000001C2);
|
| 11798 |
|
|
#define CAN2BTR0 _CAN2BTR0.Byte
|
| 11799 |
|
|
#define CAN2BTR0_BRP0 _CAN2BTR0.Bits.BRP0
|
| 11800 |
|
|
#define CAN2BTR0_BRP1 _CAN2BTR0.Bits.BRP1
|
| 11801 |
|
|
#define CAN2BTR0_BRP2 _CAN2BTR0.Bits.BRP2
|
| 11802 |
|
|
#define CAN2BTR0_BRP3 _CAN2BTR0.Bits.BRP3
|
| 11803 |
|
|
#define CAN2BTR0_BRP4 _CAN2BTR0.Bits.BRP4
|
| 11804 |
|
|
#define CAN2BTR0_BRP5 _CAN2BTR0.Bits.BRP5
|
| 11805 |
|
|
#define CAN2BTR0_SJW0 _CAN2BTR0.Bits.SJW0
|
| 11806 |
|
|
#define CAN2BTR0_SJW1 _CAN2BTR0.Bits.SJW1
|
| 11807 |
|
|
#define CAN2BTR0_BRP _CAN2BTR0.MergedBits.grpBRP
|
| 11808 |
|
|
#define CAN2BTR0_SJW _CAN2BTR0.MergedBits.grpSJW
|
| 11809 |
|
|
|
| 11810 |
|
|
|
| 11811 |
|
|
/*** CAN2BTR1 - MSCAN 2 Bus Timing Register 1; 0x000001C3 ***/
|
| 11812 |
|
|
typedef union {
|
| 11813 |
|
|
byte Byte;
|
| 11814 |
|
|
struct {
|
| 11815 |
|
|
byte TSEG10 :1; /* Time Segment 1 */
|
| 11816 |
|
|
byte TSEG11 :1; /* Time Segment 1 */
|
| 11817 |
|
|
byte TSEG12 :1; /* Time Segment 1 */
|
| 11818 |
|
|
byte TSEG13 :1; /* Time Segment 1 */
|
| 11819 |
|
|
byte TSEG20 :1; /* Time Segment 2 */
|
| 11820 |
|
|
byte TSEG21 :1; /* Time Segment 2 */
|
| 11821 |
|
|
byte TSEG22 :1; /* Time Segment 2 */
|
| 11822 |
|
|
byte SAMP :1; /* Sampling */
|
| 11823 |
|
|
} Bits;
|
| 11824 |
|
|
struct {
|
| 11825 |
|
|
byte grpTSEG_10 :4;
|
| 11826 |
|
|
byte grpTSEG_20 :3;
|
| 11827 |
|
|
byte :1;
|
| 11828 |
|
|
} MergedBits;
|
| 11829 |
|
|
} CAN2BTR1STR;
|
| 11830 |
|
|
extern volatile CAN2BTR1STR _CAN2BTR1 @(REG_BASE + 0x000001C3);
|
| 11831 |
|
|
#define CAN2BTR1 _CAN2BTR1.Byte
|
| 11832 |
|
|
#define CAN2BTR1_TSEG10 _CAN2BTR1.Bits.TSEG10
|
| 11833 |
|
|
#define CAN2BTR1_TSEG11 _CAN2BTR1.Bits.TSEG11
|
| 11834 |
|
|
#define CAN2BTR1_TSEG12 _CAN2BTR1.Bits.TSEG12
|
| 11835 |
|
|
#define CAN2BTR1_TSEG13 _CAN2BTR1.Bits.TSEG13
|
| 11836 |
|
|
#define CAN2BTR1_TSEG20 _CAN2BTR1.Bits.TSEG20
|
| 11837 |
|
|
#define CAN2BTR1_TSEG21 _CAN2BTR1.Bits.TSEG21
|
| 11838 |
|
|
#define CAN2BTR1_TSEG22 _CAN2BTR1.Bits.TSEG22
|
| 11839 |
|
|
#define CAN2BTR1_SAMP _CAN2BTR1.Bits.SAMP
|
| 11840 |
|
|
#define CAN2BTR1_TSEG_10 _CAN2BTR1.MergedBits.grpTSEG_10
|
| 11841 |
|
|
#define CAN2BTR1_TSEG_20 _CAN2BTR1.MergedBits.grpTSEG_20
|
| 11842 |
|
|
#define CAN2BTR1_TSEG CAN2BTR1_TSEG_10
|
| 11843 |
|
|
|
| 11844 |
|
|
|
| 11845 |
|
|
/*** CAN2RFLG - MSCAN 2 Receiver Flag Register; 0x000001C4 ***/
|
| 11846 |
|
|
typedef union {
|
| 11847 |
|
|
byte Byte;
|
| 11848 |
|
|
struct {
|
| 11849 |
|
|
byte RXF :1; /* Receive Buffer Full */
|
| 11850 |
|
|
byte OVRIF :1; /* Overrun Interrupt Flag */
|
| 11851 |
|
|
byte TSTAT0 :1; /* Transmitter Status Bit 0 */
|
| 11852 |
|
|
byte TSTAT1 :1; /* Transmitter Status Bit 1 */
|
| 11853 |
|
|
byte RSTAT0 :1; /* Receiver Status Bit 0 */
|
| 11854 |
|
|
byte RSTAT1 :1; /* Receiver Status Bit 1 */
|
| 11855 |
|
|
byte CSCIF :1; /* CAN Status Change Interrupt Flag */
|
| 11856 |
|
|
byte WUPIF :1; /* Wake-up Interrupt Flag */
|
| 11857 |
|
|
} Bits;
|
| 11858 |
|
|
struct {
|
| 11859 |
|
|
byte :1;
|
| 11860 |
|
|
byte :1;
|
| 11861 |
|
|
byte grpTSTAT :2;
|
| 11862 |
|
|
byte grpRSTAT :2;
|
| 11863 |
|
|
byte :1;
|
| 11864 |
|
|
byte :1;
|
| 11865 |
|
|
} MergedBits;
|
| 11866 |
|
|
} CAN2RFLGSTR;
|
| 11867 |
|
|
extern volatile CAN2RFLGSTR _CAN2RFLG @(REG_BASE + 0x000001C4);
|
| 11868 |
|
|
#define CAN2RFLG _CAN2RFLG.Byte
|
| 11869 |
|
|
#define CAN2RFLG_RXF _CAN2RFLG.Bits.RXF
|
| 11870 |
|
|
#define CAN2RFLG_OVRIF _CAN2RFLG.Bits.OVRIF
|
| 11871 |
|
|
#define CAN2RFLG_TSTAT0 _CAN2RFLG.Bits.TSTAT0
|
| 11872 |
|
|
#define CAN2RFLG_TSTAT1 _CAN2RFLG.Bits.TSTAT1
|
| 11873 |
|
|
#define CAN2RFLG_RSTAT0 _CAN2RFLG.Bits.RSTAT0
|
| 11874 |
|
|
#define CAN2RFLG_RSTAT1 _CAN2RFLG.Bits.RSTAT1
|
| 11875 |
|
|
#define CAN2RFLG_CSCIF _CAN2RFLG.Bits.CSCIF
|
| 11876 |
|
|
#define CAN2RFLG_WUPIF _CAN2RFLG.Bits.WUPIF
|
| 11877 |
|
|
#define CAN2RFLG_TSTAT _CAN2RFLG.MergedBits.grpTSTAT
|
| 11878 |
|
|
#define CAN2RFLG_RSTAT _CAN2RFLG.MergedBits.grpRSTAT
|
| 11879 |
|
|
|
| 11880 |
|
|
|
| 11881 |
|
|
/*** CAN2RIER - MSCAN 2 Receiver Interrupt Enable Register; 0x000001C5 ***/
|
| 11882 |
|
|
typedef union {
|
| 11883 |
|
|
byte Byte;
|
| 11884 |
|
|
struct {
|
| 11885 |
|
|
byte RXFIE :1; /* Receiver Full Interrupt Enable */
|
| 11886 |
|
|
byte OVRIE :1; /* Overrun Interrupt Enable */
|
| 11887 |
|
|
byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
|
| 11888 |
|
|
byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
|
| 11889 |
|
|
byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
|
| 11890 |
|
|
byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
|
| 11891 |
|
|
byte CSCIE :1; /* CAN Status Change Interrupt Enable */
|
| 11892 |
|
|
byte WUPIE :1; /* Wake-up Interrupt Enable */
|
| 11893 |
|
|
} Bits;
|
| 11894 |
|
|
struct {
|
| 11895 |
|
|
byte :1;
|
| 11896 |
|
|
byte :1;
|
| 11897 |
|
|
byte grpTSTATE :2;
|
| 11898 |
|
|
byte grpRSTATE :2;
|
| 11899 |
|
|
byte :1;
|
| 11900 |
|
|
byte :1;
|
| 11901 |
|
|
} MergedBits;
|
| 11902 |
|
|
} CAN2RIERSTR;
|
| 11903 |
|
|
extern volatile CAN2RIERSTR _CAN2RIER @(REG_BASE + 0x000001C5);
|
| 11904 |
|
|
#define CAN2RIER _CAN2RIER.Byte
|
| 11905 |
|
|
#define CAN2RIER_RXFIE _CAN2RIER.Bits.RXFIE
|
| 11906 |
|
|
#define CAN2RIER_OVRIE _CAN2RIER.Bits.OVRIE
|
| 11907 |
|
|
#define CAN2RIER_TSTATE0 _CAN2RIER.Bits.TSTATE0
|
| 11908 |
|
|
#define CAN2RIER_TSTATE1 _CAN2RIER.Bits.TSTATE1
|
| 11909 |
|
|
#define CAN2RIER_RSTATE0 _CAN2RIER.Bits.RSTATE0
|
| 11910 |
|
|
#define CAN2RIER_RSTATE1 _CAN2RIER.Bits.RSTATE1
|
| 11911 |
|
|
#define CAN2RIER_CSCIE _CAN2RIER.Bits.CSCIE
|
| 11912 |
|
|
#define CAN2RIER_WUPIE _CAN2RIER.Bits.WUPIE
|
| 11913 |
|
|
#define CAN2RIER_TSTATE _CAN2RIER.MergedBits.grpTSTATE
|
| 11914 |
|
|
#define CAN2RIER_RSTATE _CAN2RIER.MergedBits.grpRSTATE
|
| 11915 |
|
|
|
| 11916 |
|
|
|
| 11917 |
|
|
/*** CAN2TFLG - MSCAN 2 Transmitter Flag Register; 0x000001C6 ***/
|
| 11918 |
|
|
typedef union {
|
| 11919 |
|
|
byte Byte;
|
| 11920 |
|
|
struct {
|
| 11921 |
|
|
byte TXE0 :1; /* Transmitter Buffer Empty 0 */
|
| 11922 |
|
|
byte TXE1 :1; /* Transmitter Buffer Empty 1 */
|
| 11923 |
|
|
byte TXE2 :1; /* Transmitter Buffer Empty 2 */
|
| 11924 |
|
|
byte :1;
|
| 11925 |
|
|
byte :1;
|
| 11926 |
|
|
byte :1;
|
| 11927 |
|
|
byte :1;
|
| 11928 |
|
|
byte :1;
|
| 11929 |
|
|
} Bits;
|
| 11930 |
|
|
struct {
|
| 11931 |
|
|
byte grpTXE :3;
|
| 11932 |
|
|
byte :1;
|
| 11933 |
|
|
byte :1;
|
| 11934 |
|
|
byte :1;
|
| 11935 |
|
|
byte :1;
|
| 11936 |
|
|
byte :1;
|
| 11937 |
|
|
} MergedBits;
|
| 11938 |
|
|
} CAN2TFLGSTR;
|
| 11939 |
|
|
extern volatile CAN2TFLGSTR _CAN2TFLG @(REG_BASE + 0x000001C6);
|
| 11940 |
|
|
#define CAN2TFLG _CAN2TFLG.Byte
|
| 11941 |
|
|
#define CAN2TFLG_TXE0 _CAN2TFLG.Bits.TXE0
|
| 11942 |
|
|
#define CAN2TFLG_TXE1 _CAN2TFLG.Bits.TXE1
|
| 11943 |
|
|
#define CAN2TFLG_TXE2 _CAN2TFLG.Bits.TXE2
|
| 11944 |
|
|
#define CAN2TFLG_TXE _CAN2TFLG.MergedBits.grpTXE
|
| 11945 |
|
|
|
| 11946 |
|
|
|
| 11947 |
|
|
/*** CAN2TIER - MSCAN 2 Transmitter Interrupt Enable Register; 0x000001C7 ***/
|
| 11948 |
|
|
typedef union {
|
| 11949 |
|
|
byte Byte;
|
| 11950 |
|
|
struct {
|
| 11951 |
|
|
byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
|
| 11952 |
|
|
byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
|
| 11953 |
|
|
byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
|
| 11954 |
|
|
byte :1;
|
| 11955 |
|
|
byte :1;
|
| 11956 |
|
|
byte :1;
|
| 11957 |
|
|
byte :1;
|
| 11958 |
|
|
byte :1;
|
| 11959 |
|
|
} Bits;
|
| 11960 |
|
|
struct {
|
| 11961 |
|
|
byte grpTXEIE :3;
|
| 11962 |
|
|
byte :1;
|
| 11963 |
|
|
byte :1;
|
| 11964 |
|
|
byte :1;
|
| 11965 |
|
|
byte :1;
|
| 11966 |
|
|
byte :1;
|
| 11967 |
|
|
} MergedBits;
|
| 11968 |
|
|
} CAN2TIERSTR;
|
| 11969 |
|
|
extern volatile CAN2TIERSTR _CAN2TIER @(REG_BASE + 0x000001C7);
|
| 11970 |
|
|
#define CAN2TIER _CAN2TIER.Byte
|
| 11971 |
|
|
#define CAN2TIER_TXEIE0 _CAN2TIER.Bits.TXEIE0
|
| 11972 |
|
|
#define CAN2TIER_TXEIE1 _CAN2TIER.Bits.TXEIE1
|
| 11973 |
|
|
#define CAN2TIER_TXEIE2 _CAN2TIER.Bits.TXEIE2
|
| 11974 |
|
|
#define CAN2TIER_TXEIE _CAN2TIER.MergedBits.grpTXEIE
|
| 11975 |
|
|
|
| 11976 |
|
|
|
| 11977 |
|
|
/*** CAN2TARQ - MSCAN 2 Transmitter Message Abort Request; 0x000001C8 ***/
|
| 11978 |
|
|
typedef union {
|
| 11979 |
|
|
byte Byte;
|
| 11980 |
|
|
struct {
|
| 11981 |
|
|
byte ABTRQ0 :1; /* Abort Request 0 */
|
| 11982 |
|
|
byte ABTRQ1 :1; /* Abort Request 1 */
|
| 11983 |
|
|
byte ABTRQ2 :1; /* Abort Request 2 */
|
| 11984 |
|
|
byte :1;
|
| 11985 |
|
|
byte :1;
|
| 11986 |
|
|
byte :1;
|
| 11987 |
|
|
byte :1;
|
| 11988 |
|
|
byte :1;
|
| 11989 |
|
|
} Bits;
|
| 11990 |
|
|
struct {
|
| 11991 |
|
|
byte grpABTRQ :3;
|
| 11992 |
|
|
byte :1;
|
| 11993 |
|
|
byte :1;
|
| 11994 |
|
|
byte :1;
|
| 11995 |
|
|
byte :1;
|
| 11996 |
|
|
byte :1;
|
| 11997 |
|
|
} MergedBits;
|
| 11998 |
|
|
} CAN2TARQSTR;
|
| 11999 |
|
|
extern volatile CAN2TARQSTR _CAN2TARQ @(REG_BASE + 0x000001C8);
|
| 12000 |
|
|
#define CAN2TARQ _CAN2TARQ.Byte
|
| 12001 |
|
|
#define CAN2TARQ_ABTRQ0 _CAN2TARQ.Bits.ABTRQ0
|
| 12002 |
|
|
#define CAN2TARQ_ABTRQ1 _CAN2TARQ.Bits.ABTRQ1
|
| 12003 |
|
|
#define CAN2TARQ_ABTRQ2 _CAN2TARQ.Bits.ABTRQ2
|
| 12004 |
|
|
#define CAN2TARQ_ABTRQ _CAN2TARQ.MergedBits.grpABTRQ
|
| 12005 |
|
|
|
| 12006 |
|
|
|
| 12007 |
|
|
/*** CAN2TAAK - MSCAN 2 Transmitter Message Abort Control; 0x000001C9 ***/
|
| 12008 |
|
|
typedef union {
|
| 12009 |
|
|
byte Byte;
|
| 12010 |
|
|
struct {
|
| 12011 |
|
|
byte ABTAK0 :1; /* Abort Acknowledge 0 */
|
| 12012 |
|
|
byte ABTAK1 :1; /* Abort Acknowledge 1 */
|
| 12013 |
|
|
byte ABTAK2 :1; /* Abort Acknowledge 2 */
|
| 12014 |
|
|
byte :1;
|
| 12015 |
|
|
byte :1;
|
| 12016 |
|
|
byte :1;
|
| 12017 |
|
|
byte :1;
|
| 12018 |
|
|
byte :1;
|
| 12019 |
|
|
} Bits;
|
| 12020 |
|
|
struct {
|
| 12021 |
|
|
byte grpABTAK :3;
|
| 12022 |
|
|
byte :1;
|
| 12023 |
|
|
byte :1;
|
| 12024 |
|
|
byte :1;
|
| 12025 |
|
|
byte :1;
|
| 12026 |
|
|
byte :1;
|
| 12027 |
|
|
} MergedBits;
|
| 12028 |
|
|
} CAN2TAAKSTR;
|
| 12029 |
|
|
extern volatile CAN2TAAKSTR _CAN2TAAK @(REG_BASE + 0x000001C9);
|
| 12030 |
|
|
#define CAN2TAAK _CAN2TAAK.Byte
|
| 12031 |
|
|
#define CAN2TAAK_ABTAK0 _CAN2TAAK.Bits.ABTAK0
|
| 12032 |
|
|
#define CAN2TAAK_ABTAK1 _CAN2TAAK.Bits.ABTAK1
|
| 12033 |
|
|
#define CAN2TAAK_ABTAK2 _CAN2TAAK.Bits.ABTAK2
|
| 12034 |
|
|
#define CAN2TAAK_ABTAK _CAN2TAAK.MergedBits.grpABTAK
|
| 12035 |
|
|
|
| 12036 |
|
|
|
| 12037 |
|
|
/*** CAN2TBSEL - MSCAN 2 Transmit Buffer Selection; 0x000001CA ***/
|
| 12038 |
|
|
typedef union {
|
| 12039 |
|
|
byte Byte;
|
| 12040 |
|
|
struct {
|
| 12041 |
|
|
byte TX0 :1; /* Transmit Buffer Select 0 */
|
| 12042 |
|
|
byte TX1 :1; /* Transmit Buffer Select 1 */
|
| 12043 |
|
|
byte TX2 :1; /* Transmit Buffer Select 2 */
|
| 12044 |
|
|
byte :1;
|
| 12045 |
|
|
byte :1;
|
| 12046 |
|
|
byte :1;
|
| 12047 |
|
|
byte :1;
|
| 12048 |
|
|
byte :1;
|
| 12049 |
|
|
} Bits;
|
| 12050 |
|
|
struct {
|
| 12051 |
|
|
byte grpTX :3;
|
| 12052 |
|
|
byte :1;
|
| 12053 |
|
|
byte :1;
|
| 12054 |
|
|
byte :1;
|
| 12055 |
|
|
byte :1;
|
| 12056 |
|
|
byte :1;
|
| 12057 |
|
|
} MergedBits;
|
| 12058 |
|
|
} CAN2TBSELSTR;
|
| 12059 |
|
|
extern volatile CAN2TBSELSTR _CAN2TBSEL @(REG_BASE + 0x000001CA);
|
| 12060 |
|
|
#define CAN2TBSEL _CAN2TBSEL.Byte
|
| 12061 |
|
|
#define CAN2TBSEL_TX0 _CAN2TBSEL.Bits.TX0
|
| 12062 |
|
|
#define CAN2TBSEL_TX1 _CAN2TBSEL.Bits.TX1
|
| 12063 |
|
|
#define CAN2TBSEL_TX2 _CAN2TBSEL.Bits.TX2
|
| 12064 |
|
|
#define CAN2TBSEL_TX _CAN2TBSEL.MergedBits.grpTX
|
| 12065 |
|
|
|
| 12066 |
|
|
|
| 12067 |
|
|
/*** CAN2IDAC - MSCAN 2 Identifier Acceptance Control Register; 0x000001CB ***/
|
| 12068 |
|
|
typedef union {
|
| 12069 |
|
|
byte Byte;
|
| 12070 |
|
|
struct {
|
| 12071 |
|
|
byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
|
| 12072 |
|
|
byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
|
| 12073 |
|
|
byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
|
| 12074 |
|
|
byte :1;
|
| 12075 |
|
|
byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
|
| 12076 |
|
|
byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
|
| 12077 |
|
|
byte :1;
|
| 12078 |
|
|
byte :1;
|
| 12079 |
|
|
} Bits;
|
| 12080 |
|
|
struct {
|
| 12081 |
|
|
byte grpIDHIT :3;
|
| 12082 |
|
|
byte :1;
|
| 12083 |
|
|
byte grpIDAM :2;
|
| 12084 |
|
|
byte :1;
|
| 12085 |
|
|
byte :1;
|
| 12086 |
|
|
} MergedBits;
|
| 12087 |
|
|
} CAN2IDACSTR;
|
| 12088 |
|
|
extern volatile CAN2IDACSTR _CAN2IDAC @(REG_BASE + 0x000001CB);
|
| 12089 |
|
|
#define CAN2IDAC _CAN2IDAC.Byte
|
| 12090 |
|
|
#define CAN2IDAC_IDHIT0 _CAN2IDAC.Bits.IDHIT0
|
| 12091 |
|
|
#define CAN2IDAC_IDHIT1 _CAN2IDAC.Bits.IDHIT1
|
| 12092 |
|
|
#define CAN2IDAC_IDHIT2 _CAN2IDAC.Bits.IDHIT2
|
| 12093 |
|
|
#define CAN2IDAC_IDAM0 _CAN2IDAC.Bits.IDAM0
|
| 12094 |
|
|
#define CAN2IDAC_IDAM1 _CAN2IDAC.Bits.IDAM1
|
| 12095 |
|
|
#define CAN2IDAC_IDHIT _CAN2IDAC.MergedBits.grpIDHIT
|
| 12096 |
|
|
#define CAN2IDAC_IDAM _CAN2IDAC.MergedBits.grpIDAM
|
| 12097 |
|
|
|
| 12098 |
|
|
|
| 12099 |
|
|
/*** CAN2RXERR - MSCAN 2 Receive Error Counter Register; 0x000001CE ***/
|
| 12100 |
|
|
typedef union {
|
| 12101 |
|
|
byte Byte;
|
| 12102 |
|
|
struct {
|
| 12103 |
|
|
byte RXERR0 :1; /* Bit 0 */
|
| 12104 |
|
|
byte RXERR1 :1; /* Bit 1 */
|
| 12105 |
|
|
byte RXERR2 :1; /* Bit 2 */
|
| 12106 |
|
|
byte RXERR3 :1; /* Bit 3 */
|
| 12107 |
|
|
byte RXERR4 :1; /* Bit 4 */
|
| 12108 |
|
|
byte RXERR5 :1; /* Bit 5 */
|
| 12109 |
|
|
byte RXERR6 :1; /* Bit 6 */
|
| 12110 |
|
|
byte RXERR7 :1; /* Bit 7 */
|
| 12111 |
|
|
} Bits;
|
| 12112 |
|
|
struct {
|
| 12113 |
|
|
byte grpRXERR :8;
|
| 12114 |
|
|
} MergedBits;
|
| 12115 |
|
|
} CAN2RXERRSTR;
|
| 12116 |
|
|
extern volatile CAN2RXERRSTR _CAN2RXERR @(REG_BASE + 0x000001CE);
|
| 12117 |
|
|
#define CAN2RXERR _CAN2RXERR.Byte
|
| 12118 |
|
|
#define CAN2RXERR_RXERR0 _CAN2RXERR.Bits.RXERR0
|
| 12119 |
|
|
#define CAN2RXERR_RXERR1 _CAN2RXERR.Bits.RXERR1
|
| 12120 |
|
|
#define CAN2RXERR_RXERR2 _CAN2RXERR.Bits.RXERR2
|
| 12121 |
|
|
#define CAN2RXERR_RXERR3 _CAN2RXERR.Bits.RXERR3
|
| 12122 |
|
|
#define CAN2RXERR_RXERR4 _CAN2RXERR.Bits.RXERR4
|
| 12123 |
|
|
#define CAN2RXERR_RXERR5 _CAN2RXERR.Bits.RXERR5
|
| 12124 |
|
|
#define CAN2RXERR_RXERR6 _CAN2RXERR.Bits.RXERR6
|
| 12125 |
|
|
#define CAN2RXERR_RXERR7 _CAN2RXERR.Bits.RXERR7
|
| 12126 |
|
|
#define CAN2RXERR_RXERR _CAN2RXERR.MergedBits.grpRXERR
|
| 12127 |
|
|
|
| 12128 |
|
|
|
| 12129 |
|
|
/*** CAN2TXERR - MSCAN 2 Transmit Error Counter Register; 0x000001CF ***/
|
| 12130 |
|
|
typedef union {
|
| 12131 |
|
|
byte Byte;
|
| 12132 |
|
|
struct {
|
| 12133 |
|
|
byte TXERR0 :1; /* Bit 0 */
|
| 12134 |
|
|
byte TXERR1 :1; /* Bit 1 */
|
| 12135 |
|
|
byte TXERR2 :1; /* Bit 2 */
|
| 12136 |
|
|
byte TXERR3 :1; /* Bit 3 */
|
| 12137 |
|
|
byte TXERR4 :1; /* Bit 4 */
|
| 12138 |
|
|
byte TXERR5 :1; /* Bit 5 */
|
| 12139 |
|
|
byte TXERR6 :1; /* Bit 6 */
|
| 12140 |
|
|
byte TXERR7 :1; /* Bit 7 */
|
| 12141 |
|
|
} Bits;
|
| 12142 |
|
|
struct {
|
| 12143 |
|
|
byte grpTXERR :8;
|
| 12144 |
|
|
} MergedBits;
|
| 12145 |
|
|
} CAN2TXERRSTR;
|
| 12146 |
|
|
extern volatile CAN2TXERRSTR _CAN2TXERR @(REG_BASE + 0x000001CF);
|
| 12147 |
|
|
#define CAN2TXERR _CAN2TXERR.Byte
|
| 12148 |
|
|
#define CAN2TXERR_TXERR0 _CAN2TXERR.Bits.TXERR0
|
| 12149 |
|
|
#define CAN2TXERR_TXERR1 _CAN2TXERR.Bits.TXERR1
|
| 12150 |
|
|
#define CAN2TXERR_TXERR2 _CAN2TXERR.Bits.TXERR2
|
| 12151 |
|
|
#define CAN2TXERR_TXERR3 _CAN2TXERR.Bits.TXERR3
|
| 12152 |
|
|
#define CAN2TXERR_TXERR4 _CAN2TXERR.Bits.TXERR4
|
| 12153 |
|
|
#define CAN2TXERR_TXERR5 _CAN2TXERR.Bits.TXERR5
|
| 12154 |
|
|
#define CAN2TXERR_TXERR6 _CAN2TXERR.Bits.TXERR6
|
| 12155 |
|
|
#define CAN2TXERR_TXERR7 _CAN2TXERR.Bits.TXERR7
|
| 12156 |
|
|
#define CAN2TXERR_TXERR _CAN2TXERR.MergedBits.grpTXERR
|
| 12157 |
|
|
|
| 12158 |
|
|
|
| 12159 |
|
|
/*** CAN2IDAR0 - MSCAN 2 Identifier Acceptance Register 0; 0x000001D0 ***/
|
| 12160 |
|
|
typedef union {
|
| 12161 |
|
|
byte Byte;
|
| 12162 |
|
|
struct {
|
| 12163 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 12164 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 12165 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 12166 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 12167 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 12168 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 12169 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 12170 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 12171 |
|
|
} Bits;
|
| 12172 |
|
|
struct {
|
| 12173 |
|
|
byte grpAC :8;
|
| 12174 |
|
|
} MergedBits;
|
| 12175 |
|
|
} CAN2IDAR0STR;
|
| 12176 |
|
|
extern volatile CAN2IDAR0STR _CAN2IDAR0 @(REG_BASE + 0x000001D0);
|
| 12177 |
|
|
#define CAN2IDAR0 _CAN2IDAR0.Byte
|
| 12178 |
|
|
#define CAN2IDAR0_AC0 _CAN2IDAR0.Bits.AC0
|
| 12179 |
|
|
#define CAN2IDAR0_AC1 _CAN2IDAR0.Bits.AC1
|
| 12180 |
|
|
#define CAN2IDAR0_AC2 _CAN2IDAR0.Bits.AC2
|
| 12181 |
|
|
#define CAN2IDAR0_AC3 _CAN2IDAR0.Bits.AC3
|
| 12182 |
|
|
#define CAN2IDAR0_AC4 _CAN2IDAR0.Bits.AC4
|
| 12183 |
|
|
#define CAN2IDAR0_AC5 _CAN2IDAR0.Bits.AC5
|
| 12184 |
|
|
#define CAN2IDAR0_AC6 _CAN2IDAR0.Bits.AC6
|
| 12185 |
|
|
#define CAN2IDAR0_AC7 _CAN2IDAR0.Bits.AC7
|
| 12186 |
|
|
#define CAN2IDAR0_AC _CAN2IDAR0.MergedBits.grpAC
|
| 12187 |
|
|
|
| 12188 |
|
|
|
| 12189 |
|
|
/*** CAN2IDAR1 - MSCAN 2 Identifier Acceptance Register 1; 0x000001D1 ***/
|
| 12190 |
|
|
typedef union {
|
| 12191 |
|
|
byte Byte;
|
| 12192 |
|
|
struct {
|
| 12193 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 12194 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 12195 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 12196 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 12197 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 12198 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 12199 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 12200 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 12201 |
|
|
} Bits;
|
| 12202 |
|
|
struct {
|
| 12203 |
|
|
byte grpAC :8;
|
| 12204 |
|
|
} MergedBits;
|
| 12205 |
|
|
} CAN2IDAR1STR;
|
| 12206 |
|
|
extern volatile CAN2IDAR1STR _CAN2IDAR1 @(REG_BASE + 0x000001D1);
|
| 12207 |
|
|
#define CAN2IDAR1 _CAN2IDAR1.Byte
|
| 12208 |
|
|
#define CAN2IDAR1_AC0 _CAN2IDAR1.Bits.AC0
|
| 12209 |
|
|
#define CAN2IDAR1_AC1 _CAN2IDAR1.Bits.AC1
|
| 12210 |
|
|
#define CAN2IDAR1_AC2 _CAN2IDAR1.Bits.AC2
|
| 12211 |
|
|
#define CAN2IDAR1_AC3 _CAN2IDAR1.Bits.AC3
|
| 12212 |
|
|
#define CAN2IDAR1_AC4 _CAN2IDAR1.Bits.AC4
|
| 12213 |
|
|
#define CAN2IDAR1_AC5 _CAN2IDAR1.Bits.AC5
|
| 12214 |
|
|
#define CAN2IDAR1_AC6 _CAN2IDAR1.Bits.AC6
|
| 12215 |
|
|
#define CAN2IDAR1_AC7 _CAN2IDAR1.Bits.AC7
|
| 12216 |
|
|
#define CAN2IDAR1_AC _CAN2IDAR1.MergedBits.grpAC
|
| 12217 |
|
|
|
| 12218 |
|
|
|
| 12219 |
|
|
/*** CAN2IDAR2 - MSCAN 2 Identifier Acceptance Register 2; 0x000001D2 ***/
|
| 12220 |
|
|
typedef union {
|
| 12221 |
|
|
byte Byte;
|
| 12222 |
|
|
struct {
|
| 12223 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 12224 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 12225 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 12226 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 12227 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 12228 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 12229 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 12230 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 12231 |
|
|
} Bits;
|
| 12232 |
|
|
struct {
|
| 12233 |
|
|
byte grpAC :8;
|
| 12234 |
|
|
} MergedBits;
|
| 12235 |
|
|
} CAN2IDAR2STR;
|
| 12236 |
|
|
extern volatile CAN2IDAR2STR _CAN2IDAR2 @(REG_BASE + 0x000001D2);
|
| 12237 |
|
|
#define CAN2IDAR2 _CAN2IDAR2.Byte
|
| 12238 |
|
|
#define CAN2IDAR2_AC0 _CAN2IDAR2.Bits.AC0
|
| 12239 |
|
|
#define CAN2IDAR2_AC1 _CAN2IDAR2.Bits.AC1
|
| 12240 |
|
|
#define CAN2IDAR2_AC2 _CAN2IDAR2.Bits.AC2
|
| 12241 |
|
|
#define CAN2IDAR2_AC3 _CAN2IDAR2.Bits.AC3
|
| 12242 |
|
|
#define CAN2IDAR2_AC4 _CAN2IDAR2.Bits.AC4
|
| 12243 |
|
|
#define CAN2IDAR2_AC5 _CAN2IDAR2.Bits.AC5
|
| 12244 |
|
|
#define CAN2IDAR2_AC6 _CAN2IDAR2.Bits.AC6
|
| 12245 |
|
|
#define CAN2IDAR2_AC7 _CAN2IDAR2.Bits.AC7
|
| 12246 |
|
|
#define CAN2IDAR2_AC _CAN2IDAR2.MergedBits.grpAC
|
| 12247 |
|
|
|
| 12248 |
|
|
|
| 12249 |
|
|
/*** CAN2IDAR3 - MSCAN 2 Identifier Acceptance Register 3; 0x000001D3 ***/
|
| 12250 |
|
|
typedef union {
|
| 12251 |
|
|
byte Byte;
|
| 12252 |
|
|
struct {
|
| 12253 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 12254 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 12255 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 12256 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 12257 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 12258 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 12259 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 12260 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 12261 |
|
|
} Bits;
|
| 12262 |
|
|
struct {
|
| 12263 |
|
|
byte grpAC :8;
|
| 12264 |
|
|
} MergedBits;
|
| 12265 |
|
|
} CAN2IDAR3STR;
|
| 12266 |
|
|
extern volatile CAN2IDAR3STR _CAN2IDAR3 @(REG_BASE + 0x000001D3);
|
| 12267 |
|
|
#define CAN2IDAR3 _CAN2IDAR3.Byte
|
| 12268 |
|
|
#define CAN2IDAR3_AC0 _CAN2IDAR3.Bits.AC0
|
| 12269 |
|
|
#define CAN2IDAR3_AC1 _CAN2IDAR3.Bits.AC1
|
| 12270 |
|
|
#define CAN2IDAR3_AC2 _CAN2IDAR3.Bits.AC2
|
| 12271 |
|
|
#define CAN2IDAR3_AC3 _CAN2IDAR3.Bits.AC3
|
| 12272 |
|
|
#define CAN2IDAR3_AC4 _CAN2IDAR3.Bits.AC4
|
| 12273 |
|
|
#define CAN2IDAR3_AC5 _CAN2IDAR3.Bits.AC5
|
| 12274 |
|
|
#define CAN2IDAR3_AC6 _CAN2IDAR3.Bits.AC6
|
| 12275 |
|
|
#define CAN2IDAR3_AC7 _CAN2IDAR3.Bits.AC7
|
| 12276 |
|
|
#define CAN2IDAR3_AC _CAN2IDAR3.MergedBits.grpAC
|
| 12277 |
|
|
|
| 12278 |
|
|
|
| 12279 |
|
|
/*** CAN2IDMR0 - MSCAN 2 Identifier Mask Register 0; 0x000001D4 ***/
|
| 12280 |
|
|
typedef union {
|
| 12281 |
|
|
byte Byte;
|
| 12282 |
|
|
struct {
|
| 12283 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 12284 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 12285 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 12286 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 12287 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 12288 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 12289 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 12290 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 12291 |
|
|
} Bits;
|
| 12292 |
|
|
struct {
|
| 12293 |
|
|
byte grpAM :8;
|
| 12294 |
|
|
} MergedBits;
|
| 12295 |
|
|
} CAN2IDMR0STR;
|
| 12296 |
|
|
extern volatile CAN2IDMR0STR _CAN2IDMR0 @(REG_BASE + 0x000001D4);
|
| 12297 |
|
|
#define CAN2IDMR0 _CAN2IDMR0.Byte
|
| 12298 |
|
|
#define CAN2IDMR0_AM0 _CAN2IDMR0.Bits.AM0
|
| 12299 |
|
|
#define CAN2IDMR0_AM1 _CAN2IDMR0.Bits.AM1
|
| 12300 |
|
|
#define CAN2IDMR0_AM2 _CAN2IDMR0.Bits.AM2
|
| 12301 |
|
|
#define CAN2IDMR0_AM3 _CAN2IDMR0.Bits.AM3
|
| 12302 |
|
|
#define CAN2IDMR0_AM4 _CAN2IDMR0.Bits.AM4
|
| 12303 |
|
|
#define CAN2IDMR0_AM5 _CAN2IDMR0.Bits.AM5
|
| 12304 |
|
|
#define CAN2IDMR0_AM6 _CAN2IDMR0.Bits.AM6
|
| 12305 |
|
|
#define CAN2IDMR0_AM7 _CAN2IDMR0.Bits.AM7
|
| 12306 |
|
|
#define CAN2IDMR0_AM _CAN2IDMR0.MergedBits.grpAM
|
| 12307 |
|
|
|
| 12308 |
|
|
|
| 12309 |
|
|
/*** CAN2IDMR1 - MSCAN 2 Identifier Mask Register 1; 0x000001D5 ***/
|
| 12310 |
|
|
typedef union {
|
| 12311 |
|
|
byte Byte;
|
| 12312 |
|
|
struct {
|
| 12313 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 12314 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 12315 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 12316 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 12317 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 12318 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 12319 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 12320 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 12321 |
|
|
} Bits;
|
| 12322 |
|
|
struct {
|
| 12323 |
|
|
byte grpAM :8;
|
| 12324 |
|
|
} MergedBits;
|
| 12325 |
|
|
} CAN2IDMR1STR;
|
| 12326 |
|
|
extern volatile CAN2IDMR1STR _CAN2IDMR1 @(REG_BASE + 0x000001D5);
|
| 12327 |
|
|
#define CAN2IDMR1 _CAN2IDMR1.Byte
|
| 12328 |
|
|
#define CAN2IDMR1_AM0 _CAN2IDMR1.Bits.AM0
|
| 12329 |
|
|
#define CAN2IDMR1_AM1 _CAN2IDMR1.Bits.AM1
|
| 12330 |
|
|
#define CAN2IDMR1_AM2 _CAN2IDMR1.Bits.AM2
|
| 12331 |
|
|
#define CAN2IDMR1_AM3 _CAN2IDMR1.Bits.AM3
|
| 12332 |
|
|
#define CAN2IDMR1_AM4 _CAN2IDMR1.Bits.AM4
|
| 12333 |
|
|
#define CAN2IDMR1_AM5 _CAN2IDMR1.Bits.AM5
|
| 12334 |
|
|
#define CAN2IDMR1_AM6 _CAN2IDMR1.Bits.AM6
|
| 12335 |
|
|
#define CAN2IDMR1_AM7 _CAN2IDMR1.Bits.AM7
|
| 12336 |
|
|
#define CAN2IDMR1_AM _CAN2IDMR1.MergedBits.grpAM
|
| 12337 |
|
|
|
| 12338 |
|
|
|
| 12339 |
|
|
/*** CAN2IDMR2 - MSCAN 2 Identifier Mask Register 2; 0x000001D6 ***/
|
| 12340 |
|
|
typedef union {
|
| 12341 |
|
|
byte Byte;
|
| 12342 |
|
|
struct {
|
| 12343 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 12344 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 12345 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 12346 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 12347 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 12348 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 12349 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 12350 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 12351 |
|
|
} Bits;
|
| 12352 |
|
|
struct {
|
| 12353 |
|
|
byte grpAM :8;
|
| 12354 |
|
|
} MergedBits;
|
| 12355 |
|
|
} CAN2IDMR2STR;
|
| 12356 |
|
|
extern volatile CAN2IDMR2STR _CAN2IDMR2 @(REG_BASE + 0x000001D6);
|
| 12357 |
|
|
#define CAN2IDMR2 _CAN2IDMR2.Byte
|
| 12358 |
|
|
#define CAN2IDMR2_AM0 _CAN2IDMR2.Bits.AM0
|
| 12359 |
|
|
#define CAN2IDMR2_AM1 _CAN2IDMR2.Bits.AM1
|
| 12360 |
|
|
#define CAN2IDMR2_AM2 _CAN2IDMR2.Bits.AM2
|
| 12361 |
|
|
#define CAN2IDMR2_AM3 _CAN2IDMR2.Bits.AM3
|
| 12362 |
|
|
#define CAN2IDMR2_AM4 _CAN2IDMR2.Bits.AM4
|
| 12363 |
|
|
#define CAN2IDMR2_AM5 _CAN2IDMR2.Bits.AM5
|
| 12364 |
|
|
#define CAN2IDMR2_AM6 _CAN2IDMR2.Bits.AM6
|
| 12365 |
|
|
#define CAN2IDMR2_AM7 _CAN2IDMR2.Bits.AM7
|
| 12366 |
|
|
#define CAN2IDMR2_AM _CAN2IDMR2.MergedBits.grpAM
|
| 12367 |
|
|
|
| 12368 |
|
|
|
| 12369 |
|
|
/*** CAN2IDMR3 - MSCAN 2 Identifier Mask Register 3; 0x000001D7 ***/
|
| 12370 |
|
|
typedef union {
|
| 12371 |
|
|
byte Byte;
|
| 12372 |
|
|
struct {
|
| 12373 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 12374 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 12375 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 12376 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 12377 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 12378 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 12379 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 12380 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 12381 |
|
|
} Bits;
|
| 12382 |
|
|
struct {
|
| 12383 |
|
|
byte grpAM :8;
|
| 12384 |
|
|
} MergedBits;
|
| 12385 |
|
|
} CAN2IDMR3STR;
|
| 12386 |
|
|
extern volatile CAN2IDMR3STR _CAN2IDMR3 @(REG_BASE + 0x000001D7);
|
| 12387 |
|
|
#define CAN2IDMR3 _CAN2IDMR3.Byte
|
| 12388 |
|
|
#define CAN2IDMR3_AM0 _CAN2IDMR3.Bits.AM0
|
| 12389 |
|
|
#define CAN2IDMR3_AM1 _CAN2IDMR3.Bits.AM1
|
| 12390 |
|
|
#define CAN2IDMR3_AM2 _CAN2IDMR3.Bits.AM2
|
| 12391 |
|
|
#define CAN2IDMR3_AM3 _CAN2IDMR3.Bits.AM3
|
| 12392 |
|
|
#define CAN2IDMR3_AM4 _CAN2IDMR3.Bits.AM4
|
| 12393 |
|
|
#define CAN2IDMR3_AM5 _CAN2IDMR3.Bits.AM5
|
| 12394 |
|
|
#define CAN2IDMR3_AM6 _CAN2IDMR3.Bits.AM6
|
| 12395 |
|
|
#define CAN2IDMR3_AM7 _CAN2IDMR3.Bits.AM7
|
| 12396 |
|
|
#define CAN2IDMR3_AM _CAN2IDMR3.MergedBits.grpAM
|
| 12397 |
|
|
|
| 12398 |
|
|
|
| 12399 |
|
|
/*** CAN2IDAR4 - MSCAN 2 Identifier Acceptance Register 4; 0x000001D8 ***/
|
| 12400 |
|
|
typedef union {
|
| 12401 |
|
|
byte Byte;
|
| 12402 |
|
|
struct {
|
| 12403 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 12404 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 12405 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 12406 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 12407 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 12408 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 12409 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 12410 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 12411 |
|
|
} Bits;
|
| 12412 |
|
|
struct {
|
| 12413 |
|
|
byte grpAC :8;
|
| 12414 |
|
|
} MergedBits;
|
| 12415 |
|
|
} CAN2IDAR4STR;
|
| 12416 |
|
|
extern volatile CAN2IDAR4STR _CAN2IDAR4 @(REG_BASE + 0x000001D8);
|
| 12417 |
|
|
#define CAN2IDAR4 _CAN2IDAR4.Byte
|
| 12418 |
|
|
#define CAN2IDAR4_AC0 _CAN2IDAR4.Bits.AC0
|
| 12419 |
|
|
#define CAN2IDAR4_AC1 _CAN2IDAR4.Bits.AC1
|
| 12420 |
|
|
#define CAN2IDAR4_AC2 _CAN2IDAR4.Bits.AC2
|
| 12421 |
|
|
#define CAN2IDAR4_AC3 _CAN2IDAR4.Bits.AC3
|
| 12422 |
|
|
#define CAN2IDAR4_AC4 _CAN2IDAR4.Bits.AC4
|
| 12423 |
|
|
#define CAN2IDAR4_AC5 _CAN2IDAR4.Bits.AC5
|
| 12424 |
|
|
#define CAN2IDAR4_AC6 _CAN2IDAR4.Bits.AC6
|
| 12425 |
|
|
#define CAN2IDAR4_AC7 _CAN2IDAR4.Bits.AC7
|
| 12426 |
|
|
#define CAN2IDAR4_AC _CAN2IDAR4.MergedBits.grpAC
|
| 12427 |
|
|
|
| 12428 |
|
|
|
| 12429 |
|
|
/*** CAN2IDAR5 - MSCAN 2 Identifier Acceptance Register 5; 0x000001D9 ***/
|
| 12430 |
|
|
typedef union {
|
| 12431 |
|
|
byte Byte;
|
| 12432 |
|
|
struct {
|
| 12433 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 12434 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 12435 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 12436 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 12437 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 12438 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 12439 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 12440 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 12441 |
|
|
} Bits;
|
| 12442 |
|
|
struct {
|
| 12443 |
|
|
byte grpAC :8;
|
| 12444 |
|
|
} MergedBits;
|
| 12445 |
|
|
} CAN2IDAR5STR;
|
| 12446 |
|
|
extern volatile CAN2IDAR5STR _CAN2IDAR5 @(REG_BASE + 0x000001D9);
|
| 12447 |
|
|
#define CAN2IDAR5 _CAN2IDAR5.Byte
|
| 12448 |
|
|
#define CAN2IDAR5_AC0 _CAN2IDAR5.Bits.AC0
|
| 12449 |
|
|
#define CAN2IDAR5_AC1 _CAN2IDAR5.Bits.AC1
|
| 12450 |
|
|
#define CAN2IDAR5_AC2 _CAN2IDAR5.Bits.AC2
|
| 12451 |
|
|
#define CAN2IDAR5_AC3 _CAN2IDAR5.Bits.AC3
|
| 12452 |
|
|
#define CAN2IDAR5_AC4 _CAN2IDAR5.Bits.AC4
|
| 12453 |
|
|
#define CAN2IDAR5_AC5 _CAN2IDAR5.Bits.AC5
|
| 12454 |
|
|
#define CAN2IDAR5_AC6 _CAN2IDAR5.Bits.AC6
|
| 12455 |
|
|
#define CAN2IDAR5_AC7 _CAN2IDAR5.Bits.AC7
|
| 12456 |
|
|
#define CAN2IDAR5_AC _CAN2IDAR5.MergedBits.grpAC
|
| 12457 |
|
|
|
| 12458 |
|
|
|
| 12459 |
|
|
/*** CAN2IDAR6 - MSCAN 2 Identifier Acceptance Register 6; 0x000001DA ***/
|
| 12460 |
|
|
typedef union {
|
| 12461 |
|
|
byte Byte;
|
| 12462 |
|
|
struct {
|
| 12463 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 12464 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 12465 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 12466 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 12467 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 12468 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 12469 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 12470 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 12471 |
|
|
} Bits;
|
| 12472 |
|
|
struct {
|
| 12473 |
|
|
byte grpAC :8;
|
| 12474 |
|
|
} MergedBits;
|
| 12475 |
|
|
} CAN2IDAR6STR;
|
| 12476 |
|
|
extern volatile CAN2IDAR6STR _CAN2IDAR6 @(REG_BASE + 0x000001DA);
|
| 12477 |
|
|
#define CAN2IDAR6 _CAN2IDAR6.Byte
|
| 12478 |
|
|
#define CAN2IDAR6_AC0 _CAN2IDAR6.Bits.AC0
|
| 12479 |
|
|
#define CAN2IDAR6_AC1 _CAN2IDAR6.Bits.AC1
|
| 12480 |
|
|
#define CAN2IDAR6_AC2 _CAN2IDAR6.Bits.AC2
|
| 12481 |
|
|
#define CAN2IDAR6_AC3 _CAN2IDAR6.Bits.AC3
|
| 12482 |
|
|
#define CAN2IDAR6_AC4 _CAN2IDAR6.Bits.AC4
|
| 12483 |
|
|
#define CAN2IDAR6_AC5 _CAN2IDAR6.Bits.AC5
|
| 12484 |
|
|
#define CAN2IDAR6_AC6 _CAN2IDAR6.Bits.AC6
|
| 12485 |
|
|
#define CAN2IDAR6_AC7 _CAN2IDAR6.Bits.AC7
|
| 12486 |
|
|
#define CAN2IDAR6_AC _CAN2IDAR6.MergedBits.grpAC
|
| 12487 |
|
|
|
| 12488 |
|
|
|
| 12489 |
|
|
/*** CAN2IDAR7 - MSCAN 2 Identifier Acceptance Register 7; 0x000001DB ***/
|
| 12490 |
|
|
typedef union {
|
| 12491 |
|
|
byte Byte;
|
| 12492 |
|
|
struct {
|
| 12493 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 12494 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 12495 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 12496 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 12497 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 12498 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 12499 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 12500 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 12501 |
|
|
} Bits;
|
| 12502 |
|
|
struct {
|
| 12503 |
|
|
byte grpAC :8;
|
| 12504 |
|
|
} MergedBits;
|
| 12505 |
|
|
} CAN2IDAR7STR;
|
| 12506 |
|
|
extern volatile CAN2IDAR7STR _CAN2IDAR7 @(REG_BASE + 0x000001DB);
|
| 12507 |
|
|
#define CAN2IDAR7 _CAN2IDAR7.Byte
|
| 12508 |
|
|
#define CAN2IDAR7_AC0 _CAN2IDAR7.Bits.AC0
|
| 12509 |
|
|
#define CAN2IDAR7_AC1 _CAN2IDAR7.Bits.AC1
|
| 12510 |
|
|
#define CAN2IDAR7_AC2 _CAN2IDAR7.Bits.AC2
|
| 12511 |
|
|
#define CAN2IDAR7_AC3 _CAN2IDAR7.Bits.AC3
|
| 12512 |
|
|
#define CAN2IDAR7_AC4 _CAN2IDAR7.Bits.AC4
|
| 12513 |
|
|
#define CAN2IDAR7_AC5 _CAN2IDAR7.Bits.AC5
|
| 12514 |
|
|
#define CAN2IDAR7_AC6 _CAN2IDAR7.Bits.AC6
|
| 12515 |
|
|
#define CAN2IDAR7_AC7 _CAN2IDAR7.Bits.AC7
|
| 12516 |
|
|
#define CAN2IDAR7_AC _CAN2IDAR7.MergedBits.grpAC
|
| 12517 |
|
|
|
| 12518 |
|
|
|
| 12519 |
|
|
/*** CAN2IDMR4 - MSCAN 2 Identifier Mask Register 4; 0x000001DC ***/
|
| 12520 |
|
|
typedef union {
|
| 12521 |
|
|
byte Byte;
|
| 12522 |
|
|
struct {
|
| 12523 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 12524 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 12525 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 12526 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 12527 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 12528 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 12529 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 12530 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 12531 |
|
|
} Bits;
|
| 12532 |
|
|
struct {
|
| 12533 |
|
|
byte grpAM :8;
|
| 12534 |
|
|
} MergedBits;
|
| 12535 |
|
|
} CAN2IDMR4STR;
|
| 12536 |
|
|
extern volatile CAN2IDMR4STR _CAN2IDMR4 @(REG_BASE + 0x000001DC);
|
| 12537 |
|
|
#define CAN2IDMR4 _CAN2IDMR4.Byte
|
| 12538 |
|
|
#define CAN2IDMR4_AM0 _CAN2IDMR4.Bits.AM0
|
| 12539 |
|
|
#define CAN2IDMR4_AM1 _CAN2IDMR4.Bits.AM1
|
| 12540 |
|
|
#define CAN2IDMR4_AM2 _CAN2IDMR4.Bits.AM2
|
| 12541 |
|
|
#define CAN2IDMR4_AM3 _CAN2IDMR4.Bits.AM3
|
| 12542 |
|
|
#define CAN2IDMR4_AM4 _CAN2IDMR4.Bits.AM4
|
| 12543 |
|
|
#define CAN2IDMR4_AM5 _CAN2IDMR4.Bits.AM5
|
| 12544 |
|
|
#define CAN2IDMR4_AM6 _CAN2IDMR4.Bits.AM6
|
| 12545 |
|
|
#define CAN2IDMR4_AM7 _CAN2IDMR4.Bits.AM7
|
| 12546 |
|
|
#define CAN2IDMR4_AM _CAN2IDMR4.MergedBits.grpAM
|
| 12547 |
|
|
|
| 12548 |
|
|
|
| 12549 |
|
|
/*** CAN2IDMR5 - MSCAN 2 Identifier Mask Register 5; 0x000001DD ***/
|
| 12550 |
|
|
typedef union {
|
| 12551 |
|
|
byte Byte;
|
| 12552 |
|
|
struct {
|
| 12553 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 12554 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 12555 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 12556 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 12557 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 12558 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 12559 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 12560 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 12561 |
|
|
} Bits;
|
| 12562 |
|
|
struct {
|
| 12563 |
|
|
byte grpAM :8;
|
| 12564 |
|
|
} MergedBits;
|
| 12565 |
|
|
} CAN2IDMR5STR;
|
| 12566 |
|
|
extern volatile CAN2IDMR5STR _CAN2IDMR5 @(REG_BASE + 0x000001DD);
|
| 12567 |
|
|
#define CAN2IDMR5 _CAN2IDMR5.Byte
|
| 12568 |
|
|
#define CAN2IDMR5_AM0 _CAN2IDMR5.Bits.AM0
|
| 12569 |
|
|
#define CAN2IDMR5_AM1 _CAN2IDMR5.Bits.AM1
|
| 12570 |
|
|
#define CAN2IDMR5_AM2 _CAN2IDMR5.Bits.AM2
|
| 12571 |
|
|
#define CAN2IDMR5_AM3 _CAN2IDMR5.Bits.AM3
|
| 12572 |
|
|
#define CAN2IDMR5_AM4 _CAN2IDMR5.Bits.AM4
|
| 12573 |
|
|
#define CAN2IDMR5_AM5 _CAN2IDMR5.Bits.AM5
|
| 12574 |
|
|
#define CAN2IDMR5_AM6 _CAN2IDMR5.Bits.AM6
|
| 12575 |
|
|
#define CAN2IDMR5_AM7 _CAN2IDMR5.Bits.AM7
|
| 12576 |
|
|
#define CAN2IDMR5_AM _CAN2IDMR5.MergedBits.grpAM
|
| 12577 |
|
|
|
| 12578 |
|
|
|
| 12579 |
|
|
/*** CAN2IDMR6 - MSCAN 2 Identifier Mask Register 6; 0x000001DE ***/
|
| 12580 |
|
|
typedef union {
|
| 12581 |
|
|
byte Byte;
|
| 12582 |
|
|
struct {
|
| 12583 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 12584 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 12585 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 12586 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 12587 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 12588 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 12589 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 12590 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 12591 |
|
|
} Bits;
|
| 12592 |
|
|
struct {
|
| 12593 |
|
|
byte grpAM :8;
|
| 12594 |
|
|
} MergedBits;
|
| 12595 |
|
|
} CAN2IDMR6STR;
|
| 12596 |
|
|
extern volatile CAN2IDMR6STR _CAN2IDMR6 @(REG_BASE + 0x000001DE);
|
| 12597 |
|
|
#define CAN2IDMR6 _CAN2IDMR6.Byte
|
| 12598 |
|
|
#define CAN2IDMR6_AM0 _CAN2IDMR6.Bits.AM0
|
| 12599 |
|
|
#define CAN2IDMR6_AM1 _CAN2IDMR6.Bits.AM1
|
| 12600 |
|
|
#define CAN2IDMR6_AM2 _CAN2IDMR6.Bits.AM2
|
| 12601 |
|
|
#define CAN2IDMR6_AM3 _CAN2IDMR6.Bits.AM3
|
| 12602 |
|
|
#define CAN2IDMR6_AM4 _CAN2IDMR6.Bits.AM4
|
| 12603 |
|
|
#define CAN2IDMR6_AM5 _CAN2IDMR6.Bits.AM5
|
| 12604 |
|
|
#define CAN2IDMR6_AM6 _CAN2IDMR6.Bits.AM6
|
| 12605 |
|
|
#define CAN2IDMR6_AM7 _CAN2IDMR6.Bits.AM7
|
| 12606 |
|
|
#define CAN2IDMR6_AM _CAN2IDMR6.MergedBits.grpAM
|
| 12607 |
|
|
|
| 12608 |
|
|
|
| 12609 |
|
|
/*** CAN2IDMR7 - MSCAN 2 Identifier Mask Register 7; 0x000001DF ***/
|
| 12610 |
|
|
typedef union {
|
| 12611 |
|
|
byte Byte;
|
| 12612 |
|
|
struct {
|
| 12613 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 12614 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 12615 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 12616 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 12617 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 12618 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 12619 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 12620 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 12621 |
|
|
} Bits;
|
| 12622 |
|
|
struct {
|
| 12623 |
|
|
byte grpAM :8;
|
| 12624 |
|
|
} MergedBits;
|
| 12625 |
|
|
} CAN2IDMR7STR;
|
| 12626 |
|
|
extern volatile CAN2IDMR7STR _CAN2IDMR7 @(REG_BASE + 0x000001DF);
|
| 12627 |
|
|
#define CAN2IDMR7 _CAN2IDMR7.Byte
|
| 12628 |
|
|
#define CAN2IDMR7_AM0 _CAN2IDMR7.Bits.AM0
|
| 12629 |
|
|
#define CAN2IDMR7_AM1 _CAN2IDMR7.Bits.AM1
|
| 12630 |
|
|
#define CAN2IDMR7_AM2 _CAN2IDMR7.Bits.AM2
|
| 12631 |
|
|
#define CAN2IDMR7_AM3 _CAN2IDMR7.Bits.AM3
|
| 12632 |
|
|
#define CAN2IDMR7_AM4 _CAN2IDMR7.Bits.AM4
|
| 12633 |
|
|
#define CAN2IDMR7_AM5 _CAN2IDMR7.Bits.AM5
|
| 12634 |
|
|
#define CAN2IDMR7_AM6 _CAN2IDMR7.Bits.AM6
|
| 12635 |
|
|
#define CAN2IDMR7_AM7 _CAN2IDMR7.Bits.AM7
|
| 12636 |
|
|
#define CAN2IDMR7_AM _CAN2IDMR7.MergedBits.grpAM
|
| 12637 |
|
|
|
| 12638 |
|
|
|
| 12639 |
|
|
/*** CAN2RXIDR0 - MSCAN 2 Receive Identifier Register 0; 0x000001E0 ***/
|
| 12640 |
|
|
typedef union {
|
| 12641 |
|
|
byte Byte;
|
| 12642 |
|
|
struct {
|
| 12643 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 12644 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 12645 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 12646 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 12647 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 12648 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 12649 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 12650 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 12651 |
|
|
} Bits;
|
| 12652 |
|
|
struct {
|
| 12653 |
|
|
byte grpID_21 :8;
|
| 12654 |
|
|
} MergedBits;
|
| 12655 |
|
|
} CAN2RXIDR0STR;
|
| 12656 |
|
|
extern volatile CAN2RXIDR0STR _CAN2RXIDR0 @(REG_BASE + 0x000001E0);
|
| 12657 |
|
|
#define CAN2RXIDR0 _CAN2RXIDR0.Byte
|
| 12658 |
|
|
#define CAN2RXIDR0_ID21 _CAN2RXIDR0.Bits.ID21
|
| 12659 |
|
|
#define CAN2RXIDR0_ID22 _CAN2RXIDR0.Bits.ID22
|
| 12660 |
|
|
#define CAN2RXIDR0_ID23 _CAN2RXIDR0.Bits.ID23
|
| 12661 |
|
|
#define CAN2RXIDR0_ID24 _CAN2RXIDR0.Bits.ID24
|
| 12662 |
|
|
#define CAN2RXIDR0_ID25 _CAN2RXIDR0.Bits.ID25
|
| 12663 |
|
|
#define CAN2RXIDR0_ID26 _CAN2RXIDR0.Bits.ID26
|
| 12664 |
|
|
#define CAN2RXIDR0_ID27 _CAN2RXIDR0.Bits.ID27
|
| 12665 |
|
|
#define CAN2RXIDR0_ID28 _CAN2RXIDR0.Bits.ID28
|
| 12666 |
|
|
#define CAN2RXIDR0_ID_21 _CAN2RXIDR0.MergedBits.grpID_21
|
| 12667 |
|
|
#define CAN2RXIDR0_ID CAN2RXIDR0_ID_21
|
| 12668 |
|
|
|
| 12669 |
|
|
|
| 12670 |
|
|
/*** CAN2RXIDR1 - MSCAN 2 Receive Identifier Register 1; 0x000001E1 ***/
|
| 12671 |
|
|
typedef union {
|
| 12672 |
|
|
byte Byte;
|
| 12673 |
|
|
struct {
|
| 12674 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 12675 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 12676 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 12677 |
|
|
byte IDE :1; /* ID Extended */
|
| 12678 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 12679 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 12680 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 12681 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 12682 |
|
|
} Bits;
|
| 12683 |
|
|
struct {
|
| 12684 |
|
|
byte grpID_15 :3;
|
| 12685 |
|
|
byte :1;
|
| 12686 |
|
|
byte :1;
|
| 12687 |
|
|
byte grpID_18 :3;
|
| 12688 |
|
|
} MergedBits;
|
| 12689 |
|
|
} CAN2RXIDR1STR;
|
| 12690 |
|
|
extern volatile CAN2RXIDR1STR _CAN2RXIDR1 @(REG_BASE + 0x000001E1);
|
| 12691 |
|
|
#define CAN2RXIDR1 _CAN2RXIDR1.Byte
|
| 12692 |
|
|
#define CAN2RXIDR1_ID15 _CAN2RXIDR1.Bits.ID15
|
| 12693 |
|
|
#define CAN2RXIDR1_ID16 _CAN2RXIDR1.Bits.ID16
|
| 12694 |
|
|
#define CAN2RXIDR1_ID17 _CAN2RXIDR1.Bits.ID17
|
| 12695 |
|
|
#define CAN2RXIDR1_IDE _CAN2RXIDR1.Bits.IDE
|
| 12696 |
|
|
#define CAN2RXIDR1_SRR _CAN2RXIDR1.Bits.SRR
|
| 12697 |
|
|
#define CAN2RXIDR1_ID18 _CAN2RXIDR1.Bits.ID18
|
| 12698 |
|
|
#define CAN2RXIDR1_ID19 _CAN2RXIDR1.Bits.ID19
|
| 12699 |
|
|
#define CAN2RXIDR1_ID20 _CAN2RXIDR1.Bits.ID20
|
| 12700 |
|
|
#define CAN2RXIDR1_ID_15 _CAN2RXIDR1.MergedBits.grpID_15
|
| 12701 |
|
|
#define CAN2RXIDR1_ID_18 _CAN2RXIDR1.MergedBits.grpID_18
|
| 12702 |
|
|
#define CAN2RXIDR1_ID CAN2RXIDR1_ID_15
|
| 12703 |
|
|
|
| 12704 |
|
|
|
| 12705 |
|
|
/*** CAN2RXIDR2 - MSCAN 2 Receive Identifier Register 2; 0x000001E2 ***/
|
| 12706 |
|
|
typedef union {
|
| 12707 |
|
|
byte Byte;
|
| 12708 |
|
|
struct {
|
| 12709 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 12710 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 12711 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 12712 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 12713 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 12714 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 12715 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 12716 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 12717 |
|
|
} Bits;
|
| 12718 |
|
|
struct {
|
| 12719 |
|
|
byte grpID_7 :8;
|
| 12720 |
|
|
} MergedBits;
|
| 12721 |
|
|
} CAN2RXIDR2STR;
|
| 12722 |
|
|
extern volatile CAN2RXIDR2STR _CAN2RXIDR2 @(REG_BASE + 0x000001E2);
|
| 12723 |
|
|
#define CAN2RXIDR2 _CAN2RXIDR2.Byte
|
| 12724 |
|
|
#define CAN2RXIDR2_ID7 _CAN2RXIDR2.Bits.ID7
|
| 12725 |
|
|
#define CAN2RXIDR2_ID8 _CAN2RXIDR2.Bits.ID8
|
| 12726 |
|
|
#define CAN2RXIDR2_ID9 _CAN2RXIDR2.Bits.ID9
|
| 12727 |
|
|
#define CAN2RXIDR2_ID10 _CAN2RXIDR2.Bits.ID10
|
| 12728 |
|
|
#define CAN2RXIDR2_ID11 _CAN2RXIDR2.Bits.ID11
|
| 12729 |
|
|
#define CAN2RXIDR2_ID12 _CAN2RXIDR2.Bits.ID12
|
| 12730 |
|
|
#define CAN2RXIDR2_ID13 _CAN2RXIDR2.Bits.ID13
|
| 12731 |
|
|
#define CAN2RXIDR2_ID14 _CAN2RXIDR2.Bits.ID14
|
| 12732 |
|
|
#define CAN2RXIDR2_ID_7 _CAN2RXIDR2.MergedBits.grpID_7
|
| 12733 |
|
|
#define CAN2RXIDR2_ID CAN2RXIDR2_ID_7
|
| 12734 |
|
|
|
| 12735 |
|
|
|
| 12736 |
|
|
/*** CAN2RXIDR3 - MSCAN 2 Receive Identifier Register 3; 0x000001E3 ***/
|
| 12737 |
|
|
typedef union {
|
| 12738 |
|
|
byte Byte;
|
| 12739 |
|
|
struct {
|
| 12740 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 12741 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 12742 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 12743 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 12744 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 12745 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 12746 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 12747 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 12748 |
|
|
} Bits;
|
| 12749 |
|
|
struct {
|
| 12750 |
|
|
byte :1;
|
| 12751 |
|
|
byte grpID :7;
|
| 12752 |
|
|
} MergedBits;
|
| 12753 |
|
|
} CAN2RXIDR3STR;
|
| 12754 |
|
|
extern volatile CAN2RXIDR3STR _CAN2RXIDR3 @(REG_BASE + 0x000001E3);
|
| 12755 |
|
|
#define CAN2RXIDR3 _CAN2RXIDR3.Byte
|
| 12756 |
|
|
#define CAN2RXIDR3_RTR _CAN2RXIDR3.Bits.RTR
|
| 12757 |
|
|
#define CAN2RXIDR3_ID0 _CAN2RXIDR3.Bits.ID0
|
| 12758 |
|
|
#define CAN2RXIDR3_ID1 _CAN2RXIDR3.Bits.ID1
|
| 12759 |
|
|
#define CAN2RXIDR3_ID2 _CAN2RXIDR3.Bits.ID2
|
| 12760 |
|
|
#define CAN2RXIDR3_ID3 _CAN2RXIDR3.Bits.ID3
|
| 12761 |
|
|
#define CAN2RXIDR3_ID4 _CAN2RXIDR3.Bits.ID4
|
| 12762 |
|
|
#define CAN2RXIDR3_ID5 _CAN2RXIDR3.Bits.ID5
|
| 12763 |
|
|
#define CAN2RXIDR3_ID6 _CAN2RXIDR3.Bits.ID6
|
| 12764 |
|
|
#define CAN2RXIDR3_ID _CAN2RXIDR3.MergedBits.grpID
|
| 12765 |
|
|
|
| 12766 |
|
|
|
| 12767 |
|
|
/*** CAN2RXDSR0 - MSCAN 2 Receive Data Segment Register 0; 0x000001E4 ***/
|
| 12768 |
|
|
typedef union {
|
| 12769 |
|
|
byte Byte;
|
| 12770 |
|
|
struct {
|
| 12771 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 12772 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 12773 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 12774 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 12775 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 12776 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 12777 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 12778 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 12779 |
|
|
} Bits;
|
| 12780 |
|
|
struct {
|
| 12781 |
|
|
byte grpDB :8;
|
| 12782 |
|
|
} MergedBits;
|
| 12783 |
|
|
} CAN2RXDSR0STR;
|
| 12784 |
|
|
extern volatile CAN2RXDSR0STR _CAN2RXDSR0 @(REG_BASE + 0x000001E4);
|
| 12785 |
|
|
#define CAN2RXDSR0 _CAN2RXDSR0.Byte
|
| 12786 |
|
|
#define CAN2RXDSR0_DB0 _CAN2RXDSR0.Bits.DB0
|
| 12787 |
|
|
#define CAN2RXDSR0_DB1 _CAN2RXDSR0.Bits.DB1
|
| 12788 |
|
|
#define CAN2RXDSR0_DB2 _CAN2RXDSR0.Bits.DB2
|
| 12789 |
|
|
#define CAN2RXDSR0_DB3 _CAN2RXDSR0.Bits.DB3
|
| 12790 |
|
|
#define CAN2RXDSR0_DB4 _CAN2RXDSR0.Bits.DB4
|
| 12791 |
|
|
#define CAN2RXDSR0_DB5 _CAN2RXDSR0.Bits.DB5
|
| 12792 |
|
|
#define CAN2RXDSR0_DB6 _CAN2RXDSR0.Bits.DB6
|
| 12793 |
|
|
#define CAN2RXDSR0_DB7 _CAN2RXDSR0.Bits.DB7
|
| 12794 |
|
|
#define CAN2RXDSR0_DB _CAN2RXDSR0.MergedBits.grpDB
|
| 12795 |
|
|
|
| 12796 |
|
|
|
| 12797 |
|
|
/*** CAN2RXDSR1 - MSCAN 2 Receive Data Segment Register 1; 0x000001E5 ***/
|
| 12798 |
|
|
typedef union {
|
| 12799 |
|
|
byte Byte;
|
| 12800 |
|
|
struct {
|
| 12801 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 12802 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 12803 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 12804 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 12805 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 12806 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 12807 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 12808 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 12809 |
|
|
} Bits;
|
| 12810 |
|
|
struct {
|
| 12811 |
|
|
byte grpDB :8;
|
| 12812 |
|
|
} MergedBits;
|
| 12813 |
|
|
} CAN2RXDSR1STR;
|
| 12814 |
|
|
extern volatile CAN2RXDSR1STR _CAN2RXDSR1 @(REG_BASE + 0x000001E5);
|
| 12815 |
|
|
#define CAN2RXDSR1 _CAN2RXDSR1.Byte
|
| 12816 |
|
|
#define CAN2RXDSR1_DB0 _CAN2RXDSR1.Bits.DB0
|
| 12817 |
|
|
#define CAN2RXDSR1_DB1 _CAN2RXDSR1.Bits.DB1
|
| 12818 |
|
|
#define CAN2RXDSR1_DB2 _CAN2RXDSR1.Bits.DB2
|
| 12819 |
|
|
#define CAN2RXDSR1_DB3 _CAN2RXDSR1.Bits.DB3
|
| 12820 |
|
|
#define CAN2RXDSR1_DB4 _CAN2RXDSR1.Bits.DB4
|
| 12821 |
|
|
#define CAN2RXDSR1_DB5 _CAN2RXDSR1.Bits.DB5
|
| 12822 |
|
|
#define CAN2RXDSR1_DB6 _CAN2RXDSR1.Bits.DB6
|
| 12823 |
|
|
#define CAN2RXDSR1_DB7 _CAN2RXDSR1.Bits.DB7
|
| 12824 |
|
|
#define CAN2RXDSR1_DB _CAN2RXDSR1.MergedBits.grpDB
|
| 12825 |
|
|
|
| 12826 |
|
|
|
| 12827 |
|
|
/*** CAN2RXDSR2 - MSCAN 2 Receive Data Segment Register 2; 0x000001E6 ***/
|
| 12828 |
|
|
typedef union {
|
| 12829 |
|
|
byte Byte;
|
| 12830 |
|
|
struct {
|
| 12831 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 12832 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 12833 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 12834 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 12835 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 12836 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 12837 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 12838 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 12839 |
|
|
} Bits;
|
| 12840 |
|
|
struct {
|
| 12841 |
|
|
byte grpDB :8;
|
| 12842 |
|
|
} MergedBits;
|
| 12843 |
|
|
} CAN2RXDSR2STR;
|
| 12844 |
|
|
extern volatile CAN2RXDSR2STR _CAN2RXDSR2 @(REG_BASE + 0x000001E6);
|
| 12845 |
|
|
#define CAN2RXDSR2 _CAN2RXDSR2.Byte
|
| 12846 |
|
|
#define CAN2RXDSR2_DB0 _CAN2RXDSR2.Bits.DB0
|
| 12847 |
|
|
#define CAN2RXDSR2_DB1 _CAN2RXDSR2.Bits.DB1
|
| 12848 |
|
|
#define CAN2RXDSR2_DB2 _CAN2RXDSR2.Bits.DB2
|
| 12849 |
|
|
#define CAN2RXDSR2_DB3 _CAN2RXDSR2.Bits.DB3
|
| 12850 |
|
|
#define CAN2RXDSR2_DB4 _CAN2RXDSR2.Bits.DB4
|
| 12851 |
|
|
#define CAN2RXDSR2_DB5 _CAN2RXDSR2.Bits.DB5
|
| 12852 |
|
|
#define CAN2RXDSR2_DB6 _CAN2RXDSR2.Bits.DB6
|
| 12853 |
|
|
#define CAN2RXDSR2_DB7 _CAN2RXDSR2.Bits.DB7
|
| 12854 |
|
|
#define CAN2RXDSR2_DB _CAN2RXDSR2.MergedBits.grpDB
|
| 12855 |
|
|
|
| 12856 |
|
|
|
| 12857 |
|
|
/*** CAN2RXDSR3 - MSCAN 2 Receive Data Segment Register 3; 0x000001E7 ***/
|
| 12858 |
|
|
typedef union {
|
| 12859 |
|
|
byte Byte;
|
| 12860 |
|
|
struct {
|
| 12861 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 12862 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 12863 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 12864 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 12865 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 12866 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 12867 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 12868 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 12869 |
|
|
} Bits;
|
| 12870 |
|
|
struct {
|
| 12871 |
|
|
byte grpDB :8;
|
| 12872 |
|
|
} MergedBits;
|
| 12873 |
|
|
} CAN2RXDSR3STR;
|
| 12874 |
|
|
extern volatile CAN2RXDSR3STR _CAN2RXDSR3 @(REG_BASE + 0x000001E7);
|
| 12875 |
|
|
#define CAN2RXDSR3 _CAN2RXDSR3.Byte
|
| 12876 |
|
|
#define CAN2RXDSR3_DB0 _CAN2RXDSR3.Bits.DB0
|
| 12877 |
|
|
#define CAN2RXDSR3_DB1 _CAN2RXDSR3.Bits.DB1
|
| 12878 |
|
|
#define CAN2RXDSR3_DB2 _CAN2RXDSR3.Bits.DB2
|
| 12879 |
|
|
#define CAN2RXDSR3_DB3 _CAN2RXDSR3.Bits.DB3
|
| 12880 |
|
|
#define CAN2RXDSR3_DB4 _CAN2RXDSR3.Bits.DB4
|
| 12881 |
|
|
#define CAN2RXDSR3_DB5 _CAN2RXDSR3.Bits.DB5
|
| 12882 |
|
|
#define CAN2RXDSR3_DB6 _CAN2RXDSR3.Bits.DB6
|
| 12883 |
|
|
#define CAN2RXDSR3_DB7 _CAN2RXDSR3.Bits.DB7
|
| 12884 |
|
|
#define CAN2RXDSR3_DB _CAN2RXDSR3.MergedBits.grpDB
|
| 12885 |
|
|
|
| 12886 |
|
|
|
| 12887 |
|
|
/*** CAN2RXDSR4 - MSCAN 2 Receive Data Segment Register 4; 0x000001E8 ***/
|
| 12888 |
|
|
typedef union {
|
| 12889 |
|
|
byte Byte;
|
| 12890 |
|
|
struct {
|
| 12891 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 12892 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 12893 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 12894 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 12895 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 12896 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 12897 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 12898 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 12899 |
|
|
} Bits;
|
| 12900 |
|
|
struct {
|
| 12901 |
|
|
byte grpDB :8;
|
| 12902 |
|
|
} MergedBits;
|
| 12903 |
|
|
} CAN2RXDSR4STR;
|
| 12904 |
|
|
extern volatile CAN2RXDSR4STR _CAN2RXDSR4 @(REG_BASE + 0x000001E8);
|
| 12905 |
|
|
#define CAN2RXDSR4 _CAN2RXDSR4.Byte
|
| 12906 |
|
|
#define CAN2RXDSR4_DB0 _CAN2RXDSR4.Bits.DB0
|
| 12907 |
|
|
#define CAN2RXDSR4_DB1 _CAN2RXDSR4.Bits.DB1
|
| 12908 |
|
|
#define CAN2RXDSR4_DB2 _CAN2RXDSR4.Bits.DB2
|
| 12909 |
|
|
#define CAN2RXDSR4_DB3 _CAN2RXDSR4.Bits.DB3
|
| 12910 |
|
|
#define CAN2RXDSR4_DB4 _CAN2RXDSR4.Bits.DB4
|
| 12911 |
|
|
#define CAN2RXDSR4_DB5 _CAN2RXDSR4.Bits.DB5
|
| 12912 |
|
|
#define CAN2RXDSR4_DB6 _CAN2RXDSR4.Bits.DB6
|
| 12913 |
|
|
#define CAN2RXDSR4_DB7 _CAN2RXDSR4.Bits.DB7
|
| 12914 |
|
|
#define CAN2RXDSR4_DB _CAN2RXDSR4.MergedBits.grpDB
|
| 12915 |
|
|
|
| 12916 |
|
|
|
| 12917 |
|
|
/*** CAN2RXDSR5 - MSCAN 2 Receive Data Segment Register 5; 0x000001E9 ***/
|
| 12918 |
|
|
typedef union {
|
| 12919 |
|
|
byte Byte;
|
| 12920 |
|
|
struct {
|
| 12921 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 12922 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 12923 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 12924 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 12925 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 12926 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 12927 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 12928 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 12929 |
|
|
} Bits;
|
| 12930 |
|
|
struct {
|
| 12931 |
|
|
byte grpDB :8;
|
| 12932 |
|
|
} MergedBits;
|
| 12933 |
|
|
} CAN2RXDSR5STR;
|
| 12934 |
|
|
extern volatile CAN2RXDSR5STR _CAN2RXDSR5 @(REG_BASE + 0x000001E9);
|
| 12935 |
|
|
#define CAN2RXDSR5 _CAN2RXDSR5.Byte
|
| 12936 |
|
|
#define CAN2RXDSR5_DB0 _CAN2RXDSR5.Bits.DB0
|
| 12937 |
|
|
#define CAN2RXDSR5_DB1 _CAN2RXDSR5.Bits.DB1
|
| 12938 |
|
|
#define CAN2RXDSR5_DB2 _CAN2RXDSR5.Bits.DB2
|
| 12939 |
|
|
#define CAN2RXDSR5_DB3 _CAN2RXDSR5.Bits.DB3
|
| 12940 |
|
|
#define CAN2RXDSR5_DB4 _CAN2RXDSR5.Bits.DB4
|
| 12941 |
|
|
#define CAN2RXDSR5_DB5 _CAN2RXDSR5.Bits.DB5
|
| 12942 |
|
|
#define CAN2RXDSR5_DB6 _CAN2RXDSR5.Bits.DB6
|
| 12943 |
|
|
#define CAN2RXDSR5_DB7 _CAN2RXDSR5.Bits.DB7
|
| 12944 |
|
|
#define CAN2RXDSR5_DB _CAN2RXDSR5.MergedBits.grpDB
|
| 12945 |
|
|
|
| 12946 |
|
|
|
| 12947 |
|
|
/*** CAN2RXDSR6 - MSCAN 2 Receive Data Segment Register 6; 0x000001EA ***/
|
| 12948 |
|
|
typedef union {
|
| 12949 |
|
|
byte Byte;
|
| 12950 |
|
|
struct {
|
| 12951 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 12952 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 12953 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 12954 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 12955 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 12956 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 12957 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 12958 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 12959 |
|
|
} Bits;
|
| 12960 |
|
|
struct {
|
| 12961 |
|
|
byte grpDB :8;
|
| 12962 |
|
|
} MergedBits;
|
| 12963 |
|
|
} CAN2RXDSR6STR;
|
| 12964 |
|
|
extern volatile CAN2RXDSR6STR _CAN2RXDSR6 @(REG_BASE + 0x000001EA);
|
| 12965 |
|
|
#define CAN2RXDSR6 _CAN2RXDSR6.Byte
|
| 12966 |
|
|
#define CAN2RXDSR6_DB0 _CAN2RXDSR6.Bits.DB0
|
| 12967 |
|
|
#define CAN2RXDSR6_DB1 _CAN2RXDSR6.Bits.DB1
|
| 12968 |
|
|
#define CAN2RXDSR6_DB2 _CAN2RXDSR6.Bits.DB2
|
| 12969 |
|
|
#define CAN2RXDSR6_DB3 _CAN2RXDSR6.Bits.DB3
|
| 12970 |
|
|
#define CAN2RXDSR6_DB4 _CAN2RXDSR6.Bits.DB4
|
| 12971 |
|
|
#define CAN2RXDSR6_DB5 _CAN2RXDSR6.Bits.DB5
|
| 12972 |
|
|
#define CAN2RXDSR6_DB6 _CAN2RXDSR6.Bits.DB6
|
| 12973 |
|
|
#define CAN2RXDSR6_DB7 _CAN2RXDSR6.Bits.DB7
|
| 12974 |
|
|
#define CAN2RXDSR6_DB _CAN2RXDSR6.MergedBits.grpDB
|
| 12975 |
|
|
|
| 12976 |
|
|
|
| 12977 |
|
|
/*** CAN2RXDSR7 - MSCAN 2 Receive Data Segment Register 7; 0x000001EB ***/
|
| 12978 |
|
|
typedef union {
|
| 12979 |
|
|
byte Byte;
|
| 12980 |
|
|
struct {
|
| 12981 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 12982 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 12983 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 12984 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 12985 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 12986 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 12987 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 12988 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 12989 |
|
|
} Bits;
|
| 12990 |
|
|
struct {
|
| 12991 |
|
|
byte grpDB :8;
|
| 12992 |
|
|
} MergedBits;
|
| 12993 |
|
|
} CAN2RXDSR7STR;
|
| 12994 |
|
|
extern volatile CAN2RXDSR7STR _CAN2RXDSR7 @(REG_BASE + 0x000001EB);
|
| 12995 |
|
|
#define CAN2RXDSR7 _CAN2RXDSR7.Byte
|
| 12996 |
|
|
#define CAN2RXDSR7_DB0 _CAN2RXDSR7.Bits.DB0
|
| 12997 |
|
|
#define CAN2RXDSR7_DB1 _CAN2RXDSR7.Bits.DB1
|
| 12998 |
|
|
#define CAN2RXDSR7_DB2 _CAN2RXDSR7.Bits.DB2
|
| 12999 |
|
|
#define CAN2RXDSR7_DB3 _CAN2RXDSR7.Bits.DB3
|
| 13000 |
|
|
#define CAN2RXDSR7_DB4 _CAN2RXDSR7.Bits.DB4
|
| 13001 |
|
|
#define CAN2RXDSR7_DB5 _CAN2RXDSR7.Bits.DB5
|
| 13002 |
|
|
#define CAN2RXDSR7_DB6 _CAN2RXDSR7.Bits.DB6
|
| 13003 |
|
|
#define CAN2RXDSR7_DB7 _CAN2RXDSR7.Bits.DB7
|
| 13004 |
|
|
#define CAN2RXDSR7_DB _CAN2RXDSR7.MergedBits.grpDB
|
| 13005 |
|
|
|
| 13006 |
|
|
|
| 13007 |
|
|
/*** CAN2RXDLR - MSCAN 2 Receive Data Length Register; 0x000001EC ***/
|
| 13008 |
|
|
typedef union {
|
| 13009 |
|
|
byte Byte;
|
| 13010 |
|
|
struct {
|
| 13011 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 13012 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 13013 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 13014 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 13015 |
|
|
byte :1;
|
| 13016 |
|
|
byte :1;
|
| 13017 |
|
|
byte :1;
|
| 13018 |
|
|
byte :1;
|
| 13019 |
|
|
} Bits;
|
| 13020 |
|
|
struct {
|
| 13021 |
|
|
byte grpDLC :4;
|
| 13022 |
|
|
byte :1;
|
| 13023 |
|
|
byte :1;
|
| 13024 |
|
|
byte :1;
|
| 13025 |
|
|
byte :1;
|
| 13026 |
|
|
} MergedBits;
|
| 13027 |
|
|
} CAN2RXDLRSTR;
|
| 13028 |
|
|
extern volatile CAN2RXDLRSTR _CAN2RXDLR @(REG_BASE + 0x000001EC);
|
| 13029 |
|
|
#define CAN2RXDLR _CAN2RXDLR.Byte
|
| 13030 |
|
|
#define CAN2RXDLR_DLC0 _CAN2RXDLR.Bits.DLC0
|
| 13031 |
|
|
#define CAN2RXDLR_DLC1 _CAN2RXDLR.Bits.DLC1
|
| 13032 |
|
|
#define CAN2RXDLR_DLC2 _CAN2RXDLR.Bits.DLC2
|
| 13033 |
|
|
#define CAN2RXDLR_DLC3 _CAN2RXDLR.Bits.DLC3
|
| 13034 |
|
|
#define CAN2RXDLR_DLC _CAN2RXDLR.MergedBits.grpDLC
|
| 13035 |
|
|
|
| 13036 |
|
|
|
| 13037 |
|
|
/*** CAN2TXIDR0 - MSCAN 2 Transmit Identifier Register 0; 0x000001F0 ***/
|
| 13038 |
|
|
typedef union {
|
| 13039 |
|
|
byte Byte;
|
| 13040 |
|
|
struct {
|
| 13041 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 13042 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 13043 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 13044 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 13045 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 13046 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 13047 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 13048 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 13049 |
|
|
} Bits;
|
| 13050 |
|
|
struct {
|
| 13051 |
|
|
byte grpID_21 :8;
|
| 13052 |
|
|
} MergedBits;
|
| 13053 |
|
|
} CAN2TXIDR0STR;
|
| 13054 |
|
|
extern volatile CAN2TXIDR0STR _CAN2TXIDR0 @(REG_BASE + 0x000001F0);
|
| 13055 |
|
|
#define CAN2TXIDR0 _CAN2TXIDR0.Byte
|
| 13056 |
|
|
#define CAN2TXIDR0_ID21 _CAN2TXIDR0.Bits.ID21
|
| 13057 |
|
|
#define CAN2TXIDR0_ID22 _CAN2TXIDR0.Bits.ID22
|
| 13058 |
|
|
#define CAN2TXIDR0_ID23 _CAN2TXIDR0.Bits.ID23
|
| 13059 |
|
|
#define CAN2TXIDR0_ID24 _CAN2TXIDR0.Bits.ID24
|
| 13060 |
|
|
#define CAN2TXIDR0_ID25 _CAN2TXIDR0.Bits.ID25
|
| 13061 |
|
|
#define CAN2TXIDR0_ID26 _CAN2TXIDR0.Bits.ID26
|
| 13062 |
|
|
#define CAN2TXIDR0_ID27 _CAN2TXIDR0.Bits.ID27
|
| 13063 |
|
|
#define CAN2TXIDR0_ID28 _CAN2TXIDR0.Bits.ID28
|
| 13064 |
|
|
#define CAN2TXIDR0_ID_21 _CAN2TXIDR0.MergedBits.grpID_21
|
| 13065 |
|
|
#define CAN2TXIDR0_ID CAN2TXIDR0_ID_21
|
| 13066 |
|
|
|
| 13067 |
|
|
|
| 13068 |
|
|
/*** CAN2TXIDR1 - MSCAN 2 Transmit Identifier Register 1; 0x000001F1 ***/
|
| 13069 |
|
|
typedef union {
|
| 13070 |
|
|
byte Byte;
|
| 13071 |
|
|
struct {
|
| 13072 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 13073 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 13074 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 13075 |
|
|
byte IDE :1; /* ID Extended */
|
| 13076 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 13077 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 13078 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 13079 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 13080 |
|
|
} Bits;
|
| 13081 |
|
|
struct {
|
| 13082 |
|
|
byte grpID_15 :3;
|
| 13083 |
|
|
byte :1;
|
| 13084 |
|
|
byte :1;
|
| 13085 |
|
|
byte grpID_18 :3;
|
| 13086 |
|
|
} MergedBits;
|
| 13087 |
|
|
} CAN2TXIDR1STR;
|
| 13088 |
|
|
extern volatile CAN2TXIDR1STR _CAN2TXIDR1 @(REG_BASE + 0x000001F1);
|
| 13089 |
|
|
#define CAN2TXIDR1 _CAN2TXIDR1.Byte
|
| 13090 |
|
|
#define CAN2TXIDR1_ID15 _CAN2TXIDR1.Bits.ID15
|
| 13091 |
|
|
#define CAN2TXIDR1_ID16 _CAN2TXIDR1.Bits.ID16
|
| 13092 |
|
|
#define CAN2TXIDR1_ID17 _CAN2TXIDR1.Bits.ID17
|
| 13093 |
|
|
#define CAN2TXIDR1_IDE _CAN2TXIDR1.Bits.IDE
|
| 13094 |
|
|
#define CAN2TXIDR1_SRR _CAN2TXIDR1.Bits.SRR
|
| 13095 |
|
|
#define CAN2TXIDR1_ID18 _CAN2TXIDR1.Bits.ID18
|
| 13096 |
|
|
#define CAN2TXIDR1_ID19 _CAN2TXIDR1.Bits.ID19
|
| 13097 |
|
|
#define CAN2TXIDR1_ID20 _CAN2TXIDR1.Bits.ID20
|
| 13098 |
|
|
#define CAN2TXIDR1_ID_15 _CAN2TXIDR1.MergedBits.grpID_15
|
| 13099 |
|
|
#define CAN2TXIDR1_ID_18 _CAN2TXIDR1.MergedBits.grpID_18
|
| 13100 |
|
|
#define CAN2TXIDR1_ID CAN2TXIDR1_ID_15
|
| 13101 |
|
|
|
| 13102 |
|
|
|
| 13103 |
|
|
/*** CAN2TXIDR2 - MSCAN 2 Transmit Identifier Register 2; 0x000001F2 ***/
|
| 13104 |
|
|
typedef union {
|
| 13105 |
|
|
byte Byte;
|
| 13106 |
|
|
struct {
|
| 13107 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 13108 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 13109 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 13110 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 13111 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 13112 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 13113 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 13114 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 13115 |
|
|
} Bits;
|
| 13116 |
|
|
struct {
|
| 13117 |
|
|
byte grpID_7 :8;
|
| 13118 |
|
|
} MergedBits;
|
| 13119 |
|
|
} CAN2TXIDR2STR;
|
| 13120 |
|
|
extern volatile CAN2TXIDR2STR _CAN2TXIDR2 @(REG_BASE + 0x000001F2);
|
| 13121 |
|
|
#define CAN2TXIDR2 _CAN2TXIDR2.Byte
|
| 13122 |
|
|
#define CAN2TXIDR2_ID7 _CAN2TXIDR2.Bits.ID7
|
| 13123 |
|
|
#define CAN2TXIDR2_ID8 _CAN2TXIDR2.Bits.ID8
|
| 13124 |
|
|
#define CAN2TXIDR2_ID9 _CAN2TXIDR2.Bits.ID9
|
| 13125 |
|
|
#define CAN2TXIDR2_ID10 _CAN2TXIDR2.Bits.ID10
|
| 13126 |
|
|
#define CAN2TXIDR2_ID11 _CAN2TXIDR2.Bits.ID11
|
| 13127 |
|
|
#define CAN2TXIDR2_ID12 _CAN2TXIDR2.Bits.ID12
|
| 13128 |
|
|
#define CAN2TXIDR2_ID13 _CAN2TXIDR2.Bits.ID13
|
| 13129 |
|
|
#define CAN2TXIDR2_ID14 _CAN2TXIDR2.Bits.ID14
|
| 13130 |
|
|
#define CAN2TXIDR2_ID_7 _CAN2TXIDR2.MergedBits.grpID_7
|
| 13131 |
|
|
#define CAN2TXIDR2_ID CAN2TXIDR2_ID_7
|
| 13132 |
|
|
|
| 13133 |
|
|
|
| 13134 |
|
|
/*** CAN2TXIDR3 - MSCAN 2 Transmit Identifier Register 3; 0x000001F3 ***/
|
| 13135 |
|
|
typedef union {
|
| 13136 |
|
|
byte Byte;
|
| 13137 |
|
|
struct {
|
| 13138 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 13139 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 13140 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 13141 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 13142 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 13143 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 13144 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 13145 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 13146 |
|
|
} Bits;
|
| 13147 |
|
|
struct {
|
| 13148 |
|
|
byte :1;
|
| 13149 |
|
|
byte grpID :7;
|
| 13150 |
|
|
} MergedBits;
|
| 13151 |
|
|
} CAN2TXIDR3STR;
|
| 13152 |
|
|
extern volatile CAN2TXIDR3STR _CAN2TXIDR3 @(REG_BASE + 0x000001F3);
|
| 13153 |
|
|
#define CAN2TXIDR3 _CAN2TXIDR3.Byte
|
| 13154 |
|
|
#define CAN2TXIDR3_RTR _CAN2TXIDR3.Bits.RTR
|
| 13155 |
|
|
#define CAN2TXIDR3_ID0 _CAN2TXIDR3.Bits.ID0
|
| 13156 |
|
|
#define CAN2TXIDR3_ID1 _CAN2TXIDR3.Bits.ID1
|
| 13157 |
|
|
#define CAN2TXIDR3_ID2 _CAN2TXIDR3.Bits.ID2
|
| 13158 |
|
|
#define CAN2TXIDR3_ID3 _CAN2TXIDR3.Bits.ID3
|
| 13159 |
|
|
#define CAN2TXIDR3_ID4 _CAN2TXIDR3.Bits.ID4
|
| 13160 |
|
|
#define CAN2TXIDR3_ID5 _CAN2TXIDR3.Bits.ID5
|
| 13161 |
|
|
#define CAN2TXIDR3_ID6 _CAN2TXIDR3.Bits.ID6
|
| 13162 |
|
|
#define CAN2TXIDR3_ID _CAN2TXIDR3.MergedBits.grpID
|
| 13163 |
|
|
|
| 13164 |
|
|
|
| 13165 |
|
|
/*** CAN2TXDSR0 - MSCAN 2 Transmit Data Segment Register 0; 0x000001F4 ***/
|
| 13166 |
|
|
typedef union {
|
| 13167 |
|
|
byte Byte;
|
| 13168 |
|
|
struct {
|
| 13169 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 13170 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 13171 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 13172 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 13173 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 13174 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 13175 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 13176 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 13177 |
|
|
} Bits;
|
| 13178 |
|
|
struct {
|
| 13179 |
|
|
byte grpDB :8;
|
| 13180 |
|
|
} MergedBits;
|
| 13181 |
|
|
} CAN2TXDSR0STR;
|
| 13182 |
|
|
extern volatile CAN2TXDSR0STR _CAN2TXDSR0 @(REG_BASE + 0x000001F4);
|
| 13183 |
|
|
#define CAN2TXDSR0 _CAN2TXDSR0.Byte
|
| 13184 |
|
|
#define CAN2TXDSR0_DB0 _CAN2TXDSR0.Bits.DB0
|
| 13185 |
|
|
#define CAN2TXDSR0_DB1 _CAN2TXDSR0.Bits.DB1
|
| 13186 |
|
|
#define CAN2TXDSR0_DB2 _CAN2TXDSR0.Bits.DB2
|
| 13187 |
|
|
#define CAN2TXDSR0_DB3 _CAN2TXDSR0.Bits.DB3
|
| 13188 |
|
|
#define CAN2TXDSR0_DB4 _CAN2TXDSR0.Bits.DB4
|
| 13189 |
|
|
#define CAN2TXDSR0_DB5 _CAN2TXDSR0.Bits.DB5
|
| 13190 |
|
|
#define CAN2TXDSR0_DB6 _CAN2TXDSR0.Bits.DB6
|
| 13191 |
|
|
#define CAN2TXDSR0_DB7 _CAN2TXDSR0.Bits.DB7
|
| 13192 |
|
|
#define CAN2TXDSR0_DB _CAN2TXDSR0.MergedBits.grpDB
|
| 13193 |
|
|
|
| 13194 |
|
|
|
| 13195 |
|
|
/*** CAN2TXDSR1 - MSCAN 2 Transmit Data Segment Register 1; 0x000001F5 ***/
|
| 13196 |
|
|
typedef union {
|
| 13197 |
|
|
byte Byte;
|
| 13198 |
|
|
struct {
|
| 13199 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 13200 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 13201 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 13202 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 13203 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 13204 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 13205 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 13206 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 13207 |
|
|
} Bits;
|
| 13208 |
|
|
struct {
|
| 13209 |
|
|
byte grpDB :8;
|
| 13210 |
|
|
} MergedBits;
|
| 13211 |
|
|
} CAN2TXDSR1STR;
|
| 13212 |
|
|
extern volatile CAN2TXDSR1STR _CAN2TXDSR1 @(REG_BASE + 0x000001F5);
|
| 13213 |
|
|
#define CAN2TXDSR1 _CAN2TXDSR1.Byte
|
| 13214 |
|
|
#define CAN2TXDSR1_DB0 _CAN2TXDSR1.Bits.DB0
|
| 13215 |
|
|
#define CAN2TXDSR1_DB1 _CAN2TXDSR1.Bits.DB1
|
| 13216 |
|
|
#define CAN2TXDSR1_DB2 _CAN2TXDSR1.Bits.DB2
|
| 13217 |
|
|
#define CAN2TXDSR1_DB3 _CAN2TXDSR1.Bits.DB3
|
| 13218 |
|
|
#define CAN2TXDSR1_DB4 _CAN2TXDSR1.Bits.DB4
|
| 13219 |
|
|
#define CAN2TXDSR1_DB5 _CAN2TXDSR1.Bits.DB5
|
| 13220 |
|
|
#define CAN2TXDSR1_DB6 _CAN2TXDSR1.Bits.DB6
|
| 13221 |
|
|
#define CAN2TXDSR1_DB7 _CAN2TXDSR1.Bits.DB7
|
| 13222 |
|
|
#define CAN2TXDSR1_DB _CAN2TXDSR1.MergedBits.grpDB
|
| 13223 |
|
|
|
| 13224 |
|
|
|
| 13225 |
|
|
/*** CAN2TXDSR2 - MSCAN 2 Transmit Data Segment Register 2; 0x000001F6 ***/
|
| 13226 |
|
|
typedef union {
|
| 13227 |
|
|
byte Byte;
|
| 13228 |
|
|
struct {
|
| 13229 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 13230 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 13231 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 13232 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 13233 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 13234 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 13235 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 13236 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 13237 |
|
|
} Bits;
|
| 13238 |
|
|
struct {
|
| 13239 |
|
|
byte grpDB :8;
|
| 13240 |
|
|
} MergedBits;
|
| 13241 |
|
|
} CAN2TXDSR2STR;
|
| 13242 |
|
|
extern volatile CAN2TXDSR2STR _CAN2TXDSR2 @(REG_BASE + 0x000001F6);
|
| 13243 |
|
|
#define CAN2TXDSR2 _CAN2TXDSR2.Byte
|
| 13244 |
|
|
#define CAN2TXDSR2_DB0 _CAN2TXDSR2.Bits.DB0
|
| 13245 |
|
|
#define CAN2TXDSR2_DB1 _CAN2TXDSR2.Bits.DB1
|
| 13246 |
|
|
#define CAN2TXDSR2_DB2 _CAN2TXDSR2.Bits.DB2
|
| 13247 |
|
|
#define CAN2TXDSR2_DB3 _CAN2TXDSR2.Bits.DB3
|
| 13248 |
|
|
#define CAN2TXDSR2_DB4 _CAN2TXDSR2.Bits.DB4
|
| 13249 |
|
|
#define CAN2TXDSR2_DB5 _CAN2TXDSR2.Bits.DB5
|
| 13250 |
|
|
#define CAN2TXDSR2_DB6 _CAN2TXDSR2.Bits.DB6
|
| 13251 |
|
|
#define CAN2TXDSR2_DB7 _CAN2TXDSR2.Bits.DB7
|
| 13252 |
|
|
#define CAN2TXDSR2_DB _CAN2TXDSR2.MergedBits.grpDB
|
| 13253 |
|
|
|
| 13254 |
|
|
|
| 13255 |
|
|
/*** CAN2TXDSR3 - MSCAN 2 Transmit Data Segment Register 3; 0x000001F7 ***/
|
| 13256 |
|
|
typedef union {
|
| 13257 |
|
|
byte Byte;
|
| 13258 |
|
|
struct {
|
| 13259 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 13260 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 13261 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 13262 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 13263 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 13264 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 13265 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 13266 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 13267 |
|
|
} Bits;
|
| 13268 |
|
|
struct {
|
| 13269 |
|
|
byte grpDB :8;
|
| 13270 |
|
|
} MergedBits;
|
| 13271 |
|
|
} CAN2TXDSR3STR;
|
| 13272 |
|
|
extern volatile CAN2TXDSR3STR _CAN2TXDSR3 @(REG_BASE + 0x000001F7);
|
| 13273 |
|
|
#define CAN2TXDSR3 _CAN2TXDSR3.Byte
|
| 13274 |
|
|
#define CAN2TXDSR3_DB0 _CAN2TXDSR3.Bits.DB0
|
| 13275 |
|
|
#define CAN2TXDSR3_DB1 _CAN2TXDSR3.Bits.DB1
|
| 13276 |
|
|
#define CAN2TXDSR3_DB2 _CAN2TXDSR3.Bits.DB2
|
| 13277 |
|
|
#define CAN2TXDSR3_DB3 _CAN2TXDSR3.Bits.DB3
|
| 13278 |
|
|
#define CAN2TXDSR3_DB4 _CAN2TXDSR3.Bits.DB4
|
| 13279 |
|
|
#define CAN2TXDSR3_DB5 _CAN2TXDSR3.Bits.DB5
|
| 13280 |
|
|
#define CAN2TXDSR3_DB6 _CAN2TXDSR3.Bits.DB6
|
| 13281 |
|
|
#define CAN2TXDSR3_DB7 _CAN2TXDSR3.Bits.DB7
|
| 13282 |
|
|
#define CAN2TXDSR3_DB _CAN2TXDSR3.MergedBits.grpDB
|
| 13283 |
|
|
|
| 13284 |
|
|
|
| 13285 |
|
|
/*** CAN2TXDSR4 - MSCAN 2 Transmit Data Segment Register 4; 0x000001F8 ***/
|
| 13286 |
|
|
typedef union {
|
| 13287 |
|
|
byte Byte;
|
| 13288 |
|
|
struct {
|
| 13289 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 13290 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 13291 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 13292 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 13293 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 13294 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 13295 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 13296 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 13297 |
|
|
} Bits;
|
| 13298 |
|
|
struct {
|
| 13299 |
|
|
byte grpDB :8;
|
| 13300 |
|
|
} MergedBits;
|
| 13301 |
|
|
} CAN2TXDSR4STR;
|
| 13302 |
|
|
extern volatile CAN2TXDSR4STR _CAN2TXDSR4 @(REG_BASE + 0x000001F8);
|
| 13303 |
|
|
#define CAN2TXDSR4 _CAN2TXDSR4.Byte
|
| 13304 |
|
|
#define CAN2TXDSR4_DB0 _CAN2TXDSR4.Bits.DB0
|
| 13305 |
|
|
#define CAN2TXDSR4_DB1 _CAN2TXDSR4.Bits.DB1
|
| 13306 |
|
|
#define CAN2TXDSR4_DB2 _CAN2TXDSR4.Bits.DB2
|
| 13307 |
|
|
#define CAN2TXDSR4_DB3 _CAN2TXDSR4.Bits.DB3
|
| 13308 |
|
|
#define CAN2TXDSR4_DB4 _CAN2TXDSR4.Bits.DB4
|
| 13309 |
|
|
#define CAN2TXDSR4_DB5 _CAN2TXDSR4.Bits.DB5
|
| 13310 |
|
|
#define CAN2TXDSR4_DB6 _CAN2TXDSR4.Bits.DB6
|
| 13311 |
|
|
#define CAN2TXDSR4_DB7 _CAN2TXDSR4.Bits.DB7
|
| 13312 |
|
|
#define CAN2TXDSR4_DB _CAN2TXDSR4.MergedBits.grpDB
|
| 13313 |
|
|
|
| 13314 |
|
|
|
| 13315 |
|
|
/*** CAN2TXDSR5 - MSCAN 2 Transmit Data Segment Register 5; 0x000001F9 ***/
|
| 13316 |
|
|
typedef union {
|
| 13317 |
|
|
byte Byte;
|
| 13318 |
|
|
struct {
|
| 13319 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 13320 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 13321 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 13322 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 13323 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 13324 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 13325 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 13326 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 13327 |
|
|
} Bits;
|
| 13328 |
|
|
struct {
|
| 13329 |
|
|
byte grpDB :8;
|
| 13330 |
|
|
} MergedBits;
|
| 13331 |
|
|
} CAN2TXDSR5STR;
|
| 13332 |
|
|
extern volatile CAN2TXDSR5STR _CAN2TXDSR5 @(REG_BASE + 0x000001F9);
|
| 13333 |
|
|
#define CAN2TXDSR5 _CAN2TXDSR5.Byte
|
| 13334 |
|
|
#define CAN2TXDSR5_DB0 _CAN2TXDSR5.Bits.DB0
|
| 13335 |
|
|
#define CAN2TXDSR5_DB1 _CAN2TXDSR5.Bits.DB1
|
| 13336 |
|
|
#define CAN2TXDSR5_DB2 _CAN2TXDSR5.Bits.DB2
|
| 13337 |
|
|
#define CAN2TXDSR5_DB3 _CAN2TXDSR5.Bits.DB3
|
| 13338 |
|
|
#define CAN2TXDSR5_DB4 _CAN2TXDSR5.Bits.DB4
|
| 13339 |
|
|
#define CAN2TXDSR5_DB5 _CAN2TXDSR5.Bits.DB5
|
| 13340 |
|
|
#define CAN2TXDSR5_DB6 _CAN2TXDSR5.Bits.DB6
|
| 13341 |
|
|
#define CAN2TXDSR5_DB7 _CAN2TXDSR5.Bits.DB7
|
| 13342 |
|
|
#define CAN2TXDSR5_DB _CAN2TXDSR5.MergedBits.grpDB
|
| 13343 |
|
|
|
| 13344 |
|
|
|
| 13345 |
|
|
/*** CAN2TXDSR6 - MSCAN 2 Transmit Data Segment Register 6; 0x000001FA ***/
|
| 13346 |
|
|
typedef union {
|
| 13347 |
|
|
byte Byte;
|
| 13348 |
|
|
struct {
|
| 13349 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 13350 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 13351 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 13352 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 13353 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 13354 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 13355 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 13356 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 13357 |
|
|
} Bits;
|
| 13358 |
|
|
struct {
|
| 13359 |
|
|
byte grpDB :8;
|
| 13360 |
|
|
} MergedBits;
|
| 13361 |
|
|
} CAN2TXDSR6STR;
|
| 13362 |
|
|
extern volatile CAN2TXDSR6STR _CAN2TXDSR6 @(REG_BASE + 0x000001FA);
|
| 13363 |
|
|
#define CAN2TXDSR6 _CAN2TXDSR6.Byte
|
| 13364 |
|
|
#define CAN2TXDSR6_DB0 _CAN2TXDSR6.Bits.DB0
|
| 13365 |
|
|
#define CAN2TXDSR6_DB1 _CAN2TXDSR6.Bits.DB1
|
| 13366 |
|
|
#define CAN2TXDSR6_DB2 _CAN2TXDSR6.Bits.DB2
|
| 13367 |
|
|
#define CAN2TXDSR6_DB3 _CAN2TXDSR6.Bits.DB3
|
| 13368 |
|
|
#define CAN2TXDSR6_DB4 _CAN2TXDSR6.Bits.DB4
|
| 13369 |
|
|
#define CAN2TXDSR6_DB5 _CAN2TXDSR6.Bits.DB5
|
| 13370 |
|
|
#define CAN2TXDSR6_DB6 _CAN2TXDSR6.Bits.DB6
|
| 13371 |
|
|
#define CAN2TXDSR6_DB7 _CAN2TXDSR6.Bits.DB7
|
| 13372 |
|
|
#define CAN2TXDSR6_DB _CAN2TXDSR6.MergedBits.grpDB
|
| 13373 |
|
|
|
| 13374 |
|
|
|
| 13375 |
|
|
/*** CAN2TXDSR7 - MSCAN 2 Transmit Data Segment Register 7; 0x000001FB ***/
|
| 13376 |
|
|
typedef union {
|
| 13377 |
|
|
byte Byte;
|
| 13378 |
|
|
struct {
|
| 13379 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 13380 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 13381 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 13382 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 13383 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 13384 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 13385 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 13386 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 13387 |
|
|
} Bits;
|
| 13388 |
|
|
struct {
|
| 13389 |
|
|
byte grpDB :8;
|
| 13390 |
|
|
} MergedBits;
|
| 13391 |
|
|
} CAN2TXDSR7STR;
|
| 13392 |
|
|
extern volatile CAN2TXDSR7STR _CAN2TXDSR7 @(REG_BASE + 0x000001FB);
|
| 13393 |
|
|
#define CAN2TXDSR7 _CAN2TXDSR7.Byte
|
| 13394 |
|
|
#define CAN2TXDSR7_DB0 _CAN2TXDSR7.Bits.DB0
|
| 13395 |
|
|
#define CAN2TXDSR7_DB1 _CAN2TXDSR7.Bits.DB1
|
| 13396 |
|
|
#define CAN2TXDSR7_DB2 _CAN2TXDSR7.Bits.DB2
|
| 13397 |
|
|
#define CAN2TXDSR7_DB3 _CAN2TXDSR7.Bits.DB3
|
| 13398 |
|
|
#define CAN2TXDSR7_DB4 _CAN2TXDSR7.Bits.DB4
|
| 13399 |
|
|
#define CAN2TXDSR7_DB5 _CAN2TXDSR7.Bits.DB5
|
| 13400 |
|
|
#define CAN2TXDSR7_DB6 _CAN2TXDSR7.Bits.DB6
|
| 13401 |
|
|
#define CAN2TXDSR7_DB7 _CAN2TXDSR7.Bits.DB7
|
| 13402 |
|
|
#define CAN2TXDSR7_DB _CAN2TXDSR7.MergedBits.grpDB
|
| 13403 |
|
|
|
| 13404 |
|
|
|
| 13405 |
|
|
/*** CAN2TXDLR - MSCAN 2 Transmit Data Length Register; 0x000001FC ***/
|
| 13406 |
|
|
typedef union {
|
| 13407 |
|
|
byte Byte;
|
| 13408 |
|
|
struct {
|
| 13409 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 13410 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 13411 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 13412 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 13413 |
|
|
byte :1;
|
| 13414 |
|
|
byte :1;
|
| 13415 |
|
|
byte :1;
|
| 13416 |
|
|
byte :1;
|
| 13417 |
|
|
} Bits;
|
| 13418 |
|
|
struct {
|
| 13419 |
|
|
byte grpDLC :4;
|
| 13420 |
|
|
byte :1;
|
| 13421 |
|
|
byte :1;
|
| 13422 |
|
|
byte :1;
|
| 13423 |
|
|
byte :1;
|
| 13424 |
|
|
} MergedBits;
|
| 13425 |
|
|
} CAN2TXDLRSTR;
|
| 13426 |
|
|
extern volatile CAN2TXDLRSTR _CAN2TXDLR @(REG_BASE + 0x000001FC);
|
| 13427 |
|
|
#define CAN2TXDLR _CAN2TXDLR.Byte
|
| 13428 |
|
|
#define CAN2TXDLR_DLC0 _CAN2TXDLR.Bits.DLC0
|
| 13429 |
|
|
#define CAN2TXDLR_DLC1 _CAN2TXDLR.Bits.DLC1
|
| 13430 |
|
|
#define CAN2TXDLR_DLC2 _CAN2TXDLR.Bits.DLC2
|
| 13431 |
|
|
#define CAN2TXDLR_DLC3 _CAN2TXDLR.Bits.DLC3
|
| 13432 |
|
|
#define CAN2TXDLR_DLC _CAN2TXDLR.MergedBits.grpDLC
|
| 13433 |
|
|
|
| 13434 |
|
|
|
| 13435 |
|
|
/*** CAN2TXTBPR - MSCAN 2 Transmit Buffer Priority; 0x000001FF ***/
|
| 13436 |
|
|
typedef union {
|
| 13437 |
|
|
byte Byte;
|
| 13438 |
|
|
struct {
|
| 13439 |
|
|
byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
|
| 13440 |
|
|
byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
|
| 13441 |
|
|
byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
|
| 13442 |
|
|
byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
|
| 13443 |
|
|
byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
|
| 13444 |
|
|
byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
|
| 13445 |
|
|
byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
|
| 13446 |
|
|
byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
|
| 13447 |
|
|
} Bits;
|
| 13448 |
|
|
struct {
|
| 13449 |
|
|
byte grpPRIO :8;
|
| 13450 |
|
|
} MergedBits;
|
| 13451 |
|
|
} CAN2TXTBPRSTR;
|
| 13452 |
|
|
extern volatile CAN2TXTBPRSTR _CAN2TXTBPR @(REG_BASE + 0x000001FF);
|
| 13453 |
|
|
#define CAN2TXTBPR _CAN2TXTBPR.Byte
|
| 13454 |
|
|
#define CAN2TXTBPR_PRIO0 _CAN2TXTBPR.Bits.PRIO0
|
| 13455 |
|
|
#define CAN2TXTBPR_PRIO1 _CAN2TXTBPR.Bits.PRIO1
|
| 13456 |
|
|
#define CAN2TXTBPR_PRIO2 _CAN2TXTBPR.Bits.PRIO2
|
| 13457 |
|
|
#define CAN2TXTBPR_PRIO3 _CAN2TXTBPR.Bits.PRIO3
|
| 13458 |
|
|
#define CAN2TXTBPR_PRIO4 _CAN2TXTBPR.Bits.PRIO4
|
| 13459 |
|
|
#define CAN2TXTBPR_PRIO5 _CAN2TXTBPR.Bits.PRIO5
|
| 13460 |
|
|
#define CAN2TXTBPR_PRIO6 _CAN2TXTBPR.Bits.PRIO6
|
| 13461 |
|
|
#define CAN2TXTBPR_PRIO7 _CAN2TXTBPR.Bits.PRIO7
|
| 13462 |
|
|
#define CAN2TXTBPR_PRIO _CAN2TXTBPR.MergedBits.grpPRIO
|
| 13463 |
|
|
|
| 13464 |
|
|
|
| 13465 |
|
|
/*** CAN3CTL0 - MSCAN 3 Control 0 Register; 0x00000200 ***/
|
| 13466 |
|
|
typedef union {
|
| 13467 |
|
|
byte Byte;
|
| 13468 |
|
|
struct {
|
| 13469 |
|
|
byte INITRQ :1; /* Initialization Mode Request */
|
| 13470 |
|
|
byte SLPRQ :1; /* Sleep Mode Request */
|
| 13471 |
|
|
byte WUPE :1; /* Wake-Up Enable */
|
| 13472 |
|
|
byte TIME :1; /* Timer Enable */
|
| 13473 |
|
|
byte SYNCH :1; /* Synchronized Status */
|
| 13474 |
|
|
byte CSWAI :1; /* CAN Stops in Wait Mode */
|
| 13475 |
|
|
byte RXACT :1; /* Receiver Active Status */
|
| 13476 |
|
|
byte RXFRM :1; /* Received Frame Flag */
|
| 13477 |
|
|
} Bits;
|
| 13478 |
|
|
} CAN3CTL0STR;
|
| 13479 |
|
|
extern volatile CAN3CTL0STR _CAN3CTL0 @(REG_BASE + 0x00000200);
|
| 13480 |
|
|
#define CAN3CTL0 _CAN3CTL0.Byte
|
| 13481 |
|
|
#define CAN3CTL0_INITRQ _CAN3CTL0.Bits.INITRQ
|
| 13482 |
|
|
#define CAN3CTL0_SLPRQ _CAN3CTL0.Bits.SLPRQ
|
| 13483 |
|
|
#define CAN3CTL0_WUPE _CAN3CTL0.Bits.WUPE
|
| 13484 |
|
|
#define CAN3CTL0_TIME _CAN3CTL0.Bits.TIME
|
| 13485 |
|
|
#define CAN3CTL0_SYNCH _CAN3CTL0.Bits.SYNCH
|
| 13486 |
|
|
#define CAN3CTL0_CSWAI _CAN3CTL0.Bits.CSWAI
|
| 13487 |
|
|
#define CAN3CTL0_RXACT _CAN3CTL0.Bits.RXACT
|
| 13488 |
|
|
#define CAN3CTL0_RXFRM _CAN3CTL0.Bits.RXFRM
|
| 13489 |
|
|
|
| 13490 |
|
|
|
| 13491 |
|
|
/*** CAN3CTL1 - MSCAN 3 Control 1 Register; 0x00000201 ***/
|
| 13492 |
|
|
typedef union {
|
| 13493 |
|
|
byte Byte;
|
| 13494 |
|
|
struct {
|
| 13495 |
|
|
byte INITAK :1; /* Initialization Mode Acknowledge */
|
| 13496 |
|
|
byte SLPAK :1; /* Sleep Mode Acknowledge */
|
| 13497 |
|
|
byte WUPM :1; /* Wake-Up Mode */
|
| 13498 |
|
|
byte :1;
|
| 13499 |
|
|
byte LISTEN :1; /* Listen Only Mode */
|
| 13500 |
|
|
byte LOOPB :1; /* Loop Back Self Test Mode */
|
| 13501 |
|
|
byte CLKSRC :1; /* MSCAN 3 Clock Source */
|
| 13502 |
|
|
byte CANE :1; /* MSCAN 3 Enable */
|
| 13503 |
|
|
} Bits;
|
| 13504 |
|
|
} CAN3CTL1STR;
|
| 13505 |
|
|
extern volatile CAN3CTL1STR _CAN3CTL1 @(REG_BASE + 0x00000201);
|
| 13506 |
|
|
#define CAN3CTL1 _CAN3CTL1.Byte
|
| 13507 |
|
|
#define CAN3CTL1_INITAK _CAN3CTL1.Bits.INITAK
|
| 13508 |
|
|
#define CAN3CTL1_SLPAK _CAN3CTL1.Bits.SLPAK
|
| 13509 |
|
|
#define CAN3CTL1_WUPM _CAN3CTL1.Bits.WUPM
|
| 13510 |
|
|
#define CAN3CTL1_LISTEN _CAN3CTL1.Bits.LISTEN
|
| 13511 |
|
|
#define CAN3CTL1_LOOPB _CAN3CTL1.Bits.LOOPB
|
| 13512 |
|
|
#define CAN3CTL1_CLKSRC _CAN3CTL1.Bits.CLKSRC
|
| 13513 |
|
|
#define CAN3CTL1_CANE _CAN3CTL1.Bits.CANE
|
| 13514 |
|
|
|
| 13515 |
|
|
|
| 13516 |
|
|
/*** CAN3BTR0 - MSCAN 3 Bus Timing Register 0; 0x00000202 ***/
|
| 13517 |
|
|
typedef union {
|
| 13518 |
|
|
byte Byte;
|
| 13519 |
|
|
struct {
|
| 13520 |
|
|
byte BRP0 :1; /* Baud Rate Prescaler 0 */
|
| 13521 |
|
|
byte BRP1 :1; /* Baud Rate Prescaler 1 */
|
| 13522 |
|
|
byte BRP2 :1; /* Baud Rate Prescaler 2 */
|
| 13523 |
|
|
byte BRP3 :1; /* Baud Rate Prescaler 3 */
|
| 13524 |
|
|
byte BRP4 :1; /* Baud Rate Prescaler 4 */
|
| 13525 |
|
|
byte BRP5 :1; /* Baud Rate Prescaler 5 */
|
| 13526 |
|
|
byte SJW0 :1; /* Synchronization Jump Width 0 */
|
| 13527 |
|
|
byte SJW1 :1; /* Synchronization Jump Width 1 */
|
| 13528 |
|
|
} Bits;
|
| 13529 |
|
|
struct {
|
| 13530 |
|
|
byte grpBRP :6;
|
| 13531 |
|
|
byte grpSJW :2;
|
| 13532 |
|
|
} MergedBits;
|
| 13533 |
|
|
} CAN3BTR0STR;
|
| 13534 |
|
|
extern volatile CAN3BTR0STR _CAN3BTR0 @(REG_BASE + 0x00000202);
|
| 13535 |
|
|
#define CAN3BTR0 _CAN3BTR0.Byte
|
| 13536 |
|
|
#define CAN3BTR0_BRP0 _CAN3BTR0.Bits.BRP0
|
| 13537 |
|
|
#define CAN3BTR0_BRP1 _CAN3BTR0.Bits.BRP1
|
| 13538 |
|
|
#define CAN3BTR0_BRP2 _CAN3BTR0.Bits.BRP2
|
| 13539 |
|
|
#define CAN3BTR0_BRP3 _CAN3BTR0.Bits.BRP3
|
| 13540 |
|
|
#define CAN3BTR0_BRP4 _CAN3BTR0.Bits.BRP4
|
| 13541 |
|
|
#define CAN3BTR0_BRP5 _CAN3BTR0.Bits.BRP5
|
| 13542 |
|
|
#define CAN3BTR0_SJW0 _CAN3BTR0.Bits.SJW0
|
| 13543 |
|
|
#define CAN3BTR0_SJW1 _CAN3BTR0.Bits.SJW1
|
| 13544 |
|
|
#define CAN3BTR0_BRP _CAN3BTR0.MergedBits.grpBRP
|
| 13545 |
|
|
#define CAN3BTR0_SJW _CAN3BTR0.MergedBits.grpSJW
|
| 13546 |
|
|
|
| 13547 |
|
|
|
| 13548 |
|
|
/*** CAN3BTR1 - MSCAN 3 Bus Timing Register 1; 0x00000203 ***/
|
| 13549 |
|
|
typedef union {
|
| 13550 |
|
|
byte Byte;
|
| 13551 |
|
|
struct {
|
| 13552 |
|
|
byte TSEG10 :1; /* Time Segment 1 */
|
| 13553 |
|
|
byte TSEG11 :1; /* Time Segment 1 */
|
| 13554 |
|
|
byte TSEG12 :1; /* Time Segment 1 */
|
| 13555 |
|
|
byte TSEG13 :1; /* Time Segment 1 */
|
| 13556 |
|
|
byte TSEG20 :1; /* Time Segment 2 */
|
| 13557 |
|
|
byte TSEG21 :1; /* Time Segment 2 */
|
| 13558 |
|
|
byte TSEG22 :1; /* Time Segment 2 */
|
| 13559 |
|
|
byte SAMP :1; /* Sampling */
|
| 13560 |
|
|
} Bits;
|
| 13561 |
|
|
struct {
|
| 13562 |
|
|
byte grpTSEG_10 :4;
|
| 13563 |
|
|
byte grpTSEG_20 :3;
|
| 13564 |
|
|
byte :1;
|
| 13565 |
|
|
} MergedBits;
|
| 13566 |
|
|
} CAN3BTR1STR;
|
| 13567 |
|
|
extern volatile CAN3BTR1STR _CAN3BTR1 @(REG_BASE + 0x00000203);
|
| 13568 |
|
|
#define CAN3BTR1 _CAN3BTR1.Byte
|
| 13569 |
|
|
#define CAN3BTR1_TSEG10 _CAN3BTR1.Bits.TSEG10
|
| 13570 |
|
|
#define CAN3BTR1_TSEG11 _CAN3BTR1.Bits.TSEG11
|
| 13571 |
|
|
#define CAN3BTR1_TSEG12 _CAN3BTR1.Bits.TSEG12
|
| 13572 |
|
|
#define CAN3BTR1_TSEG13 _CAN3BTR1.Bits.TSEG13
|
| 13573 |
|
|
#define CAN3BTR1_TSEG20 _CAN3BTR1.Bits.TSEG20
|
| 13574 |
|
|
#define CAN3BTR1_TSEG21 _CAN3BTR1.Bits.TSEG21
|
| 13575 |
|
|
#define CAN3BTR1_TSEG22 _CAN3BTR1.Bits.TSEG22
|
| 13576 |
|
|
#define CAN3BTR1_SAMP _CAN3BTR1.Bits.SAMP
|
| 13577 |
|
|
#define CAN3BTR1_TSEG_10 _CAN3BTR1.MergedBits.grpTSEG_10
|
| 13578 |
|
|
#define CAN3BTR1_TSEG_20 _CAN3BTR1.MergedBits.grpTSEG_20
|
| 13579 |
|
|
#define CAN3BTR1_TSEG CAN3BTR1_TSEG_10
|
| 13580 |
|
|
|
| 13581 |
|
|
|
| 13582 |
|
|
/*** CAN3RFLG - MSCAN 3 Receiver Flag Register; 0x00000204 ***/
|
| 13583 |
|
|
typedef union {
|
| 13584 |
|
|
byte Byte;
|
| 13585 |
|
|
struct {
|
| 13586 |
|
|
byte RXF :1; /* Receive Buffer Full */
|
| 13587 |
|
|
byte OVRIF :1; /* Overrun Interrupt Flag */
|
| 13588 |
|
|
byte TSTAT0 :1; /* Transmitter Status Bit 0 */
|
| 13589 |
|
|
byte TSTAT1 :1; /* Transmitter Status Bit 1 */
|
| 13590 |
|
|
byte RSTAT0 :1; /* Receiver Status Bit 0 */
|
| 13591 |
|
|
byte RSTAT1 :1; /* Receiver Status Bit 1 */
|
| 13592 |
|
|
byte CSCIF :1; /* CAN Status Change Interrupt Flag */
|
| 13593 |
|
|
byte WUPIF :1; /* Wake-up Interrupt Flag */
|
| 13594 |
|
|
} Bits;
|
| 13595 |
|
|
struct {
|
| 13596 |
|
|
byte :1;
|
| 13597 |
|
|
byte :1;
|
| 13598 |
|
|
byte grpTSTAT :2;
|
| 13599 |
|
|
byte grpRSTAT :2;
|
| 13600 |
|
|
byte :1;
|
| 13601 |
|
|
byte :1;
|
| 13602 |
|
|
} MergedBits;
|
| 13603 |
|
|
} CAN3RFLGSTR;
|
| 13604 |
|
|
extern volatile CAN3RFLGSTR _CAN3RFLG @(REG_BASE + 0x00000204);
|
| 13605 |
|
|
#define CAN3RFLG _CAN3RFLG.Byte
|
| 13606 |
|
|
#define CAN3RFLG_RXF _CAN3RFLG.Bits.RXF
|
| 13607 |
|
|
#define CAN3RFLG_OVRIF _CAN3RFLG.Bits.OVRIF
|
| 13608 |
|
|
#define CAN3RFLG_TSTAT0 _CAN3RFLG.Bits.TSTAT0
|
| 13609 |
|
|
#define CAN3RFLG_TSTAT1 _CAN3RFLG.Bits.TSTAT1
|
| 13610 |
|
|
#define CAN3RFLG_RSTAT0 _CAN3RFLG.Bits.RSTAT0
|
| 13611 |
|
|
#define CAN3RFLG_RSTAT1 _CAN3RFLG.Bits.RSTAT1
|
| 13612 |
|
|
#define CAN3RFLG_CSCIF _CAN3RFLG.Bits.CSCIF
|
| 13613 |
|
|
#define CAN3RFLG_WUPIF _CAN3RFLG.Bits.WUPIF
|
| 13614 |
|
|
#define CAN3RFLG_TSTAT _CAN3RFLG.MergedBits.grpTSTAT
|
| 13615 |
|
|
#define CAN3RFLG_RSTAT _CAN3RFLG.MergedBits.grpRSTAT
|
| 13616 |
|
|
|
| 13617 |
|
|
|
| 13618 |
|
|
/*** CAN3RIER - MSCAN 3 Receiver Interrupt Enable Register; 0x00000205 ***/
|
| 13619 |
|
|
typedef union {
|
| 13620 |
|
|
byte Byte;
|
| 13621 |
|
|
struct {
|
| 13622 |
|
|
byte RXFIE :1; /* Receiver Full Interrupt Enable */
|
| 13623 |
|
|
byte OVRIE :1; /* Overrun Interrupt Enable */
|
| 13624 |
|
|
byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
|
| 13625 |
|
|
byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
|
| 13626 |
|
|
byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
|
| 13627 |
|
|
byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
|
| 13628 |
|
|
byte CSCIE :1; /* CAN Status Change Interrupt Enable */
|
| 13629 |
|
|
byte WUPIE :1; /* Wake-up Interrupt Enable */
|
| 13630 |
|
|
} Bits;
|
| 13631 |
|
|
struct {
|
| 13632 |
|
|
byte :1;
|
| 13633 |
|
|
byte :1;
|
| 13634 |
|
|
byte grpTSTATE :2;
|
| 13635 |
|
|
byte grpRSTATE :2;
|
| 13636 |
|
|
byte :1;
|
| 13637 |
|
|
byte :1;
|
| 13638 |
|
|
} MergedBits;
|
| 13639 |
|
|
} CAN3RIERSTR;
|
| 13640 |
|
|
extern volatile CAN3RIERSTR _CAN3RIER @(REG_BASE + 0x00000205);
|
| 13641 |
|
|
#define CAN3RIER _CAN3RIER.Byte
|
| 13642 |
|
|
#define CAN3RIER_RXFIE _CAN3RIER.Bits.RXFIE
|
| 13643 |
|
|
#define CAN3RIER_OVRIE _CAN3RIER.Bits.OVRIE
|
| 13644 |
|
|
#define CAN3RIER_TSTATE0 _CAN3RIER.Bits.TSTATE0
|
| 13645 |
|
|
#define CAN3RIER_TSTATE1 _CAN3RIER.Bits.TSTATE1
|
| 13646 |
|
|
#define CAN3RIER_RSTATE0 _CAN3RIER.Bits.RSTATE0
|
| 13647 |
|
|
#define CAN3RIER_RSTATE1 _CAN3RIER.Bits.RSTATE1
|
| 13648 |
|
|
#define CAN3RIER_CSCIE _CAN3RIER.Bits.CSCIE
|
| 13649 |
|
|
#define CAN3RIER_WUPIE _CAN3RIER.Bits.WUPIE
|
| 13650 |
|
|
#define CAN3RIER_TSTATE _CAN3RIER.MergedBits.grpTSTATE
|
| 13651 |
|
|
#define CAN3RIER_RSTATE _CAN3RIER.MergedBits.grpRSTATE
|
| 13652 |
|
|
|
| 13653 |
|
|
|
| 13654 |
|
|
/*** CAN3TFLG - MSCAN 3 Transmitter Flag Register; 0x00000206 ***/
|
| 13655 |
|
|
typedef union {
|
| 13656 |
|
|
byte Byte;
|
| 13657 |
|
|
struct {
|
| 13658 |
|
|
byte TXE0 :1; /* Transmitter Buffer Empty 0 */
|
| 13659 |
|
|
byte TXE1 :1; /* Transmitter Buffer Empty 1 */
|
| 13660 |
|
|
byte TXE2 :1; /* Transmitter Buffer Empty 2 */
|
| 13661 |
|
|
byte :1;
|
| 13662 |
|
|
byte :1;
|
| 13663 |
|
|
byte :1;
|
| 13664 |
|
|
byte :1;
|
| 13665 |
|
|
byte :1;
|
| 13666 |
|
|
} Bits;
|
| 13667 |
|
|
struct {
|
| 13668 |
|
|
byte grpTXE :3;
|
| 13669 |
|
|
byte :1;
|
| 13670 |
|
|
byte :1;
|
| 13671 |
|
|
byte :1;
|
| 13672 |
|
|
byte :1;
|
| 13673 |
|
|
byte :1;
|
| 13674 |
|
|
} MergedBits;
|
| 13675 |
|
|
} CAN3TFLGSTR;
|
| 13676 |
|
|
extern volatile CAN3TFLGSTR _CAN3TFLG @(REG_BASE + 0x00000206);
|
| 13677 |
|
|
#define CAN3TFLG _CAN3TFLG.Byte
|
| 13678 |
|
|
#define CAN3TFLG_TXE0 _CAN3TFLG.Bits.TXE0
|
| 13679 |
|
|
#define CAN3TFLG_TXE1 _CAN3TFLG.Bits.TXE1
|
| 13680 |
|
|
#define CAN3TFLG_TXE2 _CAN3TFLG.Bits.TXE2
|
| 13681 |
|
|
#define CAN3TFLG_TXE _CAN3TFLG.MergedBits.grpTXE
|
| 13682 |
|
|
|
| 13683 |
|
|
|
| 13684 |
|
|
/*** CAN3TIER - MSCAN 3 Transmitter Interrupt Enable Register; 0x00000207 ***/
|
| 13685 |
|
|
typedef union {
|
| 13686 |
|
|
byte Byte;
|
| 13687 |
|
|
struct {
|
| 13688 |
|
|
byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
|
| 13689 |
|
|
byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
|
| 13690 |
|
|
byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
|
| 13691 |
|
|
byte :1;
|
| 13692 |
|
|
byte :1;
|
| 13693 |
|
|
byte :1;
|
| 13694 |
|
|
byte :1;
|
| 13695 |
|
|
byte :1;
|
| 13696 |
|
|
} Bits;
|
| 13697 |
|
|
struct {
|
| 13698 |
|
|
byte grpTXEIE :3;
|
| 13699 |
|
|
byte :1;
|
| 13700 |
|
|
byte :1;
|
| 13701 |
|
|
byte :1;
|
| 13702 |
|
|
byte :1;
|
| 13703 |
|
|
byte :1;
|
| 13704 |
|
|
} MergedBits;
|
| 13705 |
|
|
} CAN3TIERSTR;
|
| 13706 |
|
|
extern volatile CAN3TIERSTR _CAN3TIER @(REG_BASE + 0x00000207);
|
| 13707 |
|
|
#define CAN3TIER _CAN3TIER.Byte
|
| 13708 |
|
|
#define CAN3TIER_TXEIE0 _CAN3TIER.Bits.TXEIE0
|
| 13709 |
|
|
#define CAN3TIER_TXEIE1 _CAN3TIER.Bits.TXEIE1
|
| 13710 |
|
|
#define CAN3TIER_TXEIE2 _CAN3TIER.Bits.TXEIE2
|
| 13711 |
|
|
#define CAN3TIER_TXEIE _CAN3TIER.MergedBits.grpTXEIE
|
| 13712 |
|
|
|
| 13713 |
|
|
|
| 13714 |
|
|
/*** CAN3TARQ - MSCAN 3 Transmitter Message Abort Request; 0x00000208 ***/
|
| 13715 |
|
|
typedef union {
|
| 13716 |
|
|
byte Byte;
|
| 13717 |
|
|
struct {
|
| 13718 |
|
|
byte ABTRQ0 :1; /* Abort Request 0 */
|
| 13719 |
|
|
byte ABTRQ1 :1; /* Abort Request 1 */
|
| 13720 |
|
|
byte ABTRQ2 :1; /* Abort Request 2 */
|
| 13721 |
|
|
byte :1;
|
| 13722 |
|
|
byte :1;
|
| 13723 |
|
|
byte :1;
|
| 13724 |
|
|
byte :1;
|
| 13725 |
|
|
byte :1;
|
| 13726 |
|
|
} Bits;
|
| 13727 |
|
|
struct {
|
| 13728 |
|
|
byte grpABTRQ :3;
|
| 13729 |
|
|
byte :1;
|
| 13730 |
|
|
byte :1;
|
| 13731 |
|
|
byte :1;
|
| 13732 |
|
|
byte :1;
|
| 13733 |
|
|
byte :1;
|
| 13734 |
|
|
} MergedBits;
|
| 13735 |
|
|
} CAN3TARQSTR;
|
| 13736 |
|
|
extern volatile CAN3TARQSTR _CAN3TARQ @(REG_BASE + 0x00000208);
|
| 13737 |
|
|
#define CAN3TARQ _CAN3TARQ.Byte
|
| 13738 |
|
|
#define CAN3TARQ_ABTRQ0 _CAN3TARQ.Bits.ABTRQ0
|
| 13739 |
|
|
#define CAN3TARQ_ABTRQ1 _CAN3TARQ.Bits.ABTRQ1
|
| 13740 |
|
|
#define CAN3TARQ_ABTRQ2 _CAN3TARQ.Bits.ABTRQ2
|
| 13741 |
|
|
#define CAN3TARQ_ABTRQ _CAN3TARQ.MergedBits.grpABTRQ
|
| 13742 |
|
|
|
| 13743 |
|
|
|
| 13744 |
|
|
/*** CAN3TAAK - MSCAN 3 Transmitter Message Abort Control; 0x00000209 ***/
|
| 13745 |
|
|
typedef union {
|
| 13746 |
|
|
byte Byte;
|
| 13747 |
|
|
struct {
|
| 13748 |
|
|
byte ABTAK0 :1; /* Abort Acknowledge 0 */
|
| 13749 |
|
|
byte ABTAK1 :1; /* Abort Acknowledge 1 */
|
| 13750 |
|
|
byte ABTAK2 :1; /* Abort Acknowledge 2 */
|
| 13751 |
|
|
byte :1;
|
| 13752 |
|
|
byte :1;
|
| 13753 |
|
|
byte :1;
|
| 13754 |
|
|
byte :1;
|
| 13755 |
|
|
byte :1;
|
| 13756 |
|
|
} Bits;
|
| 13757 |
|
|
struct {
|
| 13758 |
|
|
byte grpABTAK :3;
|
| 13759 |
|
|
byte :1;
|
| 13760 |
|
|
byte :1;
|
| 13761 |
|
|
byte :1;
|
| 13762 |
|
|
byte :1;
|
| 13763 |
|
|
byte :1;
|
| 13764 |
|
|
} MergedBits;
|
| 13765 |
|
|
} CAN3TAAKSTR;
|
| 13766 |
|
|
extern volatile CAN3TAAKSTR _CAN3TAAK @(REG_BASE + 0x00000209);
|
| 13767 |
|
|
#define CAN3TAAK _CAN3TAAK.Byte
|
| 13768 |
|
|
#define CAN3TAAK_ABTAK0 _CAN3TAAK.Bits.ABTAK0
|
| 13769 |
|
|
#define CAN3TAAK_ABTAK1 _CAN3TAAK.Bits.ABTAK1
|
| 13770 |
|
|
#define CAN3TAAK_ABTAK2 _CAN3TAAK.Bits.ABTAK2
|
| 13771 |
|
|
#define CAN3TAAK_ABTAK _CAN3TAAK.MergedBits.grpABTAK
|
| 13772 |
|
|
|
| 13773 |
|
|
|
| 13774 |
|
|
/*** CAN3TBSEL - MSCAN 3 Transmit Buffer Selection; 0x0000020A ***/
|
| 13775 |
|
|
typedef union {
|
| 13776 |
|
|
byte Byte;
|
| 13777 |
|
|
struct {
|
| 13778 |
|
|
byte TX0 :1; /* Transmit Buffer Select 0 */
|
| 13779 |
|
|
byte TX1 :1; /* Transmit Buffer Select 1 */
|
| 13780 |
|
|
byte TX2 :1; /* Transmit Buffer Select 2 */
|
| 13781 |
|
|
byte :1;
|
| 13782 |
|
|
byte :1;
|
| 13783 |
|
|
byte :1;
|
| 13784 |
|
|
byte :1;
|
| 13785 |
|
|
byte :1;
|
| 13786 |
|
|
} Bits;
|
| 13787 |
|
|
struct {
|
| 13788 |
|
|
byte grpTX :3;
|
| 13789 |
|
|
byte :1;
|
| 13790 |
|
|
byte :1;
|
| 13791 |
|
|
byte :1;
|
| 13792 |
|
|
byte :1;
|
| 13793 |
|
|
byte :1;
|
| 13794 |
|
|
} MergedBits;
|
| 13795 |
|
|
} CAN3TBSELSTR;
|
| 13796 |
|
|
extern volatile CAN3TBSELSTR _CAN3TBSEL @(REG_BASE + 0x0000020A);
|
| 13797 |
|
|
#define CAN3TBSEL _CAN3TBSEL.Byte
|
| 13798 |
|
|
#define CAN3TBSEL_TX0 _CAN3TBSEL.Bits.TX0
|
| 13799 |
|
|
#define CAN3TBSEL_TX1 _CAN3TBSEL.Bits.TX1
|
| 13800 |
|
|
#define CAN3TBSEL_TX2 _CAN3TBSEL.Bits.TX2
|
| 13801 |
|
|
#define CAN3TBSEL_TX _CAN3TBSEL.MergedBits.grpTX
|
| 13802 |
|
|
|
| 13803 |
|
|
|
| 13804 |
|
|
/*** CAN3IDAC - MSCAN 3 Identifier Acceptance Control Register; 0x0000020B ***/
|
| 13805 |
|
|
typedef union {
|
| 13806 |
|
|
byte Byte;
|
| 13807 |
|
|
struct {
|
| 13808 |
|
|
byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
|
| 13809 |
|
|
byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
|
| 13810 |
|
|
byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
|
| 13811 |
|
|
byte :1;
|
| 13812 |
|
|
byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
|
| 13813 |
|
|
byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
|
| 13814 |
|
|
byte :1;
|
| 13815 |
|
|
byte :1;
|
| 13816 |
|
|
} Bits;
|
| 13817 |
|
|
struct {
|
| 13818 |
|
|
byte grpIDHIT :3;
|
| 13819 |
|
|
byte :1;
|
| 13820 |
|
|
byte grpIDAM :2;
|
| 13821 |
|
|
byte :1;
|
| 13822 |
|
|
byte :1;
|
| 13823 |
|
|
} MergedBits;
|
| 13824 |
|
|
} CAN3IDACSTR;
|
| 13825 |
|
|
extern volatile CAN3IDACSTR _CAN3IDAC @(REG_BASE + 0x0000020B);
|
| 13826 |
|
|
#define CAN3IDAC _CAN3IDAC.Byte
|
| 13827 |
|
|
#define CAN3IDAC_IDHIT0 _CAN3IDAC.Bits.IDHIT0
|
| 13828 |
|
|
#define CAN3IDAC_IDHIT1 _CAN3IDAC.Bits.IDHIT1
|
| 13829 |
|
|
#define CAN3IDAC_IDHIT2 _CAN3IDAC.Bits.IDHIT2
|
| 13830 |
|
|
#define CAN3IDAC_IDAM0 _CAN3IDAC.Bits.IDAM0
|
| 13831 |
|
|
#define CAN3IDAC_IDAM1 _CAN3IDAC.Bits.IDAM1
|
| 13832 |
|
|
#define CAN3IDAC_IDHIT _CAN3IDAC.MergedBits.grpIDHIT
|
| 13833 |
|
|
#define CAN3IDAC_IDAM _CAN3IDAC.MergedBits.grpIDAM
|
| 13834 |
|
|
|
| 13835 |
|
|
|
| 13836 |
|
|
/*** CAN3RXERR - MSCAN 3 Receive Error Counter Register; 0x0000020E ***/
|
| 13837 |
|
|
typedef union {
|
| 13838 |
|
|
byte Byte;
|
| 13839 |
|
|
struct {
|
| 13840 |
|
|
byte RXERR0 :1; /* Bit 0 */
|
| 13841 |
|
|
byte RXERR1 :1; /* Bit 1 */
|
| 13842 |
|
|
byte RXERR2 :1; /* Bit 2 */
|
| 13843 |
|
|
byte RXERR3 :1; /* Bit 3 */
|
| 13844 |
|
|
byte RXERR4 :1; /* Bit 4 */
|
| 13845 |
|
|
byte RXERR5 :1; /* Bit 5 */
|
| 13846 |
|
|
byte RXERR6 :1; /* Bit 6 */
|
| 13847 |
|
|
byte RXERR7 :1; /* Bit 7 */
|
| 13848 |
|
|
} Bits;
|
| 13849 |
|
|
struct {
|
| 13850 |
|
|
byte grpRXERR :8;
|
| 13851 |
|
|
} MergedBits;
|
| 13852 |
|
|
} CAN3RXERRSTR;
|
| 13853 |
|
|
extern volatile CAN3RXERRSTR _CAN3RXERR @(REG_BASE + 0x0000020E);
|
| 13854 |
|
|
#define CAN3RXERR _CAN3RXERR.Byte
|
| 13855 |
|
|
#define CAN3RXERR_RXERR0 _CAN3RXERR.Bits.RXERR0
|
| 13856 |
|
|
#define CAN3RXERR_RXERR1 _CAN3RXERR.Bits.RXERR1
|
| 13857 |
|
|
#define CAN3RXERR_RXERR2 _CAN3RXERR.Bits.RXERR2
|
| 13858 |
|
|
#define CAN3RXERR_RXERR3 _CAN3RXERR.Bits.RXERR3
|
| 13859 |
|
|
#define CAN3RXERR_RXERR4 _CAN3RXERR.Bits.RXERR4
|
| 13860 |
|
|
#define CAN3RXERR_RXERR5 _CAN3RXERR.Bits.RXERR5
|
| 13861 |
|
|
#define CAN3RXERR_RXERR6 _CAN3RXERR.Bits.RXERR6
|
| 13862 |
|
|
#define CAN3RXERR_RXERR7 _CAN3RXERR.Bits.RXERR7
|
| 13863 |
|
|
#define CAN3RXERR_RXERR _CAN3RXERR.MergedBits.grpRXERR
|
| 13864 |
|
|
|
| 13865 |
|
|
|
| 13866 |
|
|
/*** CAN3TXERR - MSCAN 3 Transmit Error Counter Register; 0x0000020F ***/
|
| 13867 |
|
|
typedef union {
|
| 13868 |
|
|
byte Byte;
|
| 13869 |
|
|
struct {
|
| 13870 |
|
|
byte TXERR0 :1; /* Bit 0 */
|
| 13871 |
|
|
byte TXERR1 :1; /* Bit 1 */
|
| 13872 |
|
|
byte TXERR2 :1; /* Bit 2 */
|
| 13873 |
|
|
byte TXERR3 :1; /* Bit 3 */
|
| 13874 |
|
|
byte TXERR4 :1; /* Bit 4 */
|
| 13875 |
|
|
byte TXERR5 :1; /* Bit 5 */
|
| 13876 |
|
|
byte TXERR6 :1; /* Bit 6 */
|
| 13877 |
|
|
byte TXERR7 :1; /* Bit 7 */
|
| 13878 |
|
|
} Bits;
|
| 13879 |
|
|
struct {
|
| 13880 |
|
|
byte grpTXERR :8;
|
| 13881 |
|
|
} MergedBits;
|
| 13882 |
|
|
} CAN3TXERRSTR;
|
| 13883 |
|
|
extern volatile CAN3TXERRSTR _CAN3TXERR @(REG_BASE + 0x0000020F);
|
| 13884 |
|
|
#define CAN3TXERR _CAN3TXERR.Byte
|
| 13885 |
|
|
#define CAN3TXERR_TXERR0 _CAN3TXERR.Bits.TXERR0
|
| 13886 |
|
|
#define CAN3TXERR_TXERR1 _CAN3TXERR.Bits.TXERR1
|
| 13887 |
|
|
#define CAN3TXERR_TXERR2 _CAN3TXERR.Bits.TXERR2
|
| 13888 |
|
|
#define CAN3TXERR_TXERR3 _CAN3TXERR.Bits.TXERR3
|
| 13889 |
|
|
#define CAN3TXERR_TXERR4 _CAN3TXERR.Bits.TXERR4
|
| 13890 |
|
|
#define CAN3TXERR_TXERR5 _CAN3TXERR.Bits.TXERR5
|
| 13891 |
|
|
#define CAN3TXERR_TXERR6 _CAN3TXERR.Bits.TXERR6
|
| 13892 |
|
|
#define CAN3TXERR_TXERR7 _CAN3TXERR.Bits.TXERR7
|
| 13893 |
|
|
#define CAN3TXERR_TXERR _CAN3TXERR.MergedBits.grpTXERR
|
| 13894 |
|
|
|
| 13895 |
|
|
|
| 13896 |
|
|
/*** CAN3IDAR0 - MSCAN 3 Identifier Acceptance Register 0; 0x00000210 ***/
|
| 13897 |
|
|
typedef union {
|
| 13898 |
|
|
byte Byte;
|
| 13899 |
|
|
struct {
|
| 13900 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 13901 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 13902 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 13903 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 13904 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 13905 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 13906 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 13907 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 13908 |
|
|
} Bits;
|
| 13909 |
|
|
struct {
|
| 13910 |
|
|
byte grpAC :8;
|
| 13911 |
|
|
} MergedBits;
|
| 13912 |
|
|
} CAN3IDAR0STR;
|
| 13913 |
|
|
extern volatile CAN3IDAR0STR _CAN3IDAR0 @(REG_BASE + 0x00000210);
|
| 13914 |
|
|
#define CAN3IDAR0 _CAN3IDAR0.Byte
|
| 13915 |
|
|
#define CAN3IDAR0_AC0 _CAN3IDAR0.Bits.AC0
|
| 13916 |
|
|
#define CAN3IDAR0_AC1 _CAN3IDAR0.Bits.AC1
|
| 13917 |
|
|
#define CAN3IDAR0_AC2 _CAN3IDAR0.Bits.AC2
|
| 13918 |
|
|
#define CAN3IDAR0_AC3 _CAN3IDAR0.Bits.AC3
|
| 13919 |
|
|
#define CAN3IDAR0_AC4 _CAN3IDAR0.Bits.AC4
|
| 13920 |
|
|
#define CAN3IDAR0_AC5 _CAN3IDAR0.Bits.AC5
|
| 13921 |
|
|
#define CAN3IDAR0_AC6 _CAN3IDAR0.Bits.AC6
|
| 13922 |
|
|
#define CAN3IDAR0_AC7 _CAN3IDAR0.Bits.AC7
|
| 13923 |
|
|
#define CAN3IDAR0_AC _CAN3IDAR0.MergedBits.grpAC
|
| 13924 |
|
|
|
| 13925 |
|
|
|
| 13926 |
|
|
/*** CAN3IDAR1 - MSCAN 3 Identifier Acceptance Register 1; 0x00000211 ***/
|
| 13927 |
|
|
typedef union {
|
| 13928 |
|
|
byte Byte;
|
| 13929 |
|
|
struct {
|
| 13930 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 13931 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 13932 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 13933 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 13934 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 13935 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 13936 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 13937 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 13938 |
|
|
} Bits;
|
| 13939 |
|
|
struct {
|
| 13940 |
|
|
byte grpAC :8;
|
| 13941 |
|
|
} MergedBits;
|
| 13942 |
|
|
} CAN3IDAR1STR;
|
| 13943 |
|
|
extern volatile CAN3IDAR1STR _CAN3IDAR1 @(REG_BASE + 0x00000211);
|
| 13944 |
|
|
#define CAN3IDAR1 _CAN3IDAR1.Byte
|
| 13945 |
|
|
#define CAN3IDAR1_AC0 _CAN3IDAR1.Bits.AC0
|
| 13946 |
|
|
#define CAN3IDAR1_AC1 _CAN3IDAR1.Bits.AC1
|
| 13947 |
|
|
#define CAN3IDAR1_AC2 _CAN3IDAR1.Bits.AC2
|
| 13948 |
|
|
#define CAN3IDAR1_AC3 _CAN3IDAR1.Bits.AC3
|
| 13949 |
|
|
#define CAN3IDAR1_AC4 _CAN3IDAR1.Bits.AC4
|
| 13950 |
|
|
#define CAN3IDAR1_AC5 _CAN3IDAR1.Bits.AC5
|
| 13951 |
|
|
#define CAN3IDAR1_AC6 _CAN3IDAR1.Bits.AC6
|
| 13952 |
|
|
#define CAN3IDAR1_AC7 _CAN3IDAR1.Bits.AC7
|
| 13953 |
|
|
#define CAN3IDAR1_AC _CAN3IDAR1.MergedBits.grpAC
|
| 13954 |
|
|
|
| 13955 |
|
|
|
| 13956 |
|
|
/*** CAN3IDAR2 - MSCAN 3 Identifier Acceptance Register 2; 0x00000212 ***/
|
| 13957 |
|
|
typedef union {
|
| 13958 |
|
|
byte Byte;
|
| 13959 |
|
|
struct {
|
| 13960 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 13961 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 13962 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 13963 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 13964 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 13965 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 13966 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 13967 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 13968 |
|
|
} Bits;
|
| 13969 |
|
|
struct {
|
| 13970 |
|
|
byte grpAC :8;
|
| 13971 |
|
|
} MergedBits;
|
| 13972 |
|
|
} CAN3IDAR2STR;
|
| 13973 |
|
|
extern volatile CAN3IDAR2STR _CAN3IDAR2 @(REG_BASE + 0x00000212);
|
| 13974 |
|
|
#define CAN3IDAR2 _CAN3IDAR2.Byte
|
| 13975 |
|
|
#define CAN3IDAR2_AC0 _CAN3IDAR2.Bits.AC0
|
| 13976 |
|
|
#define CAN3IDAR2_AC1 _CAN3IDAR2.Bits.AC1
|
| 13977 |
|
|
#define CAN3IDAR2_AC2 _CAN3IDAR2.Bits.AC2
|
| 13978 |
|
|
#define CAN3IDAR2_AC3 _CAN3IDAR2.Bits.AC3
|
| 13979 |
|
|
#define CAN3IDAR2_AC4 _CAN3IDAR2.Bits.AC4
|
| 13980 |
|
|
#define CAN3IDAR2_AC5 _CAN3IDAR2.Bits.AC5
|
| 13981 |
|
|
#define CAN3IDAR2_AC6 _CAN3IDAR2.Bits.AC6
|
| 13982 |
|
|
#define CAN3IDAR2_AC7 _CAN3IDAR2.Bits.AC7
|
| 13983 |
|
|
#define CAN3IDAR2_AC _CAN3IDAR2.MergedBits.grpAC
|
| 13984 |
|
|
|
| 13985 |
|
|
|
| 13986 |
|
|
/*** CAN3IDAR3 - MSCAN 3 Identifier Acceptance Register 3; 0x00000213 ***/
|
| 13987 |
|
|
typedef union {
|
| 13988 |
|
|
byte Byte;
|
| 13989 |
|
|
struct {
|
| 13990 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 13991 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 13992 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 13993 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 13994 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 13995 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 13996 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 13997 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 13998 |
|
|
} Bits;
|
| 13999 |
|
|
struct {
|
| 14000 |
|
|
byte grpAC :8;
|
| 14001 |
|
|
} MergedBits;
|
| 14002 |
|
|
} CAN3IDAR3STR;
|
| 14003 |
|
|
extern volatile CAN3IDAR3STR _CAN3IDAR3 @(REG_BASE + 0x00000213);
|
| 14004 |
|
|
#define CAN3IDAR3 _CAN3IDAR3.Byte
|
| 14005 |
|
|
#define CAN3IDAR3_AC0 _CAN3IDAR3.Bits.AC0
|
| 14006 |
|
|
#define CAN3IDAR3_AC1 _CAN3IDAR3.Bits.AC1
|
| 14007 |
|
|
#define CAN3IDAR3_AC2 _CAN3IDAR3.Bits.AC2
|
| 14008 |
|
|
#define CAN3IDAR3_AC3 _CAN3IDAR3.Bits.AC3
|
| 14009 |
|
|
#define CAN3IDAR3_AC4 _CAN3IDAR3.Bits.AC4
|
| 14010 |
|
|
#define CAN3IDAR3_AC5 _CAN3IDAR3.Bits.AC5
|
| 14011 |
|
|
#define CAN3IDAR3_AC6 _CAN3IDAR3.Bits.AC6
|
| 14012 |
|
|
#define CAN3IDAR3_AC7 _CAN3IDAR3.Bits.AC7
|
| 14013 |
|
|
#define CAN3IDAR3_AC _CAN3IDAR3.MergedBits.grpAC
|
| 14014 |
|
|
|
| 14015 |
|
|
|
| 14016 |
|
|
/*** CAN3IDMR0 - MSCAN 3 Identifier Mask Register 0; 0x00000214 ***/
|
| 14017 |
|
|
typedef union {
|
| 14018 |
|
|
byte Byte;
|
| 14019 |
|
|
struct {
|
| 14020 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 14021 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 14022 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 14023 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 14024 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 14025 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 14026 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 14027 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 14028 |
|
|
} Bits;
|
| 14029 |
|
|
struct {
|
| 14030 |
|
|
byte grpAM :8;
|
| 14031 |
|
|
} MergedBits;
|
| 14032 |
|
|
} CAN3IDMR0STR;
|
| 14033 |
|
|
extern volatile CAN3IDMR0STR _CAN3IDMR0 @(REG_BASE + 0x00000214);
|
| 14034 |
|
|
#define CAN3IDMR0 _CAN3IDMR0.Byte
|
| 14035 |
|
|
#define CAN3IDMR0_AM0 _CAN3IDMR0.Bits.AM0
|
| 14036 |
|
|
#define CAN3IDMR0_AM1 _CAN3IDMR0.Bits.AM1
|
| 14037 |
|
|
#define CAN3IDMR0_AM2 _CAN3IDMR0.Bits.AM2
|
| 14038 |
|
|
#define CAN3IDMR0_AM3 _CAN3IDMR0.Bits.AM3
|
| 14039 |
|
|
#define CAN3IDMR0_AM4 _CAN3IDMR0.Bits.AM4
|
| 14040 |
|
|
#define CAN3IDMR0_AM5 _CAN3IDMR0.Bits.AM5
|
| 14041 |
|
|
#define CAN3IDMR0_AM6 _CAN3IDMR0.Bits.AM6
|
| 14042 |
|
|
#define CAN3IDMR0_AM7 _CAN3IDMR0.Bits.AM7
|
| 14043 |
|
|
#define CAN3IDMR0_AM _CAN3IDMR0.MergedBits.grpAM
|
| 14044 |
|
|
|
| 14045 |
|
|
|
| 14046 |
|
|
/*** CAN3IDMR1 - MSCAN 3 Identifier Mask Register 1; 0x00000215 ***/
|
| 14047 |
|
|
typedef union {
|
| 14048 |
|
|
byte Byte;
|
| 14049 |
|
|
struct {
|
| 14050 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 14051 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 14052 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 14053 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 14054 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 14055 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 14056 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 14057 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 14058 |
|
|
} Bits;
|
| 14059 |
|
|
struct {
|
| 14060 |
|
|
byte grpAM :8;
|
| 14061 |
|
|
} MergedBits;
|
| 14062 |
|
|
} CAN3IDMR1STR;
|
| 14063 |
|
|
extern volatile CAN3IDMR1STR _CAN3IDMR1 @(REG_BASE + 0x00000215);
|
| 14064 |
|
|
#define CAN3IDMR1 _CAN3IDMR1.Byte
|
| 14065 |
|
|
#define CAN3IDMR1_AM0 _CAN3IDMR1.Bits.AM0
|
| 14066 |
|
|
#define CAN3IDMR1_AM1 _CAN3IDMR1.Bits.AM1
|
| 14067 |
|
|
#define CAN3IDMR1_AM2 _CAN3IDMR1.Bits.AM2
|
| 14068 |
|
|
#define CAN3IDMR1_AM3 _CAN3IDMR1.Bits.AM3
|
| 14069 |
|
|
#define CAN3IDMR1_AM4 _CAN3IDMR1.Bits.AM4
|
| 14070 |
|
|
#define CAN3IDMR1_AM5 _CAN3IDMR1.Bits.AM5
|
| 14071 |
|
|
#define CAN3IDMR1_AM6 _CAN3IDMR1.Bits.AM6
|
| 14072 |
|
|
#define CAN3IDMR1_AM7 _CAN3IDMR1.Bits.AM7
|
| 14073 |
|
|
#define CAN3IDMR1_AM _CAN3IDMR1.MergedBits.grpAM
|
| 14074 |
|
|
|
| 14075 |
|
|
|
| 14076 |
|
|
/*** CAN3IDMR2 - MSCAN 3 Identifier Mask Register 2; 0x00000216 ***/
|
| 14077 |
|
|
typedef union {
|
| 14078 |
|
|
byte Byte;
|
| 14079 |
|
|
struct {
|
| 14080 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 14081 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 14082 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 14083 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 14084 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 14085 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 14086 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 14087 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 14088 |
|
|
} Bits;
|
| 14089 |
|
|
struct {
|
| 14090 |
|
|
byte grpAM :8;
|
| 14091 |
|
|
} MergedBits;
|
| 14092 |
|
|
} CAN3IDMR2STR;
|
| 14093 |
|
|
extern volatile CAN3IDMR2STR _CAN3IDMR2 @(REG_BASE + 0x00000216);
|
| 14094 |
|
|
#define CAN3IDMR2 _CAN3IDMR2.Byte
|
| 14095 |
|
|
#define CAN3IDMR2_AM0 _CAN3IDMR2.Bits.AM0
|
| 14096 |
|
|
#define CAN3IDMR2_AM1 _CAN3IDMR2.Bits.AM1
|
| 14097 |
|
|
#define CAN3IDMR2_AM2 _CAN3IDMR2.Bits.AM2
|
| 14098 |
|
|
#define CAN3IDMR2_AM3 _CAN3IDMR2.Bits.AM3
|
| 14099 |
|
|
#define CAN3IDMR2_AM4 _CAN3IDMR2.Bits.AM4
|
| 14100 |
|
|
#define CAN3IDMR2_AM5 _CAN3IDMR2.Bits.AM5
|
| 14101 |
|
|
#define CAN3IDMR2_AM6 _CAN3IDMR2.Bits.AM6
|
| 14102 |
|
|
#define CAN3IDMR2_AM7 _CAN3IDMR2.Bits.AM7
|
| 14103 |
|
|
#define CAN3IDMR2_AM _CAN3IDMR2.MergedBits.grpAM
|
| 14104 |
|
|
|
| 14105 |
|
|
|
| 14106 |
|
|
/*** CAN3IDMR3 - MSCAN 3 Identifier Mask Register 3; 0x00000217 ***/
|
| 14107 |
|
|
typedef union {
|
| 14108 |
|
|
byte Byte;
|
| 14109 |
|
|
struct {
|
| 14110 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 14111 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 14112 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 14113 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 14114 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 14115 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 14116 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 14117 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 14118 |
|
|
} Bits;
|
| 14119 |
|
|
struct {
|
| 14120 |
|
|
byte grpAM :8;
|
| 14121 |
|
|
} MergedBits;
|
| 14122 |
|
|
} CAN3IDMR3STR;
|
| 14123 |
|
|
extern volatile CAN3IDMR3STR _CAN3IDMR3 @(REG_BASE + 0x00000217);
|
| 14124 |
|
|
#define CAN3IDMR3 _CAN3IDMR3.Byte
|
| 14125 |
|
|
#define CAN3IDMR3_AM0 _CAN3IDMR3.Bits.AM0
|
| 14126 |
|
|
#define CAN3IDMR3_AM1 _CAN3IDMR3.Bits.AM1
|
| 14127 |
|
|
#define CAN3IDMR3_AM2 _CAN3IDMR3.Bits.AM2
|
| 14128 |
|
|
#define CAN3IDMR3_AM3 _CAN3IDMR3.Bits.AM3
|
| 14129 |
|
|
#define CAN3IDMR3_AM4 _CAN3IDMR3.Bits.AM4
|
| 14130 |
|
|
#define CAN3IDMR3_AM5 _CAN3IDMR3.Bits.AM5
|
| 14131 |
|
|
#define CAN3IDMR3_AM6 _CAN3IDMR3.Bits.AM6
|
| 14132 |
|
|
#define CAN3IDMR3_AM7 _CAN3IDMR3.Bits.AM7
|
| 14133 |
|
|
#define CAN3IDMR3_AM _CAN3IDMR3.MergedBits.grpAM
|
| 14134 |
|
|
|
| 14135 |
|
|
|
| 14136 |
|
|
/*** CAN3IDAR4 - MSCAN 3 Identifier Acceptance Register 4; 0x00000218 ***/
|
| 14137 |
|
|
typedef union {
|
| 14138 |
|
|
byte Byte;
|
| 14139 |
|
|
struct {
|
| 14140 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 14141 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 14142 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 14143 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 14144 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 14145 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 14146 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 14147 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 14148 |
|
|
} Bits;
|
| 14149 |
|
|
struct {
|
| 14150 |
|
|
byte grpAC :8;
|
| 14151 |
|
|
} MergedBits;
|
| 14152 |
|
|
} CAN3IDAR4STR;
|
| 14153 |
|
|
extern volatile CAN3IDAR4STR _CAN3IDAR4 @(REG_BASE + 0x00000218);
|
| 14154 |
|
|
#define CAN3IDAR4 _CAN3IDAR4.Byte
|
| 14155 |
|
|
#define CAN3IDAR4_AC0 _CAN3IDAR4.Bits.AC0
|
| 14156 |
|
|
#define CAN3IDAR4_AC1 _CAN3IDAR4.Bits.AC1
|
| 14157 |
|
|
#define CAN3IDAR4_AC2 _CAN3IDAR4.Bits.AC2
|
| 14158 |
|
|
#define CAN3IDAR4_AC3 _CAN3IDAR4.Bits.AC3
|
| 14159 |
|
|
#define CAN3IDAR4_AC4 _CAN3IDAR4.Bits.AC4
|
| 14160 |
|
|
#define CAN3IDAR4_AC5 _CAN3IDAR4.Bits.AC5
|
| 14161 |
|
|
#define CAN3IDAR4_AC6 _CAN3IDAR4.Bits.AC6
|
| 14162 |
|
|
#define CAN3IDAR4_AC7 _CAN3IDAR4.Bits.AC7
|
| 14163 |
|
|
#define CAN3IDAR4_AC _CAN3IDAR4.MergedBits.grpAC
|
| 14164 |
|
|
|
| 14165 |
|
|
|
| 14166 |
|
|
/*** CAN3IDAR5 - MSCAN 3 Identifier Acceptance Register 5; 0x00000219 ***/
|
| 14167 |
|
|
typedef union {
|
| 14168 |
|
|
byte Byte;
|
| 14169 |
|
|
struct {
|
| 14170 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 14171 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 14172 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 14173 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 14174 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 14175 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 14176 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 14177 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 14178 |
|
|
} Bits;
|
| 14179 |
|
|
struct {
|
| 14180 |
|
|
byte grpAC :8;
|
| 14181 |
|
|
} MergedBits;
|
| 14182 |
|
|
} CAN3IDAR5STR;
|
| 14183 |
|
|
extern volatile CAN3IDAR5STR _CAN3IDAR5 @(REG_BASE + 0x00000219);
|
| 14184 |
|
|
#define CAN3IDAR5 _CAN3IDAR5.Byte
|
| 14185 |
|
|
#define CAN3IDAR5_AC0 _CAN3IDAR5.Bits.AC0
|
| 14186 |
|
|
#define CAN3IDAR5_AC1 _CAN3IDAR5.Bits.AC1
|
| 14187 |
|
|
#define CAN3IDAR5_AC2 _CAN3IDAR5.Bits.AC2
|
| 14188 |
|
|
#define CAN3IDAR5_AC3 _CAN3IDAR5.Bits.AC3
|
| 14189 |
|
|
#define CAN3IDAR5_AC4 _CAN3IDAR5.Bits.AC4
|
| 14190 |
|
|
#define CAN3IDAR5_AC5 _CAN3IDAR5.Bits.AC5
|
| 14191 |
|
|
#define CAN3IDAR5_AC6 _CAN3IDAR5.Bits.AC6
|
| 14192 |
|
|
#define CAN3IDAR5_AC7 _CAN3IDAR5.Bits.AC7
|
| 14193 |
|
|
#define CAN3IDAR5_AC _CAN3IDAR5.MergedBits.grpAC
|
| 14194 |
|
|
|
| 14195 |
|
|
|
| 14196 |
|
|
/*** CAN3IDAR6 - MSCAN 3 Identifier Acceptance Register 6; 0x0000021A ***/
|
| 14197 |
|
|
typedef union {
|
| 14198 |
|
|
byte Byte;
|
| 14199 |
|
|
struct {
|
| 14200 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 14201 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 14202 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 14203 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 14204 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 14205 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 14206 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 14207 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 14208 |
|
|
} Bits;
|
| 14209 |
|
|
struct {
|
| 14210 |
|
|
byte grpAC :8;
|
| 14211 |
|
|
} MergedBits;
|
| 14212 |
|
|
} CAN3IDAR6STR;
|
| 14213 |
|
|
extern volatile CAN3IDAR6STR _CAN3IDAR6 @(REG_BASE + 0x0000021A);
|
| 14214 |
|
|
#define CAN3IDAR6 _CAN3IDAR6.Byte
|
| 14215 |
|
|
#define CAN3IDAR6_AC0 _CAN3IDAR6.Bits.AC0
|
| 14216 |
|
|
#define CAN3IDAR6_AC1 _CAN3IDAR6.Bits.AC1
|
| 14217 |
|
|
#define CAN3IDAR6_AC2 _CAN3IDAR6.Bits.AC2
|
| 14218 |
|
|
#define CAN3IDAR6_AC3 _CAN3IDAR6.Bits.AC3
|
| 14219 |
|
|
#define CAN3IDAR6_AC4 _CAN3IDAR6.Bits.AC4
|
| 14220 |
|
|
#define CAN3IDAR6_AC5 _CAN3IDAR6.Bits.AC5
|
| 14221 |
|
|
#define CAN3IDAR6_AC6 _CAN3IDAR6.Bits.AC6
|
| 14222 |
|
|
#define CAN3IDAR6_AC7 _CAN3IDAR6.Bits.AC7
|
| 14223 |
|
|
#define CAN3IDAR6_AC _CAN3IDAR6.MergedBits.grpAC
|
| 14224 |
|
|
|
| 14225 |
|
|
|
| 14226 |
|
|
/*** CAN3IDAR7 - MSCAN 3 Identifier Acceptance Register 7; 0x0000021B ***/
|
| 14227 |
|
|
typedef union {
|
| 14228 |
|
|
byte Byte;
|
| 14229 |
|
|
struct {
|
| 14230 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 14231 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 14232 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 14233 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 14234 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 14235 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 14236 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 14237 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 14238 |
|
|
} Bits;
|
| 14239 |
|
|
struct {
|
| 14240 |
|
|
byte grpAC :8;
|
| 14241 |
|
|
} MergedBits;
|
| 14242 |
|
|
} CAN3IDAR7STR;
|
| 14243 |
|
|
extern volatile CAN3IDAR7STR _CAN3IDAR7 @(REG_BASE + 0x0000021B);
|
| 14244 |
|
|
#define CAN3IDAR7 _CAN3IDAR7.Byte
|
| 14245 |
|
|
#define CAN3IDAR7_AC0 _CAN3IDAR7.Bits.AC0
|
| 14246 |
|
|
#define CAN3IDAR7_AC1 _CAN3IDAR7.Bits.AC1
|
| 14247 |
|
|
#define CAN3IDAR7_AC2 _CAN3IDAR7.Bits.AC2
|
| 14248 |
|
|
#define CAN3IDAR7_AC3 _CAN3IDAR7.Bits.AC3
|
| 14249 |
|
|
#define CAN3IDAR7_AC4 _CAN3IDAR7.Bits.AC4
|
| 14250 |
|
|
#define CAN3IDAR7_AC5 _CAN3IDAR7.Bits.AC5
|
| 14251 |
|
|
#define CAN3IDAR7_AC6 _CAN3IDAR7.Bits.AC6
|
| 14252 |
|
|
#define CAN3IDAR7_AC7 _CAN3IDAR7.Bits.AC7
|
| 14253 |
|
|
#define CAN3IDAR7_AC _CAN3IDAR7.MergedBits.grpAC
|
| 14254 |
|
|
|
| 14255 |
|
|
|
| 14256 |
|
|
/*** CAN3IDMR4 - MSCAN 3 Identifier Mask Register 4; 0x0000021C ***/
|
| 14257 |
|
|
typedef union {
|
| 14258 |
|
|
byte Byte;
|
| 14259 |
|
|
struct {
|
| 14260 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 14261 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 14262 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 14263 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 14264 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 14265 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 14266 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 14267 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 14268 |
|
|
} Bits;
|
| 14269 |
|
|
struct {
|
| 14270 |
|
|
byte grpAM :8;
|
| 14271 |
|
|
} MergedBits;
|
| 14272 |
|
|
} CAN3IDMR4STR;
|
| 14273 |
|
|
extern volatile CAN3IDMR4STR _CAN3IDMR4 @(REG_BASE + 0x0000021C);
|
| 14274 |
|
|
#define CAN3IDMR4 _CAN3IDMR4.Byte
|
| 14275 |
|
|
#define CAN3IDMR4_AM0 _CAN3IDMR4.Bits.AM0
|
| 14276 |
|
|
#define CAN3IDMR4_AM1 _CAN3IDMR4.Bits.AM1
|
| 14277 |
|
|
#define CAN3IDMR4_AM2 _CAN3IDMR4.Bits.AM2
|
| 14278 |
|
|
#define CAN3IDMR4_AM3 _CAN3IDMR4.Bits.AM3
|
| 14279 |
|
|
#define CAN3IDMR4_AM4 _CAN3IDMR4.Bits.AM4
|
| 14280 |
|
|
#define CAN3IDMR4_AM5 _CAN3IDMR4.Bits.AM5
|
| 14281 |
|
|
#define CAN3IDMR4_AM6 _CAN3IDMR4.Bits.AM6
|
| 14282 |
|
|
#define CAN3IDMR4_AM7 _CAN3IDMR4.Bits.AM7
|
| 14283 |
|
|
#define CAN3IDMR4_AM _CAN3IDMR4.MergedBits.grpAM
|
| 14284 |
|
|
|
| 14285 |
|
|
|
| 14286 |
|
|
/*** CAN3IDMR5 - MSCAN 3 Identifier Mask Register 5; 0x0000021D ***/
|
| 14287 |
|
|
typedef union {
|
| 14288 |
|
|
byte Byte;
|
| 14289 |
|
|
struct {
|
| 14290 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 14291 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 14292 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 14293 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 14294 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 14295 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 14296 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 14297 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 14298 |
|
|
} Bits;
|
| 14299 |
|
|
struct {
|
| 14300 |
|
|
byte grpAM :8;
|
| 14301 |
|
|
} MergedBits;
|
| 14302 |
|
|
} CAN3IDMR5STR;
|
| 14303 |
|
|
extern volatile CAN3IDMR5STR _CAN3IDMR5 @(REG_BASE + 0x0000021D);
|
| 14304 |
|
|
#define CAN3IDMR5 _CAN3IDMR5.Byte
|
| 14305 |
|
|
#define CAN3IDMR5_AM0 _CAN3IDMR5.Bits.AM0
|
| 14306 |
|
|
#define CAN3IDMR5_AM1 _CAN3IDMR5.Bits.AM1
|
| 14307 |
|
|
#define CAN3IDMR5_AM2 _CAN3IDMR5.Bits.AM2
|
| 14308 |
|
|
#define CAN3IDMR5_AM3 _CAN3IDMR5.Bits.AM3
|
| 14309 |
|
|
#define CAN3IDMR5_AM4 _CAN3IDMR5.Bits.AM4
|
| 14310 |
|
|
#define CAN3IDMR5_AM5 _CAN3IDMR5.Bits.AM5
|
| 14311 |
|
|
#define CAN3IDMR5_AM6 _CAN3IDMR5.Bits.AM6
|
| 14312 |
|
|
#define CAN3IDMR5_AM7 _CAN3IDMR5.Bits.AM7
|
| 14313 |
|
|
#define CAN3IDMR5_AM _CAN3IDMR5.MergedBits.grpAM
|
| 14314 |
|
|
|
| 14315 |
|
|
|
| 14316 |
|
|
/*** CAN3IDMR6 - MSCAN 3 Identifier Mask Register 6; 0x0000021E ***/
|
| 14317 |
|
|
typedef union {
|
| 14318 |
|
|
byte Byte;
|
| 14319 |
|
|
struct {
|
| 14320 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 14321 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 14322 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 14323 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 14324 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 14325 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 14326 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 14327 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 14328 |
|
|
} Bits;
|
| 14329 |
|
|
struct {
|
| 14330 |
|
|
byte grpAM :8;
|
| 14331 |
|
|
} MergedBits;
|
| 14332 |
|
|
} CAN3IDMR6STR;
|
| 14333 |
|
|
extern volatile CAN3IDMR6STR _CAN3IDMR6 @(REG_BASE + 0x0000021E);
|
| 14334 |
|
|
#define CAN3IDMR6 _CAN3IDMR6.Byte
|
| 14335 |
|
|
#define CAN3IDMR6_AM0 _CAN3IDMR6.Bits.AM0
|
| 14336 |
|
|
#define CAN3IDMR6_AM1 _CAN3IDMR6.Bits.AM1
|
| 14337 |
|
|
#define CAN3IDMR6_AM2 _CAN3IDMR6.Bits.AM2
|
| 14338 |
|
|
#define CAN3IDMR6_AM3 _CAN3IDMR6.Bits.AM3
|
| 14339 |
|
|
#define CAN3IDMR6_AM4 _CAN3IDMR6.Bits.AM4
|
| 14340 |
|
|
#define CAN3IDMR6_AM5 _CAN3IDMR6.Bits.AM5
|
| 14341 |
|
|
#define CAN3IDMR6_AM6 _CAN3IDMR6.Bits.AM6
|
| 14342 |
|
|
#define CAN3IDMR6_AM7 _CAN3IDMR6.Bits.AM7
|
| 14343 |
|
|
#define CAN3IDMR6_AM _CAN3IDMR6.MergedBits.grpAM
|
| 14344 |
|
|
|
| 14345 |
|
|
|
| 14346 |
|
|
/*** CAN3IDMR7 - MSCAN 3 Identifier Mask Register 7; 0x0000021F ***/
|
| 14347 |
|
|
typedef union {
|
| 14348 |
|
|
byte Byte;
|
| 14349 |
|
|
struct {
|
| 14350 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 14351 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 14352 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 14353 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 14354 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 14355 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 14356 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 14357 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 14358 |
|
|
} Bits;
|
| 14359 |
|
|
struct {
|
| 14360 |
|
|
byte grpAM :8;
|
| 14361 |
|
|
} MergedBits;
|
| 14362 |
|
|
} CAN3IDMR7STR;
|
| 14363 |
|
|
extern volatile CAN3IDMR7STR _CAN3IDMR7 @(REG_BASE + 0x0000021F);
|
| 14364 |
|
|
#define CAN3IDMR7 _CAN3IDMR7.Byte
|
| 14365 |
|
|
#define CAN3IDMR7_AM0 _CAN3IDMR7.Bits.AM0
|
| 14366 |
|
|
#define CAN3IDMR7_AM1 _CAN3IDMR7.Bits.AM1
|
| 14367 |
|
|
#define CAN3IDMR7_AM2 _CAN3IDMR7.Bits.AM2
|
| 14368 |
|
|
#define CAN3IDMR7_AM3 _CAN3IDMR7.Bits.AM3
|
| 14369 |
|
|
#define CAN3IDMR7_AM4 _CAN3IDMR7.Bits.AM4
|
| 14370 |
|
|
#define CAN3IDMR7_AM5 _CAN3IDMR7.Bits.AM5
|
| 14371 |
|
|
#define CAN3IDMR7_AM6 _CAN3IDMR7.Bits.AM6
|
| 14372 |
|
|
#define CAN3IDMR7_AM7 _CAN3IDMR7.Bits.AM7
|
| 14373 |
|
|
#define CAN3IDMR7_AM _CAN3IDMR7.MergedBits.grpAM
|
| 14374 |
|
|
|
| 14375 |
|
|
|
| 14376 |
|
|
/*** CAN3RXIDR0 - MSCAN 3 Receive Identifier Register 0; 0x00000220 ***/
|
| 14377 |
|
|
typedef union {
|
| 14378 |
|
|
byte Byte;
|
| 14379 |
|
|
struct {
|
| 14380 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 14381 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 14382 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 14383 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 14384 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 14385 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 14386 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 14387 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 14388 |
|
|
} Bits;
|
| 14389 |
|
|
struct {
|
| 14390 |
|
|
byte grpID_21 :8;
|
| 14391 |
|
|
} MergedBits;
|
| 14392 |
|
|
} CAN3RXIDR0STR;
|
| 14393 |
|
|
extern volatile CAN3RXIDR0STR _CAN3RXIDR0 @(REG_BASE + 0x00000220);
|
| 14394 |
|
|
#define CAN3RXIDR0 _CAN3RXIDR0.Byte
|
| 14395 |
|
|
#define CAN3RXIDR0_ID21 _CAN3RXIDR0.Bits.ID21
|
| 14396 |
|
|
#define CAN3RXIDR0_ID22 _CAN3RXIDR0.Bits.ID22
|
| 14397 |
|
|
#define CAN3RXIDR0_ID23 _CAN3RXIDR0.Bits.ID23
|
| 14398 |
|
|
#define CAN3RXIDR0_ID24 _CAN3RXIDR0.Bits.ID24
|
| 14399 |
|
|
#define CAN3RXIDR0_ID25 _CAN3RXIDR0.Bits.ID25
|
| 14400 |
|
|
#define CAN3RXIDR0_ID26 _CAN3RXIDR0.Bits.ID26
|
| 14401 |
|
|
#define CAN3RXIDR0_ID27 _CAN3RXIDR0.Bits.ID27
|
| 14402 |
|
|
#define CAN3RXIDR0_ID28 _CAN3RXIDR0.Bits.ID28
|
| 14403 |
|
|
#define CAN3RXIDR0_ID_21 _CAN3RXIDR0.MergedBits.grpID_21
|
| 14404 |
|
|
#define CAN3RXIDR0_ID CAN3RXIDR0_ID_21
|
| 14405 |
|
|
|
| 14406 |
|
|
|
| 14407 |
|
|
/*** CAN3RXIDR1 - MSCAN 3 Receive Identifier Register 1; 0x00000221 ***/
|
| 14408 |
|
|
typedef union {
|
| 14409 |
|
|
byte Byte;
|
| 14410 |
|
|
struct {
|
| 14411 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 14412 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 14413 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 14414 |
|
|
byte IDE :1; /* ID Extended */
|
| 14415 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 14416 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 14417 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 14418 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 14419 |
|
|
} Bits;
|
| 14420 |
|
|
struct {
|
| 14421 |
|
|
byte grpID_15 :3;
|
| 14422 |
|
|
byte :1;
|
| 14423 |
|
|
byte :1;
|
| 14424 |
|
|
byte grpID_18 :3;
|
| 14425 |
|
|
} MergedBits;
|
| 14426 |
|
|
} CAN3RXIDR1STR;
|
| 14427 |
|
|
extern volatile CAN3RXIDR1STR _CAN3RXIDR1 @(REG_BASE + 0x00000221);
|
| 14428 |
|
|
#define CAN3RXIDR1 _CAN3RXIDR1.Byte
|
| 14429 |
|
|
#define CAN3RXIDR1_ID15 _CAN3RXIDR1.Bits.ID15
|
| 14430 |
|
|
#define CAN3RXIDR1_ID16 _CAN3RXIDR1.Bits.ID16
|
| 14431 |
|
|
#define CAN3RXIDR1_ID17 _CAN3RXIDR1.Bits.ID17
|
| 14432 |
|
|
#define CAN3RXIDR1_IDE _CAN3RXIDR1.Bits.IDE
|
| 14433 |
|
|
#define CAN3RXIDR1_SRR _CAN3RXIDR1.Bits.SRR
|
| 14434 |
|
|
#define CAN3RXIDR1_ID18 _CAN3RXIDR1.Bits.ID18
|
| 14435 |
|
|
#define CAN3RXIDR1_ID19 _CAN3RXIDR1.Bits.ID19
|
| 14436 |
|
|
#define CAN3RXIDR1_ID20 _CAN3RXIDR1.Bits.ID20
|
| 14437 |
|
|
#define CAN3RXIDR1_ID_15 _CAN3RXIDR1.MergedBits.grpID_15
|
| 14438 |
|
|
#define CAN3RXIDR1_ID_18 _CAN3RXIDR1.MergedBits.grpID_18
|
| 14439 |
|
|
#define CAN3RXIDR1_ID CAN3RXIDR1_ID_15
|
| 14440 |
|
|
|
| 14441 |
|
|
|
| 14442 |
|
|
/*** CAN3RXIDR2 - MSCAN 3 Receive Identifier Register 2; 0x00000222 ***/
|
| 14443 |
|
|
typedef union {
|
| 14444 |
|
|
byte Byte;
|
| 14445 |
|
|
struct {
|
| 14446 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 14447 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 14448 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 14449 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 14450 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 14451 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 14452 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 14453 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 14454 |
|
|
} Bits;
|
| 14455 |
|
|
struct {
|
| 14456 |
|
|
byte grpID_7 :8;
|
| 14457 |
|
|
} MergedBits;
|
| 14458 |
|
|
} CAN3RXIDR2STR;
|
| 14459 |
|
|
extern volatile CAN3RXIDR2STR _CAN3RXIDR2 @(REG_BASE + 0x00000222);
|
| 14460 |
|
|
#define CAN3RXIDR2 _CAN3RXIDR2.Byte
|
| 14461 |
|
|
#define CAN3RXIDR2_ID7 _CAN3RXIDR2.Bits.ID7
|
| 14462 |
|
|
#define CAN3RXIDR2_ID8 _CAN3RXIDR2.Bits.ID8
|
| 14463 |
|
|
#define CAN3RXIDR2_ID9 _CAN3RXIDR2.Bits.ID9
|
| 14464 |
|
|
#define CAN3RXIDR2_ID10 _CAN3RXIDR2.Bits.ID10
|
| 14465 |
|
|
#define CAN3RXIDR2_ID11 _CAN3RXIDR2.Bits.ID11
|
| 14466 |
|
|
#define CAN3RXIDR2_ID12 _CAN3RXIDR2.Bits.ID12
|
| 14467 |
|
|
#define CAN3RXIDR2_ID13 _CAN3RXIDR2.Bits.ID13
|
| 14468 |
|
|
#define CAN3RXIDR2_ID14 _CAN3RXIDR2.Bits.ID14
|
| 14469 |
|
|
#define CAN3RXIDR2_ID_7 _CAN3RXIDR2.MergedBits.grpID_7
|
| 14470 |
|
|
#define CAN3RXIDR2_ID CAN3RXIDR2_ID_7
|
| 14471 |
|
|
|
| 14472 |
|
|
|
| 14473 |
|
|
/*** CAN3RXIDR3 - MSCAN 3 Receive Identifier Register 3; 0x00000223 ***/
|
| 14474 |
|
|
typedef union {
|
| 14475 |
|
|
byte Byte;
|
| 14476 |
|
|
struct {
|
| 14477 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 14478 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 14479 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 14480 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 14481 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 14482 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 14483 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 14484 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 14485 |
|
|
} Bits;
|
| 14486 |
|
|
struct {
|
| 14487 |
|
|
byte :1;
|
| 14488 |
|
|
byte grpID :7;
|
| 14489 |
|
|
} MergedBits;
|
| 14490 |
|
|
} CAN3RXIDR3STR;
|
| 14491 |
|
|
extern volatile CAN3RXIDR3STR _CAN3RXIDR3 @(REG_BASE + 0x00000223);
|
| 14492 |
|
|
#define CAN3RXIDR3 _CAN3RXIDR3.Byte
|
| 14493 |
|
|
#define CAN3RXIDR3_RTR _CAN3RXIDR3.Bits.RTR
|
| 14494 |
|
|
#define CAN3RXIDR3_ID0 _CAN3RXIDR3.Bits.ID0
|
| 14495 |
|
|
#define CAN3RXIDR3_ID1 _CAN3RXIDR3.Bits.ID1
|
| 14496 |
|
|
#define CAN3RXIDR3_ID2 _CAN3RXIDR3.Bits.ID2
|
| 14497 |
|
|
#define CAN3RXIDR3_ID3 _CAN3RXIDR3.Bits.ID3
|
| 14498 |
|
|
#define CAN3RXIDR3_ID4 _CAN3RXIDR3.Bits.ID4
|
| 14499 |
|
|
#define CAN3RXIDR3_ID5 _CAN3RXIDR3.Bits.ID5
|
| 14500 |
|
|
#define CAN3RXIDR3_ID6 _CAN3RXIDR3.Bits.ID6
|
| 14501 |
|
|
#define CAN3RXIDR3_ID _CAN3RXIDR3.MergedBits.grpID
|
| 14502 |
|
|
|
| 14503 |
|
|
|
| 14504 |
|
|
/*** CAN3RXDSR0 - MSCAN 3 Receive Data Segment Register 0; 0x00000224 ***/
|
| 14505 |
|
|
typedef union {
|
| 14506 |
|
|
byte Byte;
|
| 14507 |
|
|
struct {
|
| 14508 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14509 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14510 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14511 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14512 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14513 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14514 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14515 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14516 |
|
|
} Bits;
|
| 14517 |
|
|
struct {
|
| 14518 |
|
|
byte grpDB :8;
|
| 14519 |
|
|
} MergedBits;
|
| 14520 |
|
|
} CAN3RXDSR0STR;
|
| 14521 |
|
|
extern volatile CAN3RXDSR0STR _CAN3RXDSR0 @(REG_BASE + 0x00000224);
|
| 14522 |
|
|
#define CAN3RXDSR0 _CAN3RXDSR0.Byte
|
| 14523 |
|
|
#define CAN3RXDSR0_DB0 _CAN3RXDSR0.Bits.DB0
|
| 14524 |
|
|
#define CAN3RXDSR0_DB1 _CAN3RXDSR0.Bits.DB1
|
| 14525 |
|
|
#define CAN3RXDSR0_DB2 _CAN3RXDSR0.Bits.DB2
|
| 14526 |
|
|
#define CAN3RXDSR0_DB3 _CAN3RXDSR0.Bits.DB3
|
| 14527 |
|
|
#define CAN3RXDSR0_DB4 _CAN3RXDSR0.Bits.DB4
|
| 14528 |
|
|
#define CAN3RXDSR0_DB5 _CAN3RXDSR0.Bits.DB5
|
| 14529 |
|
|
#define CAN3RXDSR0_DB6 _CAN3RXDSR0.Bits.DB6
|
| 14530 |
|
|
#define CAN3RXDSR0_DB7 _CAN3RXDSR0.Bits.DB7
|
| 14531 |
|
|
#define CAN3RXDSR0_DB _CAN3RXDSR0.MergedBits.grpDB
|
| 14532 |
|
|
|
| 14533 |
|
|
|
| 14534 |
|
|
/*** CAN3RXDSR1 - MSCAN 3 Receive Data Segment Register 1; 0x00000225 ***/
|
| 14535 |
|
|
typedef union {
|
| 14536 |
|
|
byte Byte;
|
| 14537 |
|
|
struct {
|
| 14538 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14539 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14540 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14541 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14542 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14543 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14544 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14545 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14546 |
|
|
} Bits;
|
| 14547 |
|
|
struct {
|
| 14548 |
|
|
byte grpDB :8;
|
| 14549 |
|
|
} MergedBits;
|
| 14550 |
|
|
} CAN3RXDSR1STR;
|
| 14551 |
|
|
extern volatile CAN3RXDSR1STR _CAN3RXDSR1 @(REG_BASE + 0x00000225);
|
| 14552 |
|
|
#define CAN3RXDSR1 _CAN3RXDSR1.Byte
|
| 14553 |
|
|
#define CAN3RXDSR1_DB0 _CAN3RXDSR1.Bits.DB0
|
| 14554 |
|
|
#define CAN3RXDSR1_DB1 _CAN3RXDSR1.Bits.DB1
|
| 14555 |
|
|
#define CAN3RXDSR1_DB2 _CAN3RXDSR1.Bits.DB2
|
| 14556 |
|
|
#define CAN3RXDSR1_DB3 _CAN3RXDSR1.Bits.DB3
|
| 14557 |
|
|
#define CAN3RXDSR1_DB4 _CAN3RXDSR1.Bits.DB4
|
| 14558 |
|
|
#define CAN3RXDSR1_DB5 _CAN3RXDSR1.Bits.DB5
|
| 14559 |
|
|
#define CAN3RXDSR1_DB6 _CAN3RXDSR1.Bits.DB6
|
| 14560 |
|
|
#define CAN3RXDSR1_DB7 _CAN3RXDSR1.Bits.DB7
|
| 14561 |
|
|
#define CAN3RXDSR1_DB _CAN3RXDSR1.MergedBits.grpDB
|
| 14562 |
|
|
|
| 14563 |
|
|
|
| 14564 |
|
|
/*** CAN3RXDSR2 - MSCAN 3 Receive Data Segment Register 2; 0x00000226 ***/
|
| 14565 |
|
|
typedef union {
|
| 14566 |
|
|
byte Byte;
|
| 14567 |
|
|
struct {
|
| 14568 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14569 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14570 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14571 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14572 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14573 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14574 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14575 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14576 |
|
|
} Bits;
|
| 14577 |
|
|
struct {
|
| 14578 |
|
|
byte grpDB :8;
|
| 14579 |
|
|
} MergedBits;
|
| 14580 |
|
|
} CAN3RXDSR2STR;
|
| 14581 |
|
|
extern volatile CAN3RXDSR2STR _CAN3RXDSR2 @(REG_BASE + 0x00000226);
|
| 14582 |
|
|
#define CAN3RXDSR2 _CAN3RXDSR2.Byte
|
| 14583 |
|
|
#define CAN3RXDSR2_DB0 _CAN3RXDSR2.Bits.DB0
|
| 14584 |
|
|
#define CAN3RXDSR2_DB1 _CAN3RXDSR2.Bits.DB1
|
| 14585 |
|
|
#define CAN3RXDSR2_DB2 _CAN3RXDSR2.Bits.DB2
|
| 14586 |
|
|
#define CAN3RXDSR2_DB3 _CAN3RXDSR2.Bits.DB3
|
| 14587 |
|
|
#define CAN3RXDSR2_DB4 _CAN3RXDSR2.Bits.DB4
|
| 14588 |
|
|
#define CAN3RXDSR2_DB5 _CAN3RXDSR2.Bits.DB5
|
| 14589 |
|
|
#define CAN3RXDSR2_DB6 _CAN3RXDSR2.Bits.DB6
|
| 14590 |
|
|
#define CAN3RXDSR2_DB7 _CAN3RXDSR2.Bits.DB7
|
| 14591 |
|
|
#define CAN3RXDSR2_DB _CAN3RXDSR2.MergedBits.grpDB
|
| 14592 |
|
|
|
| 14593 |
|
|
|
| 14594 |
|
|
/*** CAN3RXDSR3 - MSCAN 3 Receive Data Segment Register 3; 0x00000227 ***/
|
| 14595 |
|
|
typedef union {
|
| 14596 |
|
|
byte Byte;
|
| 14597 |
|
|
struct {
|
| 14598 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14599 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14600 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14601 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14602 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14603 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14604 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14605 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14606 |
|
|
} Bits;
|
| 14607 |
|
|
struct {
|
| 14608 |
|
|
byte grpDB :8;
|
| 14609 |
|
|
} MergedBits;
|
| 14610 |
|
|
} CAN3RXDSR3STR;
|
| 14611 |
|
|
extern volatile CAN3RXDSR3STR _CAN3RXDSR3 @(REG_BASE + 0x00000227);
|
| 14612 |
|
|
#define CAN3RXDSR3 _CAN3RXDSR3.Byte
|
| 14613 |
|
|
#define CAN3RXDSR3_DB0 _CAN3RXDSR3.Bits.DB0
|
| 14614 |
|
|
#define CAN3RXDSR3_DB1 _CAN3RXDSR3.Bits.DB1
|
| 14615 |
|
|
#define CAN3RXDSR3_DB2 _CAN3RXDSR3.Bits.DB2
|
| 14616 |
|
|
#define CAN3RXDSR3_DB3 _CAN3RXDSR3.Bits.DB3
|
| 14617 |
|
|
#define CAN3RXDSR3_DB4 _CAN3RXDSR3.Bits.DB4
|
| 14618 |
|
|
#define CAN3RXDSR3_DB5 _CAN3RXDSR3.Bits.DB5
|
| 14619 |
|
|
#define CAN3RXDSR3_DB6 _CAN3RXDSR3.Bits.DB6
|
| 14620 |
|
|
#define CAN3RXDSR3_DB7 _CAN3RXDSR3.Bits.DB7
|
| 14621 |
|
|
#define CAN3RXDSR3_DB _CAN3RXDSR3.MergedBits.grpDB
|
| 14622 |
|
|
|
| 14623 |
|
|
|
| 14624 |
|
|
/*** CAN3RXDSR4 - MSCAN 3 Receive Data Segment Register 4; 0x00000228 ***/
|
| 14625 |
|
|
typedef union {
|
| 14626 |
|
|
byte Byte;
|
| 14627 |
|
|
struct {
|
| 14628 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14629 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14630 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14631 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14632 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14633 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14634 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14635 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14636 |
|
|
} Bits;
|
| 14637 |
|
|
struct {
|
| 14638 |
|
|
byte grpDB :8;
|
| 14639 |
|
|
} MergedBits;
|
| 14640 |
|
|
} CAN3RXDSR4STR;
|
| 14641 |
|
|
extern volatile CAN3RXDSR4STR _CAN3RXDSR4 @(REG_BASE + 0x00000228);
|
| 14642 |
|
|
#define CAN3RXDSR4 _CAN3RXDSR4.Byte
|
| 14643 |
|
|
#define CAN3RXDSR4_DB0 _CAN3RXDSR4.Bits.DB0
|
| 14644 |
|
|
#define CAN3RXDSR4_DB1 _CAN3RXDSR4.Bits.DB1
|
| 14645 |
|
|
#define CAN3RXDSR4_DB2 _CAN3RXDSR4.Bits.DB2
|
| 14646 |
|
|
#define CAN3RXDSR4_DB3 _CAN3RXDSR4.Bits.DB3
|
| 14647 |
|
|
#define CAN3RXDSR4_DB4 _CAN3RXDSR4.Bits.DB4
|
| 14648 |
|
|
#define CAN3RXDSR4_DB5 _CAN3RXDSR4.Bits.DB5
|
| 14649 |
|
|
#define CAN3RXDSR4_DB6 _CAN3RXDSR4.Bits.DB6
|
| 14650 |
|
|
#define CAN3RXDSR4_DB7 _CAN3RXDSR4.Bits.DB7
|
| 14651 |
|
|
#define CAN3RXDSR4_DB _CAN3RXDSR4.MergedBits.grpDB
|
| 14652 |
|
|
|
| 14653 |
|
|
|
| 14654 |
|
|
/*** CAN3RXDSR5 - MSCAN 3 Receive Data Segment Register 5; 0x00000229 ***/
|
| 14655 |
|
|
typedef union {
|
| 14656 |
|
|
byte Byte;
|
| 14657 |
|
|
struct {
|
| 14658 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14659 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14660 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14661 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14662 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14663 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14664 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14665 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14666 |
|
|
} Bits;
|
| 14667 |
|
|
struct {
|
| 14668 |
|
|
byte grpDB :8;
|
| 14669 |
|
|
} MergedBits;
|
| 14670 |
|
|
} CAN3RXDSR5STR;
|
| 14671 |
|
|
extern volatile CAN3RXDSR5STR _CAN3RXDSR5 @(REG_BASE + 0x00000229);
|
| 14672 |
|
|
#define CAN3RXDSR5 _CAN3RXDSR5.Byte
|
| 14673 |
|
|
#define CAN3RXDSR5_DB0 _CAN3RXDSR5.Bits.DB0
|
| 14674 |
|
|
#define CAN3RXDSR5_DB1 _CAN3RXDSR5.Bits.DB1
|
| 14675 |
|
|
#define CAN3RXDSR5_DB2 _CAN3RXDSR5.Bits.DB2
|
| 14676 |
|
|
#define CAN3RXDSR5_DB3 _CAN3RXDSR5.Bits.DB3
|
| 14677 |
|
|
#define CAN3RXDSR5_DB4 _CAN3RXDSR5.Bits.DB4
|
| 14678 |
|
|
#define CAN3RXDSR5_DB5 _CAN3RXDSR5.Bits.DB5
|
| 14679 |
|
|
#define CAN3RXDSR5_DB6 _CAN3RXDSR5.Bits.DB6
|
| 14680 |
|
|
#define CAN3RXDSR5_DB7 _CAN3RXDSR5.Bits.DB7
|
| 14681 |
|
|
#define CAN3RXDSR5_DB _CAN3RXDSR5.MergedBits.grpDB
|
| 14682 |
|
|
|
| 14683 |
|
|
|
| 14684 |
|
|
/*** CAN3RXDSR6 - MSCAN 3 Receive Data Segment Register 6; 0x0000022A ***/
|
| 14685 |
|
|
typedef union {
|
| 14686 |
|
|
byte Byte;
|
| 14687 |
|
|
struct {
|
| 14688 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14689 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14690 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14691 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14692 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14693 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14694 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14695 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14696 |
|
|
} Bits;
|
| 14697 |
|
|
struct {
|
| 14698 |
|
|
byte grpDB :8;
|
| 14699 |
|
|
} MergedBits;
|
| 14700 |
|
|
} CAN3RXDSR6STR;
|
| 14701 |
|
|
extern volatile CAN3RXDSR6STR _CAN3RXDSR6 @(REG_BASE + 0x0000022A);
|
| 14702 |
|
|
#define CAN3RXDSR6 _CAN3RXDSR6.Byte
|
| 14703 |
|
|
#define CAN3RXDSR6_DB0 _CAN3RXDSR6.Bits.DB0
|
| 14704 |
|
|
#define CAN3RXDSR6_DB1 _CAN3RXDSR6.Bits.DB1
|
| 14705 |
|
|
#define CAN3RXDSR6_DB2 _CAN3RXDSR6.Bits.DB2
|
| 14706 |
|
|
#define CAN3RXDSR6_DB3 _CAN3RXDSR6.Bits.DB3
|
| 14707 |
|
|
#define CAN3RXDSR6_DB4 _CAN3RXDSR6.Bits.DB4
|
| 14708 |
|
|
#define CAN3RXDSR6_DB5 _CAN3RXDSR6.Bits.DB5
|
| 14709 |
|
|
#define CAN3RXDSR6_DB6 _CAN3RXDSR6.Bits.DB6
|
| 14710 |
|
|
#define CAN3RXDSR6_DB7 _CAN3RXDSR6.Bits.DB7
|
| 14711 |
|
|
#define CAN3RXDSR6_DB _CAN3RXDSR6.MergedBits.grpDB
|
| 14712 |
|
|
|
| 14713 |
|
|
|
| 14714 |
|
|
/*** CAN3RXDSR7 - MSCAN 3 Receive Data Segment Register 7; 0x0000022B ***/
|
| 14715 |
|
|
typedef union {
|
| 14716 |
|
|
byte Byte;
|
| 14717 |
|
|
struct {
|
| 14718 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14719 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14720 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14721 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14722 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14723 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14724 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14725 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14726 |
|
|
} Bits;
|
| 14727 |
|
|
struct {
|
| 14728 |
|
|
byte grpDB :8;
|
| 14729 |
|
|
} MergedBits;
|
| 14730 |
|
|
} CAN3RXDSR7STR;
|
| 14731 |
|
|
extern volatile CAN3RXDSR7STR _CAN3RXDSR7 @(REG_BASE + 0x0000022B);
|
| 14732 |
|
|
#define CAN3RXDSR7 _CAN3RXDSR7.Byte
|
| 14733 |
|
|
#define CAN3RXDSR7_DB0 _CAN3RXDSR7.Bits.DB0
|
| 14734 |
|
|
#define CAN3RXDSR7_DB1 _CAN3RXDSR7.Bits.DB1
|
| 14735 |
|
|
#define CAN3RXDSR7_DB2 _CAN3RXDSR7.Bits.DB2
|
| 14736 |
|
|
#define CAN3RXDSR7_DB3 _CAN3RXDSR7.Bits.DB3
|
| 14737 |
|
|
#define CAN3RXDSR7_DB4 _CAN3RXDSR7.Bits.DB4
|
| 14738 |
|
|
#define CAN3RXDSR7_DB5 _CAN3RXDSR7.Bits.DB5
|
| 14739 |
|
|
#define CAN3RXDSR7_DB6 _CAN3RXDSR7.Bits.DB6
|
| 14740 |
|
|
#define CAN3RXDSR7_DB7 _CAN3RXDSR7.Bits.DB7
|
| 14741 |
|
|
#define CAN3RXDSR7_DB _CAN3RXDSR7.MergedBits.grpDB
|
| 14742 |
|
|
|
| 14743 |
|
|
|
| 14744 |
|
|
/*** CAN3RXDLR - MSCAN 3 Receive Data Length Register; 0x0000022C ***/
|
| 14745 |
|
|
typedef union {
|
| 14746 |
|
|
byte Byte;
|
| 14747 |
|
|
struct {
|
| 14748 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 14749 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 14750 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 14751 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 14752 |
|
|
byte :1;
|
| 14753 |
|
|
byte :1;
|
| 14754 |
|
|
byte :1;
|
| 14755 |
|
|
byte :1;
|
| 14756 |
|
|
} Bits;
|
| 14757 |
|
|
struct {
|
| 14758 |
|
|
byte grpDLC :4;
|
| 14759 |
|
|
byte :1;
|
| 14760 |
|
|
byte :1;
|
| 14761 |
|
|
byte :1;
|
| 14762 |
|
|
byte :1;
|
| 14763 |
|
|
} MergedBits;
|
| 14764 |
|
|
} CAN3RXDLRSTR;
|
| 14765 |
|
|
extern volatile CAN3RXDLRSTR _CAN3RXDLR @(REG_BASE + 0x0000022C);
|
| 14766 |
|
|
#define CAN3RXDLR _CAN3RXDLR.Byte
|
| 14767 |
|
|
#define CAN3RXDLR_DLC0 _CAN3RXDLR.Bits.DLC0
|
| 14768 |
|
|
#define CAN3RXDLR_DLC1 _CAN3RXDLR.Bits.DLC1
|
| 14769 |
|
|
#define CAN3RXDLR_DLC2 _CAN3RXDLR.Bits.DLC2
|
| 14770 |
|
|
#define CAN3RXDLR_DLC3 _CAN3RXDLR.Bits.DLC3
|
| 14771 |
|
|
#define CAN3RXDLR_DLC _CAN3RXDLR.MergedBits.grpDLC
|
| 14772 |
|
|
|
| 14773 |
|
|
|
| 14774 |
|
|
/*** CAN3TXIDR0 - MSCAN 3 Transmit Identifier Register 0; 0x00000230 ***/
|
| 14775 |
|
|
typedef union {
|
| 14776 |
|
|
byte Byte;
|
| 14777 |
|
|
struct {
|
| 14778 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 14779 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 14780 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 14781 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 14782 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 14783 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 14784 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 14785 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 14786 |
|
|
} Bits;
|
| 14787 |
|
|
struct {
|
| 14788 |
|
|
byte grpID_21 :8;
|
| 14789 |
|
|
} MergedBits;
|
| 14790 |
|
|
} CAN3TXIDR0STR;
|
| 14791 |
|
|
extern volatile CAN3TXIDR0STR _CAN3TXIDR0 @(REG_BASE + 0x00000230);
|
| 14792 |
|
|
#define CAN3TXIDR0 _CAN3TXIDR0.Byte
|
| 14793 |
|
|
#define CAN3TXIDR0_ID21 _CAN3TXIDR0.Bits.ID21
|
| 14794 |
|
|
#define CAN3TXIDR0_ID22 _CAN3TXIDR0.Bits.ID22
|
| 14795 |
|
|
#define CAN3TXIDR0_ID23 _CAN3TXIDR0.Bits.ID23
|
| 14796 |
|
|
#define CAN3TXIDR0_ID24 _CAN3TXIDR0.Bits.ID24
|
| 14797 |
|
|
#define CAN3TXIDR0_ID25 _CAN3TXIDR0.Bits.ID25
|
| 14798 |
|
|
#define CAN3TXIDR0_ID26 _CAN3TXIDR0.Bits.ID26
|
| 14799 |
|
|
#define CAN3TXIDR0_ID27 _CAN3TXIDR0.Bits.ID27
|
| 14800 |
|
|
#define CAN3TXIDR0_ID28 _CAN3TXIDR0.Bits.ID28
|
| 14801 |
|
|
#define CAN3TXIDR0_ID_21 _CAN3TXIDR0.MergedBits.grpID_21
|
| 14802 |
|
|
#define CAN3TXIDR0_ID CAN3TXIDR0_ID_21
|
| 14803 |
|
|
|
| 14804 |
|
|
|
| 14805 |
|
|
/*** CAN3TXIDR1 - MSCAN 3 Transmit Identifier Register 1; 0x00000231 ***/
|
| 14806 |
|
|
typedef union {
|
| 14807 |
|
|
byte Byte;
|
| 14808 |
|
|
struct {
|
| 14809 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 14810 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 14811 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 14812 |
|
|
byte IDE :1; /* ID Extended */
|
| 14813 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 14814 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 14815 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 14816 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 14817 |
|
|
} Bits;
|
| 14818 |
|
|
struct {
|
| 14819 |
|
|
byte grpID_15 :3;
|
| 14820 |
|
|
byte :1;
|
| 14821 |
|
|
byte :1;
|
| 14822 |
|
|
byte grpID_18 :3;
|
| 14823 |
|
|
} MergedBits;
|
| 14824 |
|
|
} CAN3TXIDR1STR;
|
| 14825 |
|
|
extern volatile CAN3TXIDR1STR _CAN3TXIDR1 @(REG_BASE + 0x00000231);
|
| 14826 |
|
|
#define CAN3TXIDR1 _CAN3TXIDR1.Byte
|
| 14827 |
|
|
#define CAN3TXIDR1_ID15 _CAN3TXIDR1.Bits.ID15
|
| 14828 |
|
|
#define CAN3TXIDR1_ID16 _CAN3TXIDR1.Bits.ID16
|
| 14829 |
|
|
#define CAN3TXIDR1_ID17 _CAN3TXIDR1.Bits.ID17
|
| 14830 |
|
|
#define CAN3TXIDR1_IDE _CAN3TXIDR1.Bits.IDE
|
| 14831 |
|
|
#define CAN3TXIDR1_SRR _CAN3TXIDR1.Bits.SRR
|
| 14832 |
|
|
#define CAN3TXIDR1_ID18 _CAN3TXIDR1.Bits.ID18
|
| 14833 |
|
|
#define CAN3TXIDR1_ID19 _CAN3TXIDR1.Bits.ID19
|
| 14834 |
|
|
#define CAN3TXIDR1_ID20 _CAN3TXIDR1.Bits.ID20
|
| 14835 |
|
|
#define CAN3TXIDR1_ID_15 _CAN3TXIDR1.MergedBits.grpID_15
|
| 14836 |
|
|
#define CAN3TXIDR1_ID_18 _CAN3TXIDR1.MergedBits.grpID_18
|
| 14837 |
|
|
#define CAN3TXIDR1_ID CAN3TXIDR1_ID_15
|
| 14838 |
|
|
|
| 14839 |
|
|
|
| 14840 |
|
|
/*** CAN3TXIDR2 - MSCAN 3 Transmit Identifier Register 2; 0x00000232 ***/
|
| 14841 |
|
|
typedef union {
|
| 14842 |
|
|
byte Byte;
|
| 14843 |
|
|
struct {
|
| 14844 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 14845 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 14846 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 14847 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 14848 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 14849 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 14850 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 14851 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 14852 |
|
|
} Bits;
|
| 14853 |
|
|
struct {
|
| 14854 |
|
|
byte grpID_7 :8;
|
| 14855 |
|
|
} MergedBits;
|
| 14856 |
|
|
} CAN3TXIDR2STR;
|
| 14857 |
|
|
extern volatile CAN3TXIDR2STR _CAN3TXIDR2 @(REG_BASE + 0x00000232);
|
| 14858 |
|
|
#define CAN3TXIDR2 _CAN3TXIDR2.Byte
|
| 14859 |
|
|
#define CAN3TXIDR2_ID7 _CAN3TXIDR2.Bits.ID7
|
| 14860 |
|
|
#define CAN3TXIDR2_ID8 _CAN3TXIDR2.Bits.ID8
|
| 14861 |
|
|
#define CAN3TXIDR2_ID9 _CAN3TXIDR2.Bits.ID9
|
| 14862 |
|
|
#define CAN3TXIDR2_ID10 _CAN3TXIDR2.Bits.ID10
|
| 14863 |
|
|
#define CAN3TXIDR2_ID11 _CAN3TXIDR2.Bits.ID11
|
| 14864 |
|
|
#define CAN3TXIDR2_ID12 _CAN3TXIDR2.Bits.ID12
|
| 14865 |
|
|
#define CAN3TXIDR2_ID13 _CAN3TXIDR2.Bits.ID13
|
| 14866 |
|
|
#define CAN3TXIDR2_ID14 _CAN3TXIDR2.Bits.ID14
|
| 14867 |
|
|
#define CAN3TXIDR2_ID_7 _CAN3TXIDR2.MergedBits.grpID_7
|
| 14868 |
|
|
#define CAN3TXIDR2_ID CAN3TXIDR2_ID_7
|
| 14869 |
|
|
|
| 14870 |
|
|
|
| 14871 |
|
|
/*** CAN3TXIDR3 - MSCAN 3 Transmit Identifier Register 3; 0x00000233 ***/
|
| 14872 |
|
|
typedef union {
|
| 14873 |
|
|
byte Byte;
|
| 14874 |
|
|
struct {
|
| 14875 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 14876 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 14877 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 14878 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 14879 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 14880 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 14881 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 14882 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 14883 |
|
|
} Bits;
|
| 14884 |
|
|
struct {
|
| 14885 |
|
|
byte :1;
|
| 14886 |
|
|
byte grpID :7;
|
| 14887 |
|
|
} MergedBits;
|
| 14888 |
|
|
} CAN3TXIDR3STR;
|
| 14889 |
|
|
extern volatile CAN3TXIDR3STR _CAN3TXIDR3 @(REG_BASE + 0x00000233);
|
| 14890 |
|
|
#define CAN3TXIDR3 _CAN3TXIDR3.Byte
|
| 14891 |
|
|
#define CAN3TXIDR3_RTR _CAN3TXIDR3.Bits.RTR
|
| 14892 |
|
|
#define CAN3TXIDR3_ID0 _CAN3TXIDR3.Bits.ID0
|
| 14893 |
|
|
#define CAN3TXIDR3_ID1 _CAN3TXIDR3.Bits.ID1
|
| 14894 |
|
|
#define CAN3TXIDR3_ID2 _CAN3TXIDR3.Bits.ID2
|
| 14895 |
|
|
#define CAN3TXIDR3_ID3 _CAN3TXIDR3.Bits.ID3
|
| 14896 |
|
|
#define CAN3TXIDR3_ID4 _CAN3TXIDR3.Bits.ID4
|
| 14897 |
|
|
#define CAN3TXIDR3_ID5 _CAN3TXIDR3.Bits.ID5
|
| 14898 |
|
|
#define CAN3TXIDR3_ID6 _CAN3TXIDR3.Bits.ID6
|
| 14899 |
|
|
#define CAN3TXIDR3_ID _CAN3TXIDR3.MergedBits.grpID
|
| 14900 |
|
|
|
| 14901 |
|
|
|
| 14902 |
|
|
/*** CAN3TXDSR0 - MSCAN 3 Transmit Data Segment Register 0; 0x00000234 ***/
|
| 14903 |
|
|
typedef union {
|
| 14904 |
|
|
byte Byte;
|
| 14905 |
|
|
struct {
|
| 14906 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14907 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14908 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14909 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14910 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14911 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14912 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14913 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14914 |
|
|
} Bits;
|
| 14915 |
|
|
struct {
|
| 14916 |
|
|
byte grpDB :8;
|
| 14917 |
|
|
} MergedBits;
|
| 14918 |
|
|
} CAN3TXDSR0STR;
|
| 14919 |
|
|
extern volatile CAN3TXDSR0STR _CAN3TXDSR0 @(REG_BASE + 0x00000234);
|
| 14920 |
|
|
#define CAN3TXDSR0 _CAN3TXDSR0.Byte
|
| 14921 |
|
|
#define CAN3TXDSR0_DB0 _CAN3TXDSR0.Bits.DB0
|
| 14922 |
|
|
#define CAN3TXDSR0_DB1 _CAN3TXDSR0.Bits.DB1
|
| 14923 |
|
|
#define CAN3TXDSR0_DB2 _CAN3TXDSR0.Bits.DB2
|
| 14924 |
|
|
#define CAN3TXDSR0_DB3 _CAN3TXDSR0.Bits.DB3
|
| 14925 |
|
|
#define CAN3TXDSR0_DB4 _CAN3TXDSR0.Bits.DB4
|
| 14926 |
|
|
#define CAN3TXDSR0_DB5 _CAN3TXDSR0.Bits.DB5
|
| 14927 |
|
|
#define CAN3TXDSR0_DB6 _CAN3TXDSR0.Bits.DB6
|
| 14928 |
|
|
#define CAN3TXDSR0_DB7 _CAN3TXDSR0.Bits.DB7
|
| 14929 |
|
|
#define CAN3TXDSR0_DB _CAN3TXDSR0.MergedBits.grpDB
|
| 14930 |
|
|
|
| 14931 |
|
|
|
| 14932 |
|
|
/*** CAN3TXDSR1 - MSCAN 3 Transmit Data Segment Register 1; 0x00000235 ***/
|
| 14933 |
|
|
typedef union {
|
| 14934 |
|
|
byte Byte;
|
| 14935 |
|
|
struct {
|
| 14936 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14937 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14938 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14939 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14940 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14941 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14942 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14943 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14944 |
|
|
} Bits;
|
| 14945 |
|
|
struct {
|
| 14946 |
|
|
byte grpDB :8;
|
| 14947 |
|
|
} MergedBits;
|
| 14948 |
|
|
} CAN3TXDSR1STR;
|
| 14949 |
|
|
extern volatile CAN3TXDSR1STR _CAN3TXDSR1 @(REG_BASE + 0x00000235);
|
| 14950 |
|
|
#define CAN3TXDSR1 _CAN3TXDSR1.Byte
|
| 14951 |
|
|
#define CAN3TXDSR1_DB0 _CAN3TXDSR1.Bits.DB0
|
| 14952 |
|
|
#define CAN3TXDSR1_DB1 _CAN3TXDSR1.Bits.DB1
|
| 14953 |
|
|
#define CAN3TXDSR1_DB2 _CAN3TXDSR1.Bits.DB2
|
| 14954 |
|
|
#define CAN3TXDSR1_DB3 _CAN3TXDSR1.Bits.DB3
|
| 14955 |
|
|
#define CAN3TXDSR1_DB4 _CAN3TXDSR1.Bits.DB4
|
| 14956 |
|
|
#define CAN3TXDSR1_DB5 _CAN3TXDSR1.Bits.DB5
|
| 14957 |
|
|
#define CAN3TXDSR1_DB6 _CAN3TXDSR1.Bits.DB6
|
| 14958 |
|
|
#define CAN3TXDSR1_DB7 _CAN3TXDSR1.Bits.DB7
|
| 14959 |
|
|
#define CAN3TXDSR1_DB _CAN3TXDSR1.MergedBits.grpDB
|
| 14960 |
|
|
|
| 14961 |
|
|
|
| 14962 |
|
|
/*** CAN3TXDSR2 - MSCAN 3 Transmit Data Segment Register 2; 0x00000236 ***/
|
| 14963 |
|
|
typedef union {
|
| 14964 |
|
|
byte Byte;
|
| 14965 |
|
|
struct {
|
| 14966 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14967 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14968 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14969 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 14970 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 14971 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 14972 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 14973 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 14974 |
|
|
} Bits;
|
| 14975 |
|
|
struct {
|
| 14976 |
|
|
byte grpDB :8;
|
| 14977 |
|
|
} MergedBits;
|
| 14978 |
|
|
} CAN3TXDSR2STR;
|
| 14979 |
|
|
extern volatile CAN3TXDSR2STR _CAN3TXDSR2 @(REG_BASE + 0x00000236);
|
| 14980 |
|
|
#define CAN3TXDSR2 _CAN3TXDSR2.Byte
|
| 14981 |
|
|
#define CAN3TXDSR2_DB0 _CAN3TXDSR2.Bits.DB0
|
| 14982 |
|
|
#define CAN3TXDSR2_DB1 _CAN3TXDSR2.Bits.DB1
|
| 14983 |
|
|
#define CAN3TXDSR2_DB2 _CAN3TXDSR2.Bits.DB2
|
| 14984 |
|
|
#define CAN3TXDSR2_DB3 _CAN3TXDSR2.Bits.DB3
|
| 14985 |
|
|
#define CAN3TXDSR2_DB4 _CAN3TXDSR2.Bits.DB4
|
| 14986 |
|
|
#define CAN3TXDSR2_DB5 _CAN3TXDSR2.Bits.DB5
|
| 14987 |
|
|
#define CAN3TXDSR2_DB6 _CAN3TXDSR2.Bits.DB6
|
| 14988 |
|
|
#define CAN3TXDSR2_DB7 _CAN3TXDSR2.Bits.DB7
|
| 14989 |
|
|
#define CAN3TXDSR2_DB _CAN3TXDSR2.MergedBits.grpDB
|
| 14990 |
|
|
|
| 14991 |
|
|
|
| 14992 |
|
|
/*** CAN3TXDSR3 - MSCAN 3 Transmit Data Segment Register 3; 0x00000237 ***/
|
| 14993 |
|
|
typedef union {
|
| 14994 |
|
|
byte Byte;
|
| 14995 |
|
|
struct {
|
| 14996 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 14997 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 14998 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 14999 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 15000 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 15001 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 15002 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 15003 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 15004 |
|
|
} Bits;
|
| 15005 |
|
|
struct {
|
| 15006 |
|
|
byte grpDB :8;
|
| 15007 |
|
|
} MergedBits;
|
| 15008 |
|
|
} CAN3TXDSR3STR;
|
| 15009 |
|
|
extern volatile CAN3TXDSR3STR _CAN3TXDSR3 @(REG_BASE + 0x00000237);
|
| 15010 |
|
|
#define CAN3TXDSR3 _CAN3TXDSR3.Byte
|
| 15011 |
|
|
#define CAN3TXDSR3_DB0 _CAN3TXDSR3.Bits.DB0
|
| 15012 |
|
|
#define CAN3TXDSR3_DB1 _CAN3TXDSR3.Bits.DB1
|
| 15013 |
|
|
#define CAN3TXDSR3_DB2 _CAN3TXDSR3.Bits.DB2
|
| 15014 |
|
|
#define CAN3TXDSR3_DB3 _CAN3TXDSR3.Bits.DB3
|
| 15015 |
|
|
#define CAN3TXDSR3_DB4 _CAN3TXDSR3.Bits.DB4
|
| 15016 |
|
|
#define CAN3TXDSR3_DB5 _CAN3TXDSR3.Bits.DB5
|
| 15017 |
|
|
#define CAN3TXDSR3_DB6 _CAN3TXDSR3.Bits.DB6
|
| 15018 |
|
|
#define CAN3TXDSR3_DB7 _CAN3TXDSR3.Bits.DB7
|
| 15019 |
|
|
#define CAN3TXDSR3_DB _CAN3TXDSR3.MergedBits.grpDB
|
| 15020 |
|
|
|
| 15021 |
|
|
|
| 15022 |
|
|
/*** CAN3TXDSR4 - MSCAN 3 Transmit Data Segment Register 4; 0x00000238 ***/
|
| 15023 |
|
|
typedef union {
|
| 15024 |
|
|
byte Byte;
|
| 15025 |
|
|
struct {
|
| 15026 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 15027 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 15028 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 15029 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 15030 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 15031 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 15032 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 15033 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 15034 |
|
|
} Bits;
|
| 15035 |
|
|
struct {
|
| 15036 |
|
|
byte grpDB :8;
|
| 15037 |
|
|
} MergedBits;
|
| 15038 |
|
|
} CAN3TXDSR4STR;
|
| 15039 |
|
|
extern volatile CAN3TXDSR4STR _CAN3TXDSR4 @(REG_BASE + 0x00000238);
|
| 15040 |
|
|
#define CAN3TXDSR4 _CAN3TXDSR4.Byte
|
| 15041 |
|
|
#define CAN3TXDSR4_DB0 _CAN3TXDSR4.Bits.DB0
|
| 15042 |
|
|
#define CAN3TXDSR4_DB1 _CAN3TXDSR4.Bits.DB1
|
| 15043 |
|
|
#define CAN3TXDSR4_DB2 _CAN3TXDSR4.Bits.DB2
|
| 15044 |
|
|
#define CAN3TXDSR4_DB3 _CAN3TXDSR4.Bits.DB3
|
| 15045 |
|
|
#define CAN3TXDSR4_DB4 _CAN3TXDSR4.Bits.DB4
|
| 15046 |
|
|
#define CAN3TXDSR4_DB5 _CAN3TXDSR4.Bits.DB5
|
| 15047 |
|
|
#define CAN3TXDSR4_DB6 _CAN3TXDSR4.Bits.DB6
|
| 15048 |
|
|
#define CAN3TXDSR4_DB7 _CAN3TXDSR4.Bits.DB7
|
| 15049 |
|
|
#define CAN3TXDSR4_DB _CAN3TXDSR4.MergedBits.grpDB
|
| 15050 |
|
|
|
| 15051 |
|
|
|
| 15052 |
|
|
/*** CAN3TXDSR5 - MSCAN 3 Transmit Data Segment Register 5; 0x00000239 ***/
|
| 15053 |
|
|
typedef union {
|
| 15054 |
|
|
byte Byte;
|
| 15055 |
|
|
struct {
|
| 15056 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 15057 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 15058 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 15059 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 15060 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 15061 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 15062 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 15063 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 15064 |
|
|
} Bits;
|
| 15065 |
|
|
struct {
|
| 15066 |
|
|
byte grpDB :8;
|
| 15067 |
|
|
} MergedBits;
|
| 15068 |
|
|
} CAN3TXDSR5STR;
|
| 15069 |
|
|
extern volatile CAN3TXDSR5STR _CAN3TXDSR5 @(REG_BASE + 0x00000239);
|
| 15070 |
|
|
#define CAN3TXDSR5 _CAN3TXDSR5.Byte
|
| 15071 |
|
|
#define CAN3TXDSR5_DB0 _CAN3TXDSR5.Bits.DB0
|
| 15072 |
|
|
#define CAN3TXDSR5_DB1 _CAN3TXDSR5.Bits.DB1
|
| 15073 |
|
|
#define CAN3TXDSR5_DB2 _CAN3TXDSR5.Bits.DB2
|
| 15074 |
|
|
#define CAN3TXDSR5_DB3 _CAN3TXDSR5.Bits.DB3
|
| 15075 |
|
|
#define CAN3TXDSR5_DB4 _CAN3TXDSR5.Bits.DB4
|
| 15076 |
|
|
#define CAN3TXDSR5_DB5 _CAN3TXDSR5.Bits.DB5
|
| 15077 |
|
|
#define CAN3TXDSR5_DB6 _CAN3TXDSR5.Bits.DB6
|
| 15078 |
|
|
#define CAN3TXDSR5_DB7 _CAN3TXDSR5.Bits.DB7
|
| 15079 |
|
|
#define CAN3TXDSR5_DB _CAN3TXDSR5.MergedBits.grpDB
|
| 15080 |
|
|
|
| 15081 |
|
|
|
| 15082 |
|
|
/*** CAN3TXDSR6 - MSCAN 3 Transmit Data Segment Register 6; 0x0000023A ***/
|
| 15083 |
|
|
typedef union {
|
| 15084 |
|
|
byte Byte;
|
| 15085 |
|
|
struct {
|
| 15086 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 15087 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 15088 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 15089 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 15090 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 15091 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 15092 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 15093 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 15094 |
|
|
} Bits;
|
| 15095 |
|
|
struct {
|
| 15096 |
|
|
byte grpDB :8;
|
| 15097 |
|
|
} MergedBits;
|
| 15098 |
|
|
} CAN3TXDSR6STR;
|
| 15099 |
|
|
extern volatile CAN3TXDSR6STR _CAN3TXDSR6 @(REG_BASE + 0x0000023A);
|
| 15100 |
|
|
#define CAN3TXDSR6 _CAN3TXDSR6.Byte
|
| 15101 |
|
|
#define CAN3TXDSR6_DB0 _CAN3TXDSR6.Bits.DB0
|
| 15102 |
|
|
#define CAN3TXDSR6_DB1 _CAN3TXDSR6.Bits.DB1
|
| 15103 |
|
|
#define CAN3TXDSR6_DB2 _CAN3TXDSR6.Bits.DB2
|
| 15104 |
|
|
#define CAN3TXDSR6_DB3 _CAN3TXDSR6.Bits.DB3
|
| 15105 |
|
|
#define CAN3TXDSR6_DB4 _CAN3TXDSR6.Bits.DB4
|
| 15106 |
|
|
#define CAN3TXDSR6_DB5 _CAN3TXDSR6.Bits.DB5
|
| 15107 |
|
|
#define CAN3TXDSR6_DB6 _CAN3TXDSR6.Bits.DB6
|
| 15108 |
|
|
#define CAN3TXDSR6_DB7 _CAN3TXDSR6.Bits.DB7
|
| 15109 |
|
|
#define CAN3TXDSR6_DB _CAN3TXDSR6.MergedBits.grpDB
|
| 15110 |
|
|
|
| 15111 |
|
|
|
| 15112 |
|
|
/*** CAN3TXDSR7 - MSCAN 3 Transmit Data Segment Register 7; 0x0000023B ***/
|
| 15113 |
|
|
typedef union {
|
| 15114 |
|
|
byte Byte;
|
| 15115 |
|
|
struct {
|
| 15116 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 15117 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 15118 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 15119 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 15120 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 15121 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 15122 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 15123 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 15124 |
|
|
} Bits;
|
| 15125 |
|
|
struct {
|
| 15126 |
|
|
byte grpDB :8;
|
| 15127 |
|
|
} MergedBits;
|
| 15128 |
|
|
} CAN3TXDSR7STR;
|
| 15129 |
|
|
extern volatile CAN3TXDSR7STR _CAN3TXDSR7 @(REG_BASE + 0x0000023B);
|
| 15130 |
|
|
#define CAN3TXDSR7 _CAN3TXDSR7.Byte
|
| 15131 |
|
|
#define CAN3TXDSR7_DB0 _CAN3TXDSR7.Bits.DB0
|
| 15132 |
|
|
#define CAN3TXDSR7_DB1 _CAN3TXDSR7.Bits.DB1
|
| 15133 |
|
|
#define CAN3TXDSR7_DB2 _CAN3TXDSR7.Bits.DB2
|
| 15134 |
|
|
#define CAN3TXDSR7_DB3 _CAN3TXDSR7.Bits.DB3
|
| 15135 |
|
|
#define CAN3TXDSR7_DB4 _CAN3TXDSR7.Bits.DB4
|
| 15136 |
|
|
#define CAN3TXDSR7_DB5 _CAN3TXDSR7.Bits.DB5
|
| 15137 |
|
|
#define CAN3TXDSR7_DB6 _CAN3TXDSR7.Bits.DB6
|
| 15138 |
|
|
#define CAN3TXDSR7_DB7 _CAN3TXDSR7.Bits.DB7
|
| 15139 |
|
|
#define CAN3TXDSR7_DB _CAN3TXDSR7.MergedBits.grpDB
|
| 15140 |
|
|
|
| 15141 |
|
|
|
| 15142 |
|
|
/*** CAN3TXDLR - MSCAN 3 Transmit Data Length Register; 0x0000023C ***/
|
| 15143 |
|
|
typedef union {
|
| 15144 |
|
|
byte Byte;
|
| 15145 |
|
|
struct {
|
| 15146 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 15147 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 15148 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 15149 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 15150 |
|
|
byte :1;
|
| 15151 |
|
|
byte :1;
|
| 15152 |
|
|
byte :1;
|
| 15153 |
|
|
byte :1;
|
| 15154 |
|
|
} Bits;
|
| 15155 |
|
|
struct {
|
| 15156 |
|
|
byte grpDLC :4;
|
| 15157 |
|
|
byte :1;
|
| 15158 |
|
|
byte :1;
|
| 15159 |
|
|
byte :1;
|
| 15160 |
|
|
byte :1;
|
| 15161 |
|
|
} MergedBits;
|
| 15162 |
|
|
} CAN3TXDLRSTR;
|
| 15163 |
|
|
extern volatile CAN3TXDLRSTR _CAN3TXDLR @(REG_BASE + 0x0000023C);
|
| 15164 |
|
|
#define CAN3TXDLR _CAN3TXDLR.Byte
|
| 15165 |
|
|
#define CAN3TXDLR_DLC0 _CAN3TXDLR.Bits.DLC0
|
| 15166 |
|
|
#define CAN3TXDLR_DLC1 _CAN3TXDLR.Bits.DLC1
|
| 15167 |
|
|
#define CAN3TXDLR_DLC2 _CAN3TXDLR.Bits.DLC2
|
| 15168 |
|
|
#define CAN3TXDLR_DLC3 _CAN3TXDLR.Bits.DLC3
|
| 15169 |
|
|
#define CAN3TXDLR_DLC _CAN3TXDLR.MergedBits.grpDLC
|
| 15170 |
|
|
|
| 15171 |
|
|
|
| 15172 |
|
|
/*** CAN3TXTBPR - MSCAN 3 Transmit Buffer Priority; 0x0000023F ***/
|
| 15173 |
|
|
typedef union {
|
| 15174 |
|
|
byte Byte;
|
| 15175 |
|
|
struct {
|
| 15176 |
|
|
byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
|
| 15177 |
|
|
byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
|
| 15178 |
|
|
byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
|
| 15179 |
|
|
byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
|
| 15180 |
|
|
byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
|
| 15181 |
|
|
byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
|
| 15182 |
|
|
byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
|
| 15183 |
|
|
byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
|
| 15184 |
|
|
} Bits;
|
| 15185 |
|
|
struct {
|
| 15186 |
|
|
byte grpPRIO :8;
|
| 15187 |
|
|
} MergedBits;
|
| 15188 |
|
|
} CAN3TXTBPRSTR;
|
| 15189 |
|
|
extern volatile CAN3TXTBPRSTR _CAN3TXTBPR @(REG_BASE + 0x0000023F);
|
| 15190 |
|
|
#define CAN3TXTBPR _CAN3TXTBPR.Byte
|
| 15191 |
|
|
#define CAN3TXTBPR_PRIO0 _CAN3TXTBPR.Bits.PRIO0
|
| 15192 |
|
|
#define CAN3TXTBPR_PRIO1 _CAN3TXTBPR.Bits.PRIO1
|
| 15193 |
|
|
#define CAN3TXTBPR_PRIO2 _CAN3TXTBPR.Bits.PRIO2
|
| 15194 |
|
|
#define CAN3TXTBPR_PRIO3 _CAN3TXTBPR.Bits.PRIO3
|
| 15195 |
|
|
#define CAN3TXTBPR_PRIO4 _CAN3TXTBPR.Bits.PRIO4
|
| 15196 |
|
|
#define CAN3TXTBPR_PRIO5 _CAN3TXTBPR.Bits.PRIO5
|
| 15197 |
|
|
#define CAN3TXTBPR_PRIO6 _CAN3TXTBPR.Bits.PRIO6
|
| 15198 |
|
|
#define CAN3TXTBPR_PRIO7 _CAN3TXTBPR.Bits.PRIO7
|
| 15199 |
|
|
#define CAN3TXTBPR_PRIO _CAN3TXTBPR.MergedBits.grpPRIO
|
| 15200 |
|
|
|
| 15201 |
|
|
|
| 15202 |
|
|
/*** PTT - Port T I/O Register; 0x00000240 ***/
|
| 15203 |
|
|
typedef union {
|
| 15204 |
|
|
byte Byte;
|
| 15205 |
|
|
struct {
|
| 15206 |
|
|
byte PTT0 :1; /* Port T Bit 0 */
|
| 15207 |
|
|
byte PTT1 :1; /* Port T Bit 1 */
|
| 15208 |
|
|
byte PTT2 :1; /* Port T Bit 2 */
|
| 15209 |
|
|
byte PTT3 :1; /* Port T Bit 3 */
|
| 15210 |
|
|
byte PTT4 :1; /* Port T Bit 4 */
|
| 15211 |
|
|
byte PTT5 :1; /* Port T Bit 5 */
|
| 15212 |
|
|
byte PTT6 :1; /* Port T Bit 6 */
|
| 15213 |
|
|
byte PTT7 :1; /* Port T Bit 7 */
|
| 15214 |
|
|
} Bits;
|
| 15215 |
|
|
struct {
|
| 15216 |
|
|
byte grpPTT :8;
|
| 15217 |
|
|
} MergedBits;
|
| 15218 |
|
|
} PTTSTR;
|
| 15219 |
|
|
extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240);
|
| 15220 |
|
|
#define PTT _PTT.Byte
|
| 15221 |
|
|
#define PTT_PTT0 _PTT.Bits.PTT0
|
| 15222 |
|
|
#define PTT_PTT1 _PTT.Bits.PTT1
|
| 15223 |
|
|
#define PTT_PTT2 _PTT.Bits.PTT2
|
| 15224 |
|
|
#define PTT_PTT3 _PTT.Bits.PTT3
|
| 15225 |
|
|
#define PTT_PTT4 _PTT.Bits.PTT4
|
| 15226 |
|
|
#define PTT_PTT5 _PTT.Bits.PTT5
|
| 15227 |
|
|
#define PTT_PTT6 _PTT.Bits.PTT6
|
| 15228 |
|
|
#define PTT_PTT7 _PTT.Bits.PTT7
|
| 15229 |
|
|
#define PTT_PTT _PTT.MergedBits.grpPTT
|
| 15230 |
|
|
|
| 15231 |
|
|
|
| 15232 |
|
|
/*** PTIT - Port T Input; 0x00000241 ***/
|
| 15233 |
|
|
typedef union {
|
| 15234 |
|
|
byte Byte;
|
| 15235 |
|
|
struct {
|
| 15236 |
|
|
byte PTIT0 :1; /* Port T Bit 0 */
|
| 15237 |
|
|
byte PTIT1 :1; /* Port T Bit 1 */
|
| 15238 |
|
|
byte PTIT2 :1; /* Port T Bit 2 */
|
| 15239 |
|
|
byte PTIT3 :1; /* Port T Bit 3 */
|
| 15240 |
|
|
byte PTIT4 :1; /* Port T Bit 4 */
|
| 15241 |
|
|
byte PTIT5 :1; /* Port T Bit 5 */
|
| 15242 |
|
|
byte PTIT6 :1; /* Port T Bit 6 */
|
| 15243 |
|
|
byte PTIT7 :1; /* Port T Bit 7 */
|
| 15244 |
|
|
} Bits;
|
| 15245 |
|
|
struct {
|
| 15246 |
|
|
byte grpPTIT :8;
|
| 15247 |
|
|
} MergedBits;
|
| 15248 |
|
|
} PTITSTR;
|
| 15249 |
|
|
extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241);
|
| 15250 |
|
|
#define PTIT _PTIT.Byte
|
| 15251 |
|
|
#define PTIT_PTIT0 _PTIT.Bits.PTIT0
|
| 15252 |
|
|
#define PTIT_PTIT1 _PTIT.Bits.PTIT1
|
| 15253 |
|
|
#define PTIT_PTIT2 _PTIT.Bits.PTIT2
|
| 15254 |
|
|
#define PTIT_PTIT3 _PTIT.Bits.PTIT3
|
| 15255 |
|
|
#define PTIT_PTIT4 _PTIT.Bits.PTIT4
|
| 15256 |
|
|
#define PTIT_PTIT5 _PTIT.Bits.PTIT5
|
| 15257 |
|
|
#define PTIT_PTIT6 _PTIT.Bits.PTIT6
|
| 15258 |
|
|
#define PTIT_PTIT7 _PTIT.Bits.PTIT7
|
| 15259 |
|
|
#define PTIT_PTIT _PTIT.MergedBits.grpPTIT
|
| 15260 |
|
|
|
| 15261 |
|
|
|
| 15262 |
|
|
/*** DDRT - Port T Data Direction Register; 0x00000242 ***/
|
| 15263 |
|
|
typedef union {
|
| 15264 |
|
|
byte Byte;
|
| 15265 |
|
|
struct {
|
| 15266 |
|
|
byte DDRT0 :1; /* Data Direction Port T Bit 0 */
|
| 15267 |
|
|
byte DDRT1 :1; /* Data Direction Port T Bit 1 */
|
| 15268 |
|
|
byte DDRT2 :1; /* Data Direction Port T Bit 2 */
|
| 15269 |
|
|
byte DDRT3 :1; /* Data Direction Port T Bit 3 */
|
| 15270 |
|
|
byte DDRT4 :1; /* Data Direction Port T Bit 4 */
|
| 15271 |
|
|
byte DDRT5 :1; /* Data Direction Port T Bit 5 */
|
| 15272 |
|
|
byte DDRT6 :1; /* Data Direction Port T Bit 6 */
|
| 15273 |
|
|
byte DDRT7 :1; /* Data Direction Port T Bit 7 */
|
| 15274 |
|
|
} Bits;
|
| 15275 |
|
|
struct {
|
| 15276 |
|
|
byte grpDDRT :8;
|
| 15277 |
|
|
} MergedBits;
|
| 15278 |
|
|
} DDRTSTR;
|
| 15279 |
|
|
extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242);
|
| 15280 |
|
|
#define DDRT _DDRT.Byte
|
| 15281 |
|
|
#define DDRT_DDRT0 _DDRT.Bits.DDRT0
|
| 15282 |
|
|
#define DDRT_DDRT1 _DDRT.Bits.DDRT1
|
| 15283 |
|
|
#define DDRT_DDRT2 _DDRT.Bits.DDRT2
|
| 15284 |
|
|
#define DDRT_DDRT3 _DDRT.Bits.DDRT3
|
| 15285 |
|
|
#define DDRT_DDRT4 _DDRT.Bits.DDRT4
|
| 15286 |
|
|
#define DDRT_DDRT5 _DDRT.Bits.DDRT5
|
| 15287 |
|
|
#define DDRT_DDRT6 _DDRT.Bits.DDRT6
|
| 15288 |
|
|
#define DDRT_DDRT7 _DDRT.Bits.DDRT7
|
| 15289 |
|
|
#define DDRT_DDRT _DDRT.MergedBits.grpDDRT
|
| 15290 |
|
|
|
| 15291 |
|
|
|
| 15292 |
|
|
/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/
|
| 15293 |
|
|
typedef union {
|
| 15294 |
|
|
byte Byte;
|
| 15295 |
|
|
struct {
|
| 15296 |
|
|
byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */
|
| 15297 |
|
|
byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */
|
| 15298 |
|
|
byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */
|
| 15299 |
|
|
byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */
|
| 15300 |
|
|
byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */
|
| 15301 |
|
|
byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */
|
| 15302 |
|
|
byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */
|
| 15303 |
|
|
byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */
|
| 15304 |
|
|
} Bits;
|
| 15305 |
|
|
struct {
|
| 15306 |
|
|
byte grpRDRT :8;
|
| 15307 |
|
|
} MergedBits;
|
| 15308 |
|
|
} RDRTSTR;
|
| 15309 |
|
|
extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243);
|
| 15310 |
|
|
#define RDRT _RDRT.Byte
|
| 15311 |
|
|
#define RDRT_RDRT0 _RDRT.Bits.RDRT0
|
| 15312 |
|
|
#define RDRT_RDRT1 _RDRT.Bits.RDRT1
|
| 15313 |
|
|
#define RDRT_RDRT2 _RDRT.Bits.RDRT2
|
| 15314 |
|
|
#define RDRT_RDRT3 _RDRT.Bits.RDRT3
|
| 15315 |
|
|
#define RDRT_RDRT4 _RDRT.Bits.RDRT4
|
| 15316 |
|
|
#define RDRT_RDRT5 _RDRT.Bits.RDRT5
|
| 15317 |
|
|
#define RDRT_RDRT6 _RDRT.Bits.RDRT6
|
| 15318 |
|
|
#define RDRT_RDRT7 _RDRT.Bits.RDRT7
|
| 15319 |
|
|
#define RDRT_RDRT _RDRT.MergedBits.grpRDRT
|
| 15320 |
|
|
|
| 15321 |
|
|
|
| 15322 |
|
|
/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/
|
| 15323 |
|
|
typedef union {
|
| 15324 |
|
|
byte Byte;
|
| 15325 |
|
|
struct {
|
| 15326 |
|
|
byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */
|
| 15327 |
|
|
byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */
|
| 15328 |
|
|
byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */
|
| 15329 |
|
|
byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */
|
| 15330 |
|
|
byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */
|
| 15331 |
|
|
byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */
|
| 15332 |
|
|
byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */
|
| 15333 |
|
|
byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */
|
| 15334 |
|
|
} Bits;
|
| 15335 |
|
|
struct {
|
| 15336 |
|
|
byte grpPERT :8;
|
| 15337 |
|
|
} MergedBits;
|
| 15338 |
|
|
} PERTSTR;
|
| 15339 |
|
|
extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244);
|
| 15340 |
|
|
#define PERT _PERT.Byte
|
| 15341 |
|
|
#define PERT_PERT0 _PERT.Bits.PERT0
|
| 15342 |
|
|
#define PERT_PERT1 _PERT.Bits.PERT1
|
| 15343 |
|
|
#define PERT_PERT2 _PERT.Bits.PERT2
|
| 15344 |
|
|
#define PERT_PERT3 _PERT.Bits.PERT3
|
| 15345 |
|
|
#define PERT_PERT4 _PERT.Bits.PERT4
|
| 15346 |
|
|
#define PERT_PERT5 _PERT.Bits.PERT5
|
| 15347 |
|
|
#define PERT_PERT6 _PERT.Bits.PERT6
|
| 15348 |
|
|
#define PERT_PERT7 _PERT.Bits.PERT7
|
| 15349 |
|
|
#define PERT_PERT _PERT.MergedBits.grpPERT
|
| 15350 |
|
|
|
| 15351 |
|
|
|
| 15352 |
|
|
/*** PPST - Port T Polarity Select Register; 0x00000245 ***/
|
| 15353 |
|
|
typedef union {
|
| 15354 |
|
|
byte Byte;
|
| 15355 |
|
|
struct {
|
| 15356 |
|
|
byte PPST0 :1; /* Pull Select Port T Bit 0 */
|
| 15357 |
|
|
byte PPST1 :1; /* Pull Select Port T Bit 1 */
|
| 15358 |
|
|
byte PPST2 :1; /* Pull Select Port T Bit 2 */
|
| 15359 |
|
|
byte PPST3 :1; /* Pull Select Port T Bit 3 */
|
| 15360 |
|
|
byte PPST4 :1; /* Pull Select Port T Bit 4 */
|
| 15361 |
|
|
byte PPST5 :1; /* Pull Select Port T Bit 5 */
|
| 15362 |
|
|
byte PPST6 :1; /* Pull Select Port T Bit 6 */
|
| 15363 |
|
|
byte PPST7 :1; /* Pull Select Port T Bit 7 */
|
| 15364 |
|
|
} Bits;
|
| 15365 |
|
|
struct {
|
| 15366 |
|
|
byte grpPPST :8;
|
| 15367 |
|
|
} MergedBits;
|
| 15368 |
|
|
} PPSTSTR;
|
| 15369 |
|
|
extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245);
|
| 15370 |
|
|
#define PPST _PPST.Byte
|
| 15371 |
|
|
#define PPST_PPST0 _PPST.Bits.PPST0
|
| 15372 |
|
|
#define PPST_PPST1 _PPST.Bits.PPST1
|
| 15373 |
|
|
#define PPST_PPST2 _PPST.Bits.PPST2
|
| 15374 |
|
|
#define PPST_PPST3 _PPST.Bits.PPST3
|
| 15375 |
|
|
#define PPST_PPST4 _PPST.Bits.PPST4
|
| 15376 |
|
|
#define PPST_PPST5 _PPST.Bits.PPST5
|
| 15377 |
|
|
#define PPST_PPST6 _PPST.Bits.PPST6
|
| 15378 |
|
|
#define PPST_PPST7 _PPST.Bits.PPST7
|
| 15379 |
|
|
#define PPST_PPST _PPST.MergedBits.grpPPST
|
| 15380 |
|
|
|
| 15381 |
|
|
|
| 15382 |
|
|
/*** PTS - Port S I/O Register; 0x00000248 ***/
|
| 15383 |
|
|
typedef union {
|
| 15384 |
|
|
byte Byte;
|
| 15385 |
|
|
struct {
|
| 15386 |
|
|
byte PTS0 :1; /* Port S Bit 0 */
|
| 15387 |
|
|
byte PTS1 :1; /* Port S Bit 1 */
|
| 15388 |
|
|
byte PTS2 :1; /* Port S Bit 2 */
|
| 15389 |
|
|
byte PTS3 :1; /* Port S Bit 3 */
|
| 15390 |
|
|
byte PTS4 :1; /* Port S Bit 4 */
|
| 15391 |
|
|
byte PTS5 :1; /* Port S Bit 5 */
|
| 15392 |
|
|
byte PTS6 :1; /* Port S Bit 6 */
|
| 15393 |
|
|
byte PTS7 :1; /* Port S Bit 7 */
|
| 15394 |
|
|
} Bits;
|
| 15395 |
|
|
struct {
|
| 15396 |
|
|
byte grpPTS :8;
|
| 15397 |
|
|
} MergedBits;
|
| 15398 |
|
|
} PTSSTR;
|
| 15399 |
|
|
extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248);
|
| 15400 |
|
|
#define PTS _PTS.Byte
|
| 15401 |
|
|
#define PTS_PTS0 _PTS.Bits.PTS0
|
| 15402 |
|
|
#define PTS_PTS1 _PTS.Bits.PTS1
|
| 15403 |
|
|
#define PTS_PTS2 _PTS.Bits.PTS2
|
| 15404 |
|
|
#define PTS_PTS3 _PTS.Bits.PTS3
|
| 15405 |
|
|
#define PTS_PTS4 _PTS.Bits.PTS4
|
| 15406 |
|
|
#define PTS_PTS5 _PTS.Bits.PTS5
|
| 15407 |
|
|
#define PTS_PTS6 _PTS.Bits.PTS6
|
| 15408 |
|
|
#define PTS_PTS7 _PTS.Bits.PTS7
|
| 15409 |
|
|
#define PTS_PTS _PTS.MergedBits.grpPTS
|
| 15410 |
|
|
|
| 15411 |
|
|
|
| 15412 |
|
|
/*** PTIS - Port S Input; 0x00000249 ***/
|
| 15413 |
|
|
typedef union {
|
| 15414 |
|
|
byte Byte;
|
| 15415 |
|
|
struct {
|
| 15416 |
|
|
byte PTIS0 :1; /* Port S Bit 0 */
|
| 15417 |
|
|
byte PTIS1 :1; /* Port S Bit 1 */
|
| 15418 |
|
|
byte PTIS2 :1; /* Port S Bit 2 */
|
| 15419 |
|
|
byte PTIS3 :1; /* Port S Bit 3 */
|
| 15420 |
|
|
byte PTIS4 :1; /* Port S Bit 4 */
|
| 15421 |
|
|
byte PTIS5 :1; /* Port S Bit 5 */
|
| 15422 |
|
|
byte PTIS6 :1; /* Port S Bit 6 */
|
| 15423 |
|
|
byte PTIS7 :1; /* Port S Bit 7 */
|
| 15424 |
|
|
} Bits;
|
| 15425 |
|
|
struct {
|
| 15426 |
|
|
byte grpPTIS :8;
|
| 15427 |
|
|
} MergedBits;
|
| 15428 |
|
|
} PTISSTR;
|
| 15429 |
|
|
extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249);
|
| 15430 |
|
|
#define PTIS _PTIS.Byte
|
| 15431 |
|
|
#define PTIS_PTIS0 _PTIS.Bits.PTIS0
|
| 15432 |
|
|
#define PTIS_PTIS1 _PTIS.Bits.PTIS1
|
| 15433 |
|
|
#define PTIS_PTIS2 _PTIS.Bits.PTIS2
|
| 15434 |
|
|
#define PTIS_PTIS3 _PTIS.Bits.PTIS3
|
| 15435 |
|
|
#define PTIS_PTIS4 _PTIS.Bits.PTIS4
|
| 15436 |
|
|
#define PTIS_PTIS5 _PTIS.Bits.PTIS5
|
| 15437 |
|
|
#define PTIS_PTIS6 _PTIS.Bits.PTIS6
|
| 15438 |
|
|
#define PTIS_PTIS7 _PTIS.Bits.PTIS7
|
| 15439 |
|
|
#define PTIS_PTIS _PTIS.MergedBits.grpPTIS
|
| 15440 |
|
|
|
| 15441 |
|
|
|
| 15442 |
|
|
/*** DDRS - Port S Data Direction Register; 0x0000024A ***/
|
| 15443 |
|
|
typedef union {
|
| 15444 |
|
|
byte Byte;
|
| 15445 |
|
|
struct {
|
| 15446 |
|
|
byte DDRS0 :1; /* Data Direction Port S Bit 0 */
|
| 15447 |
|
|
byte DDRS1 :1; /* Data Direction Port S Bit 1 */
|
| 15448 |
|
|
byte DDRS2 :1; /* Data Direction Port S Bit 2 */
|
| 15449 |
|
|
byte DDRS3 :1; /* Data Direction Port S Bit 3 */
|
| 15450 |
|
|
byte DDRS4 :1; /* Data Direction Port S Bit 4 */
|
| 15451 |
|
|
byte DDRS5 :1; /* Data Direction Port S Bit 5 */
|
| 15452 |
|
|
byte DDRS6 :1; /* Data Direction Port S Bit 6 */
|
| 15453 |
|
|
byte DDRS7 :1; /* Data Direction Port S Bit 7 */
|
| 15454 |
|
|
} Bits;
|
| 15455 |
|
|
struct {
|
| 15456 |
|
|
byte grpDDRS :8;
|
| 15457 |
|
|
} MergedBits;
|
| 15458 |
|
|
} DDRSSTR;
|
| 15459 |
|
|
extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A);
|
| 15460 |
|
|
#define DDRS _DDRS.Byte
|
| 15461 |
|
|
#define DDRS_DDRS0 _DDRS.Bits.DDRS0
|
| 15462 |
|
|
#define DDRS_DDRS1 _DDRS.Bits.DDRS1
|
| 15463 |
|
|
#define DDRS_DDRS2 _DDRS.Bits.DDRS2
|
| 15464 |
|
|
#define DDRS_DDRS3 _DDRS.Bits.DDRS3
|
| 15465 |
|
|
#define DDRS_DDRS4 _DDRS.Bits.DDRS4
|
| 15466 |
|
|
#define DDRS_DDRS5 _DDRS.Bits.DDRS5
|
| 15467 |
|
|
#define DDRS_DDRS6 _DDRS.Bits.DDRS6
|
| 15468 |
|
|
#define DDRS_DDRS7 _DDRS.Bits.DDRS7
|
| 15469 |
|
|
#define DDRS_DDRS _DDRS.MergedBits.grpDDRS
|
| 15470 |
|
|
|
| 15471 |
|
|
|
| 15472 |
|
|
/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/
|
| 15473 |
|
|
typedef union {
|
| 15474 |
|
|
byte Byte;
|
| 15475 |
|
|
struct {
|
| 15476 |
|
|
byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */
|
| 15477 |
|
|
byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */
|
| 15478 |
|
|
byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */
|
| 15479 |
|
|
byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */
|
| 15480 |
|
|
byte RDRS4 :1; /* Reduced Drive Port S Bit 4 */
|
| 15481 |
|
|
byte RDRS5 :1; /* Reduced Drive Port S Bit 5 */
|
| 15482 |
|
|
byte RDRS6 :1; /* Reduced Drive Port S Bit 6 */
|
| 15483 |
|
|
byte RDRS7 :1; /* Reduced Drive Port S Bit 7 */
|
| 15484 |
|
|
} Bits;
|
| 15485 |
|
|
struct {
|
| 15486 |
|
|
byte grpRDRS :8;
|
| 15487 |
|
|
} MergedBits;
|
| 15488 |
|
|
} RDRSSTR;
|
| 15489 |
|
|
extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B);
|
| 15490 |
|
|
#define RDRS _RDRS.Byte
|
| 15491 |
|
|
#define RDRS_RDRS0 _RDRS.Bits.RDRS0
|
| 15492 |
|
|
#define RDRS_RDRS1 _RDRS.Bits.RDRS1
|
| 15493 |
|
|
#define RDRS_RDRS2 _RDRS.Bits.RDRS2
|
| 15494 |
|
|
#define RDRS_RDRS3 _RDRS.Bits.RDRS3
|
| 15495 |
|
|
#define RDRS_RDRS4 _RDRS.Bits.RDRS4
|
| 15496 |
|
|
#define RDRS_RDRS5 _RDRS.Bits.RDRS5
|
| 15497 |
|
|
#define RDRS_RDRS6 _RDRS.Bits.RDRS6
|
| 15498 |
|
|
#define RDRS_RDRS7 _RDRS.Bits.RDRS7
|
| 15499 |
|
|
#define RDRS_RDRS _RDRS.MergedBits.grpRDRS
|
| 15500 |
|
|
|
| 15501 |
|
|
|
| 15502 |
|
|
/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/
|
| 15503 |
|
|
typedef union {
|
| 15504 |
|
|
byte Byte;
|
| 15505 |
|
|
struct {
|
| 15506 |
|
|
byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */
|
| 15507 |
|
|
byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */
|
| 15508 |
|
|
byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */
|
| 15509 |
|
|
byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */
|
| 15510 |
|
|
byte PERS4 :1; /* Pull Device Enable Port S Bit 4 */
|
| 15511 |
|
|
byte PERS5 :1; /* Pull Device Enable Port S Bit 5 */
|
| 15512 |
|
|
byte PERS6 :1; /* Pull Device Enable Port S Bit 6 */
|
| 15513 |
|
|
byte PERS7 :1; /* Pull Device Enable Port S Bit 7 */
|
| 15514 |
|
|
} Bits;
|
| 15515 |
|
|
struct {
|
| 15516 |
|
|
byte grpPERS :8;
|
| 15517 |
|
|
} MergedBits;
|
| 15518 |
|
|
} PERSSTR;
|
| 15519 |
|
|
extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C);
|
| 15520 |
|
|
#define PERS _PERS.Byte
|
| 15521 |
|
|
#define PERS_PERS0 _PERS.Bits.PERS0
|
| 15522 |
|
|
#define PERS_PERS1 _PERS.Bits.PERS1
|
| 15523 |
|
|
#define PERS_PERS2 _PERS.Bits.PERS2
|
| 15524 |
|
|
#define PERS_PERS3 _PERS.Bits.PERS3
|
| 15525 |
|
|
#define PERS_PERS4 _PERS.Bits.PERS4
|
| 15526 |
|
|
#define PERS_PERS5 _PERS.Bits.PERS5
|
| 15527 |
|
|
#define PERS_PERS6 _PERS.Bits.PERS6
|
| 15528 |
|
|
#define PERS_PERS7 _PERS.Bits.PERS7
|
| 15529 |
|
|
#define PERS_PERS _PERS.MergedBits.grpPERS
|
| 15530 |
|
|
|
| 15531 |
|
|
|
| 15532 |
|
|
/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/
|
| 15533 |
|
|
typedef union {
|
| 15534 |
|
|
byte Byte;
|
| 15535 |
|
|
struct {
|
| 15536 |
|
|
byte PPSS0 :1; /* Pull Select Port S Bit 0 */
|
| 15537 |
|
|
byte PPSS1 :1; /* Pull Select Port S Bit 1 */
|
| 15538 |
|
|
byte PPSS2 :1; /* Pull Select Port S Bit 2 */
|
| 15539 |
|
|
byte PPSS3 :1; /* Pull Select Port S Bit 3 */
|
| 15540 |
|
|
byte PPSS4 :1; /* Pull Select Port S Bit 4 */
|
| 15541 |
|
|
byte PPSS5 :1; /* Pull Select Port S Bit 5 */
|
| 15542 |
|
|
byte PPSS6 :1; /* Pull Select Port S Bit 6 */
|
| 15543 |
|
|
byte PPSS7 :1; /* Pull Select Port S Bit 7 */
|
| 15544 |
|
|
} Bits;
|
| 15545 |
|
|
struct {
|
| 15546 |
|
|
byte grpPPSS :8;
|
| 15547 |
|
|
} MergedBits;
|
| 15548 |
|
|
} PPSSSTR;
|
| 15549 |
|
|
extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D);
|
| 15550 |
|
|
#define PPSS _PPSS.Byte
|
| 15551 |
|
|
#define PPSS_PPSS0 _PPSS.Bits.PPSS0
|
| 15552 |
|
|
#define PPSS_PPSS1 _PPSS.Bits.PPSS1
|
| 15553 |
|
|
#define PPSS_PPSS2 _PPSS.Bits.PPSS2
|
| 15554 |
|
|
#define PPSS_PPSS3 _PPSS.Bits.PPSS3
|
| 15555 |
|
|
#define PPSS_PPSS4 _PPSS.Bits.PPSS4
|
| 15556 |
|
|
#define PPSS_PPSS5 _PPSS.Bits.PPSS5
|
| 15557 |
|
|
#define PPSS_PPSS6 _PPSS.Bits.PPSS6
|
| 15558 |
|
|
#define PPSS_PPSS7 _PPSS.Bits.PPSS7
|
| 15559 |
|
|
#define PPSS_PPSS _PPSS.MergedBits.grpPPSS
|
| 15560 |
|
|
|
| 15561 |
|
|
|
| 15562 |
|
|
/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/
|
| 15563 |
|
|
typedef union {
|
| 15564 |
|
|
byte Byte;
|
| 15565 |
|
|
struct {
|
| 15566 |
|
|
byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */
|
| 15567 |
|
|
byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */
|
| 15568 |
|
|
byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */
|
| 15569 |
|
|
byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */
|
| 15570 |
|
|
byte WOMS4 :1; /* Wired-Or Mode Port S Bit 4 */
|
| 15571 |
|
|
byte WOMS5 :1; /* Wired-Or Mode Port S Bit 5 */
|
| 15572 |
|
|
byte WOMS6 :1; /* Wired-Or Mode Port S Bit 6 */
|
| 15573 |
|
|
byte WOMS7 :1; /* Wired-Or Mode Port S Bit 7 */
|
| 15574 |
|
|
} Bits;
|
| 15575 |
|
|
struct {
|
| 15576 |
|
|
byte grpWOMS :8;
|
| 15577 |
|
|
} MergedBits;
|
| 15578 |
|
|
} WOMSSTR;
|
| 15579 |
|
|
extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E);
|
| 15580 |
|
|
#define WOMS _WOMS.Byte
|
| 15581 |
|
|
#define WOMS_WOMS0 _WOMS.Bits.WOMS0
|
| 15582 |
|
|
#define WOMS_WOMS1 _WOMS.Bits.WOMS1
|
| 15583 |
|
|
#define WOMS_WOMS2 _WOMS.Bits.WOMS2
|
| 15584 |
|
|
#define WOMS_WOMS3 _WOMS.Bits.WOMS3
|
| 15585 |
|
|
#define WOMS_WOMS4 _WOMS.Bits.WOMS4
|
| 15586 |
|
|
#define WOMS_WOMS5 _WOMS.Bits.WOMS5
|
| 15587 |
|
|
#define WOMS_WOMS6 _WOMS.Bits.WOMS6
|
| 15588 |
|
|
#define WOMS_WOMS7 _WOMS.Bits.WOMS7
|
| 15589 |
|
|
#define WOMS_WOMS _WOMS.MergedBits.grpWOMS
|
| 15590 |
|
|
|
| 15591 |
|
|
|
| 15592 |
|
|
/*** PTM - Port M I/O Register; 0x00000250 ***/
|
| 15593 |
|
|
typedef union {
|
| 15594 |
|
|
byte Byte;
|
| 15595 |
|
|
struct {
|
| 15596 |
|
|
byte PTM0 :1; /* Port T Bit 0 */
|
| 15597 |
|
|
byte PTM1 :1; /* Port T Bit 1 */
|
| 15598 |
|
|
byte PTM2 :1; /* Port T Bit 2 */
|
| 15599 |
|
|
byte PTM3 :1; /* Port T Bit 3 */
|
| 15600 |
|
|
byte PTM4 :1; /* Port T Bit 4 */
|
| 15601 |
|
|
byte PTM5 :1; /* Port T Bit 5 */
|
| 15602 |
|
|
byte PTM6 :1; /* Port T Bit 6 */
|
| 15603 |
|
|
byte PTM7 :1; /* Port T Bit 7 */
|
| 15604 |
|
|
} Bits;
|
| 15605 |
|
|
struct {
|
| 15606 |
|
|
byte grpPTM :8;
|
| 15607 |
|
|
} MergedBits;
|
| 15608 |
|
|
} PTMSTR;
|
| 15609 |
|
|
extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250);
|
| 15610 |
|
|
#define PTM _PTM.Byte
|
| 15611 |
|
|
#define PTM_PTM0 _PTM.Bits.PTM0
|
| 15612 |
|
|
#define PTM_PTM1 _PTM.Bits.PTM1
|
| 15613 |
|
|
#define PTM_PTM2 _PTM.Bits.PTM2
|
| 15614 |
|
|
#define PTM_PTM3 _PTM.Bits.PTM3
|
| 15615 |
|
|
#define PTM_PTM4 _PTM.Bits.PTM4
|
| 15616 |
|
|
#define PTM_PTM5 _PTM.Bits.PTM5
|
| 15617 |
|
|
#define PTM_PTM6 _PTM.Bits.PTM6
|
| 15618 |
|
|
#define PTM_PTM7 _PTM.Bits.PTM7
|
| 15619 |
|
|
#define PTM_PTM _PTM.MergedBits.grpPTM
|
| 15620 |
|
|
|
| 15621 |
|
|
|
| 15622 |
|
|
/*** PTIM - Port M Input; 0x00000251 ***/
|
| 15623 |
|
|
typedef union {
|
| 15624 |
|
|
byte Byte;
|
| 15625 |
|
|
struct {
|
| 15626 |
|
|
byte PTIM0 :1; /* Port M Bit 0 */
|
| 15627 |
|
|
byte PTIM1 :1; /* Port M Bit 1 */
|
| 15628 |
|
|
byte PTIM2 :1; /* Port M Bit 2 */
|
| 15629 |
|
|
byte PTIM3 :1; /* Port M Bit 3 */
|
| 15630 |
|
|
byte PTIM4 :1; /* Port M Bit 4 */
|
| 15631 |
|
|
byte PTIM5 :1; /* Port M Bit 5 */
|
| 15632 |
|
|
byte PTIM6 :1; /* Port M Bit 6 */
|
| 15633 |
|
|
byte PTIM7 :1; /* Port M Bit 7 */
|
| 15634 |
|
|
} Bits;
|
| 15635 |
|
|
struct {
|
| 15636 |
|
|
byte grpPTIM :8;
|
| 15637 |
|
|
} MergedBits;
|
| 15638 |
|
|
} PTIMSTR;
|
| 15639 |
|
|
extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251);
|
| 15640 |
|
|
#define PTIM _PTIM.Byte
|
| 15641 |
|
|
#define PTIM_PTIM0 _PTIM.Bits.PTIM0
|
| 15642 |
|
|
#define PTIM_PTIM1 _PTIM.Bits.PTIM1
|
| 15643 |
|
|
#define PTIM_PTIM2 _PTIM.Bits.PTIM2
|
| 15644 |
|
|
#define PTIM_PTIM3 _PTIM.Bits.PTIM3
|
| 15645 |
|
|
#define PTIM_PTIM4 _PTIM.Bits.PTIM4
|
| 15646 |
|
|
#define PTIM_PTIM5 _PTIM.Bits.PTIM5
|
| 15647 |
|
|
#define PTIM_PTIM6 _PTIM.Bits.PTIM6
|
| 15648 |
|
|
#define PTIM_PTIM7 _PTIM.Bits.PTIM7
|
| 15649 |
|
|
#define PTIM_PTIM _PTIM.MergedBits.grpPTIM
|
| 15650 |
|
|
|
| 15651 |
|
|
|
| 15652 |
|
|
/*** DDRM - Port M Data Direction Register; 0x00000252 ***/
|
| 15653 |
|
|
typedef union {
|
| 15654 |
|
|
byte Byte;
|
| 15655 |
|
|
struct {
|
| 15656 |
|
|
byte DDRM0 :1; /* Data Direction Port M Bit 0 */
|
| 15657 |
|
|
byte DDRM1 :1; /* Data Direction Port M Bit 1 */
|
| 15658 |
|
|
byte DDRM2 :1; /* Data Direction Port M Bit 2 */
|
| 15659 |
|
|
byte DDRM3 :1; /* Data Direction Port M Bit 3 */
|
| 15660 |
|
|
byte DDRM4 :1; /* Data Direction Port M Bit 4 */
|
| 15661 |
|
|
byte DDRM5 :1; /* Data Direction Port M Bit 5 */
|
| 15662 |
|
|
byte DDRM6 :1; /* Data Direction Port M Bit 6 */
|
| 15663 |
|
|
byte DDRM7 :1; /* Data Direction Port M Bit 7 */
|
| 15664 |
|
|
} Bits;
|
| 15665 |
|
|
struct {
|
| 15666 |
|
|
byte grpDDRM :8;
|
| 15667 |
|
|
} MergedBits;
|
| 15668 |
|
|
} DDRMSTR;
|
| 15669 |
|
|
extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252);
|
| 15670 |
|
|
#define DDRM _DDRM.Byte
|
| 15671 |
|
|
#define DDRM_DDRM0 _DDRM.Bits.DDRM0
|
| 15672 |
|
|
#define DDRM_DDRM1 _DDRM.Bits.DDRM1
|
| 15673 |
|
|
#define DDRM_DDRM2 _DDRM.Bits.DDRM2
|
| 15674 |
|
|
#define DDRM_DDRM3 _DDRM.Bits.DDRM3
|
| 15675 |
|
|
#define DDRM_DDRM4 _DDRM.Bits.DDRM4
|
| 15676 |
|
|
#define DDRM_DDRM5 _DDRM.Bits.DDRM5
|
| 15677 |
|
|
#define DDRM_DDRM6 _DDRM.Bits.DDRM6
|
| 15678 |
|
|
#define DDRM_DDRM7 _DDRM.Bits.DDRM7
|
| 15679 |
|
|
#define DDRM_DDRM _DDRM.MergedBits.grpDDRM
|
| 15680 |
|
|
|
| 15681 |
|
|
|
| 15682 |
|
|
/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/
|
| 15683 |
|
|
typedef union {
|
| 15684 |
|
|
byte Byte;
|
| 15685 |
|
|
struct {
|
| 15686 |
|
|
byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */
|
| 15687 |
|
|
byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */
|
| 15688 |
|
|
byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */
|
| 15689 |
|
|
byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */
|
| 15690 |
|
|
byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */
|
| 15691 |
|
|
byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */
|
| 15692 |
|
|
byte RDRM6 :1; /* Reduced Drive Port M Bit 6 */
|
| 15693 |
|
|
byte RDRM7 :1; /* Reduced Drive Port M Bit 7 */
|
| 15694 |
|
|
} Bits;
|
| 15695 |
|
|
struct {
|
| 15696 |
|
|
byte grpRDRM :8;
|
| 15697 |
|
|
} MergedBits;
|
| 15698 |
|
|
} RDRMSTR;
|
| 15699 |
|
|
extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253);
|
| 15700 |
|
|
#define RDRM _RDRM.Byte
|
| 15701 |
|
|
#define RDRM_RDRM0 _RDRM.Bits.RDRM0
|
| 15702 |
|
|
#define RDRM_RDRM1 _RDRM.Bits.RDRM1
|
| 15703 |
|
|
#define RDRM_RDRM2 _RDRM.Bits.RDRM2
|
| 15704 |
|
|
#define RDRM_RDRM3 _RDRM.Bits.RDRM3
|
| 15705 |
|
|
#define RDRM_RDRM4 _RDRM.Bits.RDRM4
|
| 15706 |
|
|
#define RDRM_RDRM5 _RDRM.Bits.RDRM5
|
| 15707 |
|
|
#define RDRM_RDRM6 _RDRM.Bits.RDRM6
|
| 15708 |
|
|
#define RDRM_RDRM7 _RDRM.Bits.RDRM7
|
| 15709 |
|
|
#define RDRM_RDRM _RDRM.MergedBits.grpRDRM
|
| 15710 |
|
|
|
| 15711 |
|
|
|
| 15712 |
|
|
/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/
|
| 15713 |
|
|
typedef union {
|
| 15714 |
|
|
byte Byte;
|
| 15715 |
|
|
struct {
|
| 15716 |
|
|
byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */
|
| 15717 |
|
|
byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */
|
| 15718 |
|
|
byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */
|
| 15719 |
|
|
byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */
|
| 15720 |
|
|
byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */
|
| 15721 |
|
|
byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */
|
| 15722 |
|
|
byte PERM6 :1; /* Pull Device Enable Port M Bit 6 */
|
| 15723 |
|
|
byte PERM7 :1; /* Pull Device Enable Port M Bit 7 */
|
| 15724 |
|
|
} Bits;
|
| 15725 |
|
|
struct {
|
| 15726 |
|
|
byte grpPERM :8;
|
| 15727 |
|
|
} MergedBits;
|
| 15728 |
|
|
} PERMSTR;
|
| 15729 |
|
|
extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254);
|
| 15730 |
|
|
#define PERM _PERM.Byte
|
| 15731 |
|
|
#define PERM_PERM0 _PERM.Bits.PERM0
|
| 15732 |
|
|
#define PERM_PERM1 _PERM.Bits.PERM1
|
| 15733 |
|
|
#define PERM_PERM2 _PERM.Bits.PERM2
|
| 15734 |
|
|
#define PERM_PERM3 _PERM.Bits.PERM3
|
| 15735 |
|
|
#define PERM_PERM4 _PERM.Bits.PERM4
|
| 15736 |
|
|
#define PERM_PERM5 _PERM.Bits.PERM5
|
| 15737 |
|
|
#define PERM_PERM6 _PERM.Bits.PERM6
|
| 15738 |
|
|
#define PERM_PERM7 _PERM.Bits.PERM7
|
| 15739 |
|
|
#define PERM_PERM _PERM.MergedBits.grpPERM
|
| 15740 |
|
|
|
| 15741 |
|
|
|
| 15742 |
|
|
/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/
|
| 15743 |
|
|
typedef union {
|
| 15744 |
|
|
byte Byte;
|
| 15745 |
|
|
struct {
|
| 15746 |
|
|
byte PPSM0 :1; /* Pull Select Port M Bit 0 */
|
| 15747 |
|
|
byte PPSM1 :1; /* Pull Select Port M Bit 1 */
|
| 15748 |
|
|
byte PPSM2 :1; /* Pull Select Port M Bit 2 */
|
| 15749 |
|
|
byte PPSM3 :1; /* Pull Select Port M Bit 3 */
|
| 15750 |
|
|
byte PPSM4 :1; /* Pull Select Port M Bit 4 */
|
| 15751 |
|
|
byte PPSM5 :1; /* Pull Select Port M Bit 5 */
|
| 15752 |
|
|
byte PPSM6 :1; /* Pull Select Port M Bit 6 */
|
| 15753 |
|
|
byte PPSM7 :1; /* Pull Select Port M Bit 7 */
|
| 15754 |
|
|
} Bits;
|
| 15755 |
|
|
struct {
|
| 15756 |
|
|
byte grpPPSM :8;
|
| 15757 |
|
|
} MergedBits;
|
| 15758 |
|
|
} PPSMSTR;
|
| 15759 |
|
|
extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255);
|
| 15760 |
|
|
#define PPSM _PPSM.Byte
|
| 15761 |
|
|
#define PPSM_PPSM0 _PPSM.Bits.PPSM0
|
| 15762 |
|
|
#define PPSM_PPSM1 _PPSM.Bits.PPSM1
|
| 15763 |
|
|
#define PPSM_PPSM2 _PPSM.Bits.PPSM2
|
| 15764 |
|
|
#define PPSM_PPSM3 _PPSM.Bits.PPSM3
|
| 15765 |
|
|
#define PPSM_PPSM4 _PPSM.Bits.PPSM4
|
| 15766 |
|
|
#define PPSM_PPSM5 _PPSM.Bits.PPSM5
|
| 15767 |
|
|
#define PPSM_PPSM6 _PPSM.Bits.PPSM6
|
| 15768 |
|
|
#define PPSM_PPSM7 _PPSM.Bits.PPSM7
|
| 15769 |
|
|
#define PPSM_PPSM _PPSM.MergedBits.grpPPSM
|
| 15770 |
|
|
|
| 15771 |
|
|
|
| 15772 |
|
|
/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/
|
| 15773 |
|
|
typedef union {
|
| 15774 |
|
|
byte Byte;
|
| 15775 |
|
|
struct {
|
| 15776 |
|
|
byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */
|
| 15777 |
|
|
byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */
|
| 15778 |
|
|
byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */
|
| 15779 |
|
|
byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */
|
| 15780 |
|
|
byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */
|
| 15781 |
|
|
byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */
|
| 15782 |
|
|
byte WOMM6 :1; /* Wired-Or Mode Port M Bit 6 */
|
| 15783 |
|
|
byte WOMM7 :1; /* Wired-Or Mode Port M Bit 7 */
|
| 15784 |
|
|
} Bits;
|
| 15785 |
|
|
struct {
|
| 15786 |
|
|
byte grpWOMM :8;
|
| 15787 |
|
|
} MergedBits;
|
| 15788 |
|
|
} WOMMSTR;
|
| 15789 |
|
|
extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256);
|
| 15790 |
|
|
#define WOMM _WOMM.Byte
|
| 15791 |
|
|
#define WOMM_WOMM0 _WOMM.Bits.WOMM0
|
| 15792 |
|
|
#define WOMM_WOMM1 _WOMM.Bits.WOMM1
|
| 15793 |
|
|
#define WOMM_WOMM2 _WOMM.Bits.WOMM2
|
| 15794 |
|
|
#define WOMM_WOMM3 _WOMM.Bits.WOMM3
|
| 15795 |
|
|
#define WOMM_WOMM4 _WOMM.Bits.WOMM4
|
| 15796 |
|
|
#define WOMM_WOMM5 _WOMM.Bits.WOMM5
|
| 15797 |
|
|
#define WOMM_WOMM6 _WOMM.Bits.WOMM6
|
| 15798 |
|
|
#define WOMM_WOMM7 _WOMM.Bits.WOMM7
|
| 15799 |
|
|
#define WOMM_WOMM _WOMM.MergedBits.grpWOMM
|
| 15800 |
|
|
|
| 15801 |
|
|
|
| 15802 |
|
|
/*** MODRR - Module Routing Register; 0x00000257 ***/
|
| 15803 |
|
|
typedef union {
|
| 15804 |
|
|
byte Byte;
|
| 15805 |
|
|
struct {
|
| 15806 |
|
|
byte MODRR0 :1; /* CAN0 Routing */
|
| 15807 |
|
|
byte MODRR1 :1; /* CAN0 Routing */
|
| 15808 |
|
|
byte MODRR2 :1; /* CAN4 Routing */
|
| 15809 |
|
|
byte MODRR3 :1; /* CAN4 Routing */
|
| 15810 |
|
|
byte MODRR4 :1; /* SPI0 Routing */
|
| 15811 |
|
|
byte MODRR5 :1; /* SPI1 Routing */
|
| 15812 |
|
|
byte MODRR6 :1; /* SPI2 Routing */
|
| 15813 |
|
|
byte :1;
|
| 15814 |
|
|
} Bits;
|
| 15815 |
|
|
struct {
|
| 15816 |
|
|
byte grpMODRR :7;
|
| 15817 |
|
|
byte :1;
|
| 15818 |
|
|
} MergedBits;
|
| 15819 |
|
|
} MODRRSTR;
|
| 15820 |
|
|
extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000257);
|
| 15821 |
|
|
#define MODRR _MODRR.Byte
|
| 15822 |
|
|
#define MODRR_MODRR0 _MODRR.Bits.MODRR0
|
| 15823 |
|
|
#define MODRR_MODRR1 _MODRR.Bits.MODRR1
|
| 15824 |
|
|
#define MODRR_MODRR2 _MODRR.Bits.MODRR2
|
| 15825 |
|
|
#define MODRR_MODRR3 _MODRR.Bits.MODRR3
|
| 15826 |
|
|
#define MODRR_MODRR4 _MODRR.Bits.MODRR4
|
| 15827 |
|
|
#define MODRR_MODRR5 _MODRR.Bits.MODRR5
|
| 15828 |
|
|
#define MODRR_MODRR6 _MODRR.Bits.MODRR6
|
| 15829 |
|
|
#define MODRR_MODRR _MODRR.MergedBits.grpMODRR
|
| 15830 |
|
|
|
| 15831 |
|
|
|
| 15832 |
|
|
/*** PTP - Port P I/O Register; 0x00000258 ***/
|
| 15833 |
|
|
typedef union {
|
| 15834 |
|
|
byte Byte;
|
| 15835 |
|
|
struct {
|
| 15836 |
|
|
byte PTP0 :1; /* Port P Bit 0 */
|
| 15837 |
|
|
byte PTP1 :1; /* Port P Bit 1 */
|
| 15838 |
|
|
byte PTP2 :1; /* Port P Bit 2 */
|
| 15839 |
|
|
byte PTP3 :1; /* Port P Bit 3 */
|
| 15840 |
|
|
byte PTP4 :1; /* Port P Bit 4 */
|
| 15841 |
|
|
byte PTP5 :1; /* Port P Bit 5 */
|
| 15842 |
|
|
byte PTP6 :1; /* Port P Bit 6 */
|
| 15843 |
|
|
byte PTP7 :1; /* Port P Bit 7 */
|
| 15844 |
|
|
} Bits;
|
| 15845 |
|
|
struct {
|
| 15846 |
|
|
byte grpPTP :8;
|
| 15847 |
|
|
} MergedBits;
|
| 15848 |
|
|
} PTPSTR;
|
| 15849 |
|
|
extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258);
|
| 15850 |
|
|
#define PTP _PTP.Byte
|
| 15851 |
|
|
#define PTP_PTP0 _PTP.Bits.PTP0
|
| 15852 |
|
|
#define PTP_PTP1 _PTP.Bits.PTP1
|
| 15853 |
|
|
#define PTP_PTP2 _PTP.Bits.PTP2
|
| 15854 |
|
|
#define PTP_PTP3 _PTP.Bits.PTP3
|
| 15855 |
|
|
#define PTP_PTP4 _PTP.Bits.PTP4
|
| 15856 |
|
|
#define PTP_PTP5 _PTP.Bits.PTP5
|
| 15857 |
|
|
#define PTP_PTP6 _PTP.Bits.PTP6
|
| 15858 |
|
|
#define PTP_PTP7 _PTP.Bits.PTP7
|
| 15859 |
|
|
#define PTP_PTP _PTP.MergedBits.grpPTP
|
| 15860 |
|
|
|
| 15861 |
|
|
|
| 15862 |
|
|
/*** PTIP - Port P Input; 0x00000259 ***/
|
| 15863 |
|
|
typedef union {
|
| 15864 |
|
|
byte Byte;
|
| 15865 |
|
|
struct {
|
| 15866 |
|
|
byte PTIP0 :1; /* Port P Bit 0 */
|
| 15867 |
|
|
byte PTIP1 :1; /* Port P Bit 1 */
|
| 15868 |
|
|
byte PTIP2 :1; /* Port P Bit 2 */
|
| 15869 |
|
|
byte PTIP3 :1; /* Port P Bit 3 */
|
| 15870 |
|
|
byte PTIP4 :1; /* Port P Bit 4 */
|
| 15871 |
|
|
byte PTIP5 :1; /* Port P Bit 5 */
|
| 15872 |
|
|
byte PTIP6 :1; /* Port P Bit 6 */
|
| 15873 |
|
|
byte PTIP7 :1; /* Port P Bit 7 */
|
| 15874 |
|
|
} Bits;
|
| 15875 |
|
|
struct {
|
| 15876 |
|
|
byte grpPTIP :8;
|
| 15877 |
|
|
} MergedBits;
|
| 15878 |
|
|
} PTIPSTR;
|
| 15879 |
|
|
extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259);
|
| 15880 |
|
|
#define PTIP _PTIP.Byte
|
| 15881 |
|
|
#define PTIP_PTIP0 _PTIP.Bits.PTIP0
|
| 15882 |
|
|
#define PTIP_PTIP1 _PTIP.Bits.PTIP1
|
| 15883 |
|
|
#define PTIP_PTIP2 _PTIP.Bits.PTIP2
|
| 15884 |
|
|
#define PTIP_PTIP3 _PTIP.Bits.PTIP3
|
| 15885 |
|
|
#define PTIP_PTIP4 _PTIP.Bits.PTIP4
|
| 15886 |
|
|
#define PTIP_PTIP5 _PTIP.Bits.PTIP5
|
| 15887 |
|
|
#define PTIP_PTIP6 _PTIP.Bits.PTIP6
|
| 15888 |
|
|
#define PTIP_PTIP7 _PTIP.Bits.PTIP7
|
| 15889 |
|
|
#define PTIP_PTIP _PTIP.MergedBits.grpPTIP
|
| 15890 |
|
|
|
| 15891 |
|
|
|
| 15892 |
|
|
/*** DDRP - Port P Data Direction Register; 0x0000025A ***/
|
| 15893 |
|
|
typedef union {
|
| 15894 |
|
|
byte Byte;
|
| 15895 |
|
|
struct {
|
| 15896 |
|
|
byte DDRP0 :1; /* Data Direction Port P Bit 0 */
|
| 15897 |
|
|
byte DDRP1 :1; /* Data Direction Port P Bit 1 */
|
| 15898 |
|
|
byte DDRP2 :1; /* Data Direction Port P Bit 2 */
|
| 15899 |
|
|
byte DDRP3 :1; /* Data Direction Port P Bit 3 */
|
| 15900 |
|
|
byte DDRP4 :1; /* Data Direction Port P Bit 4 */
|
| 15901 |
|
|
byte DDRP5 :1; /* Data Direction Port P Bit 5 */
|
| 15902 |
|
|
byte DDRP6 :1; /* Data Direction Port P Bit 6 */
|
| 15903 |
|
|
byte DDRP7 :1; /* Data Direction Port P Bit 7 */
|
| 15904 |
|
|
} Bits;
|
| 15905 |
|
|
struct {
|
| 15906 |
|
|
byte grpDDRP :8;
|
| 15907 |
|
|
} MergedBits;
|
| 15908 |
|
|
} DDRPSTR;
|
| 15909 |
|
|
extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A);
|
| 15910 |
|
|
#define DDRP _DDRP.Byte
|
| 15911 |
|
|
#define DDRP_DDRP0 _DDRP.Bits.DDRP0
|
| 15912 |
|
|
#define DDRP_DDRP1 _DDRP.Bits.DDRP1
|
| 15913 |
|
|
#define DDRP_DDRP2 _DDRP.Bits.DDRP2
|
| 15914 |
|
|
#define DDRP_DDRP3 _DDRP.Bits.DDRP3
|
| 15915 |
|
|
#define DDRP_DDRP4 _DDRP.Bits.DDRP4
|
| 15916 |
|
|
#define DDRP_DDRP5 _DDRP.Bits.DDRP5
|
| 15917 |
|
|
#define DDRP_DDRP6 _DDRP.Bits.DDRP6
|
| 15918 |
|
|
#define DDRP_DDRP7 _DDRP.Bits.DDRP7
|
| 15919 |
|
|
#define DDRP_DDRP _DDRP.MergedBits.grpDDRP
|
| 15920 |
|
|
|
| 15921 |
|
|
|
| 15922 |
|
|
/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/
|
| 15923 |
|
|
typedef union {
|
| 15924 |
|
|
byte Byte;
|
| 15925 |
|
|
struct {
|
| 15926 |
|
|
byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */
|
| 15927 |
|
|
byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */
|
| 15928 |
|
|
byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */
|
| 15929 |
|
|
byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */
|
| 15930 |
|
|
byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */
|
| 15931 |
|
|
byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */
|
| 15932 |
|
|
byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */
|
| 15933 |
|
|
byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */
|
| 15934 |
|
|
} Bits;
|
| 15935 |
|
|
struct {
|
| 15936 |
|
|
byte grpRDRP :8;
|
| 15937 |
|
|
} MergedBits;
|
| 15938 |
|
|
} RDRPSTR;
|
| 15939 |
|
|
extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B);
|
| 15940 |
|
|
#define RDRP _RDRP.Byte
|
| 15941 |
|
|
#define RDRP_RDRP0 _RDRP.Bits.RDRP0
|
| 15942 |
|
|
#define RDRP_RDRP1 _RDRP.Bits.RDRP1
|
| 15943 |
|
|
#define RDRP_RDRP2 _RDRP.Bits.RDRP2
|
| 15944 |
|
|
#define RDRP_RDRP3 _RDRP.Bits.RDRP3
|
| 15945 |
|
|
#define RDRP_RDRP4 _RDRP.Bits.RDRP4
|
| 15946 |
|
|
#define RDRP_RDRP5 _RDRP.Bits.RDRP5
|
| 15947 |
|
|
#define RDRP_RDRP6 _RDRP.Bits.RDRP6
|
| 15948 |
|
|
#define RDRP_RDRP7 _RDRP.Bits.RDRP7
|
| 15949 |
|
|
#define RDRP_RDRP _RDRP.MergedBits.grpRDRP
|
| 15950 |
|
|
|
| 15951 |
|
|
|
| 15952 |
|
|
/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/
|
| 15953 |
|
|
typedef union {
|
| 15954 |
|
|
byte Byte;
|
| 15955 |
|
|
struct {
|
| 15956 |
|
|
byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */
|
| 15957 |
|
|
byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */
|
| 15958 |
|
|
byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */
|
| 15959 |
|
|
byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */
|
| 15960 |
|
|
byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */
|
| 15961 |
|
|
byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */
|
| 15962 |
|
|
byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */
|
| 15963 |
|
|
byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */
|
| 15964 |
|
|
} Bits;
|
| 15965 |
|
|
struct {
|
| 15966 |
|
|
byte grpPERP :8;
|
| 15967 |
|
|
} MergedBits;
|
| 15968 |
|
|
} PERPSTR;
|
| 15969 |
|
|
extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C);
|
| 15970 |
|
|
#define PERP _PERP.Byte
|
| 15971 |
|
|
#define PERP_PERP0 _PERP.Bits.PERP0
|
| 15972 |
|
|
#define PERP_PERP1 _PERP.Bits.PERP1
|
| 15973 |
|
|
#define PERP_PERP2 _PERP.Bits.PERP2
|
| 15974 |
|
|
#define PERP_PERP3 _PERP.Bits.PERP3
|
| 15975 |
|
|
#define PERP_PERP4 _PERP.Bits.PERP4
|
| 15976 |
|
|
#define PERP_PERP5 _PERP.Bits.PERP5
|
| 15977 |
|
|
#define PERP_PERP6 _PERP.Bits.PERP6
|
| 15978 |
|
|
#define PERP_PERP7 _PERP.Bits.PERP7
|
| 15979 |
|
|
#define PERP_PERP _PERP.MergedBits.grpPERP
|
| 15980 |
|
|
|
| 15981 |
|
|
|
| 15982 |
|
|
/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/
|
| 15983 |
|
|
typedef union {
|
| 15984 |
|
|
byte Byte;
|
| 15985 |
|
|
struct {
|
| 15986 |
|
|
byte PPSP0 :1; /* Pull Select Port P Bit 0 */
|
| 15987 |
|
|
byte PPSP1 :1; /* Pull Select Port P Bit 1 */
|
| 15988 |
|
|
byte PPSP2 :1; /* Pull Select Port P Bit 2 */
|
| 15989 |
|
|
byte PPSP3 :1; /* Pull Select Port P Bit 3 */
|
| 15990 |
|
|
byte PPSP4 :1; /* Pull Select Port P Bit 4 */
|
| 15991 |
|
|
byte PPSP5 :1; /* Pull Select Port P Bit 5 */
|
| 15992 |
|
|
byte PPSP6 :1; /* Pull Select Port P Bit 6 */
|
| 15993 |
|
|
byte PPSP7 :1; /* Pull Select Port P Bit 7 */
|
| 15994 |
|
|
} Bits;
|
| 15995 |
|
|
struct {
|
| 15996 |
|
|
byte grpPPSP :8;
|
| 15997 |
|
|
} MergedBits;
|
| 15998 |
|
|
} PPSPSTR;
|
| 15999 |
|
|
extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D);
|
| 16000 |
|
|
#define PPSP _PPSP.Byte
|
| 16001 |
|
|
#define PPSP_PPSP0 _PPSP.Bits.PPSP0
|
| 16002 |
|
|
#define PPSP_PPSP1 _PPSP.Bits.PPSP1
|
| 16003 |
|
|
#define PPSP_PPSP2 _PPSP.Bits.PPSP2
|
| 16004 |
|
|
#define PPSP_PPSP3 _PPSP.Bits.PPSP3
|
| 16005 |
|
|
#define PPSP_PPSP4 _PPSP.Bits.PPSP4
|
| 16006 |
|
|
#define PPSP_PPSP5 _PPSP.Bits.PPSP5
|
| 16007 |
|
|
#define PPSP_PPSP6 _PPSP.Bits.PPSP6
|
| 16008 |
|
|
#define PPSP_PPSP7 _PPSP.Bits.PPSP7
|
| 16009 |
|
|
#define PPSP_PPSP _PPSP.MergedBits.grpPPSP
|
| 16010 |
|
|
|
| 16011 |
|
|
|
| 16012 |
|
|
/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/
|
| 16013 |
|
|
typedef union {
|
| 16014 |
|
|
byte Byte;
|
| 16015 |
|
|
struct {
|
| 16016 |
|
|
byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */
|
| 16017 |
|
|
byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */
|
| 16018 |
|
|
byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */
|
| 16019 |
|
|
byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */
|
| 16020 |
|
|
byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */
|
| 16021 |
|
|
byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */
|
| 16022 |
|
|
byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */
|
| 16023 |
|
|
byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */
|
| 16024 |
|
|
} Bits;
|
| 16025 |
|
|
struct {
|
| 16026 |
|
|
byte grpPIEP :8;
|
| 16027 |
|
|
} MergedBits;
|
| 16028 |
|
|
} PIEPSTR;
|
| 16029 |
|
|
extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E);
|
| 16030 |
|
|
#define PIEP _PIEP.Byte
|
| 16031 |
|
|
#define PIEP_PIEP0 _PIEP.Bits.PIEP0
|
| 16032 |
|
|
#define PIEP_PIEP1 _PIEP.Bits.PIEP1
|
| 16033 |
|
|
#define PIEP_PIEP2 _PIEP.Bits.PIEP2
|
| 16034 |
|
|
#define PIEP_PIEP3 _PIEP.Bits.PIEP3
|
| 16035 |
|
|
#define PIEP_PIEP4 _PIEP.Bits.PIEP4
|
| 16036 |
|
|
#define PIEP_PIEP5 _PIEP.Bits.PIEP5
|
| 16037 |
|
|
#define PIEP_PIEP6 _PIEP.Bits.PIEP6
|
| 16038 |
|
|
#define PIEP_PIEP7 _PIEP.Bits.PIEP7
|
| 16039 |
|
|
#define PIEP_PIEP _PIEP.MergedBits.grpPIEP
|
| 16040 |
|
|
|
| 16041 |
|
|
|
| 16042 |
|
|
/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/
|
| 16043 |
|
|
typedef union {
|
| 16044 |
|
|
byte Byte;
|
| 16045 |
|
|
struct {
|
| 16046 |
|
|
byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */
|
| 16047 |
|
|
byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */
|
| 16048 |
|
|
byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */
|
| 16049 |
|
|
byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */
|
| 16050 |
|
|
byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */
|
| 16051 |
|
|
byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */
|
| 16052 |
|
|
byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */
|
| 16053 |
|
|
byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */
|
| 16054 |
|
|
} Bits;
|
| 16055 |
|
|
struct {
|
| 16056 |
|
|
byte grpPIFP :8;
|
| 16057 |
|
|
} MergedBits;
|
| 16058 |
|
|
} PIFPSTR;
|
| 16059 |
|
|
extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F);
|
| 16060 |
|
|
#define PIFP _PIFP.Byte
|
| 16061 |
|
|
#define PIFP_PIFP0 _PIFP.Bits.PIFP0
|
| 16062 |
|
|
#define PIFP_PIFP1 _PIFP.Bits.PIFP1
|
| 16063 |
|
|
#define PIFP_PIFP2 _PIFP.Bits.PIFP2
|
| 16064 |
|
|
#define PIFP_PIFP3 _PIFP.Bits.PIFP3
|
| 16065 |
|
|
#define PIFP_PIFP4 _PIFP.Bits.PIFP4
|
| 16066 |
|
|
#define PIFP_PIFP5 _PIFP.Bits.PIFP5
|
| 16067 |
|
|
#define PIFP_PIFP6 _PIFP.Bits.PIFP6
|
| 16068 |
|
|
#define PIFP_PIFP7 _PIFP.Bits.PIFP7
|
| 16069 |
|
|
#define PIFP_PIFP _PIFP.MergedBits.grpPIFP
|
| 16070 |
|
|
|
| 16071 |
|
|
|
| 16072 |
|
|
/*** PTH - Port H I/O Register; 0x00000260 ***/
|
| 16073 |
|
|
typedef union {
|
| 16074 |
|
|
byte Byte;
|
| 16075 |
|
|
struct {
|
| 16076 |
|
|
byte PTH0 :1; /* Port H Bit 0 */
|
| 16077 |
|
|
byte PTH1 :1; /* Port H Bit 1 */
|
| 16078 |
|
|
byte PTH2 :1; /* Port H Bit 2 */
|
| 16079 |
|
|
byte PTH3 :1; /* Port H Bit 3 */
|
| 16080 |
|
|
byte PTH4 :1; /* Port H Bit 4 */
|
| 16081 |
|
|
byte PTH5 :1; /* Port H Bit 5 */
|
| 16082 |
|
|
byte PTH6 :1; /* Port H Bit 6 */
|
| 16083 |
|
|
byte PTH7 :1; /* Port H Bit 7 */
|
| 16084 |
|
|
} Bits;
|
| 16085 |
|
|
struct {
|
| 16086 |
|
|
byte grpPTH :8;
|
| 16087 |
|
|
} MergedBits;
|
| 16088 |
|
|
} PTHSTR;
|
| 16089 |
|
|
extern volatile PTHSTR _PTH @(REG_BASE + 0x00000260);
|
| 16090 |
|
|
#define PTH _PTH.Byte
|
| 16091 |
|
|
#define PTH_PTH0 _PTH.Bits.PTH0
|
| 16092 |
|
|
#define PTH_PTH1 _PTH.Bits.PTH1
|
| 16093 |
|
|
#define PTH_PTH2 _PTH.Bits.PTH2
|
| 16094 |
|
|
#define PTH_PTH3 _PTH.Bits.PTH3
|
| 16095 |
|
|
#define PTH_PTH4 _PTH.Bits.PTH4
|
| 16096 |
|
|
#define PTH_PTH5 _PTH.Bits.PTH5
|
| 16097 |
|
|
#define PTH_PTH6 _PTH.Bits.PTH6
|
| 16098 |
|
|
#define PTH_PTH7 _PTH.Bits.PTH7
|
| 16099 |
|
|
#define PTH_PTH _PTH.MergedBits.grpPTH
|
| 16100 |
|
|
|
| 16101 |
|
|
|
| 16102 |
|
|
/*** PTIH - Port H Input Register; 0x00000261 ***/
|
| 16103 |
|
|
typedef union {
|
| 16104 |
|
|
byte Byte;
|
| 16105 |
|
|
struct {
|
| 16106 |
|
|
byte PTIH0 :1; /* Port H Bit 0 */
|
| 16107 |
|
|
byte PTIH1 :1; /* Port H Bit 1 */
|
| 16108 |
|
|
byte PTIH2 :1; /* Port H Bit 2 */
|
| 16109 |
|
|
byte PTIH3 :1; /* Port H Bit 3 */
|
| 16110 |
|
|
byte PTIH4 :1; /* Port H Bit 4 */
|
| 16111 |
|
|
byte PTIH5 :1; /* Port H Bit 5 */
|
| 16112 |
|
|
byte PTIH6 :1; /* Port H Bit 6 */
|
| 16113 |
|
|
byte PTIH7 :1; /* Port H Bit 7 */
|
| 16114 |
|
|
} Bits;
|
| 16115 |
|
|
struct {
|
| 16116 |
|
|
byte grpPTIH :8;
|
| 16117 |
|
|
} MergedBits;
|
| 16118 |
|
|
} PTIHSTR;
|
| 16119 |
|
|
extern volatile PTIHSTR _PTIH @(REG_BASE + 0x00000261);
|
| 16120 |
|
|
#define PTIH _PTIH.Byte
|
| 16121 |
|
|
#define PTIH_PTIH0 _PTIH.Bits.PTIH0
|
| 16122 |
|
|
#define PTIH_PTIH1 _PTIH.Bits.PTIH1
|
| 16123 |
|
|
#define PTIH_PTIH2 _PTIH.Bits.PTIH2
|
| 16124 |
|
|
#define PTIH_PTIH3 _PTIH.Bits.PTIH3
|
| 16125 |
|
|
#define PTIH_PTIH4 _PTIH.Bits.PTIH4
|
| 16126 |
|
|
#define PTIH_PTIH5 _PTIH.Bits.PTIH5
|
| 16127 |
|
|
#define PTIH_PTIH6 _PTIH.Bits.PTIH6
|
| 16128 |
|
|
#define PTIH_PTIH7 _PTIH.Bits.PTIH7
|
| 16129 |
|
|
#define PTIH_PTIH _PTIH.MergedBits.grpPTIH
|
| 16130 |
|
|
|
| 16131 |
|
|
|
| 16132 |
|
|
/*** DDRH - Port H Data Direction Register; 0x00000262 ***/
|
| 16133 |
|
|
typedef union {
|
| 16134 |
|
|
byte Byte;
|
| 16135 |
|
|
struct {
|
| 16136 |
|
|
byte DDRH0 :1; /* Data Direction Port H Bit 0 */
|
| 16137 |
|
|
byte DDRH1 :1; /* Data Direction Port H Bit 1 */
|
| 16138 |
|
|
byte DDRH2 :1; /* Data Direction Port H Bit 2 */
|
| 16139 |
|
|
byte DDRH3 :1; /* Data Direction Port H Bit 3 */
|
| 16140 |
|
|
byte DDRH4 :1; /* Data Direction Port H Bit 4 */
|
| 16141 |
|
|
byte DDRH5 :1; /* Data Direction Port H Bit 5 */
|
| 16142 |
|
|
byte DDRH6 :1; /* Data Direction Port H Bit 6 */
|
| 16143 |
|
|
byte DDRH7 :1; /* Data Direction Port H Bit 7 */
|
| 16144 |
|
|
} Bits;
|
| 16145 |
|
|
struct {
|
| 16146 |
|
|
byte grpDDRH :8;
|
| 16147 |
|
|
} MergedBits;
|
| 16148 |
|
|
} DDRHSTR;
|
| 16149 |
|
|
extern volatile DDRHSTR _DDRH @(REG_BASE + 0x00000262);
|
| 16150 |
|
|
#define DDRH _DDRH.Byte
|
| 16151 |
|
|
#define DDRH_DDRH0 _DDRH.Bits.DDRH0
|
| 16152 |
|
|
#define DDRH_DDRH1 _DDRH.Bits.DDRH1
|
| 16153 |
|
|
#define DDRH_DDRH2 _DDRH.Bits.DDRH2
|
| 16154 |
|
|
#define DDRH_DDRH3 _DDRH.Bits.DDRH3
|
| 16155 |
|
|
#define DDRH_DDRH4 _DDRH.Bits.DDRH4
|
| 16156 |
|
|
#define DDRH_DDRH5 _DDRH.Bits.DDRH5
|
| 16157 |
|
|
#define DDRH_DDRH6 _DDRH.Bits.DDRH6
|
| 16158 |
|
|
#define DDRH_DDRH7 _DDRH.Bits.DDRH7
|
| 16159 |
|
|
#define DDRH_DDRH _DDRH.MergedBits.grpDDRH
|
| 16160 |
|
|
|
| 16161 |
|
|
|
| 16162 |
|
|
/*** RDRH - Port H Reduced Drive Register; 0x00000263 ***/
|
| 16163 |
|
|
typedef union {
|
| 16164 |
|
|
byte Byte;
|
| 16165 |
|
|
struct {
|
| 16166 |
|
|
byte RDRH0 :1; /* Reduced Drive Port H Bit 0 */
|
| 16167 |
|
|
byte RDRH1 :1; /* Reduced Drive Port H Bit 1 */
|
| 16168 |
|
|
byte RDRH2 :1; /* Reduced Drive Port H Bit 2 */
|
| 16169 |
|
|
byte RDRH3 :1; /* Reduced Drive Port H Bit 3 */
|
| 16170 |
|
|
byte RDRH4 :1; /* Reduced Drive Port H Bit 4 */
|
| 16171 |
|
|
byte RDRH5 :1; /* Reduced Drive Port H Bit 5 */
|
| 16172 |
|
|
byte RDRH6 :1; /* Reduced Drive Port H Bit 6 */
|
| 16173 |
|
|
byte RDRH7 :1; /* Reduced Drive Port H Bit 7 */
|
| 16174 |
|
|
} Bits;
|
| 16175 |
|
|
struct {
|
| 16176 |
|
|
byte grpRDRH :8;
|
| 16177 |
|
|
} MergedBits;
|
| 16178 |
|
|
} RDRHSTR;
|
| 16179 |
|
|
extern volatile RDRHSTR _RDRH @(REG_BASE + 0x00000263);
|
| 16180 |
|
|
#define RDRH _RDRH.Byte
|
| 16181 |
|
|
#define RDRH_RDRH0 _RDRH.Bits.RDRH0
|
| 16182 |
|
|
#define RDRH_RDRH1 _RDRH.Bits.RDRH1
|
| 16183 |
|
|
#define RDRH_RDRH2 _RDRH.Bits.RDRH2
|
| 16184 |
|
|
#define RDRH_RDRH3 _RDRH.Bits.RDRH3
|
| 16185 |
|
|
#define RDRH_RDRH4 _RDRH.Bits.RDRH4
|
| 16186 |
|
|
#define RDRH_RDRH5 _RDRH.Bits.RDRH5
|
| 16187 |
|
|
#define RDRH_RDRH6 _RDRH.Bits.RDRH6
|
| 16188 |
|
|
#define RDRH_RDRH7 _RDRH.Bits.RDRH7
|
| 16189 |
|
|
#define RDRH_RDRH _RDRH.MergedBits.grpRDRH
|
| 16190 |
|
|
|
| 16191 |
|
|
|
| 16192 |
|
|
/*** PERH - Port H Pull Device Enable Register; 0x00000264 ***/
|
| 16193 |
|
|
typedef union {
|
| 16194 |
|
|
byte Byte;
|
| 16195 |
|
|
struct {
|
| 16196 |
|
|
byte PERH0 :1; /* Pull Device Enable Port H Bit 0 */
|
| 16197 |
|
|
byte PERH1 :1; /* Pull Device Enable Port H Bit 1 */
|
| 16198 |
|
|
byte PERH2 :1; /* Pull Device Enable Port H Bit 2 */
|
| 16199 |
|
|
byte PERH3 :1; /* Pull Device Enable Port H Bit 3 */
|
| 16200 |
|
|
byte PERH4 :1; /* Pull Device Enable Port H Bit 4 */
|
| 16201 |
|
|
byte PERH5 :1; /* Pull Device Enable Port H Bit 5 */
|
| 16202 |
|
|
byte PERH6 :1; /* Pull Device Enable Port H Bit 6 */
|
| 16203 |
|
|
byte PERH7 :1; /* Pull Device Enable Port H Bit 7 */
|
| 16204 |
|
|
} Bits;
|
| 16205 |
|
|
struct {
|
| 16206 |
|
|
byte grpPERH :8;
|
| 16207 |
|
|
} MergedBits;
|
| 16208 |
|
|
} PERHSTR;
|
| 16209 |
|
|
extern volatile PERHSTR _PERH @(REG_BASE + 0x00000264);
|
| 16210 |
|
|
#define PERH _PERH.Byte
|
| 16211 |
|
|
#define PERH_PERH0 _PERH.Bits.PERH0
|
| 16212 |
|
|
#define PERH_PERH1 _PERH.Bits.PERH1
|
| 16213 |
|
|
#define PERH_PERH2 _PERH.Bits.PERH2
|
| 16214 |
|
|
#define PERH_PERH3 _PERH.Bits.PERH3
|
| 16215 |
|
|
#define PERH_PERH4 _PERH.Bits.PERH4
|
| 16216 |
|
|
#define PERH_PERH5 _PERH.Bits.PERH5
|
| 16217 |
|
|
#define PERH_PERH6 _PERH.Bits.PERH6
|
| 16218 |
|
|
#define PERH_PERH7 _PERH.Bits.PERH7
|
| 16219 |
|
|
#define PERH_PERH _PERH.MergedBits.grpPERH
|
| 16220 |
|
|
|
| 16221 |
|
|
|
| 16222 |
|
|
/*** PPSH - Port H Polarity Select Register; 0x00000265 ***/
|
| 16223 |
|
|
typedef union {
|
| 16224 |
|
|
byte Byte;
|
| 16225 |
|
|
struct {
|
| 16226 |
|
|
byte PPSH0 :1; /* Pull Select Port H Bit 0 */
|
| 16227 |
|
|
byte PPSH1 :1; /* Pull Select Port H Bit 1 */
|
| 16228 |
|
|
byte PPSH2 :1; /* Pull Select Port H Bit 2 */
|
| 16229 |
|
|
byte PPSH3 :1; /* Pull Select Port H Bit 3 */
|
| 16230 |
|
|
byte PPSH4 :1; /* Pull Select Port H Bit 4 */
|
| 16231 |
|
|
byte PPSH5 :1; /* Pull Select Port H Bit 5 */
|
| 16232 |
|
|
byte PPSH6 :1; /* Pull Select Port H Bit 6 */
|
| 16233 |
|
|
byte PPSH7 :1; /* Pull Select Port H Bit 7 */
|
| 16234 |
|
|
} Bits;
|
| 16235 |
|
|
struct {
|
| 16236 |
|
|
byte grpPPSH :8;
|
| 16237 |
|
|
} MergedBits;
|
| 16238 |
|
|
} PPSHSTR;
|
| 16239 |
|
|
extern volatile PPSHSTR _PPSH @(REG_BASE + 0x00000265);
|
| 16240 |
|
|
#define PPSH _PPSH.Byte
|
| 16241 |
|
|
#define PPSH_PPSH0 _PPSH.Bits.PPSH0
|
| 16242 |
|
|
#define PPSH_PPSH1 _PPSH.Bits.PPSH1
|
| 16243 |
|
|
#define PPSH_PPSH2 _PPSH.Bits.PPSH2
|
| 16244 |
|
|
#define PPSH_PPSH3 _PPSH.Bits.PPSH3
|
| 16245 |
|
|
#define PPSH_PPSH4 _PPSH.Bits.PPSH4
|
| 16246 |
|
|
#define PPSH_PPSH5 _PPSH.Bits.PPSH5
|
| 16247 |
|
|
#define PPSH_PPSH6 _PPSH.Bits.PPSH6
|
| 16248 |
|
|
#define PPSH_PPSH7 _PPSH.Bits.PPSH7
|
| 16249 |
|
|
#define PPSH_PPSH _PPSH.MergedBits.grpPPSH
|
| 16250 |
|
|
|
| 16251 |
|
|
|
| 16252 |
|
|
/*** PIEH - Port H Interrupt Enable Register; 0x00000266 ***/
|
| 16253 |
|
|
typedef union {
|
| 16254 |
|
|
byte Byte;
|
| 16255 |
|
|
struct {
|
| 16256 |
|
|
byte PIEH0 :1; /* Interrupt Enable Port H Bit 0 */
|
| 16257 |
|
|
byte PIEH1 :1; /* Interrupt Enable Port H Bit 1 */
|
| 16258 |
|
|
byte PIEH2 :1; /* Interrupt Enable Port H Bit 2 */
|
| 16259 |
|
|
byte PIEH3 :1; /* Interrupt Enable Port H Bit 3 */
|
| 16260 |
|
|
byte PIEH4 :1; /* Interrupt Enable Port H Bit 4 */
|
| 16261 |
|
|
byte PIEH5 :1; /* Interrupt Enable Port H Bit 5 */
|
| 16262 |
|
|
byte PIEH6 :1; /* Interrupt Enable Port H Bit 6 */
|
| 16263 |
|
|
byte PIEH7 :1; /* Interrupt Enable Port H Bit 7 */
|
| 16264 |
|
|
} Bits;
|
| 16265 |
|
|
struct {
|
| 16266 |
|
|
byte grpPIEH :8;
|
| 16267 |
|
|
} MergedBits;
|
| 16268 |
|
|
} PIEHSTR;
|
| 16269 |
|
|
extern volatile PIEHSTR _PIEH @(REG_BASE + 0x00000266);
|
| 16270 |
|
|
#define PIEH _PIEH.Byte
|
| 16271 |
|
|
#define PIEH_PIEH0 _PIEH.Bits.PIEH0
|
| 16272 |
|
|
#define PIEH_PIEH1 _PIEH.Bits.PIEH1
|
| 16273 |
|
|
#define PIEH_PIEH2 _PIEH.Bits.PIEH2
|
| 16274 |
|
|
#define PIEH_PIEH3 _PIEH.Bits.PIEH3
|
| 16275 |
|
|
#define PIEH_PIEH4 _PIEH.Bits.PIEH4
|
| 16276 |
|
|
#define PIEH_PIEH5 _PIEH.Bits.PIEH5
|
| 16277 |
|
|
#define PIEH_PIEH6 _PIEH.Bits.PIEH6
|
| 16278 |
|
|
#define PIEH_PIEH7 _PIEH.Bits.PIEH7
|
| 16279 |
|
|
#define PIEH_PIEH _PIEH.MergedBits.grpPIEH
|
| 16280 |
|
|
|
| 16281 |
|
|
|
| 16282 |
|
|
/*** PIFH - Port H Interrupt Flag Register; 0x00000267 ***/
|
| 16283 |
|
|
typedef union {
|
| 16284 |
|
|
byte Byte;
|
| 16285 |
|
|
struct {
|
| 16286 |
|
|
byte PIFH0 :1; /* Interrupt Flags Port H Bit 0 */
|
| 16287 |
|
|
byte PIFH1 :1; /* Interrupt Flags Port H Bit 1 */
|
| 16288 |
|
|
byte PIFH2 :1; /* Interrupt Flags Port H Bit 2 */
|
| 16289 |
|
|
byte PIFH3 :1; /* Interrupt Flags Port H Bit 3 */
|
| 16290 |
|
|
byte PIFH4 :1; /* Interrupt Flags Port H Bit 4 */
|
| 16291 |
|
|
byte PIFH5 :1; /* Interrupt Flags Port H Bit 5 */
|
| 16292 |
|
|
byte PIFH6 :1; /* Interrupt Flags Port H Bit 6 */
|
| 16293 |
|
|
byte PIFH7 :1; /* Interrupt Flags Port H Bit 7 */
|
| 16294 |
|
|
} Bits;
|
| 16295 |
|
|
struct {
|
| 16296 |
|
|
byte grpPIFH :8;
|
| 16297 |
|
|
} MergedBits;
|
| 16298 |
|
|
} PIFHSTR;
|
| 16299 |
|
|
extern volatile PIFHSTR _PIFH @(REG_BASE + 0x00000267);
|
| 16300 |
|
|
#define PIFH _PIFH.Byte
|
| 16301 |
|
|
#define PIFH_PIFH0 _PIFH.Bits.PIFH0
|
| 16302 |
|
|
#define PIFH_PIFH1 _PIFH.Bits.PIFH1
|
| 16303 |
|
|
#define PIFH_PIFH2 _PIFH.Bits.PIFH2
|
| 16304 |
|
|
#define PIFH_PIFH3 _PIFH.Bits.PIFH3
|
| 16305 |
|
|
#define PIFH_PIFH4 _PIFH.Bits.PIFH4
|
| 16306 |
|
|
#define PIFH_PIFH5 _PIFH.Bits.PIFH5
|
| 16307 |
|
|
#define PIFH_PIFH6 _PIFH.Bits.PIFH6
|
| 16308 |
|
|
#define PIFH_PIFH7 _PIFH.Bits.PIFH7
|
| 16309 |
|
|
#define PIFH_PIFH _PIFH.MergedBits.grpPIFH
|
| 16310 |
|
|
|
| 16311 |
|
|
|
| 16312 |
|
|
/*** PTJ - Port J I/O Register; 0x00000268 ***/
|
| 16313 |
|
|
typedef union {
|
| 16314 |
|
|
byte Byte;
|
| 16315 |
|
|
struct {
|
| 16316 |
|
|
byte PTJ0 :1; /* Port J Bit 0 */
|
| 16317 |
|
|
byte PTJ1 :1; /* Port J Bit 1 */
|
| 16318 |
|
|
byte :1;
|
| 16319 |
|
|
byte :1;
|
| 16320 |
|
|
byte :1;
|
| 16321 |
|
|
byte :1;
|
| 16322 |
|
|
byte PTJ6 :1; /* Port J Bit 6 */
|
| 16323 |
|
|
byte PTJ7 :1; /* Port J Bit 7 */
|
| 16324 |
|
|
} Bits;
|
| 16325 |
|
|
struct {
|
| 16326 |
|
|
byte grpPTJ :2;
|
| 16327 |
|
|
byte :1;
|
| 16328 |
|
|
byte :1;
|
| 16329 |
|
|
byte :1;
|
| 16330 |
|
|
byte :1;
|
| 16331 |
|
|
byte grpPTJ_6 :2;
|
| 16332 |
|
|
} MergedBits;
|
| 16333 |
|
|
} PTJSTR;
|
| 16334 |
|
|
extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268);
|
| 16335 |
|
|
#define PTJ _PTJ.Byte
|
| 16336 |
|
|
#define PTJ_PTJ0 _PTJ.Bits.PTJ0
|
| 16337 |
|
|
#define PTJ_PTJ1 _PTJ.Bits.PTJ1
|
| 16338 |
|
|
#define PTJ_PTJ6 _PTJ.Bits.PTJ6
|
| 16339 |
|
|
#define PTJ_PTJ7 _PTJ.Bits.PTJ7
|
| 16340 |
|
|
#define PTJ_PTJ _PTJ.MergedBits.grpPTJ
|
| 16341 |
|
|
#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6
|
| 16342 |
|
|
|
| 16343 |
|
|
|
| 16344 |
|
|
/*** PTIJ - Port J Input Register; 0x00000269 ***/
|
| 16345 |
|
|
typedef union {
|
| 16346 |
|
|
byte Byte;
|
| 16347 |
|
|
struct {
|
| 16348 |
|
|
byte PTIJ0 :1; /* Port J Bit 0 */
|
| 16349 |
|
|
byte PTIJ1 :1; /* Port J Bit 1 */
|
| 16350 |
|
|
byte :1;
|
| 16351 |
|
|
byte :1;
|
| 16352 |
|
|
byte :1;
|
| 16353 |
|
|
byte :1;
|
| 16354 |
|
|
byte PTIJ6 :1; /* Port J Bit 6 */
|
| 16355 |
|
|
byte PTIJ7 :1; /* Port J Bit 7 */
|
| 16356 |
|
|
} Bits;
|
| 16357 |
|
|
struct {
|
| 16358 |
|
|
byte grpPTIJ :2;
|
| 16359 |
|
|
byte :1;
|
| 16360 |
|
|
byte :1;
|
| 16361 |
|
|
byte :1;
|
| 16362 |
|
|
byte :1;
|
| 16363 |
|
|
byte grpPTIJ_6 :2;
|
| 16364 |
|
|
} MergedBits;
|
| 16365 |
|
|
} PTIJSTR;
|
| 16366 |
|
|
extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269);
|
| 16367 |
|
|
#define PTIJ _PTIJ.Byte
|
| 16368 |
|
|
#define PTIJ_PTIJ0 _PTIJ.Bits.PTIJ0
|
| 16369 |
|
|
#define PTIJ_PTIJ1 _PTIJ.Bits.PTIJ1
|
| 16370 |
|
|
#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6
|
| 16371 |
|
|
#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7
|
| 16372 |
|
|
#define PTIJ_PTIJ _PTIJ.MergedBits.grpPTIJ
|
| 16373 |
|
|
#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6
|
| 16374 |
|
|
|
| 16375 |
|
|
|
| 16376 |
|
|
/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/
|
| 16377 |
|
|
typedef union {
|
| 16378 |
|
|
byte Byte;
|
| 16379 |
|
|
struct {
|
| 16380 |
|
|
byte DDRJ0 :1; /* Data Direction Port J Bit 0 */
|
| 16381 |
|
|
byte DDRJ1 :1; /* Data Direction Port J Bit 1 */
|
| 16382 |
|
|
byte :1;
|
| 16383 |
|
|
byte :1;
|
| 16384 |
|
|
byte :1;
|
| 16385 |
|
|
byte :1;
|
| 16386 |
|
|
byte DDRJ6 :1; /* Data Direction Port J Bit 6 */
|
| 16387 |
|
|
byte DDRJ7 :1; /* Data Direction Port J Bit 7 */
|
| 16388 |
|
|
} Bits;
|
| 16389 |
|
|
struct {
|
| 16390 |
|
|
byte grpDDRJ :2;
|
| 16391 |
|
|
byte :1;
|
| 16392 |
|
|
byte :1;
|
| 16393 |
|
|
byte :1;
|
| 16394 |
|
|
byte :1;
|
| 16395 |
|
|
byte grpDDRJ_6 :2;
|
| 16396 |
|
|
} MergedBits;
|
| 16397 |
|
|
} DDRJSTR;
|
| 16398 |
|
|
extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A);
|
| 16399 |
|
|
#define DDRJ _DDRJ.Byte
|
| 16400 |
|
|
#define DDRJ_DDRJ0 _DDRJ.Bits.DDRJ0
|
| 16401 |
|
|
#define DDRJ_DDRJ1 _DDRJ.Bits.DDRJ1
|
| 16402 |
|
|
#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6
|
| 16403 |
|
|
#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7
|
| 16404 |
|
|
#define DDRJ_DDRJ _DDRJ.MergedBits.grpDDRJ
|
| 16405 |
|
|
#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6
|
| 16406 |
|
|
|
| 16407 |
|
|
|
| 16408 |
|
|
/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/
|
| 16409 |
|
|
typedef union {
|
| 16410 |
|
|
byte Byte;
|
| 16411 |
|
|
struct {
|
| 16412 |
|
|
byte RDRJ0 :1; /* Reduced Drive Port J Bit 0 */
|
| 16413 |
|
|
byte RDRJ1 :1; /* Reduced Drive Port J Bit 1 */
|
| 16414 |
|
|
byte :1;
|
| 16415 |
|
|
byte :1;
|
| 16416 |
|
|
byte :1;
|
| 16417 |
|
|
byte :1;
|
| 16418 |
|
|
byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */
|
| 16419 |
|
|
byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */
|
| 16420 |
|
|
} Bits;
|
| 16421 |
|
|
struct {
|
| 16422 |
|
|
byte grpRDRJ :2;
|
| 16423 |
|
|
byte :1;
|
| 16424 |
|
|
byte :1;
|
| 16425 |
|
|
byte :1;
|
| 16426 |
|
|
byte :1;
|
| 16427 |
|
|
byte grpRDRJ_6 :2;
|
| 16428 |
|
|
} MergedBits;
|
| 16429 |
|
|
} RDRJSTR;
|
| 16430 |
|
|
extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B);
|
| 16431 |
|
|
#define RDRJ _RDRJ.Byte
|
| 16432 |
|
|
#define RDRJ_RDRJ0 _RDRJ.Bits.RDRJ0
|
| 16433 |
|
|
#define RDRJ_RDRJ1 _RDRJ.Bits.RDRJ1
|
| 16434 |
|
|
#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6
|
| 16435 |
|
|
#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7
|
| 16436 |
|
|
#define RDRJ_RDRJ _RDRJ.MergedBits.grpRDRJ
|
| 16437 |
|
|
#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6
|
| 16438 |
|
|
|
| 16439 |
|
|
|
| 16440 |
|
|
/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/
|
| 16441 |
|
|
typedef union {
|
| 16442 |
|
|
byte Byte;
|
| 16443 |
|
|
struct {
|
| 16444 |
|
|
byte PERJ0 :1; /* Pull Device Enable Port J Bit 0 */
|
| 16445 |
|
|
byte PERJ1 :1; /* Pull Device Enable Port J Bit 1 */
|
| 16446 |
|
|
byte :1;
|
| 16447 |
|
|
byte :1;
|
| 16448 |
|
|
byte :1;
|
| 16449 |
|
|
byte :1;
|
| 16450 |
|
|
byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */
|
| 16451 |
|
|
byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */
|
| 16452 |
|
|
} Bits;
|
| 16453 |
|
|
struct {
|
| 16454 |
|
|
byte grpPERJ :2;
|
| 16455 |
|
|
byte :1;
|
| 16456 |
|
|
byte :1;
|
| 16457 |
|
|
byte :1;
|
| 16458 |
|
|
byte :1;
|
| 16459 |
|
|
byte grpPERJ_6 :2;
|
| 16460 |
|
|
} MergedBits;
|
| 16461 |
|
|
} PERJSTR;
|
| 16462 |
|
|
extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C);
|
| 16463 |
|
|
#define PERJ _PERJ.Byte
|
| 16464 |
|
|
#define PERJ_PERJ0 _PERJ.Bits.PERJ0
|
| 16465 |
|
|
#define PERJ_PERJ1 _PERJ.Bits.PERJ1
|
| 16466 |
|
|
#define PERJ_PERJ6 _PERJ.Bits.PERJ6
|
| 16467 |
|
|
#define PERJ_PERJ7 _PERJ.Bits.PERJ7
|
| 16468 |
|
|
#define PERJ_PERJ _PERJ.MergedBits.grpPERJ
|
| 16469 |
|
|
#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6
|
| 16470 |
|
|
|
| 16471 |
|
|
|
| 16472 |
|
|
/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/
|
| 16473 |
|
|
typedef union {
|
| 16474 |
|
|
byte Byte;
|
| 16475 |
|
|
struct {
|
| 16476 |
|
|
byte PPSJ0 :1; /* Pull Select Port J Bit 0 */
|
| 16477 |
|
|
byte PPSJ1 :1; /* Pull Select Port J Bit 1 */
|
| 16478 |
|
|
byte :1;
|
| 16479 |
|
|
byte :1;
|
| 16480 |
|
|
byte :1;
|
| 16481 |
|
|
byte :1;
|
| 16482 |
|
|
byte PPSJ6 :1; /* Pull Select Port J Bit 6 */
|
| 16483 |
|
|
byte PPSJ7 :1; /* Pull Select Port J Bit 7 */
|
| 16484 |
|
|
} Bits;
|
| 16485 |
|
|
struct {
|
| 16486 |
|
|
byte grpPPSJ :2;
|
| 16487 |
|
|
byte :1;
|
| 16488 |
|
|
byte :1;
|
| 16489 |
|
|
byte :1;
|
| 16490 |
|
|
byte :1;
|
| 16491 |
|
|
byte grpPPSJ_6 :2;
|
| 16492 |
|
|
} MergedBits;
|
| 16493 |
|
|
} PPSJSTR;
|
| 16494 |
|
|
extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D);
|
| 16495 |
|
|
#define PPSJ _PPSJ.Byte
|
| 16496 |
|
|
#define PPSJ_PPSJ0 _PPSJ.Bits.PPSJ0
|
| 16497 |
|
|
#define PPSJ_PPSJ1 _PPSJ.Bits.PPSJ1
|
| 16498 |
|
|
#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6
|
| 16499 |
|
|
#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7
|
| 16500 |
|
|
#define PPSJ_PPSJ _PPSJ.MergedBits.grpPPSJ
|
| 16501 |
|
|
#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6
|
| 16502 |
|
|
|
| 16503 |
|
|
|
| 16504 |
|
|
/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/
|
| 16505 |
|
|
typedef union {
|
| 16506 |
|
|
byte Byte;
|
| 16507 |
|
|
struct {
|
| 16508 |
|
|
byte PIEJ0 :1; /* Interrupt Enable Port J Bit 0 */
|
| 16509 |
|
|
byte PIEJ1 :1; /* Interrupt Enable Port J Bit 1 */
|
| 16510 |
|
|
byte :1;
|
| 16511 |
|
|
byte :1;
|
| 16512 |
|
|
byte :1;
|
| 16513 |
|
|
byte :1;
|
| 16514 |
|
|
byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */
|
| 16515 |
|
|
byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */
|
| 16516 |
|
|
} Bits;
|
| 16517 |
|
|
struct {
|
| 16518 |
|
|
byte grpPIEJ :2;
|
| 16519 |
|
|
byte :1;
|
| 16520 |
|
|
byte :1;
|
| 16521 |
|
|
byte :1;
|
| 16522 |
|
|
byte :1;
|
| 16523 |
|
|
byte grpPIEJ_6 :2;
|
| 16524 |
|
|
} MergedBits;
|
| 16525 |
|
|
} PIEJSTR;
|
| 16526 |
|
|
extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E);
|
| 16527 |
|
|
#define PIEJ _PIEJ.Byte
|
| 16528 |
|
|
#define PIEJ_PIEJ0 _PIEJ.Bits.PIEJ0
|
| 16529 |
|
|
#define PIEJ_PIEJ1 _PIEJ.Bits.PIEJ1
|
| 16530 |
|
|
#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6
|
| 16531 |
|
|
#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7
|
| 16532 |
|
|
#define PIEJ_PIEJ _PIEJ.MergedBits.grpPIEJ
|
| 16533 |
|
|
#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6
|
| 16534 |
|
|
|
| 16535 |
|
|
|
| 16536 |
|
|
/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/
|
| 16537 |
|
|
typedef union {
|
| 16538 |
|
|
byte Byte;
|
| 16539 |
|
|
struct {
|
| 16540 |
|
|
byte PIFJ0 :1; /* Interrupt Flags Port J Bit 0 */
|
| 16541 |
|
|
byte PIFJ1 :1; /* Interrupt Flags Port J Bit 1 */
|
| 16542 |
|
|
byte :1;
|
| 16543 |
|
|
byte :1;
|
| 16544 |
|
|
byte :1;
|
| 16545 |
|
|
byte :1;
|
| 16546 |
|
|
byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */
|
| 16547 |
|
|
byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */
|
| 16548 |
|
|
} Bits;
|
| 16549 |
|
|
struct {
|
| 16550 |
|
|
byte grpPIFJ :2;
|
| 16551 |
|
|
byte :1;
|
| 16552 |
|
|
byte :1;
|
| 16553 |
|
|
byte :1;
|
| 16554 |
|
|
byte :1;
|
| 16555 |
|
|
byte grpPIFJ_6 :2;
|
| 16556 |
|
|
} MergedBits;
|
| 16557 |
|
|
} PIFJSTR;
|
| 16558 |
|
|
extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F);
|
| 16559 |
|
|
#define PIFJ _PIFJ.Byte
|
| 16560 |
|
|
#define PIFJ_PIFJ0 _PIFJ.Bits.PIFJ0
|
| 16561 |
|
|
#define PIFJ_PIFJ1 _PIFJ.Bits.PIFJ1
|
| 16562 |
|
|
#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6
|
| 16563 |
|
|
#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7
|
| 16564 |
|
|
#define PIFJ_PIFJ _PIFJ.MergedBits.grpPIFJ
|
| 16565 |
|
|
#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6
|
| 16566 |
|
|
|
| 16567 |
|
|
|
| 16568 |
|
|
/*** CAN4CTL0 - MSCAN4 Control 0 Register; 0x00000280 ***/
|
| 16569 |
|
|
typedef union {
|
| 16570 |
|
|
byte Byte;
|
| 16571 |
|
|
struct {
|
| 16572 |
|
|
byte INITRQ :1; /* Initialization Mode Request */
|
| 16573 |
|
|
byte SLPRQ :1; /* Sleep Mode Request */
|
| 16574 |
|
|
byte WUPE :1; /* Wake-Up Enable */
|
| 16575 |
|
|
byte TIME :1; /* Timer Enable */
|
| 16576 |
|
|
byte SYNCH :1; /* Synchronized Status */
|
| 16577 |
|
|
byte CSWAI :1; /* CAN Stops in Wait Mode */
|
| 16578 |
|
|
byte RXACT :1; /* Receiver Active Status */
|
| 16579 |
|
|
byte RXFRM :1; /* Received Frame Flag */
|
| 16580 |
|
|
} Bits;
|
| 16581 |
|
|
} CAN4CTL0STR;
|
| 16582 |
|
|
extern volatile CAN4CTL0STR _CAN4CTL0 @(REG_BASE + 0x00000280);
|
| 16583 |
|
|
#define CAN4CTL0 _CAN4CTL0.Byte
|
| 16584 |
|
|
#define CAN4CTL0_INITRQ _CAN4CTL0.Bits.INITRQ
|
| 16585 |
|
|
#define CAN4CTL0_SLPRQ _CAN4CTL0.Bits.SLPRQ
|
| 16586 |
|
|
#define CAN4CTL0_WUPE _CAN4CTL0.Bits.WUPE
|
| 16587 |
|
|
#define CAN4CTL0_TIME _CAN4CTL0.Bits.TIME
|
| 16588 |
|
|
#define CAN4CTL0_SYNCH _CAN4CTL0.Bits.SYNCH
|
| 16589 |
|
|
#define CAN4CTL0_CSWAI _CAN4CTL0.Bits.CSWAI
|
| 16590 |
|
|
#define CAN4CTL0_RXACT _CAN4CTL0.Bits.RXACT
|
| 16591 |
|
|
#define CAN4CTL0_RXFRM _CAN4CTL0.Bits.RXFRM
|
| 16592 |
|
|
|
| 16593 |
|
|
|
| 16594 |
|
|
/*** CAN4CTL1 - MSCAN4 Control 1 Register; 0x00000281 ***/
|
| 16595 |
|
|
typedef union {
|
| 16596 |
|
|
byte Byte;
|
| 16597 |
|
|
struct {
|
| 16598 |
|
|
byte INITAK :1; /* Initialization Mode Acknowledge */
|
| 16599 |
|
|
byte SLPAK :1; /* Sleep Mode Acknowledge */
|
| 16600 |
|
|
byte WUPM :1; /* Wake-Up Mode */
|
| 16601 |
|
|
byte :1;
|
| 16602 |
|
|
byte LISTEN :1; /* Listen Only Mode */
|
| 16603 |
|
|
byte LOOPB :1; /* Loop Back Self Test Mode */
|
| 16604 |
|
|
byte CLKSRC :1; /* MSCAN4 Clock Source */
|
| 16605 |
|
|
byte CANE :1; /* MSCAN4 Enable */
|
| 16606 |
|
|
} Bits;
|
| 16607 |
|
|
} CAN4CTL1STR;
|
| 16608 |
|
|
extern volatile CAN4CTL1STR _CAN4CTL1 @(REG_BASE + 0x00000281);
|
| 16609 |
|
|
#define CAN4CTL1 _CAN4CTL1.Byte
|
| 16610 |
|
|
#define CAN4CTL1_INITAK _CAN4CTL1.Bits.INITAK
|
| 16611 |
|
|
#define CAN4CTL1_SLPAK _CAN4CTL1.Bits.SLPAK
|
| 16612 |
|
|
#define CAN4CTL1_WUPM _CAN4CTL1.Bits.WUPM
|
| 16613 |
|
|
#define CAN4CTL1_LISTEN _CAN4CTL1.Bits.LISTEN
|
| 16614 |
|
|
#define CAN4CTL1_LOOPB _CAN4CTL1.Bits.LOOPB
|
| 16615 |
|
|
#define CAN4CTL1_CLKSRC _CAN4CTL1.Bits.CLKSRC
|
| 16616 |
|
|
#define CAN4CTL1_CANE _CAN4CTL1.Bits.CANE
|
| 16617 |
|
|
|
| 16618 |
|
|
|
| 16619 |
|
|
/*** CAN4BTR0 - MSCAN4 Bus Timing Register 0; 0x00000282 ***/
|
| 16620 |
|
|
typedef union {
|
| 16621 |
|
|
byte Byte;
|
| 16622 |
|
|
struct {
|
| 16623 |
|
|
byte BRP0 :1; /* Baud Rate Prescaler 0 */
|
| 16624 |
|
|
byte BRP1 :1; /* Baud Rate Prescaler 1 */
|
| 16625 |
|
|
byte BRP2 :1; /* Baud Rate Prescaler 2 */
|
| 16626 |
|
|
byte BRP3 :1; /* Baud Rate Prescaler 3 */
|
| 16627 |
|
|
byte BRP4 :1; /* Baud Rate Prescaler 4 */
|
| 16628 |
|
|
byte BRP5 :1; /* Baud Rate Prescaler 5 */
|
| 16629 |
|
|
byte SJW0 :1; /* Synchronization Jump Width 0 */
|
| 16630 |
|
|
byte SJW1 :1; /* Synchronization Jump Width 1 */
|
| 16631 |
|
|
} Bits;
|
| 16632 |
|
|
struct {
|
| 16633 |
|
|
byte grpBRP :6;
|
| 16634 |
|
|
byte grpSJW :2;
|
| 16635 |
|
|
} MergedBits;
|
| 16636 |
|
|
} CAN4BTR0STR;
|
| 16637 |
|
|
extern volatile CAN4BTR0STR _CAN4BTR0 @(REG_BASE + 0x00000282);
|
| 16638 |
|
|
#define CAN4BTR0 _CAN4BTR0.Byte
|
| 16639 |
|
|
#define CAN4BTR0_BRP0 _CAN4BTR0.Bits.BRP0
|
| 16640 |
|
|
#define CAN4BTR0_BRP1 _CAN4BTR0.Bits.BRP1
|
| 16641 |
|
|
#define CAN4BTR0_BRP2 _CAN4BTR0.Bits.BRP2
|
| 16642 |
|
|
#define CAN4BTR0_BRP3 _CAN4BTR0.Bits.BRP3
|
| 16643 |
|
|
#define CAN4BTR0_BRP4 _CAN4BTR0.Bits.BRP4
|
| 16644 |
|
|
#define CAN4BTR0_BRP5 _CAN4BTR0.Bits.BRP5
|
| 16645 |
|
|
#define CAN4BTR0_SJW0 _CAN4BTR0.Bits.SJW0
|
| 16646 |
|
|
#define CAN4BTR0_SJW1 _CAN4BTR0.Bits.SJW1
|
| 16647 |
|
|
#define CAN4BTR0_BRP _CAN4BTR0.MergedBits.grpBRP
|
| 16648 |
|
|
#define CAN4BTR0_SJW _CAN4BTR0.MergedBits.grpSJW
|
| 16649 |
|
|
|
| 16650 |
|
|
|
| 16651 |
|
|
/*** CAN4BTR1 - MSCAN4 Bus Timing Register 1; 0x00000283 ***/
|
| 16652 |
|
|
typedef union {
|
| 16653 |
|
|
byte Byte;
|
| 16654 |
|
|
struct {
|
| 16655 |
|
|
byte TSEG10 :1; /* Time Segment 1 */
|
| 16656 |
|
|
byte TSEG11 :1; /* Time Segment 1 */
|
| 16657 |
|
|
byte TSEG12 :1; /* Time Segment 1 */
|
| 16658 |
|
|
byte TSEG13 :1; /* Time Segment 1 */
|
| 16659 |
|
|
byte TSEG20 :1; /* Time Segment 2 */
|
| 16660 |
|
|
byte TSEG21 :1; /* Time Segment 2 */
|
| 16661 |
|
|
byte TSEG22 :1; /* Time Segment 2 */
|
| 16662 |
|
|
byte SAMP :1; /* Sampling */
|
| 16663 |
|
|
} Bits;
|
| 16664 |
|
|
struct {
|
| 16665 |
|
|
byte grpTSEG_10 :4;
|
| 16666 |
|
|
byte grpTSEG_20 :3;
|
| 16667 |
|
|
byte :1;
|
| 16668 |
|
|
} MergedBits;
|
| 16669 |
|
|
} CAN4BTR1STR;
|
| 16670 |
|
|
extern volatile CAN4BTR1STR _CAN4BTR1 @(REG_BASE + 0x00000283);
|
| 16671 |
|
|
#define CAN4BTR1 _CAN4BTR1.Byte
|
| 16672 |
|
|
#define CAN4BTR1_TSEG10 _CAN4BTR1.Bits.TSEG10
|
| 16673 |
|
|
#define CAN4BTR1_TSEG11 _CAN4BTR1.Bits.TSEG11
|
| 16674 |
|
|
#define CAN4BTR1_TSEG12 _CAN4BTR1.Bits.TSEG12
|
| 16675 |
|
|
#define CAN4BTR1_TSEG13 _CAN4BTR1.Bits.TSEG13
|
| 16676 |
|
|
#define CAN4BTR1_TSEG20 _CAN4BTR1.Bits.TSEG20
|
| 16677 |
|
|
#define CAN4BTR1_TSEG21 _CAN4BTR1.Bits.TSEG21
|
| 16678 |
|
|
#define CAN4BTR1_TSEG22 _CAN4BTR1.Bits.TSEG22
|
| 16679 |
|
|
#define CAN4BTR1_SAMP _CAN4BTR1.Bits.SAMP
|
| 16680 |
|
|
#define CAN4BTR1_TSEG_10 _CAN4BTR1.MergedBits.grpTSEG_10
|
| 16681 |
|
|
#define CAN4BTR1_TSEG_20 _CAN4BTR1.MergedBits.grpTSEG_20
|
| 16682 |
|
|
#define CAN4BTR1_TSEG CAN4BTR1_TSEG_10
|
| 16683 |
|
|
|
| 16684 |
|
|
|
| 16685 |
|
|
/*** CAN4RFLG - MSCAN4 Receiver Flag Register; 0x00000284 ***/
|
| 16686 |
|
|
typedef union {
|
| 16687 |
|
|
byte Byte;
|
| 16688 |
|
|
struct {
|
| 16689 |
|
|
byte RXF :1; /* Receive Buffer Full */
|
| 16690 |
|
|
byte OVRIF :1; /* Overrun Interrupt Flag */
|
| 16691 |
|
|
byte TSTAT0 :1; /* Transmitter Status Bit 0 */
|
| 16692 |
|
|
byte TSTAT1 :1; /* Transmitter Status Bit 1 */
|
| 16693 |
|
|
byte RSTAT0 :1; /* Receiver Status Bit 0 */
|
| 16694 |
|
|
byte RSTAT1 :1; /* Receiver Status Bit 1 */
|
| 16695 |
|
|
byte CSCIF :1; /* CAN Status Change Interrupt Flag */
|
| 16696 |
|
|
byte WUPIF :1; /* Wake-up Interrupt Flag */
|
| 16697 |
|
|
} Bits;
|
| 16698 |
|
|
struct {
|
| 16699 |
|
|
byte :1;
|
| 16700 |
|
|
byte :1;
|
| 16701 |
|
|
byte grpTSTAT :2;
|
| 16702 |
|
|
byte grpRSTAT :2;
|
| 16703 |
|
|
byte :1;
|
| 16704 |
|
|
byte :1;
|
| 16705 |
|
|
} MergedBits;
|
| 16706 |
|
|
} CAN4RFLGSTR;
|
| 16707 |
|
|
extern volatile CAN4RFLGSTR _CAN4RFLG @(REG_BASE + 0x00000284);
|
| 16708 |
|
|
#define CAN4RFLG _CAN4RFLG.Byte
|
| 16709 |
|
|
#define CAN4RFLG_RXF _CAN4RFLG.Bits.RXF
|
| 16710 |
|
|
#define CAN4RFLG_OVRIF _CAN4RFLG.Bits.OVRIF
|
| 16711 |
|
|
#define CAN4RFLG_TSTAT0 _CAN4RFLG.Bits.TSTAT0
|
| 16712 |
|
|
#define CAN4RFLG_TSTAT1 _CAN4RFLG.Bits.TSTAT1
|
| 16713 |
|
|
#define CAN4RFLG_RSTAT0 _CAN4RFLG.Bits.RSTAT0
|
| 16714 |
|
|
#define CAN4RFLG_RSTAT1 _CAN4RFLG.Bits.RSTAT1
|
| 16715 |
|
|
#define CAN4RFLG_CSCIF _CAN4RFLG.Bits.CSCIF
|
| 16716 |
|
|
#define CAN4RFLG_WUPIF _CAN4RFLG.Bits.WUPIF
|
| 16717 |
|
|
#define CAN4RFLG_TSTAT _CAN4RFLG.MergedBits.grpTSTAT
|
| 16718 |
|
|
#define CAN4RFLG_RSTAT _CAN4RFLG.MergedBits.grpRSTAT
|
| 16719 |
|
|
|
| 16720 |
|
|
|
| 16721 |
|
|
/*** CAN4RIER - MSCAN4 Receiver Interrupt Enable Register; 0x00000285 ***/
|
| 16722 |
|
|
typedef union {
|
| 16723 |
|
|
byte Byte;
|
| 16724 |
|
|
struct {
|
| 16725 |
|
|
byte RXFIE :1; /* Receiver Full Interrupt Enable */
|
| 16726 |
|
|
byte OVRIE :1; /* Overrun Interrupt Enable */
|
| 16727 |
|
|
byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
|
| 16728 |
|
|
byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
|
| 16729 |
|
|
byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
|
| 16730 |
|
|
byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
|
| 16731 |
|
|
byte CSCIE :1; /* CAN Status Change Interrupt Enable */
|
| 16732 |
|
|
byte WUPIE :1; /* Wake-up Interrupt Enable */
|
| 16733 |
|
|
} Bits;
|
| 16734 |
|
|
struct {
|
| 16735 |
|
|
byte :1;
|
| 16736 |
|
|
byte :1;
|
| 16737 |
|
|
byte grpTSTATE :2;
|
| 16738 |
|
|
byte grpRSTATE :2;
|
| 16739 |
|
|
byte :1;
|
| 16740 |
|
|
byte :1;
|
| 16741 |
|
|
} MergedBits;
|
| 16742 |
|
|
} CAN4RIERSTR;
|
| 16743 |
|
|
extern volatile CAN4RIERSTR _CAN4RIER @(REG_BASE + 0x00000285);
|
| 16744 |
|
|
#define CAN4RIER _CAN4RIER.Byte
|
| 16745 |
|
|
#define CAN4RIER_RXFIE _CAN4RIER.Bits.RXFIE
|
| 16746 |
|
|
#define CAN4RIER_OVRIE _CAN4RIER.Bits.OVRIE
|
| 16747 |
|
|
#define CAN4RIER_TSTATE0 _CAN4RIER.Bits.TSTATE0
|
| 16748 |
|
|
#define CAN4RIER_TSTATE1 _CAN4RIER.Bits.TSTATE1
|
| 16749 |
|
|
#define CAN4RIER_RSTATE0 _CAN4RIER.Bits.RSTATE0
|
| 16750 |
|
|
#define CAN4RIER_RSTATE1 _CAN4RIER.Bits.RSTATE1
|
| 16751 |
|
|
#define CAN4RIER_CSCIE _CAN4RIER.Bits.CSCIE
|
| 16752 |
|
|
#define CAN4RIER_WUPIE _CAN4RIER.Bits.WUPIE
|
| 16753 |
|
|
#define CAN4RIER_TSTATE _CAN4RIER.MergedBits.grpTSTATE
|
| 16754 |
|
|
#define CAN4RIER_RSTATE _CAN4RIER.MergedBits.grpRSTATE
|
| 16755 |
|
|
|
| 16756 |
|
|
|
| 16757 |
|
|
/*** CAN4TFLG - MSCAN4 Transmitter Flag Register; 0x00000286 ***/
|
| 16758 |
|
|
typedef union {
|
| 16759 |
|
|
byte Byte;
|
| 16760 |
|
|
struct {
|
| 16761 |
|
|
byte TXE0 :1; /* Transmitter Buffer Empty 0 */
|
| 16762 |
|
|
byte TXE1 :1; /* Transmitter Buffer Empty 1 */
|
| 16763 |
|
|
byte TXE2 :1; /* Transmitter Buffer Empty 2 */
|
| 16764 |
|
|
byte :1;
|
| 16765 |
|
|
byte :1;
|
| 16766 |
|
|
byte :1;
|
| 16767 |
|
|
byte :1;
|
| 16768 |
|
|
byte :1;
|
| 16769 |
|
|
} Bits;
|
| 16770 |
|
|
struct {
|
| 16771 |
|
|
byte grpTXE :3;
|
| 16772 |
|
|
byte :1;
|
| 16773 |
|
|
byte :1;
|
| 16774 |
|
|
byte :1;
|
| 16775 |
|
|
byte :1;
|
| 16776 |
|
|
byte :1;
|
| 16777 |
|
|
} MergedBits;
|
| 16778 |
|
|
} CAN4TFLGSTR;
|
| 16779 |
|
|
extern volatile CAN4TFLGSTR _CAN4TFLG @(REG_BASE + 0x00000286);
|
| 16780 |
|
|
#define CAN4TFLG _CAN4TFLG.Byte
|
| 16781 |
|
|
#define CAN4TFLG_TXE0 _CAN4TFLG.Bits.TXE0
|
| 16782 |
|
|
#define CAN4TFLG_TXE1 _CAN4TFLG.Bits.TXE1
|
| 16783 |
|
|
#define CAN4TFLG_TXE2 _CAN4TFLG.Bits.TXE2
|
| 16784 |
|
|
#define CAN4TFLG_TXE _CAN4TFLG.MergedBits.grpTXE
|
| 16785 |
|
|
|
| 16786 |
|
|
|
| 16787 |
|
|
/*** CAN4TIER - MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 ***/
|
| 16788 |
|
|
typedef union {
|
| 16789 |
|
|
byte Byte;
|
| 16790 |
|
|
struct {
|
| 16791 |
|
|
byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
|
| 16792 |
|
|
byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
|
| 16793 |
|
|
byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
|
| 16794 |
|
|
byte :1;
|
| 16795 |
|
|
byte :1;
|
| 16796 |
|
|
byte :1;
|
| 16797 |
|
|
byte :1;
|
| 16798 |
|
|
byte :1;
|
| 16799 |
|
|
} Bits;
|
| 16800 |
|
|
struct {
|
| 16801 |
|
|
byte grpTXEIE :3;
|
| 16802 |
|
|
byte :1;
|
| 16803 |
|
|
byte :1;
|
| 16804 |
|
|
byte :1;
|
| 16805 |
|
|
byte :1;
|
| 16806 |
|
|
byte :1;
|
| 16807 |
|
|
} MergedBits;
|
| 16808 |
|
|
} CAN4TIERSTR;
|
| 16809 |
|
|
extern volatile CAN4TIERSTR _CAN4TIER @(REG_BASE + 0x00000287);
|
| 16810 |
|
|
#define CAN4TIER _CAN4TIER.Byte
|
| 16811 |
|
|
#define CAN4TIER_TXEIE0 _CAN4TIER.Bits.TXEIE0
|
| 16812 |
|
|
#define CAN4TIER_TXEIE1 _CAN4TIER.Bits.TXEIE1
|
| 16813 |
|
|
#define CAN4TIER_TXEIE2 _CAN4TIER.Bits.TXEIE2
|
| 16814 |
|
|
#define CAN4TIER_TXEIE _CAN4TIER.MergedBits.grpTXEIE
|
| 16815 |
|
|
|
| 16816 |
|
|
|
| 16817 |
|
|
/*** CAN4TARQ - MSCAN 4 Transmitter Message Abort Request; 0x00000288 ***/
|
| 16818 |
|
|
typedef union {
|
| 16819 |
|
|
byte Byte;
|
| 16820 |
|
|
struct {
|
| 16821 |
|
|
byte ABTRQ0 :1; /* Abort Request 0 */
|
| 16822 |
|
|
byte ABTRQ1 :1; /* Abort Request 1 */
|
| 16823 |
|
|
byte ABTRQ2 :1; /* Abort Request 2 */
|
| 16824 |
|
|
byte :1;
|
| 16825 |
|
|
byte :1;
|
| 16826 |
|
|
byte :1;
|
| 16827 |
|
|
byte :1;
|
| 16828 |
|
|
byte :1;
|
| 16829 |
|
|
} Bits;
|
| 16830 |
|
|
struct {
|
| 16831 |
|
|
byte grpABTRQ :3;
|
| 16832 |
|
|
byte :1;
|
| 16833 |
|
|
byte :1;
|
| 16834 |
|
|
byte :1;
|
| 16835 |
|
|
byte :1;
|
| 16836 |
|
|
byte :1;
|
| 16837 |
|
|
} MergedBits;
|
| 16838 |
|
|
} CAN4TARQSTR;
|
| 16839 |
|
|
extern volatile CAN4TARQSTR _CAN4TARQ @(REG_BASE + 0x00000288);
|
| 16840 |
|
|
#define CAN4TARQ _CAN4TARQ.Byte
|
| 16841 |
|
|
#define CAN4TARQ_ABTRQ0 _CAN4TARQ.Bits.ABTRQ0
|
| 16842 |
|
|
#define CAN4TARQ_ABTRQ1 _CAN4TARQ.Bits.ABTRQ1
|
| 16843 |
|
|
#define CAN4TARQ_ABTRQ2 _CAN4TARQ.Bits.ABTRQ2
|
| 16844 |
|
|
#define CAN4TARQ_ABTRQ _CAN4TARQ.MergedBits.grpABTRQ
|
| 16845 |
|
|
|
| 16846 |
|
|
|
| 16847 |
|
|
/*** CAN4TAAK - MSCAN4 Transmitter Message Abort Control; 0x00000289 ***/
|
| 16848 |
|
|
typedef union {
|
| 16849 |
|
|
byte Byte;
|
| 16850 |
|
|
struct {
|
| 16851 |
|
|
byte ABTAK0 :1; /* Abort Acknowledge 0 */
|
| 16852 |
|
|
byte ABTAK1 :1; /* Abort Acknowledge 1 */
|
| 16853 |
|
|
byte ABTAK2 :1; /* Abort Acknowledge 2 */
|
| 16854 |
|
|
byte :1;
|
| 16855 |
|
|
byte :1;
|
| 16856 |
|
|
byte :1;
|
| 16857 |
|
|
byte :1;
|
| 16858 |
|
|
byte :1;
|
| 16859 |
|
|
} Bits;
|
| 16860 |
|
|
struct {
|
| 16861 |
|
|
byte grpABTAK :3;
|
| 16862 |
|
|
byte :1;
|
| 16863 |
|
|
byte :1;
|
| 16864 |
|
|
byte :1;
|
| 16865 |
|
|
byte :1;
|
| 16866 |
|
|
byte :1;
|
| 16867 |
|
|
} MergedBits;
|
| 16868 |
|
|
} CAN4TAAKSTR;
|
| 16869 |
|
|
extern volatile CAN4TAAKSTR _CAN4TAAK @(REG_BASE + 0x00000289);
|
| 16870 |
|
|
#define CAN4TAAK _CAN4TAAK.Byte
|
| 16871 |
|
|
#define CAN4TAAK_ABTAK0 _CAN4TAAK.Bits.ABTAK0
|
| 16872 |
|
|
#define CAN4TAAK_ABTAK1 _CAN4TAAK.Bits.ABTAK1
|
| 16873 |
|
|
#define CAN4TAAK_ABTAK2 _CAN4TAAK.Bits.ABTAK2
|
| 16874 |
|
|
#define CAN4TAAK_ABTAK _CAN4TAAK.MergedBits.grpABTAK
|
| 16875 |
|
|
|
| 16876 |
|
|
|
| 16877 |
|
|
/*** CAN4TBSEL - MSCAN4 Transmit Buffer Selection; 0x0000028A ***/
|
| 16878 |
|
|
typedef union {
|
| 16879 |
|
|
byte Byte;
|
| 16880 |
|
|
struct {
|
| 16881 |
|
|
byte TX0 :1; /* Transmit Buffer Select 0 */
|
| 16882 |
|
|
byte TX1 :1; /* Transmit Buffer Select 1 */
|
| 16883 |
|
|
byte TX2 :1; /* Transmit Buffer Select 2 */
|
| 16884 |
|
|
byte :1;
|
| 16885 |
|
|
byte :1;
|
| 16886 |
|
|
byte :1;
|
| 16887 |
|
|
byte :1;
|
| 16888 |
|
|
byte :1;
|
| 16889 |
|
|
} Bits;
|
| 16890 |
|
|
struct {
|
| 16891 |
|
|
byte grpTX :3;
|
| 16892 |
|
|
byte :1;
|
| 16893 |
|
|
byte :1;
|
| 16894 |
|
|
byte :1;
|
| 16895 |
|
|
byte :1;
|
| 16896 |
|
|
byte :1;
|
| 16897 |
|
|
} MergedBits;
|
| 16898 |
|
|
} CAN4TBSELSTR;
|
| 16899 |
|
|
extern volatile CAN4TBSELSTR _CAN4TBSEL @(REG_BASE + 0x0000028A);
|
| 16900 |
|
|
#define CAN4TBSEL _CAN4TBSEL.Byte
|
| 16901 |
|
|
#define CAN4TBSEL_TX0 _CAN4TBSEL.Bits.TX0
|
| 16902 |
|
|
#define CAN4TBSEL_TX1 _CAN4TBSEL.Bits.TX1
|
| 16903 |
|
|
#define CAN4TBSEL_TX2 _CAN4TBSEL.Bits.TX2
|
| 16904 |
|
|
#define CAN4TBSEL_TX _CAN4TBSEL.MergedBits.grpTX
|
| 16905 |
|
|
|
| 16906 |
|
|
|
| 16907 |
|
|
/*** CAN4IDAC - MSCAN4 Identifier Acceptance Control Register; 0x0000028B ***/
|
| 16908 |
|
|
typedef union {
|
| 16909 |
|
|
byte Byte;
|
| 16910 |
|
|
struct {
|
| 16911 |
|
|
byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
|
| 16912 |
|
|
byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
|
| 16913 |
|
|
byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
|
| 16914 |
|
|
byte :1;
|
| 16915 |
|
|
byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
|
| 16916 |
|
|
byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
|
| 16917 |
|
|
byte :1;
|
| 16918 |
|
|
byte :1;
|
| 16919 |
|
|
} Bits;
|
| 16920 |
|
|
struct {
|
| 16921 |
|
|
byte grpIDHIT :3;
|
| 16922 |
|
|
byte :1;
|
| 16923 |
|
|
byte grpIDAM :2;
|
| 16924 |
|
|
byte :1;
|
| 16925 |
|
|
byte :1;
|
| 16926 |
|
|
} MergedBits;
|
| 16927 |
|
|
} CAN4IDACSTR;
|
| 16928 |
|
|
extern volatile CAN4IDACSTR _CAN4IDAC @(REG_BASE + 0x0000028B);
|
| 16929 |
|
|
#define CAN4IDAC _CAN4IDAC.Byte
|
| 16930 |
|
|
#define CAN4IDAC_IDHIT0 _CAN4IDAC.Bits.IDHIT0
|
| 16931 |
|
|
#define CAN4IDAC_IDHIT1 _CAN4IDAC.Bits.IDHIT1
|
| 16932 |
|
|
#define CAN4IDAC_IDHIT2 _CAN4IDAC.Bits.IDHIT2
|
| 16933 |
|
|
#define CAN4IDAC_IDAM0 _CAN4IDAC.Bits.IDAM0
|
| 16934 |
|
|
#define CAN4IDAC_IDAM1 _CAN4IDAC.Bits.IDAM1
|
| 16935 |
|
|
#define CAN4IDAC_IDHIT _CAN4IDAC.MergedBits.grpIDHIT
|
| 16936 |
|
|
#define CAN4IDAC_IDAM _CAN4IDAC.MergedBits.grpIDAM
|
| 16937 |
|
|
|
| 16938 |
|
|
|
| 16939 |
|
|
/*** CAN4RXERR - MSCAN4 Receive Error Counter Register; 0x0000028E ***/
|
| 16940 |
|
|
typedef union {
|
| 16941 |
|
|
byte Byte;
|
| 16942 |
|
|
struct {
|
| 16943 |
|
|
byte RXERR0 :1; /* Bit 0 */
|
| 16944 |
|
|
byte RXERR1 :1; /* Bit 1 */
|
| 16945 |
|
|
byte RXERR2 :1; /* Bit 2 */
|
| 16946 |
|
|
byte RXERR3 :1; /* Bit 3 */
|
| 16947 |
|
|
byte RXERR4 :1; /* Bit 4 */
|
| 16948 |
|
|
byte RXERR5 :1; /* Bit 5 */
|
| 16949 |
|
|
byte RXERR6 :1; /* Bit 6 */
|
| 16950 |
|
|
byte RXERR7 :1; /* Bit 7 */
|
| 16951 |
|
|
} Bits;
|
| 16952 |
|
|
struct {
|
| 16953 |
|
|
byte grpRXERR :8;
|
| 16954 |
|
|
} MergedBits;
|
| 16955 |
|
|
} CAN4RXERRSTR;
|
| 16956 |
|
|
extern volatile CAN4RXERRSTR _CAN4RXERR @(REG_BASE + 0x0000028E);
|
| 16957 |
|
|
#define CAN4RXERR _CAN4RXERR.Byte
|
| 16958 |
|
|
#define CAN4RXERR_RXERR0 _CAN4RXERR.Bits.RXERR0
|
| 16959 |
|
|
#define CAN4RXERR_RXERR1 _CAN4RXERR.Bits.RXERR1
|
| 16960 |
|
|
#define CAN4RXERR_RXERR2 _CAN4RXERR.Bits.RXERR2
|
| 16961 |
|
|
#define CAN4RXERR_RXERR3 _CAN4RXERR.Bits.RXERR3
|
| 16962 |
|
|
#define CAN4RXERR_RXERR4 _CAN4RXERR.Bits.RXERR4
|
| 16963 |
|
|
#define CAN4RXERR_RXERR5 _CAN4RXERR.Bits.RXERR5
|
| 16964 |
|
|
#define CAN4RXERR_RXERR6 _CAN4RXERR.Bits.RXERR6
|
| 16965 |
|
|
#define CAN4RXERR_RXERR7 _CAN4RXERR.Bits.RXERR7
|
| 16966 |
|
|
#define CAN4RXERR_RXERR _CAN4RXERR.MergedBits.grpRXERR
|
| 16967 |
|
|
|
| 16968 |
|
|
|
| 16969 |
|
|
/*** CAN4TXERR - MSCAN4 Transmit Error Counter Register; 0x0000028F ***/
|
| 16970 |
|
|
typedef union {
|
| 16971 |
|
|
byte Byte;
|
| 16972 |
|
|
struct {
|
| 16973 |
|
|
byte TXERR0 :1; /* Bit 0 */
|
| 16974 |
|
|
byte TXERR1 :1; /* Bit 1 */
|
| 16975 |
|
|
byte TXERR2 :1; /* Bit 2 */
|
| 16976 |
|
|
byte TXERR3 :1; /* Bit 3 */
|
| 16977 |
|
|
byte TXERR4 :1; /* Bit 4 */
|
| 16978 |
|
|
byte TXERR5 :1; /* Bit 5 */
|
| 16979 |
|
|
byte TXERR6 :1; /* Bit 6 */
|
| 16980 |
|
|
byte TXERR7 :1; /* Bit 7 */
|
| 16981 |
|
|
} Bits;
|
| 16982 |
|
|
struct {
|
| 16983 |
|
|
byte grpTXERR :8;
|
| 16984 |
|
|
} MergedBits;
|
| 16985 |
|
|
} CAN4TXERRSTR;
|
| 16986 |
|
|
extern volatile CAN4TXERRSTR _CAN4TXERR @(REG_BASE + 0x0000028F);
|
| 16987 |
|
|
#define CAN4TXERR _CAN4TXERR.Byte
|
| 16988 |
|
|
#define CAN4TXERR_TXERR0 _CAN4TXERR.Bits.TXERR0
|
| 16989 |
|
|
#define CAN4TXERR_TXERR1 _CAN4TXERR.Bits.TXERR1
|
| 16990 |
|
|
#define CAN4TXERR_TXERR2 _CAN4TXERR.Bits.TXERR2
|
| 16991 |
|
|
#define CAN4TXERR_TXERR3 _CAN4TXERR.Bits.TXERR3
|
| 16992 |
|
|
#define CAN4TXERR_TXERR4 _CAN4TXERR.Bits.TXERR4
|
| 16993 |
|
|
#define CAN4TXERR_TXERR5 _CAN4TXERR.Bits.TXERR5
|
| 16994 |
|
|
#define CAN4TXERR_TXERR6 _CAN4TXERR.Bits.TXERR6
|
| 16995 |
|
|
#define CAN4TXERR_TXERR7 _CAN4TXERR.Bits.TXERR7
|
| 16996 |
|
|
#define CAN4TXERR_TXERR _CAN4TXERR.MergedBits.grpTXERR
|
| 16997 |
|
|
|
| 16998 |
|
|
|
| 16999 |
|
|
/*** CAN4IDAR0 - MSCAN4 Identifier Acceptance Register 0; 0x00000290 ***/
|
| 17000 |
|
|
typedef union {
|
| 17001 |
|
|
byte Byte;
|
| 17002 |
|
|
struct {
|
| 17003 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 17004 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 17005 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 17006 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 17007 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 17008 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 17009 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 17010 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 17011 |
|
|
} Bits;
|
| 17012 |
|
|
struct {
|
| 17013 |
|
|
byte grpAC :8;
|
| 17014 |
|
|
} MergedBits;
|
| 17015 |
|
|
} CAN4IDAR0STR;
|
| 17016 |
|
|
extern volatile CAN4IDAR0STR _CAN4IDAR0 @(REG_BASE + 0x00000290);
|
| 17017 |
|
|
#define CAN4IDAR0 _CAN4IDAR0.Byte
|
| 17018 |
|
|
#define CAN4IDAR0_AC0 _CAN4IDAR0.Bits.AC0
|
| 17019 |
|
|
#define CAN4IDAR0_AC1 _CAN4IDAR0.Bits.AC1
|
| 17020 |
|
|
#define CAN4IDAR0_AC2 _CAN4IDAR0.Bits.AC2
|
| 17021 |
|
|
#define CAN4IDAR0_AC3 _CAN4IDAR0.Bits.AC3
|
| 17022 |
|
|
#define CAN4IDAR0_AC4 _CAN4IDAR0.Bits.AC4
|
| 17023 |
|
|
#define CAN4IDAR0_AC5 _CAN4IDAR0.Bits.AC5
|
| 17024 |
|
|
#define CAN4IDAR0_AC6 _CAN4IDAR0.Bits.AC6
|
| 17025 |
|
|
#define CAN4IDAR0_AC7 _CAN4IDAR0.Bits.AC7
|
| 17026 |
|
|
#define CAN4IDAR0_AC _CAN4IDAR0.MergedBits.grpAC
|
| 17027 |
|
|
|
| 17028 |
|
|
|
| 17029 |
|
|
/*** CAN4IDAR1 - MSCAN4 Identifier Acceptance Register 1; 0x00000291 ***/
|
| 17030 |
|
|
typedef union {
|
| 17031 |
|
|
byte Byte;
|
| 17032 |
|
|
struct {
|
| 17033 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 17034 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 17035 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 17036 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 17037 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 17038 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 17039 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 17040 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 17041 |
|
|
} Bits;
|
| 17042 |
|
|
struct {
|
| 17043 |
|
|
byte grpAC :8;
|
| 17044 |
|
|
} MergedBits;
|
| 17045 |
|
|
} CAN4IDAR1STR;
|
| 17046 |
|
|
extern volatile CAN4IDAR1STR _CAN4IDAR1 @(REG_BASE + 0x00000291);
|
| 17047 |
|
|
#define CAN4IDAR1 _CAN4IDAR1.Byte
|
| 17048 |
|
|
#define CAN4IDAR1_AC0 _CAN4IDAR1.Bits.AC0
|
| 17049 |
|
|
#define CAN4IDAR1_AC1 _CAN4IDAR1.Bits.AC1
|
| 17050 |
|
|
#define CAN4IDAR1_AC2 _CAN4IDAR1.Bits.AC2
|
| 17051 |
|
|
#define CAN4IDAR1_AC3 _CAN4IDAR1.Bits.AC3
|
| 17052 |
|
|
#define CAN4IDAR1_AC4 _CAN4IDAR1.Bits.AC4
|
| 17053 |
|
|
#define CAN4IDAR1_AC5 _CAN4IDAR1.Bits.AC5
|
| 17054 |
|
|
#define CAN4IDAR1_AC6 _CAN4IDAR1.Bits.AC6
|
| 17055 |
|
|
#define CAN4IDAR1_AC7 _CAN4IDAR1.Bits.AC7
|
| 17056 |
|
|
#define CAN4IDAR1_AC _CAN4IDAR1.MergedBits.grpAC
|
| 17057 |
|
|
|
| 17058 |
|
|
|
| 17059 |
|
|
/*** CAN4IDAR2 - MSCAN4 Identifier Acceptance Register 2; 0x00000292 ***/
|
| 17060 |
|
|
typedef union {
|
| 17061 |
|
|
byte Byte;
|
| 17062 |
|
|
struct {
|
| 17063 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 17064 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 17065 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 17066 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 17067 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 17068 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 17069 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 17070 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 17071 |
|
|
} Bits;
|
| 17072 |
|
|
struct {
|
| 17073 |
|
|
byte grpAC :8;
|
| 17074 |
|
|
} MergedBits;
|
| 17075 |
|
|
} CAN4IDAR2STR;
|
| 17076 |
|
|
extern volatile CAN4IDAR2STR _CAN4IDAR2 @(REG_BASE + 0x00000292);
|
| 17077 |
|
|
#define CAN4IDAR2 _CAN4IDAR2.Byte
|
| 17078 |
|
|
#define CAN4IDAR2_AC0 _CAN4IDAR2.Bits.AC0
|
| 17079 |
|
|
#define CAN4IDAR2_AC1 _CAN4IDAR2.Bits.AC1
|
| 17080 |
|
|
#define CAN4IDAR2_AC2 _CAN4IDAR2.Bits.AC2
|
| 17081 |
|
|
#define CAN4IDAR2_AC3 _CAN4IDAR2.Bits.AC3
|
| 17082 |
|
|
#define CAN4IDAR2_AC4 _CAN4IDAR2.Bits.AC4
|
| 17083 |
|
|
#define CAN4IDAR2_AC5 _CAN4IDAR2.Bits.AC5
|
| 17084 |
|
|
#define CAN4IDAR2_AC6 _CAN4IDAR2.Bits.AC6
|
| 17085 |
|
|
#define CAN4IDAR2_AC7 _CAN4IDAR2.Bits.AC7
|
| 17086 |
|
|
#define CAN4IDAR2_AC _CAN4IDAR2.MergedBits.grpAC
|
| 17087 |
|
|
|
| 17088 |
|
|
|
| 17089 |
|
|
/*** CAN4IDAR3 - MSCAN4 Identifier Acceptance Register 3; 0x00000293 ***/
|
| 17090 |
|
|
typedef union {
|
| 17091 |
|
|
byte Byte;
|
| 17092 |
|
|
struct {
|
| 17093 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 17094 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 17095 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 17096 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 17097 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 17098 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 17099 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 17100 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 17101 |
|
|
} Bits;
|
| 17102 |
|
|
struct {
|
| 17103 |
|
|
byte grpAC :8;
|
| 17104 |
|
|
} MergedBits;
|
| 17105 |
|
|
} CAN4IDAR3STR;
|
| 17106 |
|
|
extern volatile CAN4IDAR3STR _CAN4IDAR3 @(REG_BASE + 0x00000293);
|
| 17107 |
|
|
#define CAN4IDAR3 _CAN4IDAR3.Byte
|
| 17108 |
|
|
#define CAN4IDAR3_AC0 _CAN4IDAR3.Bits.AC0
|
| 17109 |
|
|
#define CAN4IDAR3_AC1 _CAN4IDAR3.Bits.AC1
|
| 17110 |
|
|
#define CAN4IDAR3_AC2 _CAN4IDAR3.Bits.AC2
|
| 17111 |
|
|
#define CAN4IDAR3_AC3 _CAN4IDAR3.Bits.AC3
|
| 17112 |
|
|
#define CAN4IDAR3_AC4 _CAN4IDAR3.Bits.AC4
|
| 17113 |
|
|
#define CAN4IDAR3_AC5 _CAN4IDAR3.Bits.AC5
|
| 17114 |
|
|
#define CAN4IDAR3_AC6 _CAN4IDAR3.Bits.AC6
|
| 17115 |
|
|
#define CAN4IDAR3_AC7 _CAN4IDAR3.Bits.AC7
|
| 17116 |
|
|
#define CAN4IDAR3_AC _CAN4IDAR3.MergedBits.grpAC
|
| 17117 |
|
|
|
| 17118 |
|
|
|
| 17119 |
|
|
/*** CAN4IDMR0 - MSCAN4 Identifier Mask Register 0; 0x00000294 ***/
|
| 17120 |
|
|
typedef union {
|
| 17121 |
|
|
byte Byte;
|
| 17122 |
|
|
struct {
|
| 17123 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 17124 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 17125 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 17126 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 17127 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 17128 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 17129 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 17130 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 17131 |
|
|
} Bits;
|
| 17132 |
|
|
struct {
|
| 17133 |
|
|
byte grpAM :8;
|
| 17134 |
|
|
} MergedBits;
|
| 17135 |
|
|
} CAN4IDMR0STR;
|
| 17136 |
|
|
extern volatile CAN4IDMR0STR _CAN4IDMR0 @(REG_BASE + 0x00000294);
|
| 17137 |
|
|
#define CAN4IDMR0 _CAN4IDMR0.Byte
|
| 17138 |
|
|
#define CAN4IDMR0_AM0 _CAN4IDMR0.Bits.AM0
|
| 17139 |
|
|
#define CAN4IDMR0_AM1 _CAN4IDMR0.Bits.AM1
|
| 17140 |
|
|
#define CAN4IDMR0_AM2 _CAN4IDMR0.Bits.AM2
|
| 17141 |
|
|
#define CAN4IDMR0_AM3 _CAN4IDMR0.Bits.AM3
|
| 17142 |
|
|
#define CAN4IDMR0_AM4 _CAN4IDMR0.Bits.AM4
|
| 17143 |
|
|
#define CAN4IDMR0_AM5 _CAN4IDMR0.Bits.AM5
|
| 17144 |
|
|
#define CAN4IDMR0_AM6 _CAN4IDMR0.Bits.AM6
|
| 17145 |
|
|
#define CAN4IDMR0_AM7 _CAN4IDMR0.Bits.AM7
|
| 17146 |
|
|
#define CAN4IDMR0_AM _CAN4IDMR0.MergedBits.grpAM
|
| 17147 |
|
|
|
| 17148 |
|
|
|
| 17149 |
|
|
/*** CAN4IDMR1 - MSCAN4 Identifier Mask Register 1; 0x00000295 ***/
|
| 17150 |
|
|
typedef union {
|
| 17151 |
|
|
byte Byte;
|
| 17152 |
|
|
struct {
|
| 17153 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 17154 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 17155 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 17156 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 17157 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 17158 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 17159 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 17160 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 17161 |
|
|
} Bits;
|
| 17162 |
|
|
struct {
|
| 17163 |
|
|
byte grpAM :8;
|
| 17164 |
|
|
} MergedBits;
|
| 17165 |
|
|
} CAN4IDMR1STR;
|
| 17166 |
|
|
extern volatile CAN4IDMR1STR _CAN4IDMR1 @(REG_BASE + 0x00000295);
|
| 17167 |
|
|
#define CAN4IDMR1 _CAN4IDMR1.Byte
|
| 17168 |
|
|
#define CAN4IDMR1_AM0 _CAN4IDMR1.Bits.AM0
|
| 17169 |
|
|
#define CAN4IDMR1_AM1 _CAN4IDMR1.Bits.AM1
|
| 17170 |
|
|
#define CAN4IDMR1_AM2 _CAN4IDMR1.Bits.AM2
|
| 17171 |
|
|
#define CAN4IDMR1_AM3 _CAN4IDMR1.Bits.AM3
|
| 17172 |
|
|
#define CAN4IDMR1_AM4 _CAN4IDMR1.Bits.AM4
|
| 17173 |
|
|
#define CAN4IDMR1_AM5 _CAN4IDMR1.Bits.AM5
|
| 17174 |
|
|
#define CAN4IDMR1_AM6 _CAN4IDMR1.Bits.AM6
|
| 17175 |
|
|
#define CAN4IDMR1_AM7 _CAN4IDMR1.Bits.AM7
|
| 17176 |
|
|
#define CAN4IDMR1_AM _CAN4IDMR1.MergedBits.grpAM
|
| 17177 |
|
|
|
| 17178 |
|
|
|
| 17179 |
|
|
/*** CAN4IDMR2 - MSCAN4 Identifier Mask Register 2; 0x00000296 ***/
|
| 17180 |
|
|
typedef union {
|
| 17181 |
|
|
byte Byte;
|
| 17182 |
|
|
struct {
|
| 17183 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 17184 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 17185 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 17186 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 17187 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 17188 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 17189 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 17190 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 17191 |
|
|
} Bits;
|
| 17192 |
|
|
struct {
|
| 17193 |
|
|
byte grpAM :8;
|
| 17194 |
|
|
} MergedBits;
|
| 17195 |
|
|
} CAN4IDMR2STR;
|
| 17196 |
|
|
extern volatile CAN4IDMR2STR _CAN4IDMR2 @(REG_BASE + 0x00000296);
|
| 17197 |
|
|
#define CAN4IDMR2 _CAN4IDMR2.Byte
|
| 17198 |
|
|
#define CAN4IDMR2_AM0 _CAN4IDMR2.Bits.AM0
|
| 17199 |
|
|
#define CAN4IDMR2_AM1 _CAN4IDMR2.Bits.AM1
|
| 17200 |
|
|
#define CAN4IDMR2_AM2 _CAN4IDMR2.Bits.AM2
|
| 17201 |
|
|
#define CAN4IDMR2_AM3 _CAN4IDMR2.Bits.AM3
|
| 17202 |
|
|
#define CAN4IDMR2_AM4 _CAN4IDMR2.Bits.AM4
|
| 17203 |
|
|
#define CAN4IDMR2_AM5 _CAN4IDMR2.Bits.AM5
|
| 17204 |
|
|
#define CAN4IDMR2_AM6 _CAN4IDMR2.Bits.AM6
|
| 17205 |
|
|
#define CAN4IDMR2_AM7 _CAN4IDMR2.Bits.AM7
|
| 17206 |
|
|
#define CAN4IDMR2_AM _CAN4IDMR2.MergedBits.grpAM
|
| 17207 |
|
|
|
| 17208 |
|
|
|
| 17209 |
|
|
/*** CAN4IDMR3 - MSCAN4 Identifier Mask Register 3; 0x00000297 ***/
|
| 17210 |
|
|
typedef union {
|
| 17211 |
|
|
byte Byte;
|
| 17212 |
|
|
struct {
|
| 17213 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 17214 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 17215 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 17216 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 17217 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 17218 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 17219 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 17220 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 17221 |
|
|
} Bits;
|
| 17222 |
|
|
struct {
|
| 17223 |
|
|
byte grpAM :8;
|
| 17224 |
|
|
} MergedBits;
|
| 17225 |
|
|
} CAN4IDMR3STR;
|
| 17226 |
|
|
extern volatile CAN4IDMR3STR _CAN4IDMR3 @(REG_BASE + 0x00000297);
|
| 17227 |
|
|
#define CAN4IDMR3 _CAN4IDMR3.Byte
|
| 17228 |
|
|
#define CAN4IDMR3_AM0 _CAN4IDMR3.Bits.AM0
|
| 17229 |
|
|
#define CAN4IDMR3_AM1 _CAN4IDMR3.Bits.AM1
|
| 17230 |
|
|
#define CAN4IDMR3_AM2 _CAN4IDMR3.Bits.AM2
|
| 17231 |
|
|
#define CAN4IDMR3_AM3 _CAN4IDMR3.Bits.AM3
|
| 17232 |
|
|
#define CAN4IDMR3_AM4 _CAN4IDMR3.Bits.AM4
|
| 17233 |
|
|
#define CAN4IDMR3_AM5 _CAN4IDMR3.Bits.AM5
|
| 17234 |
|
|
#define CAN4IDMR3_AM6 _CAN4IDMR3.Bits.AM6
|
| 17235 |
|
|
#define CAN4IDMR3_AM7 _CAN4IDMR3.Bits.AM7
|
| 17236 |
|
|
#define CAN4IDMR3_AM _CAN4IDMR3.MergedBits.grpAM
|
| 17237 |
|
|
|
| 17238 |
|
|
|
| 17239 |
|
|
/*** CAN4IDAR4 - MSCAN4 Identifier Acceptance Register 4; 0x00000298 ***/
|
| 17240 |
|
|
typedef union {
|
| 17241 |
|
|
byte Byte;
|
| 17242 |
|
|
struct {
|
| 17243 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 17244 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 17245 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 17246 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 17247 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 17248 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 17249 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 17250 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 17251 |
|
|
} Bits;
|
| 17252 |
|
|
struct {
|
| 17253 |
|
|
byte grpAC :8;
|
| 17254 |
|
|
} MergedBits;
|
| 17255 |
|
|
} CAN4IDAR4STR;
|
| 17256 |
|
|
extern volatile CAN4IDAR4STR _CAN4IDAR4 @(REG_BASE + 0x00000298);
|
| 17257 |
|
|
#define CAN4IDAR4 _CAN4IDAR4.Byte
|
| 17258 |
|
|
#define CAN4IDAR4_AC0 _CAN4IDAR4.Bits.AC0
|
| 17259 |
|
|
#define CAN4IDAR4_AC1 _CAN4IDAR4.Bits.AC1
|
| 17260 |
|
|
#define CAN4IDAR4_AC2 _CAN4IDAR4.Bits.AC2
|
| 17261 |
|
|
#define CAN4IDAR4_AC3 _CAN4IDAR4.Bits.AC3
|
| 17262 |
|
|
#define CAN4IDAR4_AC4 _CAN4IDAR4.Bits.AC4
|
| 17263 |
|
|
#define CAN4IDAR4_AC5 _CAN4IDAR4.Bits.AC5
|
| 17264 |
|
|
#define CAN4IDAR4_AC6 _CAN4IDAR4.Bits.AC6
|
| 17265 |
|
|
#define CAN4IDAR4_AC7 _CAN4IDAR4.Bits.AC7
|
| 17266 |
|
|
#define CAN4IDAR4_AC _CAN4IDAR4.MergedBits.grpAC
|
| 17267 |
|
|
|
| 17268 |
|
|
|
| 17269 |
|
|
/*** CAN4IDAR5 - MSCAN4 Identifier Acceptance Register 5; 0x00000299 ***/
|
| 17270 |
|
|
typedef union {
|
| 17271 |
|
|
byte Byte;
|
| 17272 |
|
|
struct {
|
| 17273 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 17274 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 17275 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 17276 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 17277 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 17278 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 17279 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 17280 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 17281 |
|
|
} Bits;
|
| 17282 |
|
|
struct {
|
| 17283 |
|
|
byte grpAC :8;
|
| 17284 |
|
|
} MergedBits;
|
| 17285 |
|
|
} CAN4IDAR5STR;
|
| 17286 |
|
|
extern volatile CAN4IDAR5STR _CAN4IDAR5 @(REG_BASE + 0x00000299);
|
| 17287 |
|
|
#define CAN4IDAR5 _CAN4IDAR5.Byte
|
| 17288 |
|
|
#define CAN4IDAR5_AC0 _CAN4IDAR5.Bits.AC0
|
| 17289 |
|
|
#define CAN4IDAR5_AC1 _CAN4IDAR5.Bits.AC1
|
| 17290 |
|
|
#define CAN4IDAR5_AC2 _CAN4IDAR5.Bits.AC2
|
| 17291 |
|
|
#define CAN4IDAR5_AC3 _CAN4IDAR5.Bits.AC3
|
| 17292 |
|
|
#define CAN4IDAR5_AC4 _CAN4IDAR5.Bits.AC4
|
| 17293 |
|
|
#define CAN4IDAR5_AC5 _CAN4IDAR5.Bits.AC5
|
| 17294 |
|
|
#define CAN4IDAR5_AC6 _CAN4IDAR5.Bits.AC6
|
| 17295 |
|
|
#define CAN4IDAR5_AC7 _CAN4IDAR5.Bits.AC7
|
| 17296 |
|
|
#define CAN4IDAR5_AC _CAN4IDAR5.MergedBits.grpAC
|
| 17297 |
|
|
|
| 17298 |
|
|
|
| 17299 |
|
|
/*** CAN4IDAR6 - MSCAN4 Identifier Acceptance Register 6; 0x0000029A ***/
|
| 17300 |
|
|
typedef union {
|
| 17301 |
|
|
byte Byte;
|
| 17302 |
|
|
struct {
|
| 17303 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 17304 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 17305 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 17306 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 17307 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 17308 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 17309 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 17310 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 17311 |
|
|
} Bits;
|
| 17312 |
|
|
struct {
|
| 17313 |
|
|
byte grpAC :8;
|
| 17314 |
|
|
} MergedBits;
|
| 17315 |
|
|
} CAN4IDAR6STR;
|
| 17316 |
|
|
extern volatile CAN4IDAR6STR _CAN4IDAR6 @(REG_BASE + 0x0000029A);
|
| 17317 |
|
|
#define CAN4IDAR6 _CAN4IDAR6.Byte
|
| 17318 |
|
|
#define CAN4IDAR6_AC0 _CAN4IDAR6.Bits.AC0
|
| 17319 |
|
|
#define CAN4IDAR6_AC1 _CAN4IDAR6.Bits.AC1
|
| 17320 |
|
|
#define CAN4IDAR6_AC2 _CAN4IDAR6.Bits.AC2
|
| 17321 |
|
|
#define CAN4IDAR6_AC3 _CAN4IDAR6.Bits.AC3
|
| 17322 |
|
|
#define CAN4IDAR6_AC4 _CAN4IDAR6.Bits.AC4
|
| 17323 |
|
|
#define CAN4IDAR6_AC5 _CAN4IDAR6.Bits.AC5
|
| 17324 |
|
|
#define CAN4IDAR6_AC6 _CAN4IDAR6.Bits.AC6
|
| 17325 |
|
|
#define CAN4IDAR6_AC7 _CAN4IDAR6.Bits.AC7
|
| 17326 |
|
|
#define CAN4IDAR6_AC _CAN4IDAR6.MergedBits.grpAC
|
| 17327 |
|
|
|
| 17328 |
|
|
|
| 17329 |
|
|
/*** CAN4IDAR7 - MSCAN4 Identifier Acceptance Register 7; 0x0000029B ***/
|
| 17330 |
|
|
typedef union {
|
| 17331 |
|
|
byte Byte;
|
| 17332 |
|
|
struct {
|
| 17333 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 17334 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 17335 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 17336 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 17337 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 17338 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 17339 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 17340 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 17341 |
|
|
} Bits;
|
| 17342 |
|
|
struct {
|
| 17343 |
|
|
byte grpAC :8;
|
| 17344 |
|
|
} MergedBits;
|
| 17345 |
|
|
} CAN4IDAR7STR;
|
| 17346 |
|
|
extern volatile CAN4IDAR7STR _CAN4IDAR7 @(REG_BASE + 0x0000029B);
|
| 17347 |
|
|
#define CAN4IDAR7 _CAN4IDAR7.Byte
|
| 17348 |
|
|
#define CAN4IDAR7_AC0 _CAN4IDAR7.Bits.AC0
|
| 17349 |
|
|
#define CAN4IDAR7_AC1 _CAN4IDAR7.Bits.AC1
|
| 17350 |
|
|
#define CAN4IDAR7_AC2 _CAN4IDAR7.Bits.AC2
|
| 17351 |
|
|
#define CAN4IDAR7_AC3 _CAN4IDAR7.Bits.AC3
|
| 17352 |
|
|
#define CAN4IDAR7_AC4 _CAN4IDAR7.Bits.AC4
|
| 17353 |
|
|
#define CAN4IDAR7_AC5 _CAN4IDAR7.Bits.AC5
|
| 17354 |
|
|
#define CAN4IDAR7_AC6 _CAN4IDAR7.Bits.AC6
|
| 17355 |
|
|
#define CAN4IDAR7_AC7 _CAN4IDAR7.Bits.AC7
|
| 17356 |
|
|
#define CAN4IDAR7_AC _CAN4IDAR7.MergedBits.grpAC
|
| 17357 |
|
|
|
| 17358 |
|
|
|
| 17359 |
|
|
/*** CAN4IDMR4 - MSCAN4 Identifier Mask Register 4; 0x0000029C ***/
|
| 17360 |
|
|
typedef union {
|
| 17361 |
|
|
byte Byte;
|
| 17362 |
|
|
struct {
|
| 17363 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 17364 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 17365 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 17366 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 17367 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 17368 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 17369 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 17370 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 17371 |
|
|
} Bits;
|
| 17372 |
|
|
struct {
|
| 17373 |
|
|
byte grpAM :8;
|
| 17374 |
|
|
} MergedBits;
|
| 17375 |
|
|
} CAN4IDMR4STR;
|
| 17376 |
|
|
extern volatile CAN4IDMR4STR _CAN4IDMR4 @(REG_BASE + 0x0000029C);
|
| 17377 |
|
|
#define CAN4IDMR4 _CAN4IDMR4.Byte
|
| 17378 |
|
|
#define CAN4IDMR4_AM0 _CAN4IDMR4.Bits.AM0
|
| 17379 |
|
|
#define CAN4IDMR4_AM1 _CAN4IDMR4.Bits.AM1
|
| 17380 |
|
|
#define CAN4IDMR4_AM2 _CAN4IDMR4.Bits.AM2
|
| 17381 |
|
|
#define CAN4IDMR4_AM3 _CAN4IDMR4.Bits.AM3
|
| 17382 |
|
|
#define CAN4IDMR4_AM4 _CAN4IDMR4.Bits.AM4
|
| 17383 |
|
|
#define CAN4IDMR4_AM5 _CAN4IDMR4.Bits.AM5
|
| 17384 |
|
|
#define CAN4IDMR4_AM6 _CAN4IDMR4.Bits.AM6
|
| 17385 |
|
|
#define CAN4IDMR4_AM7 _CAN4IDMR4.Bits.AM7
|
| 17386 |
|
|
#define CAN4IDMR4_AM _CAN4IDMR4.MergedBits.grpAM
|
| 17387 |
|
|
|
| 17388 |
|
|
|
| 17389 |
|
|
/*** CAN4IDMR5 - MSCAN4 Identifier Mask Register 5; 0x0000029D ***/
|
| 17390 |
|
|
typedef union {
|
| 17391 |
|
|
byte Byte;
|
| 17392 |
|
|
struct {
|
| 17393 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 17394 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 17395 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 17396 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 17397 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 17398 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 17399 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 17400 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 17401 |
|
|
} Bits;
|
| 17402 |
|
|
struct {
|
| 17403 |
|
|
byte grpAM :8;
|
| 17404 |
|
|
} MergedBits;
|
| 17405 |
|
|
} CAN4IDMR5STR;
|
| 17406 |
|
|
extern volatile CAN4IDMR5STR _CAN4IDMR5 @(REG_BASE + 0x0000029D);
|
| 17407 |
|
|
#define CAN4IDMR5 _CAN4IDMR5.Byte
|
| 17408 |
|
|
#define CAN4IDMR5_AM0 _CAN4IDMR5.Bits.AM0
|
| 17409 |
|
|
#define CAN4IDMR5_AM1 _CAN4IDMR5.Bits.AM1
|
| 17410 |
|
|
#define CAN4IDMR5_AM2 _CAN4IDMR5.Bits.AM2
|
| 17411 |
|
|
#define CAN4IDMR5_AM3 _CAN4IDMR5.Bits.AM3
|
| 17412 |
|
|
#define CAN4IDMR5_AM4 _CAN4IDMR5.Bits.AM4
|
| 17413 |
|
|
#define CAN4IDMR5_AM5 _CAN4IDMR5.Bits.AM5
|
| 17414 |
|
|
#define CAN4IDMR5_AM6 _CAN4IDMR5.Bits.AM6
|
| 17415 |
|
|
#define CAN4IDMR5_AM7 _CAN4IDMR5.Bits.AM7
|
| 17416 |
|
|
#define CAN4IDMR5_AM _CAN4IDMR5.MergedBits.grpAM
|
| 17417 |
|
|
|
| 17418 |
|
|
|
| 17419 |
|
|
/*** CAN4IDMR6 - MSCAN4 Identifier Mask Register 6; 0x0000029E ***/
|
| 17420 |
|
|
typedef union {
|
| 17421 |
|
|
byte Byte;
|
| 17422 |
|
|
struct {
|
| 17423 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 17424 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 17425 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 17426 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 17427 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 17428 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 17429 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 17430 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 17431 |
|
|
} Bits;
|
| 17432 |
|
|
struct {
|
| 17433 |
|
|
byte grpAM :8;
|
| 17434 |
|
|
} MergedBits;
|
| 17435 |
|
|
} CAN4IDMR6STR;
|
| 17436 |
|
|
extern volatile CAN4IDMR6STR _CAN4IDMR6 @(REG_BASE + 0x0000029E);
|
| 17437 |
|
|
#define CAN4IDMR6 _CAN4IDMR6.Byte
|
| 17438 |
|
|
#define CAN4IDMR6_AM0 _CAN4IDMR6.Bits.AM0
|
| 17439 |
|
|
#define CAN4IDMR6_AM1 _CAN4IDMR6.Bits.AM1
|
| 17440 |
|
|
#define CAN4IDMR6_AM2 _CAN4IDMR6.Bits.AM2
|
| 17441 |
|
|
#define CAN4IDMR6_AM3 _CAN4IDMR6.Bits.AM3
|
| 17442 |
|
|
#define CAN4IDMR6_AM4 _CAN4IDMR6.Bits.AM4
|
| 17443 |
|
|
#define CAN4IDMR6_AM5 _CAN4IDMR6.Bits.AM5
|
| 17444 |
|
|
#define CAN4IDMR6_AM6 _CAN4IDMR6.Bits.AM6
|
| 17445 |
|
|
#define CAN4IDMR6_AM7 _CAN4IDMR6.Bits.AM7
|
| 17446 |
|
|
#define CAN4IDMR6_AM _CAN4IDMR6.MergedBits.grpAM
|
| 17447 |
|
|
|
| 17448 |
|
|
|
| 17449 |
|
|
/*** CAN4IDMR7 - MSCAN4 Identifier Mask Register 7; 0x0000029F ***/
|
| 17450 |
|
|
typedef union {
|
| 17451 |
|
|
byte Byte;
|
| 17452 |
|
|
struct {
|
| 17453 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 17454 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 17455 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 17456 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 17457 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 17458 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 17459 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 17460 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 17461 |
|
|
} Bits;
|
| 17462 |
|
|
struct {
|
| 17463 |
|
|
byte grpAM :8;
|
| 17464 |
|
|
} MergedBits;
|
| 17465 |
|
|
} CAN4IDMR7STR;
|
| 17466 |
|
|
extern volatile CAN4IDMR7STR _CAN4IDMR7 @(REG_BASE + 0x0000029F);
|
| 17467 |
|
|
#define CAN4IDMR7 _CAN4IDMR7.Byte
|
| 17468 |
|
|
#define CAN4IDMR7_AM0 _CAN4IDMR7.Bits.AM0
|
| 17469 |
|
|
#define CAN4IDMR7_AM1 _CAN4IDMR7.Bits.AM1
|
| 17470 |
|
|
#define CAN4IDMR7_AM2 _CAN4IDMR7.Bits.AM2
|
| 17471 |
|
|
#define CAN4IDMR7_AM3 _CAN4IDMR7.Bits.AM3
|
| 17472 |
|
|
#define CAN4IDMR7_AM4 _CAN4IDMR7.Bits.AM4
|
| 17473 |
|
|
#define CAN4IDMR7_AM5 _CAN4IDMR7.Bits.AM5
|
| 17474 |
|
|
#define CAN4IDMR7_AM6 _CAN4IDMR7.Bits.AM6
|
| 17475 |
|
|
#define CAN4IDMR7_AM7 _CAN4IDMR7.Bits.AM7
|
| 17476 |
|
|
#define CAN4IDMR7_AM _CAN4IDMR7.MergedBits.grpAM
|
| 17477 |
|
|
|
| 17478 |
|
|
|
| 17479 |
|
|
/*** CAN4RXIDR0 - MSCAN4 Receive Identifier Register 0; 0x000002A0 ***/
|
| 17480 |
|
|
typedef union {
|
| 17481 |
|
|
byte Byte;
|
| 17482 |
|
|
struct {
|
| 17483 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 17484 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 17485 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 17486 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 17487 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 17488 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 17489 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 17490 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 17491 |
|
|
} Bits;
|
| 17492 |
|
|
struct {
|
| 17493 |
|
|
byte grpID_21 :8;
|
| 17494 |
|
|
} MergedBits;
|
| 17495 |
|
|
} CAN4RXIDR0STR;
|
| 17496 |
|
|
extern volatile CAN4RXIDR0STR _CAN4RXIDR0 @(REG_BASE + 0x000002A0);
|
| 17497 |
|
|
#define CAN4RXIDR0 _CAN4RXIDR0.Byte
|
| 17498 |
|
|
#define CAN4RXIDR0_ID21 _CAN4RXIDR0.Bits.ID21
|
| 17499 |
|
|
#define CAN4RXIDR0_ID22 _CAN4RXIDR0.Bits.ID22
|
| 17500 |
|
|
#define CAN4RXIDR0_ID23 _CAN4RXIDR0.Bits.ID23
|
| 17501 |
|
|
#define CAN4RXIDR0_ID24 _CAN4RXIDR0.Bits.ID24
|
| 17502 |
|
|
#define CAN4RXIDR0_ID25 _CAN4RXIDR0.Bits.ID25
|
| 17503 |
|
|
#define CAN4RXIDR0_ID26 _CAN4RXIDR0.Bits.ID26
|
| 17504 |
|
|
#define CAN4RXIDR0_ID27 _CAN4RXIDR0.Bits.ID27
|
| 17505 |
|
|
#define CAN4RXIDR0_ID28 _CAN4RXIDR0.Bits.ID28
|
| 17506 |
|
|
#define CAN4RXIDR0_ID_21 _CAN4RXIDR0.MergedBits.grpID_21
|
| 17507 |
|
|
#define CAN4RXIDR0_ID CAN4RXIDR0_ID_21
|
| 17508 |
|
|
|
| 17509 |
|
|
|
| 17510 |
|
|
/*** CAN4RXIDR1 - MSCAN4 Receive Identifier Register 1; 0x000002A1 ***/
|
| 17511 |
|
|
typedef union {
|
| 17512 |
|
|
byte Byte;
|
| 17513 |
|
|
struct {
|
| 17514 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 17515 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 17516 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 17517 |
|
|
byte IDE :1; /* ID Extended */
|
| 17518 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 17519 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 17520 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 17521 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 17522 |
|
|
} Bits;
|
| 17523 |
|
|
struct {
|
| 17524 |
|
|
byte grpID_15 :3;
|
| 17525 |
|
|
byte :1;
|
| 17526 |
|
|
byte :1;
|
| 17527 |
|
|
byte grpID_18 :3;
|
| 17528 |
|
|
} MergedBits;
|
| 17529 |
|
|
} CAN4RXIDR1STR;
|
| 17530 |
|
|
extern volatile CAN4RXIDR1STR _CAN4RXIDR1 @(REG_BASE + 0x000002A1);
|
| 17531 |
|
|
#define CAN4RXIDR1 _CAN4RXIDR1.Byte
|
| 17532 |
|
|
#define CAN4RXIDR1_ID15 _CAN4RXIDR1.Bits.ID15
|
| 17533 |
|
|
#define CAN4RXIDR1_ID16 _CAN4RXIDR1.Bits.ID16
|
| 17534 |
|
|
#define CAN4RXIDR1_ID17 _CAN4RXIDR1.Bits.ID17
|
| 17535 |
|
|
#define CAN4RXIDR1_IDE _CAN4RXIDR1.Bits.IDE
|
| 17536 |
|
|
#define CAN4RXIDR1_SRR _CAN4RXIDR1.Bits.SRR
|
| 17537 |
|
|
#define CAN4RXIDR1_ID18 _CAN4RXIDR1.Bits.ID18
|
| 17538 |
|
|
#define CAN4RXIDR1_ID19 _CAN4RXIDR1.Bits.ID19
|
| 17539 |
|
|
#define CAN4RXIDR1_ID20 _CAN4RXIDR1.Bits.ID20
|
| 17540 |
|
|
#define CAN4RXIDR1_ID_15 _CAN4RXIDR1.MergedBits.grpID_15
|
| 17541 |
|
|
#define CAN4RXIDR1_ID_18 _CAN4RXIDR1.MergedBits.grpID_18
|
| 17542 |
|
|
#define CAN4RXIDR1_ID CAN4RXIDR1_ID_15
|
| 17543 |
|
|
|
| 17544 |
|
|
|
| 17545 |
|
|
/*** CAN4RXIDR2 - MSCAN4 Receive Identifier Register 2; 0x000002A2 ***/
|
| 17546 |
|
|
typedef union {
|
| 17547 |
|
|
byte Byte;
|
| 17548 |
|
|
struct {
|
| 17549 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 17550 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 17551 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 17552 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 17553 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 17554 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 17555 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 17556 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 17557 |
|
|
} Bits;
|
| 17558 |
|
|
struct {
|
| 17559 |
|
|
byte grpID_7 :8;
|
| 17560 |
|
|
} MergedBits;
|
| 17561 |
|
|
} CAN4RXIDR2STR;
|
| 17562 |
|
|
extern volatile CAN4RXIDR2STR _CAN4RXIDR2 @(REG_BASE + 0x000002A2);
|
| 17563 |
|
|
#define CAN4RXIDR2 _CAN4RXIDR2.Byte
|
| 17564 |
|
|
#define CAN4RXIDR2_ID7 _CAN4RXIDR2.Bits.ID7
|
| 17565 |
|
|
#define CAN4RXIDR2_ID8 _CAN4RXIDR2.Bits.ID8
|
| 17566 |
|
|
#define CAN4RXIDR2_ID9 _CAN4RXIDR2.Bits.ID9
|
| 17567 |
|
|
#define CAN4RXIDR2_ID10 _CAN4RXIDR2.Bits.ID10
|
| 17568 |
|
|
#define CAN4RXIDR2_ID11 _CAN4RXIDR2.Bits.ID11
|
| 17569 |
|
|
#define CAN4RXIDR2_ID12 _CAN4RXIDR2.Bits.ID12
|
| 17570 |
|
|
#define CAN4RXIDR2_ID13 _CAN4RXIDR2.Bits.ID13
|
| 17571 |
|
|
#define CAN4RXIDR2_ID14 _CAN4RXIDR2.Bits.ID14
|
| 17572 |
|
|
#define CAN4RXIDR2_ID_7 _CAN4RXIDR2.MergedBits.grpID_7
|
| 17573 |
|
|
#define CAN4RXIDR2_ID CAN4RXIDR2_ID_7
|
| 17574 |
|
|
|
| 17575 |
|
|
|
| 17576 |
|
|
/*** CAN4RXIDR3 - MSCAN4 Receive Identifier Register 3; 0x000002A3 ***/
|
| 17577 |
|
|
typedef union {
|
| 17578 |
|
|
byte Byte;
|
| 17579 |
|
|
struct {
|
| 17580 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 17581 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 17582 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 17583 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 17584 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 17585 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 17586 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 17587 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 17588 |
|
|
} Bits;
|
| 17589 |
|
|
struct {
|
| 17590 |
|
|
byte :1;
|
| 17591 |
|
|
byte grpID :7;
|
| 17592 |
|
|
} MergedBits;
|
| 17593 |
|
|
} CAN4RXIDR3STR;
|
| 17594 |
|
|
extern volatile CAN4RXIDR3STR _CAN4RXIDR3 @(REG_BASE + 0x000002A3);
|
| 17595 |
|
|
#define CAN4RXIDR3 _CAN4RXIDR3.Byte
|
| 17596 |
|
|
#define CAN4RXIDR3_RTR _CAN4RXIDR3.Bits.RTR
|
| 17597 |
|
|
#define CAN4RXIDR3_ID0 _CAN4RXIDR3.Bits.ID0
|
| 17598 |
|
|
#define CAN4RXIDR3_ID1 _CAN4RXIDR3.Bits.ID1
|
| 17599 |
|
|
#define CAN4RXIDR3_ID2 _CAN4RXIDR3.Bits.ID2
|
| 17600 |
|
|
#define CAN4RXIDR3_ID3 _CAN4RXIDR3.Bits.ID3
|
| 17601 |
|
|
#define CAN4RXIDR3_ID4 _CAN4RXIDR3.Bits.ID4
|
| 17602 |
|
|
#define CAN4RXIDR3_ID5 _CAN4RXIDR3.Bits.ID5
|
| 17603 |
|
|
#define CAN4RXIDR3_ID6 _CAN4RXIDR3.Bits.ID6
|
| 17604 |
|
|
#define CAN4RXIDR3_ID _CAN4RXIDR3.MergedBits.grpID
|
| 17605 |
|
|
|
| 17606 |
|
|
|
| 17607 |
|
|
/*** CAN4RXDSR0 - MSCAN4 Receive Data Segment Register 0; 0x000002A4 ***/
|
| 17608 |
|
|
typedef union {
|
| 17609 |
|
|
byte Byte;
|
| 17610 |
|
|
struct {
|
| 17611 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 17612 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 17613 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 17614 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 17615 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 17616 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 17617 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 17618 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 17619 |
|
|
} Bits;
|
| 17620 |
|
|
struct {
|
| 17621 |
|
|
byte grpDB :8;
|
| 17622 |
|
|
} MergedBits;
|
| 17623 |
|
|
} CAN4RXDSR0STR;
|
| 17624 |
|
|
extern volatile CAN4RXDSR0STR _CAN4RXDSR0 @(REG_BASE + 0x000002A4);
|
| 17625 |
|
|
#define CAN4RXDSR0 _CAN4RXDSR0.Byte
|
| 17626 |
|
|
#define CAN4RXDSR0_DB0 _CAN4RXDSR0.Bits.DB0
|
| 17627 |
|
|
#define CAN4RXDSR0_DB1 _CAN4RXDSR0.Bits.DB1
|
| 17628 |
|
|
#define CAN4RXDSR0_DB2 _CAN4RXDSR0.Bits.DB2
|
| 17629 |
|
|
#define CAN4RXDSR0_DB3 _CAN4RXDSR0.Bits.DB3
|
| 17630 |
|
|
#define CAN4RXDSR0_DB4 _CAN4RXDSR0.Bits.DB4
|
| 17631 |
|
|
#define CAN4RXDSR0_DB5 _CAN4RXDSR0.Bits.DB5
|
| 17632 |
|
|
#define CAN4RXDSR0_DB6 _CAN4RXDSR0.Bits.DB6
|
| 17633 |
|
|
#define CAN4RXDSR0_DB7 _CAN4RXDSR0.Bits.DB7
|
| 17634 |
|
|
#define CAN4RXDSR0_DB _CAN4RXDSR0.MergedBits.grpDB
|
| 17635 |
|
|
|
| 17636 |
|
|
|
| 17637 |
|
|
/*** CAN4RXDSR1 - MSCAN4 Receive Data Segment Register 1; 0x000002A5 ***/
|
| 17638 |
|
|
typedef union {
|
| 17639 |
|
|
byte Byte;
|
| 17640 |
|
|
struct {
|
| 17641 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 17642 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 17643 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 17644 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 17645 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 17646 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 17647 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 17648 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 17649 |
|
|
} Bits;
|
| 17650 |
|
|
struct {
|
| 17651 |
|
|
byte grpDB :8;
|
| 17652 |
|
|
} MergedBits;
|
| 17653 |
|
|
} CAN4RXDSR1STR;
|
| 17654 |
|
|
extern volatile CAN4RXDSR1STR _CAN4RXDSR1 @(REG_BASE + 0x000002A5);
|
| 17655 |
|
|
#define CAN4RXDSR1 _CAN4RXDSR1.Byte
|
| 17656 |
|
|
#define CAN4RXDSR1_DB0 _CAN4RXDSR1.Bits.DB0
|
| 17657 |
|
|
#define CAN4RXDSR1_DB1 _CAN4RXDSR1.Bits.DB1
|
| 17658 |
|
|
#define CAN4RXDSR1_DB2 _CAN4RXDSR1.Bits.DB2
|
| 17659 |
|
|
#define CAN4RXDSR1_DB3 _CAN4RXDSR1.Bits.DB3
|
| 17660 |
|
|
#define CAN4RXDSR1_DB4 _CAN4RXDSR1.Bits.DB4
|
| 17661 |
|
|
#define CAN4RXDSR1_DB5 _CAN4RXDSR1.Bits.DB5
|
| 17662 |
|
|
#define CAN4RXDSR1_DB6 _CAN4RXDSR1.Bits.DB6
|
| 17663 |
|
|
#define CAN4RXDSR1_DB7 _CAN4RXDSR1.Bits.DB7
|
| 17664 |
|
|
#define CAN4RXDSR1_DB _CAN4RXDSR1.MergedBits.grpDB
|
| 17665 |
|
|
|
| 17666 |
|
|
|
| 17667 |
|
|
/*** CAN4RXDSR2 - MSCAN4 Receive Data Segment Register 2; 0x000002A6 ***/
|
| 17668 |
|
|
typedef union {
|
| 17669 |
|
|
byte Byte;
|
| 17670 |
|
|
struct {
|
| 17671 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 17672 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 17673 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 17674 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 17675 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 17676 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 17677 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 17678 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 17679 |
|
|
} Bits;
|
| 17680 |
|
|
struct {
|
| 17681 |
|
|
byte grpDB :8;
|
| 17682 |
|
|
} MergedBits;
|
| 17683 |
|
|
} CAN4RXDSR2STR;
|
| 17684 |
|
|
extern volatile CAN4RXDSR2STR _CAN4RXDSR2 @(REG_BASE + 0x000002A6);
|
| 17685 |
|
|
#define CAN4RXDSR2 _CAN4RXDSR2.Byte
|
| 17686 |
|
|
#define CAN4RXDSR2_DB0 _CAN4RXDSR2.Bits.DB0
|
| 17687 |
|
|
#define CAN4RXDSR2_DB1 _CAN4RXDSR2.Bits.DB1
|
| 17688 |
|
|
#define CAN4RXDSR2_DB2 _CAN4RXDSR2.Bits.DB2
|
| 17689 |
|
|
#define CAN4RXDSR2_DB3 _CAN4RXDSR2.Bits.DB3
|
| 17690 |
|
|
#define CAN4RXDSR2_DB4 _CAN4RXDSR2.Bits.DB4
|
| 17691 |
|
|
#define CAN4RXDSR2_DB5 _CAN4RXDSR2.Bits.DB5
|
| 17692 |
|
|
#define CAN4RXDSR2_DB6 _CAN4RXDSR2.Bits.DB6
|
| 17693 |
|
|
#define CAN4RXDSR2_DB7 _CAN4RXDSR2.Bits.DB7
|
| 17694 |
|
|
#define CAN4RXDSR2_DB _CAN4RXDSR2.MergedBits.grpDB
|
| 17695 |
|
|
|
| 17696 |
|
|
|
| 17697 |
|
|
/*** CAN4RXDSR3 - MSCAN4 Receive Data Segment Register 3; 0x000002A7 ***/
|
| 17698 |
|
|
typedef union {
|
| 17699 |
|
|
byte Byte;
|
| 17700 |
|
|
struct {
|
| 17701 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 17702 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 17703 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 17704 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 17705 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 17706 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 17707 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 17708 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 17709 |
|
|
} Bits;
|
| 17710 |
|
|
struct {
|
| 17711 |
|
|
byte grpDB :8;
|
| 17712 |
|
|
} MergedBits;
|
| 17713 |
|
|
} CAN4RXDSR3STR;
|
| 17714 |
|
|
extern volatile CAN4RXDSR3STR _CAN4RXDSR3 @(REG_BASE + 0x000002A7);
|
| 17715 |
|
|
#define CAN4RXDSR3 _CAN4RXDSR3.Byte
|
| 17716 |
|
|
#define CAN4RXDSR3_DB0 _CAN4RXDSR3.Bits.DB0
|
| 17717 |
|
|
#define CAN4RXDSR3_DB1 _CAN4RXDSR3.Bits.DB1
|
| 17718 |
|
|
#define CAN4RXDSR3_DB2 _CAN4RXDSR3.Bits.DB2
|
| 17719 |
|
|
#define CAN4RXDSR3_DB3 _CAN4RXDSR3.Bits.DB3
|
| 17720 |
|
|
#define CAN4RXDSR3_DB4 _CAN4RXDSR3.Bits.DB4
|
| 17721 |
|
|
#define CAN4RXDSR3_DB5 _CAN4RXDSR3.Bits.DB5
|
| 17722 |
|
|
#define CAN4RXDSR3_DB6 _CAN4RXDSR3.Bits.DB6
|
| 17723 |
|
|
#define CAN4RXDSR3_DB7 _CAN4RXDSR3.Bits.DB7
|
| 17724 |
|
|
#define CAN4RXDSR3_DB _CAN4RXDSR3.MergedBits.grpDB
|
| 17725 |
|
|
|
| 17726 |
|
|
|
| 17727 |
|
|
/*** CAN4RXDSR4 - MSCAN4 Receive Data Segment Register 4; 0x000002A8 ***/
|
| 17728 |
|
|
typedef union {
|
| 17729 |
|
|
byte Byte;
|
| 17730 |
|
|
struct {
|
| 17731 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 17732 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 17733 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 17734 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 17735 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 17736 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 17737 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 17738 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 17739 |
|
|
} Bits;
|
| 17740 |
|
|
struct {
|
| 17741 |
|
|
byte grpDB :8;
|
| 17742 |
|
|
} MergedBits;
|
| 17743 |
|
|
} CAN4RXDSR4STR;
|
| 17744 |
|
|
extern volatile CAN4RXDSR4STR _CAN4RXDSR4 @(REG_BASE + 0x000002A8);
|
| 17745 |
|
|
#define CAN4RXDSR4 _CAN4RXDSR4.Byte
|
| 17746 |
|
|
#define CAN4RXDSR4_DB0 _CAN4RXDSR4.Bits.DB0
|
| 17747 |
|
|
#define CAN4RXDSR4_DB1 _CAN4RXDSR4.Bits.DB1
|
| 17748 |
|
|
#define CAN4RXDSR4_DB2 _CAN4RXDSR4.Bits.DB2
|
| 17749 |
|
|
#define CAN4RXDSR4_DB3 _CAN4RXDSR4.Bits.DB3
|
| 17750 |
|
|
#define CAN4RXDSR4_DB4 _CAN4RXDSR4.Bits.DB4
|
| 17751 |
|
|
#define CAN4RXDSR4_DB5 _CAN4RXDSR4.Bits.DB5
|
| 17752 |
|
|
#define CAN4RXDSR4_DB6 _CAN4RXDSR4.Bits.DB6
|
| 17753 |
|
|
#define CAN4RXDSR4_DB7 _CAN4RXDSR4.Bits.DB7
|
| 17754 |
|
|
#define CAN4RXDSR4_DB _CAN4RXDSR4.MergedBits.grpDB
|
| 17755 |
|
|
|
| 17756 |
|
|
|
| 17757 |
|
|
/*** CAN4RXDSR5 - MSCAN4 Receive Data Segment Register 5; 0x000002A9 ***/
|
| 17758 |
|
|
typedef union {
|
| 17759 |
|
|
byte Byte;
|
| 17760 |
|
|
struct {
|
| 17761 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 17762 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 17763 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 17764 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 17765 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 17766 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 17767 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 17768 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 17769 |
|
|
} Bits;
|
| 17770 |
|
|
struct {
|
| 17771 |
|
|
byte grpDB :8;
|
| 17772 |
|
|
} MergedBits;
|
| 17773 |
|
|
} CAN4RXDSR5STR;
|
| 17774 |
|
|
extern volatile CAN4RXDSR5STR _CAN4RXDSR5 @(REG_BASE + 0x000002A9);
|
| 17775 |
|
|
#define CAN4RXDSR5 _CAN4RXDSR5.Byte
|
| 17776 |
|
|
#define CAN4RXDSR5_DB0 _CAN4RXDSR5.Bits.DB0
|
| 17777 |
|
|
#define CAN4RXDSR5_DB1 _CAN4RXDSR5.Bits.DB1
|
| 17778 |
|
|
#define CAN4RXDSR5_DB2 _CAN4RXDSR5.Bits.DB2
|
| 17779 |
|
|
#define CAN4RXDSR5_DB3 _CAN4RXDSR5.Bits.DB3
|
| 17780 |
|
|
#define CAN4RXDSR5_DB4 _CAN4RXDSR5.Bits.DB4
|
| 17781 |
|
|
#define CAN4RXDSR5_DB5 _CAN4RXDSR5.Bits.DB5
|
| 17782 |
|
|
#define CAN4RXDSR5_DB6 _CAN4RXDSR5.Bits.DB6
|
| 17783 |
|
|
#define CAN4RXDSR5_DB7 _CAN4RXDSR5.Bits.DB7
|
| 17784 |
|
|
#define CAN4RXDSR5_DB _CAN4RXDSR5.MergedBits.grpDB
|
| 17785 |
|
|
|
| 17786 |
|
|
|
| 17787 |
|
|
/*** CAN4RXDSR6 - MSCAN4 Receive Data Segment Register 6; 0x000002AA ***/
|
| 17788 |
|
|
typedef union {
|
| 17789 |
|
|
byte Byte;
|
| 17790 |
|
|
struct {
|
| 17791 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 17792 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 17793 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 17794 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 17795 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 17796 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 17797 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 17798 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 17799 |
|
|
} Bits;
|
| 17800 |
|
|
struct {
|
| 17801 |
|
|
byte grpDB :8;
|
| 17802 |
|
|
} MergedBits;
|
| 17803 |
|
|
} CAN4RXDSR6STR;
|
| 17804 |
|
|
extern volatile CAN4RXDSR6STR _CAN4RXDSR6 @(REG_BASE + 0x000002AA);
|
| 17805 |
|
|
#define CAN4RXDSR6 _CAN4RXDSR6.Byte
|
| 17806 |
|
|
#define CAN4RXDSR6_DB0 _CAN4RXDSR6.Bits.DB0
|
| 17807 |
|
|
#define CAN4RXDSR6_DB1 _CAN4RXDSR6.Bits.DB1
|
| 17808 |
|
|
#define CAN4RXDSR6_DB2 _CAN4RXDSR6.Bits.DB2
|
| 17809 |
|
|
#define CAN4RXDSR6_DB3 _CAN4RXDSR6.Bits.DB3
|
| 17810 |
|
|
#define CAN4RXDSR6_DB4 _CAN4RXDSR6.Bits.DB4
|
| 17811 |
|
|
#define CAN4RXDSR6_DB5 _CAN4RXDSR6.Bits.DB5
|
| 17812 |
|
|
#define CAN4RXDSR6_DB6 _CAN4RXDSR6.Bits.DB6
|
| 17813 |
|
|
#define CAN4RXDSR6_DB7 _CAN4RXDSR6.Bits.DB7
|
| 17814 |
|
|
#define CAN4RXDSR6_DB _CAN4RXDSR6.MergedBits.grpDB
|
| 17815 |
|
|
|
| 17816 |
|
|
|
| 17817 |
|
|
/*** CAN4RXDSR7 - MSCAN4 Receive Data Segment Register 7; 0x000002AB ***/
|
| 17818 |
|
|
typedef union {
|
| 17819 |
|
|
byte Byte;
|
| 17820 |
|
|
struct {
|
| 17821 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 17822 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 17823 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 17824 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 17825 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 17826 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 17827 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 17828 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 17829 |
|
|
} Bits;
|
| 17830 |
|
|
struct {
|
| 17831 |
|
|
byte grpDB :8;
|
| 17832 |
|
|
} MergedBits;
|
| 17833 |
|
|
} CAN4RXDSR7STR;
|
| 17834 |
|
|
extern volatile CAN4RXDSR7STR _CAN4RXDSR7 @(REG_BASE + 0x000002AB);
|
| 17835 |
|
|
#define CAN4RXDSR7 _CAN4RXDSR7.Byte
|
| 17836 |
|
|
#define CAN4RXDSR7_DB0 _CAN4RXDSR7.Bits.DB0
|
| 17837 |
|
|
#define CAN4RXDSR7_DB1 _CAN4RXDSR7.Bits.DB1
|
| 17838 |
|
|
#define CAN4RXDSR7_DB2 _CAN4RXDSR7.Bits.DB2
|
| 17839 |
|
|
#define CAN4RXDSR7_DB3 _CAN4RXDSR7.Bits.DB3
|
| 17840 |
|
|
#define CAN4RXDSR7_DB4 _CAN4RXDSR7.Bits.DB4
|
| 17841 |
|
|
#define CAN4RXDSR7_DB5 _CAN4RXDSR7.Bits.DB5
|
| 17842 |
|
|
#define CAN4RXDSR7_DB6 _CAN4RXDSR7.Bits.DB6
|
| 17843 |
|
|
#define CAN4RXDSR7_DB7 _CAN4RXDSR7.Bits.DB7
|
| 17844 |
|
|
#define CAN4RXDSR7_DB _CAN4RXDSR7.MergedBits.grpDB
|
| 17845 |
|
|
|
| 17846 |
|
|
|
| 17847 |
|
|
/*** CAN4RXDLR - MSCAN4 Receive Data Length Register; 0x000002AC ***/
|
| 17848 |
|
|
typedef union {
|
| 17849 |
|
|
byte Byte;
|
| 17850 |
|
|
struct {
|
| 17851 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 17852 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 17853 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 17854 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 17855 |
|
|
byte :1;
|
| 17856 |
|
|
byte :1;
|
| 17857 |
|
|
byte :1;
|
| 17858 |
|
|
byte :1;
|
| 17859 |
|
|
} Bits;
|
| 17860 |
|
|
struct {
|
| 17861 |
|
|
byte grpDLC :4;
|
| 17862 |
|
|
byte :1;
|
| 17863 |
|
|
byte :1;
|
| 17864 |
|
|
byte :1;
|
| 17865 |
|
|
byte :1;
|
| 17866 |
|
|
} MergedBits;
|
| 17867 |
|
|
} CAN4RXDLRSTR;
|
| 17868 |
|
|
extern volatile CAN4RXDLRSTR _CAN4RXDLR @(REG_BASE + 0x000002AC);
|
| 17869 |
|
|
#define CAN4RXDLR _CAN4RXDLR.Byte
|
| 17870 |
|
|
#define CAN4RXDLR_DLC0 _CAN4RXDLR.Bits.DLC0
|
| 17871 |
|
|
#define CAN4RXDLR_DLC1 _CAN4RXDLR.Bits.DLC1
|
| 17872 |
|
|
#define CAN4RXDLR_DLC2 _CAN4RXDLR.Bits.DLC2
|
| 17873 |
|
|
#define CAN4RXDLR_DLC3 _CAN4RXDLR.Bits.DLC3
|
| 17874 |
|
|
#define CAN4RXDLR_DLC _CAN4RXDLR.MergedBits.grpDLC
|
| 17875 |
|
|
|
| 17876 |
|
|
|
| 17877 |
|
|
/*** CAN4TXIDR0 - MSCAN4 Transmit Identifier Register 0; 0x000002B0 ***/
|
| 17878 |
|
|
typedef union {
|
| 17879 |
|
|
byte Byte;
|
| 17880 |
|
|
struct {
|
| 17881 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 17882 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 17883 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 17884 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 17885 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 17886 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 17887 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 17888 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 17889 |
|
|
} Bits;
|
| 17890 |
|
|
struct {
|
| 17891 |
|
|
byte grpID_21 :8;
|
| 17892 |
|
|
} MergedBits;
|
| 17893 |
|
|
} CAN4TXIDR0STR;
|
| 17894 |
|
|
extern volatile CAN4TXIDR0STR _CAN4TXIDR0 @(REG_BASE + 0x000002B0);
|
| 17895 |
|
|
#define CAN4TXIDR0 _CAN4TXIDR0.Byte
|
| 17896 |
|
|
#define CAN4TXIDR0_ID21 _CAN4TXIDR0.Bits.ID21
|
| 17897 |
|
|
#define CAN4TXIDR0_ID22 _CAN4TXIDR0.Bits.ID22
|
| 17898 |
|
|
#define CAN4TXIDR0_ID23 _CAN4TXIDR0.Bits.ID23
|
| 17899 |
|
|
#define CAN4TXIDR0_ID24 _CAN4TXIDR0.Bits.ID24
|
| 17900 |
|
|
#define CAN4TXIDR0_ID25 _CAN4TXIDR0.Bits.ID25
|
| 17901 |
|
|
#define CAN4TXIDR0_ID26 _CAN4TXIDR0.Bits.ID26
|
| 17902 |
|
|
#define CAN4TXIDR0_ID27 _CAN4TXIDR0.Bits.ID27
|
| 17903 |
|
|
#define CAN4TXIDR0_ID28 _CAN4TXIDR0.Bits.ID28
|
| 17904 |
|
|
#define CAN4TXIDR0_ID_21 _CAN4TXIDR0.MergedBits.grpID_21
|
| 17905 |
|
|
#define CAN4TXIDR0_ID CAN4TXIDR0_ID_21
|
| 17906 |
|
|
|
| 17907 |
|
|
|
| 17908 |
|
|
/*** CAN4TXIDR1 - MSCAN4 Transmit Identifier Register 1; 0x000002B1 ***/
|
| 17909 |
|
|
typedef union {
|
| 17910 |
|
|
byte Byte;
|
| 17911 |
|
|
struct {
|
| 17912 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 17913 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 17914 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 17915 |
|
|
byte IDE :1; /* ID Extended */
|
| 17916 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 17917 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 17918 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 17919 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 17920 |
|
|
} Bits;
|
| 17921 |
|
|
struct {
|
| 17922 |
|
|
byte grpID_15 :3;
|
| 17923 |
|
|
byte :1;
|
| 17924 |
|
|
byte :1;
|
| 17925 |
|
|
byte grpID_18 :3;
|
| 17926 |
|
|
} MergedBits;
|
| 17927 |
|
|
} CAN4TXIDR1STR;
|
| 17928 |
|
|
extern volatile CAN4TXIDR1STR _CAN4TXIDR1 @(REG_BASE + 0x000002B1);
|
| 17929 |
|
|
#define CAN4TXIDR1 _CAN4TXIDR1.Byte
|
| 17930 |
|
|
#define CAN4TXIDR1_ID15 _CAN4TXIDR1.Bits.ID15
|
| 17931 |
|
|
#define CAN4TXIDR1_ID16 _CAN4TXIDR1.Bits.ID16
|
| 17932 |
|
|
#define CAN4TXIDR1_ID17 _CAN4TXIDR1.Bits.ID17
|
| 17933 |
|
|
#define CAN4TXIDR1_IDE _CAN4TXIDR1.Bits.IDE
|
| 17934 |
|
|
#define CAN4TXIDR1_SRR _CAN4TXIDR1.Bits.SRR
|
| 17935 |
|
|
#define CAN4TXIDR1_ID18 _CAN4TXIDR1.Bits.ID18
|
| 17936 |
|
|
#define CAN4TXIDR1_ID19 _CAN4TXIDR1.Bits.ID19
|
| 17937 |
|
|
#define CAN4TXIDR1_ID20 _CAN4TXIDR1.Bits.ID20
|
| 17938 |
|
|
#define CAN4TXIDR1_ID_15 _CAN4TXIDR1.MergedBits.grpID_15
|
| 17939 |
|
|
#define CAN4TXIDR1_ID_18 _CAN4TXIDR1.MergedBits.grpID_18
|
| 17940 |
|
|
#define CAN4TXIDR1_ID CAN4TXIDR1_ID_15
|
| 17941 |
|
|
|
| 17942 |
|
|
|
| 17943 |
|
|
/*** CAN4TXIDR2 - MSCAN4 Transmit Identifier Register 2; 0x000002B2 ***/
|
| 17944 |
|
|
typedef union {
|
| 17945 |
|
|
byte Byte;
|
| 17946 |
|
|
struct {
|
| 17947 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 17948 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 17949 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 17950 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 17951 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 17952 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 17953 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 17954 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 17955 |
|
|
} Bits;
|
| 17956 |
|
|
struct {
|
| 17957 |
|
|
byte grpID_7 :8;
|
| 17958 |
|
|
} MergedBits;
|
| 17959 |
|
|
} CAN4TXIDR2STR;
|
| 17960 |
|
|
extern volatile CAN4TXIDR2STR _CAN4TXIDR2 @(REG_BASE + 0x000002B2);
|
| 17961 |
|
|
#define CAN4TXIDR2 _CAN4TXIDR2.Byte
|
| 17962 |
|
|
#define CAN4TXIDR2_ID7 _CAN4TXIDR2.Bits.ID7
|
| 17963 |
|
|
#define CAN4TXIDR2_ID8 _CAN4TXIDR2.Bits.ID8
|
| 17964 |
|
|
#define CAN4TXIDR2_ID9 _CAN4TXIDR2.Bits.ID9
|
| 17965 |
|
|
#define CAN4TXIDR2_ID10 _CAN4TXIDR2.Bits.ID10
|
| 17966 |
|
|
#define CAN4TXIDR2_ID11 _CAN4TXIDR2.Bits.ID11
|
| 17967 |
|
|
#define CAN4TXIDR2_ID12 _CAN4TXIDR2.Bits.ID12
|
| 17968 |
|
|
#define CAN4TXIDR2_ID13 _CAN4TXIDR2.Bits.ID13
|
| 17969 |
|
|
#define CAN4TXIDR2_ID14 _CAN4TXIDR2.Bits.ID14
|
| 17970 |
|
|
#define CAN4TXIDR2_ID_7 _CAN4TXIDR2.MergedBits.grpID_7
|
| 17971 |
|
|
#define CAN4TXIDR2_ID CAN4TXIDR2_ID_7
|
| 17972 |
|
|
|
| 17973 |
|
|
|
| 17974 |
|
|
/*** CAN4TXIDR3 - MSCAN4 Transmit Identifier Register 3; 0x000002B3 ***/
|
| 17975 |
|
|
typedef union {
|
| 17976 |
|
|
byte Byte;
|
| 17977 |
|
|
struct {
|
| 17978 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 17979 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 17980 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 17981 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 17982 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 17983 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 17984 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 17985 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 17986 |
|
|
} Bits;
|
| 17987 |
|
|
struct {
|
| 17988 |
|
|
byte :1;
|
| 17989 |
|
|
byte grpID :7;
|
| 17990 |
|
|
} MergedBits;
|
| 17991 |
|
|
} CAN4TXIDR3STR;
|
| 17992 |
|
|
extern volatile CAN4TXIDR3STR _CAN4TXIDR3 @(REG_BASE + 0x000002B3);
|
| 17993 |
|
|
#define CAN4TXIDR3 _CAN4TXIDR3.Byte
|
| 17994 |
|
|
#define CAN4TXIDR3_RTR _CAN4TXIDR3.Bits.RTR
|
| 17995 |
|
|
#define CAN4TXIDR3_ID0 _CAN4TXIDR3.Bits.ID0
|
| 17996 |
|
|
#define CAN4TXIDR3_ID1 _CAN4TXIDR3.Bits.ID1
|
| 17997 |
|
|
#define CAN4TXIDR3_ID2 _CAN4TXIDR3.Bits.ID2
|
| 17998 |
|
|
#define CAN4TXIDR3_ID3 _CAN4TXIDR3.Bits.ID3
|
| 17999 |
|
|
#define CAN4TXIDR3_ID4 _CAN4TXIDR3.Bits.ID4
|
| 18000 |
|
|
#define CAN4TXIDR3_ID5 _CAN4TXIDR3.Bits.ID5
|
| 18001 |
|
|
#define CAN4TXIDR3_ID6 _CAN4TXIDR3.Bits.ID6
|
| 18002 |
|
|
#define CAN4TXIDR3_ID _CAN4TXIDR3.MergedBits.grpID
|
| 18003 |
|
|
|
| 18004 |
|
|
|
| 18005 |
|
|
/*** CAN4TXDSR0 - MSCAN4 Transmit Data Segment Register 0; 0x000002B4 ***/
|
| 18006 |
|
|
typedef union {
|
| 18007 |
|
|
byte Byte;
|
| 18008 |
|
|
struct {
|
| 18009 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 18010 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 18011 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 18012 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 18013 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 18014 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 18015 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 18016 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 18017 |
|
|
} Bits;
|
| 18018 |
|
|
struct {
|
| 18019 |
|
|
byte grpDB :8;
|
| 18020 |
|
|
} MergedBits;
|
| 18021 |
|
|
} CAN4TXDSR0STR;
|
| 18022 |
|
|
extern volatile CAN4TXDSR0STR _CAN4TXDSR0 @(REG_BASE + 0x000002B4);
|
| 18023 |
|
|
#define CAN4TXDSR0 _CAN4TXDSR0.Byte
|
| 18024 |
|
|
#define CAN4TXDSR0_DB0 _CAN4TXDSR0.Bits.DB0
|
| 18025 |
|
|
#define CAN4TXDSR0_DB1 _CAN4TXDSR0.Bits.DB1
|
| 18026 |
|
|
#define CAN4TXDSR0_DB2 _CAN4TXDSR0.Bits.DB2
|
| 18027 |
|
|
#define CAN4TXDSR0_DB3 _CAN4TXDSR0.Bits.DB3
|
| 18028 |
|
|
#define CAN4TXDSR0_DB4 _CAN4TXDSR0.Bits.DB4
|
| 18029 |
|
|
#define CAN4TXDSR0_DB5 _CAN4TXDSR0.Bits.DB5
|
| 18030 |
|
|
#define CAN4TXDSR0_DB6 _CAN4TXDSR0.Bits.DB6
|
| 18031 |
|
|
#define CAN4TXDSR0_DB7 _CAN4TXDSR0.Bits.DB7
|
| 18032 |
|
|
#define CAN4TXDSR0_DB _CAN4TXDSR0.MergedBits.grpDB
|
| 18033 |
|
|
|
| 18034 |
|
|
|
| 18035 |
|
|
/*** CAN4TXDSR1 - MSCAN4 Transmit Data Segment Register 1; 0x000002B5 ***/
|
| 18036 |
|
|
typedef union {
|
| 18037 |
|
|
byte Byte;
|
| 18038 |
|
|
struct {
|
| 18039 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 18040 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 18041 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 18042 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 18043 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 18044 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 18045 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 18046 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 18047 |
|
|
} Bits;
|
| 18048 |
|
|
struct {
|
| 18049 |
|
|
byte grpDB :8;
|
| 18050 |
|
|
} MergedBits;
|
| 18051 |
|
|
} CAN4TXDSR1STR;
|
| 18052 |
|
|
extern volatile CAN4TXDSR1STR _CAN4TXDSR1 @(REG_BASE + 0x000002B5);
|
| 18053 |
|
|
#define CAN4TXDSR1 _CAN4TXDSR1.Byte
|
| 18054 |
|
|
#define CAN4TXDSR1_DB0 _CAN4TXDSR1.Bits.DB0
|
| 18055 |
|
|
#define CAN4TXDSR1_DB1 _CAN4TXDSR1.Bits.DB1
|
| 18056 |
|
|
#define CAN4TXDSR1_DB2 _CAN4TXDSR1.Bits.DB2
|
| 18057 |
|
|
#define CAN4TXDSR1_DB3 _CAN4TXDSR1.Bits.DB3
|
| 18058 |
|
|
#define CAN4TXDSR1_DB4 _CAN4TXDSR1.Bits.DB4
|
| 18059 |
|
|
#define CAN4TXDSR1_DB5 _CAN4TXDSR1.Bits.DB5
|
| 18060 |
|
|
#define CAN4TXDSR1_DB6 _CAN4TXDSR1.Bits.DB6
|
| 18061 |
|
|
#define CAN4TXDSR1_DB7 _CAN4TXDSR1.Bits.DB7
|
| 18062 |
|
|
#define CAN4TXDSR1_DB _CAN4TXDSR1.MergedBits.grpDB
|
| 18063 |
|
|
|
| 18064 |
|
|
|
| 18065 |
|
|
/*** CAN4TXDSR2 - MSCAN4 Transmit Data Segment Register 2; 0x000002B6 ***/
|
| 18066 |
|
|
typedef union {
|
| 18067 |
|
|
byte Byte;
|
| 18068 |
|
|
struct {
|
| 18069 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 18070 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 18071 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 18072 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 18073 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 18074 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 18075 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 18076 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 18077 |
|
|
} Bits;
|
| 18078 |
|
|
struct {
|
| 18079 |
|
|
byte grpDB :8;
|
| 18080 |
|
|
} MergedBits;
|
| 18081 |
|
|
} CAN4TXDSR2STR;
|
| 18082 |
|
|
extern volatile CAN4TXDSR2STR _CAN4TXDSR2 @(REG_BASE + 0x000002B6);
|
| 18083 |
|
|
#define CAN4TXDSR2 _CAN4TXDSR2.Byte
|
| 18084 |
|
|
#define CAN4TXDSR2_DB0 _CAN4TXDSR2.Bits.DB0
|
| 18085 |
|
|
#define CAN4TXDSR2_DB1 _CAN4TXDSR2.Bits.DB1
|
| 18086 |
|
|
#define CAN4TXDSR2_DB2 _CAN4TXDSR2.Bits.DB2
|
| 18087 |
|
|
#define CAN4TXDSR2_DB3 _CAN4TXDSR2.Bits.DB3
|
| 18088 |
|
|
#define CAN4TXDSR2_DB4 _CAN4TXDSR2.Bits.DB4
|
| 18089 |
|
|
#define CAN4TXDSR2_DB5 _CAN4TXDSR2.Bits.DB5
|
| 18090 |
|
|
#define CAN4TXDSR2_DB6 _CAN4TXDSR2.Bits.DB6
|
| 18091 |
|
|
#define CAN4TXDSR2_DB7 _CAN4TXDSR2.Bits.DB7
|
| 18092 |
|
|
#define CAN4TXDSR2_DB _CAN4TXDSR2.MergedBits.grpDB
|
| 18093 |
|
|
|
| 18094 |
|
|
|
| 18095 |
|
|
/*** CAN4TXDSR3 - MSCAN4 Transmit Data Segment Register 3; 0x000002B7 ***/
|
| 18096 |
|
|
typedef union {
|
| 18097 |
|
|
byte Byte;
|
| 18098 |
|
|
struct {
|
| 18099 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 18100 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 18101 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 18102 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 18103 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 18104 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 18105 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 18106 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 18107 |
|
|
} Bits;
|
| 18108 |
|
|
struct {
|
| 18109 |
|
|
byte grpDB :8;
|
| 18110 |
|
|
} MergedBits;
|
| 18111 |
|
|
} CAN4TXDSR3STR;
|
| 18112 |
|
|
extern volatile CAN4TXDSR3STR _CAN4TXDSR3 @(REG_BASE + 0x000002B7);
|
| 18113 |
|
|
#define CAN4TXDSR3 _CAN4TXDSR3.Byte
|
| 18114 |
|
|
#define CAN4TXDSR3_DB0 _CAN4TXDSR3.Bits.DB0
|
| 18115 |
|
|
#define CAN4TXDSR3_DB1 _CAN4TXDSR3.Bits.DB1
|
| 18116 |
|
|
#define CAN4TXDSR3_DB2 _CAN4TXDSR3.Bits.DB2
|
| 18117 |
|
|
#define CAN4TXDSR3_DB3 _CAN4TXDSR3.Bits.DB3
|
| 18118 |
|
|
#define CAN4TXDSR3_DB4 _CAN4TXDSR3.Bits.DB4
|
| 18119 |
|
|
#define CAN4TXDSR3_DB5 _CAN4TXDSR3.Bits.DB5
|
| 18120 |
|
|
#define CAN4TXDSR3_DB6 _CAN4TXDSR3.Bits.DB6
|
| 18121 |
|
|
#define CAN4TXDSR3_DB7 _CAN4TXDSR3.Bits.DB7
|
| 18122 |
|
|
#define CAN4TXDSR3_DB _CAN4TXDSR3.MergedBits.grpDB
|
| 18123 |
|
|
|
| 18124 |
|
|
|
| 18125 |
|
|
/*** CAN4TXDSR4 - MSCAN4 Transmit Data Segment Register 4; 0x000002B8 ***/
|
| 18126 |
|
|
typedef union {
|
| 18127 |
|
|
byte Byte;
|
| 18128 |
|
|
struct {
|
| 18129 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 18130 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 18131 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 18132 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 18133 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 18134 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 18135 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 18136 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 18137 |
|
|
} Bits;
|
| 18138 |
|
|
struct {
|
| 18139 |
|
|
byte grpDB :8;
|
| 18140 |
|
|
} MergedBits;
|
| 18141 |
|
|
} CAN4TXDSR4STR;
|
| 18142 |
|
|
extern volatile CAN4TXDSR4STR _CAN4TXDSR4 @(REG_BASE + 0x000002B8);
|
| 18143 |
|
|
#define CAN4TXDSR4 _CAN4TXDSR4.Byte
|
| 18144 |
|
|
#define CAN4TXDSR4_DB0 _CAN4TXDSR4.Bits.DB0
|
| 18145 |
|
|
#define CAN4TXDSR4_DB1 _CAN4TXDSR4.Bits.DB1
|
| 18146 |
|
|
#define CAN4TXDSR4_DB2 _CAN4TXDSR4.Bits.DB2
|
| 18147 |
|
|
#define CAN4TXDSR4_DB3 _CAN4TXDSR4.Bits.DB3
|
| 18148 |
|
|
#define CAN4TXDSR4_DB4 _CAN4TXDSR4.Bits.DB4
|
| 18149 |
|
|
#define CAN4TXDSR4_DB5 _CAN4TXDSR4.Bits.DB5
|
| 18150 |
|
|
#define CAN4TXDSR4_DB6 _CAN4TXDSR4.Bits.DB6
|
| 18151 |
|
|
#define CAN4TXDSR4_DB7 _CAN4TXDSR4.Bits.DB7
|
| 18152 |
|
|
#define CAN4TXDSR4_DB _CAN4TXDSR4.MergedBits.grpDB
|
| 18153 |
|
|
|
| 18154 |
|
|
|
| 18155 |
|
|
/*** CAN4TXDSR5 - MSCAN4 Transmit Data Segment Register 5; 0x000002B9 ***/
|
| 18156 |
|
|
typedef union {
|
| 18157 |
|
|
byte Byte;
|
| 18158 |
|
|
struct {
|
| 18159 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 18160 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 18161 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 18162 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 18163 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 18164 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 18165 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 18166 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 18167 |
|
|
} Bits;
|
| 18168 |
|
|
struct {
|
| 18169 |
|
|
byte grpDB :8;
|
| 18170 |
|
|
} MergedBits;
|
| 18171 |
|
|
} CAN4TXDSR5STR;
|
| 18172 |
|
|
extern volatile CAN4TXDSR5STR _CAN4TXDSR5 @(REG_BASE + 0x000002B9);
|
| 18173 |
|
|
#define CAN4TXDSR5 _CAN4TXDSR5.Byte
|
| 18174 |
|
|
#define CAN4TXDSR5_DB0 _CAN4TXDSR5.Bits.DB0
|
| 18175 |
|
|
#define CAN4TXDSR5_DB1 _CAN4TXDSR5.Bits.DB1
|
| 18176 |
|
|
#define CAN4TXDSR5_DB2 _CAN4TXDSR5.Bits.DB2
|
| 18177 |
|
|
#define CAN4TXDSR5_DB3 _CAN4TXDSR5.Bits.DB3
|
| 18178 |
|
|
#define CAN4TXDSR5_DB4 _CAN4TXDSR5.Bits.DB4
|
| 18179 |
|
|
#define CAN4TXDSR5_DB5 _CAN4TXDSR5.Bits.DB5
|
| 18180 |
|
|
#define CAN4TXDSR5_DB6 _CAN4TXDSR5.Bits.DB6
|
| 18181 |
|
|
#define CAN4TXDSR5_DB7 _CAN4TXDSR5.Bits.DB7
|
| 18182 |
|
|
#define CAN4TXDSR5_DB _CAN4TXDSR5.MergedBits.grpDB
|
| 18183 |
|
|
|
| 18184 |
|
|
|
| 18185 |
|
|
/*** CAN4TXDSR6 - MSCAN4 Transmit Data Segment Register 6; 0x000002BA ***/
|
| 18186 |
|
|
typedef union {
|
| 18187 |
|
|
byte Byte;
|
| 18188 |
|
|
struct {
|
| 18189 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 18190 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 18191 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 18192 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 18193 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 18194 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 18195 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 18196 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 18197 |
|
|
} Bits;
|
| 18198 |
|
|
struct {
|
| 18199 |
|
|
byte grpDB :8;
|
| 18200 |
|
|
} MergedBits;
|
| 18201 |
|
|
} CAN4TXDSR6STR;
|
| 18202 |
|
|
extern volatile CAN4TXDSR6STR _CAN4TXDSR6 @(REG_BASE + 0x000002BA);
|
| 18203 |
|
|
#define CAN4TXDSR6 _CAN4TXDSR6.Byte
|
| 18204 |
|
|
#define CAN4TXDSR6_DB0 _CAN4TXDSR6.Bits.DB0
|
| 18205 |
|
|
#define CAN4TXDSR6_DB1 _CAN4TXDSR6.Bits.DB1
|
| 18206 |
|
|
#define CAN4TXDSR6_DB2 _CAN4TXDSR6.Bits.DB2
|
| 18207 |
|
|
#define CAN4TXDSR6_DB3 _CAN4TXDSR6.Bits.DB3
|
| 18208 |
|
|
#define CAN4TXDSR6_DB4 _CAN4TXDSR6.Bits.DB4
|
| 18209 |
|
|
#define CAN4TXDSR6_DB5 _CAN4TXDSR6.Bits.DB5
|
| 18210 |
|
|
#define CAN4TXDSR6_DB6 _CAN4TXDSR6.Bits.DB6
|
| 18211 |
|
|
#define CAN4TXDSR6_DB7 _CAN4TXDSR6.Bits.DB7
|
| 18212 |
|
|
#define CAN4TXDSR6_DB _CAN4TXDSR6.MergedBits.grpDB
|
| 18213 |
|
|
|
| 18214 |
|
|
|
| 18215 |
|
|
/*** CAN4TXDSR7 - MSCAN4 Transmit Data Segment Register 7; 0x000002BB ***/
|
| 18216 |
|
|
typedef union {
|
| 18217 |
|
|
byte Byte;
|
| 18218 |
|
|
struct {
|
| 18219 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 18220 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 18221 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 18222 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 18223 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 18224 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 18225 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 18226 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 18227 |
|
|
} Bits;
|
| 18228 |
|
|
struct {
|
| 18229 |
|
|
byte grpDB :8;
|
| 18230 |
|
|
} MergedBits;
|
| 18231 |
|
|
} CAN4TXDSR7STR;
|
| 18232 |
|
|
extern volatile CAN4TXDSR7STR _CAN4TXDSR7 @(REG_BASE + 0x000002BB);
|
| 18233 |
|
|
#define CAN4TXDSR7 _CAN4TXDSR7.Byte
|
| 18234 |
|
|
#define CAN4TXDSR7_DB0 _CAN4TXDSR7.Bits.DB0
|
| 18235 |
|
|
#define CAN4TXDSR7_DB1 _CAN4TXDSR7.Bits.DB1
|
| 18236 |
|
|
#define CAN4TXDSR7_DB2 _CAN4TXDSR7.Bits.DB2
|
| 18237 |
|
|
#define CAN4TXDSR7_DB3 _CAN4TXDSR7.Bits.DB3
|
| 18238 |
|
|
#define CAN4TXDSR7_DB4 _CAN4TXDSR7.Bits.DB4
|
| 18239 |
|
|
#define CAN4TXDSR7_DB5 _CAN4TXDSR7.Bits.DB5
|
| 18240 |
|
|
#define CAN4TXDSR7_DB6 _CAN4TXDSR7.Bits.DB6
|
| 18241 |
|
|
#define CAN4TXDSR7_DB7 _CAN4TXDSR7.Bits.DB7
|
| 18242 |
|
|
#define CAN4TXDSR7_DB _CAN4TXDSR7.MergedBits.grpDB
|
| 18243 |
|
|
|
| 18244 |
|
|
|
| 18245 |
|
|
/*** CAN4TXDLR - MSCAN4 Transmit Data Length Register; 0x000002BC ***/
|
| 18246 |
|
|
typedef union {
|
| 18247 |
|
|
byte Byte;
|
| 18248 |
|
|
struct {
|
| 18249 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 18250 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 18251 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 18252 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 18253 |
|
|
byte :1;
|
| 18254 |
|
|
byte :1;
|
| 18255 |
|
|
byte :1;
|
| 18256 |
|
|
byte :1;
|
| 18257 |
|
|
} Bits;
|
| 18258 |
|
|
struct {
|
| 18259 |
|
|
byte grpDLC :4;
|
| 18260 |
|
|
byte :1;
|
| 18261 |
|
|
byte :1;
|
| 18262 |
|
|
byte :1;
|
| 18263 |
|
|
byte :1;
|
| 18264 |
|
|
} MergedBits;
|
| 18265 |
|
|
} CAN4TXDLRSTR;
|
| 18266 |
|
|
extern volatile CAN4TXDLRSTR _CAN4TXDLR @(REG_BASE + 0x000002BC);
|
| 18267 |
|
|
#define CAN4TXDLR _CAN4TXDLR.Byte
|
| 18268 |
|
|
#define CAN4TXDLR_DLC0 _CAN4TXDLR.Bits.DLC0
|
| 18269 |
|
|
#define CAN4TXDLR_DLC1 _CAN4TXDLR.Bits.DLC1
|
| 18270 |
|
|
#define CAN4TXDLR_DLC2 _CAN4TXDLR.Bits.DLC2
|
| 18271 |
|
|
#define CAN4TXDLR_DLC3 _CAN4TXDLR.Bits.DLC3
|
| 18272 |
|
|
#define CAN4TXDLR_DLC _CAN4TXDLR.MergedBits.grpDLC
|
| 18273 |
|
|
|
| 18274 |
|
|
|
| 18275 |
|
|
/*** CAN4TXTBPR - MSCAN4 Transmit Transmit Buffer Priority; 0x000002BF ***/
|
| 18276 |
|
|
typedef union {
|
| 18277 |
|
|
byte Byte;
|
| 18278 |
|
|
struct {
|
| 18279 |
|
|
byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
|
| 18280 |
|
|
byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
|
| 18281 |
|
|
byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
|
| 18282 |
|
|
byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
|
| 18283 |
|
|
byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
|
| 18284 |
|
|
byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
|
| 18285 |
|
|
byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
|
| 18286 |
|
|
byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
|
| 18287 |
|
|
} Bits;
|
| 18288 |
|
|
struct {
|
| 18289 |
|
|
byte grpPRIO :8;
|
| 18290 |
|
|
} MergedBits;
|
| 18291 |
|
|
} CAN4TXTBPRSTR;
|
| 18292 |
|
|
extern volatile CAN4TXTBPRSTR _CAN4TXTBPR @(REG_BASE + 0x000002BF);
|
| 18293 |
|
|
#define CAN4TXTBPR _CAN4TXTBPR.Byte
|
| 18294 |
|
|
#define CAN4TXTBPR_PRIO0 _CAN4TXTBPR.Bits.PRIO0
|
| 18295 |
|
|
#define CAN4TXTBPR_PRIO1 _CAN4TXTBPR.Bits.PRIO1
|
| 18296 |
|
|
#define CAN4TXTBPR_PRIO2 _CAN4TXTBPR.Bits.PRIO2
|
| 18297 |
|
|
#define CAN4TXTBPR_PRIO3 _CAN4TXTBPR.Bits.PRIO3
|
| 18298 |
|
|
#define CAN4TXTBPR_PRIO4 _CAN4TXTBPR.Bits.PRIO4
|
| 18299 |
|
|
#define CAN4TXTBPR_PRIO5 _CAN4TXTBPR.Bits.PRIO5
|
| 18300 |
|
|
#define CAN4TXTBPR_PRIO6 _CAN4TXTBPR.Bits.PRIO6
|
| 18301 |
|
|
#define CAN4TXTBPR_PRIO7 _CAN4TXTBPR.Bits.PRIO7
|
| 18302 |
|
|
#define CAN4TXTBPR_PRIO _CAN4TXTBPR.MergedBits.grpPRIO
|
| 18303 |
|
|
|
| 18304 |
|
|
|
| 18305 |
|
|
/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/
|
| 18306 |
|
|
typedef union {
|
| 18307 |
|
|
byte Byte;
|
| 18308 |
|
|
struct {
|
| 18309 |
|
|
byte :1;
|
| 18310 |
|
|
byte UNSEC :1; /* Unsecure */
|
| 18311 |
|
|
byte CLKSW :1; /* Clock switch */
|
| 18312 |
|
|
byte TRACE :1; /* TRACE1 BDM firmware command is being executed */
|
| 18313 |
|
|
byte SDV :1; /* Shift data valid */
|
| 18314 |
|
|
byte ENTAG :1; /* Tagging enable */
|
| 18315 |
|
|
byte BDMACT :1; /* BDM active status */
|
| 18316 |
|
|
byte ENBDM :1; /* Enable BDM */
|
| 18317 |
|
|
} Bits;
|
| 18318 |
|
|
} BDMSTSSTR;
|
| 18319 |
|
|
extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01);
|
| 18320 |
|
|
#define BDMSTS _BDMSTS.Byte
|
| 18321 |
|
|
#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC
|
| 18322 |
|
|
#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW
|
| 18323 |
|
|
#define BDMSTS_TRACE _BDMSTS.Bits.TRACE
|
| 18324 |
|
|
#define BDMSTS_SDV _BDMSTS.Bits.SDV
|
| 18325 |
|
|
#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG
|
| 18326 |
|
|
#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT
|
| 18327 |
|
|
#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM
|
| 18328 |
|
|
|
| 18329 |
|
|
|
| 18330 |
|
|
/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/
|
| 18331 |
|
|
typedef union {
|
| 18332 |
|
|
byte Byte;
|
| 18333 |
|
|
struct {
|
| 18334 |
|
|
byte CCR0 :1; /* BDM CCR Holding Bit 0 */
|
| 18335 |
|
|
byte CCR1 :1; /* BDM CCR Holding Bit 1 */
|
| 18336 |
|
|
byte CCR2 :1; /* BDM CCR Holding Bit 2 */
|
| 18337 |
|
|
byte CCR3 :1; /* BDM CCR Holding Bit 3 */
|
| 18338 |
|
|
byte CCR4 :1; /* BDM CCR Holding Bit 4 */
|
| 18339 |
|
|
byte CCR5 :1; /* BDM CCR Holding Bit 5 */
|
| 18340 |
|
|
byte CCR6 :1; /* BDM CCR Holding Bit 6 */
|
| 18341 |
|
|
byte CCR7 :1; /* BDM CCR Holding Bit 7 */
|
| 18342 |
|
|
} Bits;
|
| 18343 |
|
|
struct {
|
| 18344 |
|
|
byte grpCCR :8;
|
| 18345 |
|
|
} MergedBits;
|
| 18346 |
|
|
} BDMCCRSTR;
|
| 18347 |
|
|
extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06);
|
| 18348 |
|
|
#define BDMCCR _BDMCCR.Byte
|
| 18349 |
|
|
#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0
|
| 18350 |
|
|
#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1
|
| 18351 |
|
|
#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2
|
| 18352 |
|
|
#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3
|
| 18353 |
|
|
#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4
|
| 18354 |
|
|
#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5
|
| 18355 |
|
|
#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6
|
| 18356 |
|
|
#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7
|
| 18357 |
|
|
#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR
|
| 18358 |
|
|
|
| 18359 |
|
|
|
| 18360 |
|
|
/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/
|
| 18361 |
|
|
typedef union {
|
| 18362 |
|
|
byte Byte;
|
| 18363 |
|
|
struct {
|
| 18364 |
|
|
byte :1;
|
| 18365 |
|
|
byte :1;
|
| 18366 |
|
|
byte :1;
|
| 18367 |
|
|
byte REG11 :1; /* Internal register map position */
|
| 18368 |
|
|
byte REG12 :1; /* Internal register map position */
|
| 18369 |
|
|
byte REG13 :1; /* Internal register map position */
|
| 18370 |
|
|
byte REG14 :1; /* Internal register map position */
|
| 18371 |
|
|
byte REG15 :1; /* Internal register map position */
|
| 18372 |
|
|
} Bits;
|
| 18373 |
|
|
struct {
|
| 18374 |
|
|
byte :1;
|
| 18375 |
|
|
byte :1;
|
| 18376 |
|
|
byte :1;
|
| 18377 |
|
|
byte grpREG_11 :5;
|
| 18378 |
|
|
} MergedBits;
|
| 18379 |
|
|
} BDMINRSTR;
|
| 18380 |
|
|
extern volatile BDMINRSTR _BDMINR @(0x0000FF07);
|
| 18381 |
|
|
#define BDMINR _BDMINR.Byte
|
| 18382 |
|
|
#define BDMINR_REG11 _BDMINR.Bits.REG11
|
| 18383 |
|
|
#define BDMINR_REG12 _BDMINR.Bits.REG12
|
| 18384 |
|
|
#define BDMINR_REG13 _BDMINR.Bits.REG13
|
| 18385 |
|
|
#define BDMINR_REG14 _BDMINR.Bits.REG14
|
| 18386 |
|
|
#define BDMINR_REG15 _BDMINR.Bits.REG15
|
| 18387 |
|
|
#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11
|
| 18388 |
|
|
#define BDMINR_REG BDMINR_REG_11
|
| 18389 |
|
|
|
| 18390 |
|
|
|
| 18391 |
|
|
/* Watchdog reset macro */
|
| 18392 |
|
|
#ifdef _lint
|
| 18393 |
|
|
#define __RESET_WATCHDOG() /* empty */
|
| 18394 |
|
|
#else
|
| 18395 |
|
|
#define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */
|
| 18396 |
|
|
#endif
|
| 18397 |
|
|
|
| 18398 |
|
|
#endif
|
| 18399 |
|
|
|
| 18400 |
|
|
/*
|
| 18401 |
|
|
** ###################################################################
|
| 18402 |
|
|
**
|
| 18403 |
|
|
** This file was created by UNIS Processor Expert 03.33 for
|
| 18404 |
|
|
** the Motorola HCS12 series of microcontrollers.
|
| 18405 |
|
|
**
|
| 18406 |
|
|
** ###################################################################
|
| 18407 |
|
|
*/
|
| 18408 |
|
|
|
