1 |
588 |
jeremybenn |
// HCS12 Core erasing + unsecuring command file:
|
2 |
|
|
// These commands mass erase the chip then program the security byte to 0xFE (unsecured state).
|
3 |
|
|
|
4 |
|
|
// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers:
|
5 |
|
|
|
6 |
|
|
// An average programming clock of 175 kHz is chosen.
|
7 |
|
|
|
8 |
|
|
// If the oscillator frequency is less than 10 MHz, the value to store
|
9 |
|
|
// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ".
|
10 |
|
|
|
11 |
|
|
// If the oscillator frequency is higher than 10 MHz, the value to store
|
12 |
|
|
// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400 + 0x40 (to set PRDIV8 flag)".
|
13 |
|
|
|
14 |
|
|
// Datasheet proposed values:
|
15 |
|
|
//
|
16 |
|
|
// oscillator frequency ECLKDIV/FCLKDIV value (hexadecimal)
|
17 |
|
|
//
|
18 |
|
|
// 16 MHz $49
|
19 |
|
|
// 8 MHz $27
|
20 |
|
|
// 4 MHz $13
|
21 |
|
|
// 2 MHz $9
|
22 |
|
|
// 1 MHz $4
|
23 |
|
|
|
24 |
|
|
define CLKDIV 0x49
|
25 |
|
|
|
26 |
|
|
FLASH MEMUNMAP // do not interact with regular flash programming monitor
|
27 |
|
|
|
28 |
|
|
//mass erase flash
|
29 |
|
|
wb 0x100 CLKDIV // set FCLKDIV clock divider
|
30 |
|
|
wb 0x103 0 // FCFNG select block 0
|
31 |
|
|
wb 0x102 0x10 // set the WRALL bit in FTSTMOD to affect all blocks
|
32 |
|
|
wb 0x104 0xFF // FPROT all protection disabled
|
33 |
|
|
wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register
|
34 |
|
|
ww 0x108 0xD000 // write to FADDR address register
|
35 |
|
|
ww 0x10A 0x0000 // write to FDATA data register
|
36 |
|
|
wb 0x106 0x41 // write MASS ERASE command in FCMD register
|
37 |
|
|
wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command
|
38 |
|
|
wait 20 // wait for command to complete
|
39 |
|
|
|
40 |
|
|
//mass erase eeprom
|
41 |
|
|
wb 0x110 CLKDIV // set ECLKDV clock divider
|
42 |
|
|
wb 0x114 0xFF // EPROT all protection disabled
|
43 |
|
|
wb 0x115 0x30 // clear PVIOL and ACCERR in ESTAT register
|
44 |
|
|
ww 0x118 0x0400 // write to EADDR eeprom address register
|
45 |
|
|
ww 0x11A 0x0000 // write to EDATA eeprom data register
|
46 |
|
|
wb 0x116 0x41 // write MASS ERASE command in ECMD register
|
47 |
|
|
wb 0x115 0x80 // clear CBEIF in ESTAT register to execute the command
|
48 |
|
|
wait 20 // wait for command to complete
|
49 |
|
|
|
50 |
|
|
reset
|
51 |
|
|
|
52 |
|
|
//reprogram Security byte to Unsecure state
|
53 |
|
|
wb 0x100 CLKDIV // set FCLKDIV clock divider
|
54 |
|
|
wb 0x103 0 // FCFNG select block 0
|
55 |
|
|
wb 0x104 0xFF // FPROT all protection disabled
|
56 |
|
|
wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register
|
57 |
|
|
ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state
|
58 |
|
|
wb 0x106 0x20 // write MEMORY PROGRAM command in FCMD register
|
59 |
|
|
wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command
|
60 |
|
|
wait 20 // wait for command to complete
|
61 |
|
|
|
62 |
|
|
reset
|
63 |
|
|
|
64 |
|
|
FLASH MEMMAP // restore regular flash programming monitor
|
65 |
|
|
undef CLKDIV // undefine variable
|
66 |
|
|
|