1 |
588 |
jeremybenn |
/** ###################################################################
|
2 |
|
|
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
3 |
|
|
** Filename : Cpu.C
|
4 |
|
|
** Project : RTOSDemo
|
5 |
|
|
** Processor : MC9S12C32CFU
|
6 |
|
|
** Beantype : MC9S12C32_80
|
7 |
|
|
** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276
|
8 |
|
|
** Compiler : Metrowerks HC12 C Compiler
|
9 |
|
|
** Date/Time : 18/06/2005, 18:00
|
10 |
|
|
** Abstract :
|
11 |
|
|
** This bean "MC9S12C32_80" implements properties, methods,
|
12 |
|
|
** and events of the CPU.
|
13 |
|
|
** Settings :
|
14 |
|
|
**
|
15 |
|
|
** Contents :
|
16 |
|
|
** EnableInt - void Cpu_EnableInt(void);
|
17 |
|
|
** DisableInt - void Cpu_DisableInt(void);
|
18 |
|
|
** SetWaitMode - void Cpu_SetWaitMode(void);
|
19 |
|
|
** SetStopMode - void Cpu_SetStopMode(void);
|
20 |
|
|
**
|
21 |
|
|
** (c) Copyright UNIS, spol. s r.o. 1997-2002
|
22 |
|
|
** UNIS, spol. s r.o.
|
23 |
|
|
** Jundrovska 33
|
24 |
|
|
** 624 00 Brno
|
25 |
|
|
** Czech Republic
|
26 |
|
|
** http : www.processorexpert.com
|
27 |
|
|
** mail : info@processorexpert.com
|
28 |
|
|
** ###################################################################*/
|
29 |
|
|
|
30 |
|
|
/* MODULE Cpu. */
|
31 |
|
|
|
32 |
|
|
#include "Byte1.h"
|
33 |
|
|
#include "TickTimer.h"
|
34 |
|
|
#include "ButtonInterrupt.h"
|
35 |
|
|
#include "PE_Types.h"
|
36 |
|
|
#include "PE_Error.h"
|
37 |
|
|
#include "PE_Const.h"
|
38 |
|
|
#include "IO_Map.h"
|
39 |
|
|
#include "PE_Timer.h"
|
40 |
|
|
#include "Events.h"
|
41 |
|
|
#include "Cpu.h"
|
42 |
|
|
|
43 |
|
|
#define CGM_DELAY 3071UL
|
44 |
|
|
|
45 |
|
|
|
46 |
|
|
/* Global variables */
|
47 |
|
|
volatile byte CCR_reg; /* Current CCR reegister */
|
48 |
|
|
byte CpuMode = HIGH_SPEED; /* Current speed mode */
|
49 |
|
|
|
50 |
|
|
|
51 |
|
|
/*
|
52 |
|
|
** ===================================================================
|
53 |
|
|
** Method : Cpu_Interrupt (bean MC9S12C32_80)
|
54 |
|
|
**
|
55 |
|
|
** Description :
|
56 |
|
|
** This method is internal. It is used by Processor Expert
|
57 |
|
|
** only.
|
58 |
|
|
** ===================================================================
|
59 |
|
|
*/
|
60 |
|
|
#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
|
61 |
|
|
|
62 |
|
|
__interrupt void Cpu_Interrupt(void)
|
63 |
|
|
{
|
64 |
|
|
}
|
65 |
|
|
|
66 |
|
|
#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */
|
67 |
|
|
|
68 |
|
|
/*
|
69 |
|
|
** ===================================================================
|
70 |
|
|
** Method : Cpu_DisableInt (bean MC9S12C32_80)
|
71 |
|
|
**
|
72 |
|
|
** Description :
|
73 |
|
|
** Disable maskable interrupts
|
74 |
|
|
** Parameters : None
|
75 |
|
|
** Returns : Nothing
|
76 |
|
|
** ===================================================================
|
77 |
|
|
*/
|
78 |
|
|
/*
|
79 |
|
|
void Cpu_DisableInt(void)
|
80 |
|
|
|
81 |
|
|
** This method is implemented as macro in the header module. **
|
82 |
|
|
*/
|
83 |
|
|
|
84 |
|
|
/*
|
85 |
|
|
** ===================================================================
|
86 |
|
|
** Method : Cpu_EnableInt (bean MC9S12C32_80)
|
87 |
|
|
**
|
88 |
|
|
** Description :
|
89 |
|
|
** Enable maskable interrupts
|
90 |
|
|
** Parameters : None
|
91 |
|
|
** Returns : Nothing
|
92 |
|
|
** ===================================================================
|
93 |
|
|
*/
|
94 |
|
|
/*
|
95 |
|
|
void Cpu_EnableInt(void)
|
96 |
|
|
|
97 |
|
|
** This method is implemented as macro in the header module. **
|
98 |
|
|
*/
|
99 |
|
|
|
100 |
|
|
/*
|
101 |
|
|
** ===================================================================
|
102 |
|
|
** Method : Cpu_SetStopMode (bean MC9S12C32_80)
|
103 |
|
|
**
|
104 |
|
|
** Description :
|
105 |
|
|
** Set low power mode - Stop mode. For more information
|
106 |
|
|
** about the stop mode see documentation of this CPU.
|
107 |
|
|
** Parameters : None
|
108 |
|
|
** Returns : Nothing
|
109 |
|
|
** ===================================================================
|
110 |
|
|
*/
|
111 |
|
|
/*
|
112 |
|
|
void Cpu_SetStopMode(void)
|
113 |
|
|
|
114 |
|
|
** This method is implemented as macro in the header module. **
|
115 |
|
|
*/
|
116 |
|
|
|
117 |
|
|
/*
|
118 |
|
|
** ===================================================================
|
119 |
|
|
** Method : Cpu_SetWaitMode (bean MC9S12C32_80)
|
120 |
|
|
**
|
121 |
|
|
** Description :
|
122 |
|
|
** Set low power mode - Wait mode. For more information
|
123 |
|
|
** about the wait mode see documentation of this CPU.
|
124 |
|
|
** Release from Watch mode: Reset or interrupt
|
125 |
|
|
** Parameters : None
|
126 |
|
|
** Returns : Nothing
|
127 |
|
|
** ===================================================================
|
128 |
|
|
*/
|
129 |
|
|
/*
|
130 |
|
|
void Cpu_SetWaitMode(void)
|
131 |
|
|
|
132 |
|
|
** This method is implemented as macro in the header module. **
|
133 |
|
|
*/
|
134 |
|
|
|
135 |
|
|
/*
|
136 |
|
|
** ===================================================================
|
137 |
|
|
** Method : _EntryPoint (bean MC9S12C32_80)
|
138 |
|
|
**
|
139 |
|
|
** Description :
|
140 |
|
|
** This method is internal. It is used by Processor Expert
|
141 |
|
|
** only.
|
142 |
|
|
** ===================================================================
|
143 |
|
|
*/
|
144 |
|
|
extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */
|
145 |
|
|
#define INITRG_ADR 0x0011 /* Register map position register */
|
146 |
|
|
#pragma NO_FRAME
|
147 |
|
|
#pragma NO_EXIT
|
148 |
|
|
void _EntryPoint(void)
|
149 |
|
|
{
|
150 |
|
|
/*** ### MC9S12C32_80 "Cpu" init code ... ***/
|
151 |
|
|
/*** PE initialization code after reset ***/
|
152 |
|
|
/* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */
|
153 |
|
|
*(byte*)INITRG_ADR = 0; /* Set the register map position */
|
154 |
|
|
asm nop; /* nop instruction */
|
155 |
|
|
INITRM=8; /* Set the RAM map position */
|
156 |
|
|
/* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */
|
157 |
|
|
MISC=1;
|
158 |
|
|
/* System clock initialization */
|
159 |
|
|
CLKSEL=0;
|
160 |
|
|
CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */
|
161 |
|
|
PLLCTL_PLLON = 0; /* Disable the PLL */
|
162 |
|
|
SYNR = 23; /* Set the multiplier register */
|
163 |
|
|
REFDV = 15; /* Set the divider register */
|
164 |
|
|
PLLCTL = 192;
|
165 |
|
|
PLLCTL_PLLON = 1; /* Enable the PLL */
|
166 |
|
|
while(!CRGFLG_LOCK); /* Wait */
|
167 |
|
|
CLKSEL_PLLSEL = 1; /* Select clock source from PLL */
|
168 |
|
|
/*** End of PE initialization code after reset ***/
|
169 |
|
|
|
170 |
|
|
__asm jmp _Startup; /* Jump to C startup code */
|
171 |
|
|
}
|
172 |
|
|
|
173 |
|
|
/*
|
174 |
|
|
** ===================================================================
|
175 |
|
|
** Method : PE_low_level_init (bean MC9S12C32_80)
|
176 |
|
|
**
|
177 |
|
|
** Description :
|
178 |
|
|
** This method is internal. It is used by Processor Expert
|
179 |
|
|
** only.
|
180 |
|
|
** ===================================================================
|
181 |
|
|
*/
|
182 |
|
|
void PE_low_level_init(void)
|
183 |
|
|
{
|
184 |
|
|
/* Common initialization of the CPU registers */
|
185 |
|
|
/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */
|
186 |
|
|
output( TSCR1, input( TSCR1 ) & ~192 | 32 );
|
187 |
|
|
/* TCTL2: OM0=0,OL0=0 */
|
188 |
|
|
output( TCTL2, input( TCTL2 ) & ~3 );
|
189 |
|
|
/* TCTL1: OM7=0,OL7=0 */
|
190 |
|
|
output( TCTL1, input( TCTL1 ) & ~192 );
|
191 |
|
|
/* TIE: C0I=0 */
|
192 |
|
|
output( TIE, input( TIE ) & ~1 );
|
193 |
|
|
/* TTOV: TOV0=0 */
|
194 |
|
|
output( TTOV, input( TTOV ) & ~1 );
|
195 |
|
|
/* TSCR2: TOI=0,TCRE=1 */
|
196 |
|
|
output( TSCR2, input( TSCR2 ) & ~128 | 8 );
|
197 |
|
|
/* TIOS: IOS7=1,IOS0=1 */
|
198 |
|
|
output( TIOS, input( TIOS ) | 129 );
|
199 |
|
|
/* PPSP: PPSP0=0 */
|
200 |
|
|
output( PPSP, input( PPSP ) & ~1 );
|
201 |
|
|
/* PERP: PERP0=1 */
|
202 |
|
|
output( PERP, input( PERP ) | 1 );
|
203 |
|
|
/* DDRP: DDRP0=0 */
|
204 |
|
|
output( DDRP, input( DDRP ) & ~1 );
|
205 |
|
|
/* PWMCTL: PSWAI=0,PFRZ=0 */
|
206 |
|
|
output( PWMCTL, input( PWMCTL ) & ~12 );
|
207 |
|
|
/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */
|
208 |
|
|
output( PWMSDN, 0 );
|
209 |
|
|
/* ### MC9S12C32_80 "Cpu" init code ... */
|
210 |
|
|
/* ### ByteIO "Byte1" init code ... */
|
211 |
|
|
PORTB = 0; /* Prepare value for output */
|
212 |
|
|
DDRB = 255; /* Set direction to output */
|
213 |
|
|
/* ### TimerInt "TickTimer" init code ... */
|
214 |
|
|
TickTimer_Init();
|
215 |
|
|
/* ### External interrupt "ButtonInterrupt" init code ... */
|
216 |
|
|
PIEP_PIEP0 = 0; /* Disable interrupt */
|
217 |
|
|
/* Common peripheral initialization - ENABLE */
|
218 |
|
|
/* TSCR1: TEN=1 */
|
219 |
|
|
output( TSCR1, input( TSCR1 ) | 128 );
|
220 |
|
|
INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */
|
221 |
|
|
__DI(); /* Disable interrupts */
|
222 |
|
|
}
|
223 |
|
|
|
224 |
|
|
/* END Cpu. */
|
225 |
|
|
|
226 |
|
|
/*
|
227 |
|
|
** ###################################################################
|
228 |
|
|
**
|
229 |
|
|
** This file was created by UNIS Processor Expert 03.33 for
|
230 |
|
|
** the Motorola HCS12 series of microcontrollers.
|
231 |
|
|
**
|
232 |
|
|
** ###################################################################
|
233 |
|
|
*/
|