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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [HCS12_CodeWarrior_small/] [CODE/] [IO_Map.C] - Blame information for rev 588

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/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : IO_Map.C
**     Project   : RTOSDemo
**     Processor : MC9S12C32CFU
**     Beantype  : IO_Map
**     Version   : Driver 01.01
**     Compiler  : Metrowerks HC12 C Compiler
**     Date/Time : 10/05/2005, 11:11
**     Abstract  :
**         This bean "IO_Map" implements an IO devices mapping.
**     Settings  :
**
**     Contents  :
**         No public methods
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2002
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : info@processorexpert.com
** ###################################################################*/
/* Based on CPU DB MC9S12C32_80, version 2.87.264 */
#include "PE_types.h"
#include "IO_Map.h"
 
volatile ARMCOPSTR _ARMCOP;                                /* CRG COP Timer Arm/Reset Register */
volatile ATDDIENSTR _ATDDIEN;                              /* ATD Input Enable Mask Register */
volatile ATDSTAT0STR _ATDSTAT0;                            /* A/D Status Register 0 */
volatile ATDSTAT1STR _ATDSTAT1;                            /* A/D Status Register 1 */
volatile BDMCCRSTR _BDMCCR;                                /* BDM CCR Holding Register */
volatile BDMINRSTR _BDMINR;                                /* BDM Internal Register Position Register */
volatile BDMSTSSTR _BDMSTS;                                /* BDM Status Register */
volatile BKP0HSTR _BKP0H;                                  /* First Address High Byte Breakpoint Register */
volatile BKP0LSTR _BKP0L;                                  /* First Address Low Byte Breakpoint Register */
volatile BKP0XSTR _BKP0X;                                  /* First Address Memory Expansion Breakpoint Register */
volatile BKP1HSTR _BKP1H;                                  /* Data (Second Address) High Byte Breakpoint Register */
volatile BKP1LSTR _BKP1L;                                  /* Data (Second Address) Low Byte Breakpoint Register */
volatile BKP1XSTR _BKP1X;                                  /* Second Address Memory Expansion Breakpoint Register */
volatile BKPCT0STR _BKPCT0;                                /* Breakpoint Control Register 0 */
volatile BKPCT1STR _BKPCT1;                                /* Breakpoint Control Register 1 */
volatile CANBTR0STR _CANBTR0;                              /* MSCAN Bus Timing Register 0 */
volatile CANBTR1STR _CANBTR1;                              /* MSCAN Bus Timing Register 1 */
volatile CANCTL0STR _CANCTL0;                              /* MSCAN Control 0 Register */
volatile CANCTL1STR _CANCTL1;                              /* MSCAN Control 1 Register */
volatile CANIDACSTR _CANIDAC;                              /* MSCAN Identifier Acceptance Control Register */
volatile CANIDAR0STR _CANIDAR0;                            /* MSCAN Identifier Acceptance Register 0 */
volatile CANIDAR1STR _CANIDAR1;                            /* MSCAN Identifier Acceptance Register 1 */
volatile CANIDAR2STR _CANIDAR2;                            /* MSCAN Identifier Acceptance Register 2 */
volatile CANIDAR3STR _CANIDAR3;                            /* MSCAN Identifier Acceptance Register 3 */
volatile CANIDAR4STR _CANIDAR4;                            /* MSCAN Identifier Acceptance Register 4 */
volatile CANIDAR5STR _CANIDAR5;                            /* MSCAN Identifier Acceptance Register 5 */
volatile CANIDAR6STR _CANIDAR6;                            /* MSCAN Identifier Acceptance Register 6 */
volatile CANIDAR7STR _CANIDAR7;                            /* MSCAN Identifier Acceptance Register 7 */
volatile CANIDMR0STR _CANIDMR0;                            /* MSCAN Identifier Mask Register 0 */
volatile CANIDMR1STR _CANIDMR1;                            /* MSCAN Identifier Mask Register 1 */
volatile CANIDMR2STR _CANIDMR2;                            /* MSCAN Identifier Mask Register 2 */
volatile CANIDMR3STR _CANIDMR3;                            /* MSCAN Identifier Mask Register 3 */
volatile CANIDMR4STR _CANIDMR4;                            /* MSCAN Identifier Mask Register 4 */
volatile CANIDMR5STR _CANIDMR5;                            /* MSCAN Identifier Mask Register 5 */
volatile CANIDMR6STR _CANIDMR6;                            /* MSCAN Identifier Mask Register 6 */
volatile CANIDMR7STR _CANIDMR7;                            /* MSCAN Identifier Mask Register 7 */
volatile CANRFLGSTR _CANRFLG;                              /* MSCAN Receiver Flag Register */
volatile CANRIERSTR _CANRIER;                              /* MSCAN Receiver Interrupt Enable Register */
volatile CANRXDLRSTR _CANRXDLR;                            /* MSCAN Receive Data Length Register */
volatile CANRXDSR0STR _CANRXDSR0;                          /* MSCAN Receive Data Segment Register 0 */
volatile CANRXDSR1STR _CANRXDSR1;                          /* MSCAN Receive Data Segment Register 1 */
volatile CANRXDSR2STR _CANRXDSR2;                          /* MSCAN Receive Data Segment Register 2 */
volatile CANRXDSR3STR _CANRXDSR3;                          /* MSCAN Receive Data Segment Register 3 */
volatile CANRXDSR4STR _CANRXDSR4;                          /* MSCAN Receive Data Segment Register 4 */
volatile CANRXDSR5STR _CANRXDSR5;                          /* MSCAN Receive Data Segment Register 5 */
volatile CANRXDSR6STR _CANRXDSR6;                          /* MSCAN Receive Data Segment Register 6 */
volatile CANRXDSR7STR _CANRXDSR7;                          /* MSCAN Receive Data Segment Register 7 */
volatile CANRXERRSTR _CANRXERR;                            /* MSCAN Receive Error Counter Register */
volatile CANRXIDR0STR _CANRXIDR0;                          /* MSCAN Receive Identifier Register 0 */
volatile CANRXIDR1STR _CANRXIDR1;                          /* MSCAN Receive Identifier Register 1 */
volatile CANRXIDR2STR _CANRXIDR2;                          /* MSCAN Receive Identifier Register 2 */
volatile CANRXIDR3STR _CANRXIDR3;                          /* MSCAN Receive Identifier Register 3 */
volatile CANTAAKSTR _CANTAAK;                              /* MSCAN Transmitter Message Abort Control */
volatile CANTARQSTR _CANTARQ;                              /* MSCAN Transmitter Message Abort Request */
volatile CANTBSELSTR _CANTBSEL;                            /* MSCAN Transmit Buffer Selection */
volatile CANTFLGSTR _CANTFLG;                              /* MSCAN Transmitter Flag Register */
volatile CANTIERSTR _CANTIER;                              /* MSCAN Transmitter Interrupt Enable Register */
volatile CANTXDLRSTR _CANTXDLR;                            /* MSCAN Transmit Data Length Register */
volatile CANTXDSR0STR _CANTXDSR0;                          /* MSCAN Transmit Data Segment Register 0 */
volatile CANTXDSR1STR _CANTXDSR1;                          /* MSCAN Transmit Data Segment Register 1 */
volatile CANTXDSR2STR _CANTXDSR2;                          /* MSCAN Transmit Data Segment Register 2 */
volatile CANTXDSR3STR _CANTXDSR3;                          /* MSCAN Transmit Data Segment Register 3 */
volatile CANTXDSR4STR _CANTXDSR4;                          /* MSCAN Transmit Data Segment Register 4 */
volatile CANTXDSR5STR _CANTXDSR5;                          /* MSCAN Transmit Data Segment Register 5 */
volatile CANTXDSR6STR _CANTXDSR6;                          /* MSCAN Transmit Data Segment Register 6 */
volatile CANTXDSR7STR _CANTXDSR7;                          /* MSCAN Transmit Data Segment Register 7 */
volatile CANTXERRSTR _CANTXERR;                            /* MSCAN Transmit Error Counter Register */
volatile CANTXIDR0STR _CANTXIDR0;                          /* MSCAN Transmit Identifier Register 0 */
volatile CANTXIDR1STR _CANTXIDR1;                          /* MSCAN Transmit Identifier Register 1 */
volatile CANTXIDR2STR _CANTXIDR2;                          /* MSCAN Transmit Identifier Register 2 */
volatile CANTXIDR3STR _CANTXIDR3;                          /* MSCAN Transmit Identifier Register 3 */
volatile CANTXTBPRSTR _CANTXTBPR;                          /* MSCAN Transmit Buffer Priority */
volatile CFORCSTR _CFORC;                                  /* Timer Compare Force Register */
volatile CLKSELSTR _CLKSEL;                                /* CRG Clock Select Register */
volatile COPCTLSTR _COPCTL;                                /* CRG COP Control Register */
volatile CRGFLGSTR _CRGFLG;                                /* CRG Flags Register */
volatile CRGINTSTR _CRGINT;                                /* CRG Interrupt Enable Register */
volatile CTCTLSTR _CTCTL;                                  /* CRG Test Control Register */
volatile CTFLGSTR _CTFLG;                                  /* CRG Test Flags Register */
volatile DDRADSTR _DDRAD;                                  /* Port AD Data Direction Register */
volatile DDRESTR _DDRE;                                    /* Port E Data Direction Register */
volatile DDRJSTR _DDRJ;                                    /* Port J Data Direction Register */
volatile DDRKSTR _DDRK;                                    /* Port K Data Direction Register */
volatile DDRMSTR _DDRM;                                    /* Port M Data Direction Register */
volatile DDRPSTR _DDRP;                                    /* Port P Data Direction Register */
volatile DDRSSTR _DDRS;                                    /* Port S Data Direction Register */
volatile DDRTSTR _DDRT;                                    /* Port T Data Direction Register */
volatile EBICTLSTR _EBICTL;                                /* External Bus Interface Control */
volatile FCLKDIVSTR _FCLKDIV;                              /* Flash Clock Divider Register */
volatile FCMDSTR _FCMD;                                    /* Flash Command Buffer and Register */
volatile FCNFGSTR _FCNFG;                                  /* Flash Configuration Register */
volatile FPROTSTR _FPROT;                                  /* Flash Protection Register */
volatile FSECSTR _FSEC;                                    /* Flash Security Register */
volatile FSTATSTR _FSTAT;                                  /* Flash Status Register */
volatile HPRIOSTR _HPRIO;                                  /* Highest Priority I Interrupt */
volatile INITEESTR _INITEE;                                /* Initialization of Internal EEPROM Position Register */
volatile INITRGSTR _INITRG;                                /* Initialization of Internal Register Position Register */
volatile INITRMSTR _INITRM;                                /* Initialization of Internal RAM Position Register */
volatile INTCRSTR _INTCR;                                  /* Interrupt Control Register */
volatile ITCRSTR _ITCR;                                    /* Interrupt Test Control Register */
volatile ITESTSTR _ITEST;                                  /* Interrupt Test Register */
volatile MEMSIZ0STR _MEMSIZ0;                              /* Memory Size Register Zero */
volatile MEMSIZ1STR _MEMSIZ1;                              /* Memory Size Register One */
volatile MISCSTR _MISC;                                    /* Miscellaneous Mapping Control Register */
volatile MODESTR _MODE;                                    /* Mode Register */
volatile MODRRSTR _MODRR;                                  /* Module Routing Register */
volatile MTST0STR _MTST0;                                  /* MTST0 */
volatile MTST1STR _MTST1;                                  /* MTST1 */
volatile OC7DSTR _OC7D;                                    /* Output Compare 7 Data Register */
volatile OC7MSTR _OC7M;                                    /* Output Compare 7 Mask Register */
volatile PACTLSTR _PACTL;                                  /* 16-Bit Pulse Accumulator A Control Register */
volatile PAFLGSTR _PAFLG;                                  /* Pulse Accumulator A Flag Register */
volatile PARTIDHSTR _PARTIDH;                              /* Part ID Register High */
volatile PARTIDLSTR _PARTIDL;                              /* Part ID Register Low */
volatile PEARSTR _PEAR;                                    /* Port E Assignment Register */
volatile PERADSTR _PERAD;                                  /* Port AD Pull Device Enable Register */
volatile PERJSTR _PERJ;                                    /* Port J Pull Device Enable Register */
volatile PERMSTR _PERM;                                    /* Port M Pull Device Enable Register */
volatile PERPSTR _PERP;                                    /* Port P Pull Device Enable Register */
volatile PERSSTR _PERS;                                    /* Port S Pull Device Enable Register */
volatile PERTSTR _PERT;                                    /* Port T Pull Device Enable Register */
volatile PIEJSTR _PIEJ;                                    /* Port J Interrupt Enable Register */
volatile PIEPSTR _PIEP;                                    /* Port P Interrupt Enable Register */
volatile PIFJSTR _PIFJ;                                    /* Port J Interrupt Flag Register */
volatile PIFPSTR _PIFP;                                    /* Port P Interrupt Flag Register */
volatile PLLCTLSTR _PLLCTL;                                /* CRG PLL Control Register */
volatile PORTAD0STR _PORTAD0;                              /* Port AD0 Register */
volatile PORTESTR _PORTE;                                  /* Port E Register */
volatile PORTKSTR _PORTK;                                  /* Port K Data Register */
volatile PPAGESTR _PPAGE;                                  /* Page Index Register */
volatile PPSADSTR _PPSAD;                                  /* Port AD Polarity Select Register */
volatile PPSJSTR _PPSJ;                                    /* PortJP Polarity Select Register */
volatile PPSMSTR _PPSM;                                    /* Port M Polarity Select Register */
volatile PPSPSTR _PPSP;                                    /* Port P Polarity Select Register */
volatile PPSSSTR _PPSS;                                    /* Port S Polarity Select Register */
volatile PPSTSTR _PPST;                                    /* Port T Polarity Select Register */
volatile PTADSTR _PTAD;                                    /* Port AD I/O Register */
volatile PTIADSTR _PTIAD;                                  /* Port AD Input Register */
volatile PTIJSTR _PTIJ;                                    /* Port J Input Register */
volatile PTIMSTR _PTIM;                                    /* Port M Input */
volatile PTIPSTR _PTIP;                                    /* Port P Input */
volatile PTISSTR _PTIS;                                    /* Port S Input */
volatile PTITSTR _PTIT;                                    /* Port T Input */
volatile PTJSTR _PTJ;                                      /* Port J I/O Register */
volatile PTMSTR _PTM;                                      /* Port M I/O Register */
volatile PTPSTR _PTP;                                      /* Port P I/O Register */
volatile PTSSTR _PTS;                                      /* Port S I/O Register */
volatile PTTSTR _PTT;                                      /* Port T I/O Register */
volatile PUCRSTR _PUCR;                                    /* Pull-Up Control Register */
volatile PWMCAESTR _PWMCAE;                                /* PWM Center Align Enable Register */
volatile PWMCLKSTR _PWMCLK;                                /* PWM Clock Select Register */
volatile PWMCTLSTR _PWMCTL;                                /* PWM Control Register */
volatile PWMESTR _PWME;                                    /* PWM Enable Register */
volatile PWMPOLSTR _PWMPOL;                                /* PWM Polarity Register */
volatile PWMPRCLKSTR _PWMPRCLK;                            /* PWM Prescale Clock Select Register */
volatile PWMSCLASTR _PWMSCLA;                              /* PWM Scale A Register */
volatile PWMSCLBSTR _PWMSCLB;                              /* PWM Scale B Register */
volatile PWMSDNSTR _PWMSDN;                                /* PWM Shutdown Register */
volatile RDRADSTR _RDRAD;                                  /* Port AD Reduced Drive Register */
volatile RDRIVSTR _RDRIV;                                  /* Reduced Drive of I/O Lines */
volatile RDRJSTR _RDRJ;                                    /* Port J Reduced Drive Register */
volatile RDRMSTR _RDRM;                                    /* Port M Reduced Drive Register */
volatile RDRPSTR _RDRP;                                    /* Port P Reduced Drive Register */
volatile RDRSSTR _RDRS;                                    /* Port S Reduced Drive Register */
volatile RDRTSTR _RDRT;                                    /* Port T Reduced Drive Register */
volatile REFDVSTR _REFDV;                                  /* CRG Reference Divider Register */
volatile RTICTLSTR _RTICTL;                                /* CRG RTI Control Register */
volatile SCICR1STR _SCICR1;                                /* SCI Control Register 1 */
volatile SCICR2STR _SCICR2;                                /* SCI Control Register 2 */
volatile SCIDRHSTR _SCIDRH;                                /* SCI Data Register High */
volatile SCIDRLSTR _SCIDRL;                                /* SCI Data Register Low */
volatile SCISR1STR _SCISR1;                                /* SCI Status Register 1 */
volatile SCISR2STR _SCISR2;                                /* SCI Status Register 2 */
volatile SPIBRSTR _SPIBR;                                  /* SPI Baud Rate Register */
volatile SPICR1STR _SPICR1;                                /* SPI Control Register */
volatile SPICR2STR _SPICR2;                                /* SPI Control Register 2 */
volatile SPIDRSTR _SPIDR;                                  /* SPI Data Register */
volatile SPISRSTR _SPISR;                                  /* SPI Status Register */
volatile SYNRSTR _SYNR;                                    /* CRG Synthesizer Register */
volatile TCTL1STR _TCTL1;                                  /* Timer Control Register 1 */
volatile TCTL2STR _TCTL2;                                  /* Timer Control Register 2 */
volatile TCTL3STR _TCTL3;                                  /* Timer Control Register 3 */
volatile TCTL4STR _TCTL4;                                  /* Timer Control Register 4 */
volatile TFLG1STR _TFLG1;                                  /* Main Timer Interrupt Flag 1 */
volatile TFLG2STR _TFLG2;                                  /* Main Timer Interrupt Flag 2 */
volatile TIESTR _TIE;                                      /* Timer Interrupt Enable Register */
volatile TIOSSTR _TIOS;                                    /* Timer Input Capture/Output Compare Select */
volatile TSCR1STR _TSCR1;                                  /* Timer System Control Register1 */
volatile TSCR2STR _TSCR2;                                  /* Timer System Control Register 2 */
volatile TTOVSTR _TTOV;                                    /* Timer Toggle On Overflow Register */
volatile WOMMSTR _WOMM;                                    /* Port M Wired-Or Mode Register */
volatile WOMSSTR _WOMS;                                    /* Port S Wired-Or Mode Register */
volatile ATDCTL23STR _ATDCTL23;                            /* ATD Control Register 23 */
volatile ATDCTL45STR _ATDCTL45;                            /* ATD Control Register 45 */
volatile ATDDR0STR _ATDDR0;                                /* A/D Conversion Result Register 0 */
volatile ATDDR1STR _ATDDR1;                                /* A/D Conversion Result Register 1 */
volatile ATDDR2STR _ATDDR2;                                /* A/D Conversion Result Register 2 */
volatile ATDDR3STR _ATDDR3;                                /* A/D Conversion Result Register 3 */
volatile ATDDR4STR _ATDDR4;                                /* A/D Conversion Result Register 4 */
volatile ATDDR5STR _ATDDR5;                                /* A/D Conversion Result Register 5 */
volatile ATDDR6STR _ATDDR6;                                /* A/D Conversion Result Register 6 */
volatile ATDDR7STR _ATDDR7;                                /* A/D Conversion Result Register 7 */
volatile DDRABSTR _DDRAB;                                  /* Port AB Data Direction Register */
volatile PACNTSTR _PACNT;                                  /* Pulse Accumulators Count Register */
volatile PORTABSTR _PORTAB;                                /* Port AB Register */
volatile PWMCNT01STR _PWMCNT01;                            /* PWM Channel Counter 01 Register */
volatile PWMCNT23STR _PWMCNT23;                            /* PWM Channel Counter 23 Register */
volatile PWMCNT45STR _PWMCNT45;                            /* PWM Channel Counter 45 Register */
volatile PWMDTY01STR _PWMDTY01;                            /* PWM Channel Duty 01 Register */
volatile PWMDTY23STR _PWMDTY23;                            /* PWM Channel Duty 23 Register */
volatile PWMDTY45STR _PWMDTY45;                            /* PWM Channel Duty 45 Register */
volatile PWMPER01STR _PWMPER01;                            /* PWM Channel Period 01 Register */
volatile PWMPER23STR _PWMPER23;                            /* PWM Channel Period 23 Register */
volatile PWMPER45STR _PWMPER45;                            /* PWM Channel Period 45 Register */
volatile SCIBDSTR _SCIBD;                                  /* SCI Baud Rate Register */
volatile TC0STR _TC0;                                      /* Timer Input Capture/Output Compare Register 0 */
volatile TC1STR _TC1;                                      /* Timer Input Capture/Output Compare Register 1 */
volatile TC2STR _TC2;                                      /* Timer Input Capture/Output Compare Register 2 */
volatile TC3STR _TC3;                                      /* Timer Input Capture/Output Compare Register 3 */
volatile TC4STR _TC4;                                      /* Timer Input Capture/Output Compare Register 4 */
volatile TC5STR _TC5;                                      /* Timer Input Capture/Output Compare Register 5 */
volatile TC6STR _TC6;                                      /* Timer Input Capture/Output Compare Register 6 */
volatile TC7STR _TC7;                                      /* Timer Input Capture/Output Compare Register 7 */
volatile TCNTSTR _TCNT;                                    /* Timer Count Register */
/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 03.33 for
**     the Motorola HCS12 series of microcontrollers.
**
** ###################################################################
*/

Line No.	Rev	Author	Line
1	588	jeremybenn	`/** ###################################################################`
2			`** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.`
3			`** Filename : IO_Map.C`
4			`** Project : RTOSDemo`
5			`** Processor : MC9S12C32CFU`
6			`** Beantype : IO_Map`
7			`** Version : Driver 01.01`
8			`** Compiler : Metrowerks HC12 C Compiler`
9			`** Date/Time : 10/05/2005, 11:11`
10			`** Abstract :`
11			`** This bean "IO_Map" implements an IO devices mapping.`
12			`** Settings :`
13			`**`
14			`** Contents :`
15			`** No public methods`
16			`**`
17			`** (c) Copyright UNIS, spol. s r.o. 1997-2002`
18			`** UNIS, spol. s r.o.`
19			`** Jundrovska 33`
20			`** 624 00 Brno`
21			`** Czech Republic`
22			`** http : www.processorexpert.com`
23			`** mail : info@processorexpert.com`
24			`** ###################################################################*/`
25			`/* Based on CPU DB MC9S12C32_80, version 2.87.264 */`
26			`#include "PE_types.h"`
27			`#include "IO_Map.h"`
28
29			`volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */`
30			`volatile ATDDIENSTR _ATDDIEN; /* ATD Input Enable Mask Register */`
31			`volatile ATDSTAT0STR _ATDSTAT0; /* A/D Status Register 0 */`
32			`volatile ATDSTAT1STR _ATDSTAT1; /* A/D Status Register 1 */`
33			`volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */`
34			`volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */`
35			`volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */`
36			`volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */`
37			`volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */`
38			`volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */`
39			`volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */`
40			`volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */`
41			`volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */`
42			`volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */`
43			`volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */`
44			`volatile CANBTR0STR _CANBTR0; /* MSCAN Bus Timing Register 0 */`
45			`volatile CANBTR1STR _CANBTR1; /* MSCAN Bus Timing Register 1 */`
46			`volatile CANCTL0STR _CANCTL0; /* MSCAN Control 0 Register */`
47			`volatile CANCTL1STR _CANCTL1; /* MSCAN Control 1 Register */`
48			`volatile CANIDACSTR _CANIDAC; /* MSCAN Identifier Acceptance Control Register */`
49			`volatile CANIDAR0STR _CANIDAR0; /* MSCAN Identifier Acceptance Register 0 */`
50			`volatile CANIDAR1STR _CANIDAR1; /* MSCAN Identifier Acceptance Register 1 */`
51			`volatile CANIDAR2STR _CANIDAR2; /* MSCAN Identifier Acceptance Register 2 */`
52			`volatile CANIDAR3STR _CANIDAR3; /* MSCAN Identifier Acceptance Register 3 */`
53			`volatile CANIDAR4STR _CANIDAR4; /* MSCAN Identifier Acceptance Register 4 */`
54			`volatile CANIDAR5STR _CANIDAR5; /* MSCAN Identifier Acceptance Register 5 */`
55			`volatile CANIDAR6STR _CANIDAR6; /* MSCAN Identifier Acceptance Register 6 */`
56			`volatile CANIDAR7STR _CANIDAR7; /* MSCAN Identifier Acceptance Register 7 */`
57			`volatile CANIDMR0STR _CANIDMR0; /* MSCAN Identifier Mask Register 0 */`
58			`volatile CANIDMR1STR _CANIDMR1; /* MSCAN Identifier Mask Register 1 */`
59			`volatile CANIDMR2STR _CANIDMR2; /* MSCAN Identifier Mask Register 2 */`
60			`volatile CANIDMR3STR _CANIDMR3; /* MSCAN Identifier Mask Register 3 */`
61			`volatile CANIDMR4STR _CANIDMR4; /* MSCAN Identifier Mask Register 4 */`
62			`volatile CANIDMR5STR _CANIDMR5; /* MSCAN Identifier Mask Register 5 */`
63			`volatile CANIDMR6STR _CANIDMR6; /* MSCAN Identifier Mask Register 6 */`
64			`volatile CANIDMR7STR _CANIDMR7; /* MSCAN Identifier Mask Register 7 */`
65			`volatile CANRFLGSTR _CANRFLG; /* MSCAN Receiver Flag Register */`
66			`volatile CANRIERSTR _CANRIER; /* MSCAN Receiver Interrupt Enable Register */`
67			`volatile CANRXDLRSTR _CANRXDLR; /* MSCAN Receive Data Length Register */`
68			`volatile CANRXDSR0STR _CANRXDSR0; /* MSCAN Receive Data Segment Register 0 */`
69			`volatile CANRXDSR1STR _CANRXDSR1; /* MSCAN Receive Data Segment Register 1 */`
70			`volatile CANRXDSR2STR _CANRXDSR2; /* MSCAN Receive Data Segment Register 2 */`
71			`volatile CANRXDSR3STR _CANRXDSR3; /* MSCAN Receive Data Segment Register 3 */`
72			`volatile CANRXDSR4STR _CANRXDSR4; /* MSCAN Receive Data Segment Register 4 */`
73			`volatile CANRXDSR5STR _CANRXDSR5; /* MSCAN Receive Data Segment Register 5 */`
74			`volatile CANRXDSR6STR _CANRXDSR6; /* MSCAN Receive Data Segment Register 6 */`
75			`volatile CANRXDSR7STR _CANRXDSR7; /* MSCAN Receive Data Segment Register 7 */`
76			`volatile CANRXERRSTR _CANRXERR; /* MSCAN Receive Error Counter Register */`
77			`volatile CANRXIDR0STR _CANRXIDR0; /* MSCAN Receive Identifier Register 0 */`
78			`volatile CANRXIDR1STR _CANRXIDR1; /* MSCAN Receive Identifier Register 1 */`
79			`volatile CANRXIDR2STR _CANRXIDR2; /* MSCAN Receive Identifier Register 2 */`
80			`volatile CANRXIDR3STR _CANRXIDR3; /* MSCAN Receive Identifier Register 3 */`
81			`volatile CANTAAKSTR _CANTAAK; /* MSCAN Transmitter Message Abort Control */`
82			`volatile CANTARQSTR _CANTARQ; /* MSCAN Transmitter Message Abort Request */`
83			`volatile CANTBSELSTR _CANTBSEL; /* MSCAN Transmit Buffer Selection */`
84			`volatile CANTFLGSTR _CANTFLG; /* MSCAN Transmitter Flag Register */`
85			`volatile CANTIERSTR _CANTIER; /* MSCAN Transmitter Interrupt Enable Register */`
86			`volatile CANTXDLRSTR _CANTXDLR; /* MSCAN Transmit Data Length Register */`
87			`volatile CANTXDSR0STR _CANTXDSR0; /* MSCAN Transmit Data Segment Register 0 */`
88			`volatile CANTXDSR1STR _CANTXDSR1; /* MSCAN Transmit Data Segment Register 1 */`
89			`volatile CANTXDSR2STR _CANTXDSR2; /* MSCAN Transmit Data Segment Register 2 */`
90			`volatile CANTXDSR3STR _CANTXDSR3; /* MSCAN Transmit Data Segment Register 3 */`
91			`volatile CANTXDSR4STR _CANTXDSR4; /* MSCAN Transmit Data Segment Register 4 */`
92			`volatile CANTXDSR5STR _CANTXDSR5; /* MSCAN Transmit Data Segment Register 5 */`
93			`volatile CANTXDSR6STR _CANTXDSR6; /* MSCAN Transmit Data Segment Register 6 */`
94			`volatile CANTXDSR7STR _CANTXDSR7; /* MSCAN Transmit Data Segment Register 7 */`
95			`volatile CANTXERRSTR _CANTXERR; /* MSCAN Transmit Error Counter Register */`
96			`volatile CANTXIDR0STR _CANTXIDR0; /* MSCAN Transmit Identifier Register 0 */`
97			`volatile CANTXIDR1STR _CANTXIDR1; /* MSCAN Transmit Identifier Register 1 */`
98			`volatile CANTXIDR2STR _CANTXIDR2; /* MSCAN Transmit Identifier Register 2 */`
99			`volatile CANTXIDR3STR _CANTXIDR3; /* MSCAN Transmit Identifier Register 3 */`
100			`volatile CANTXTBPRSTR _CANTXTBPR; /* MSCAN Transmit Buffer Priority */`
101			`volatile CFORCSTR _CFORC; /* Timer Compare Force Register */`
102			`volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */`
103			`volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */`
104			`volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */`
105			`volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */`
106			`volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */`
107			`volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */`
108			`volatile DDRADSTR _DDRAD; /* Port AD Data Direction Register */`
109			`volatile DDRESTR _DDRE; /* Port E Data Direction Register */`
110			`volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */`
111			`volatile DDRKSTR _DDRK; /* Port K Data Direction Register */`
112			`volatile DDRMSTR _DDRM; /* Port M Data Direction Register */`
113			`volatile DDRPSTR _DDRP; /* Port P Data Direction Register */`
114			`volatile DDRSSTR _DDRS; /* Port S Data Direction Register */`
115			`volatile DDRTSTR _DDRT; /* Port T Data Direction Register */`
116			`volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */`
117			`volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */`
118			`volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */`
119			`volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */`
120			`volatile FPROTSTR _FPROT; /* Flash Protection Register */`
121			`volatile FSECSTR _FSEC; /* Flash Security Register */`
122			`volatile FSTATSTR _FSTAT; /* Flash Status Register */`
123			`volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */`
124			`volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */`
125			`volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */`
126			`volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */`
127			`volatile INTCRSTR _INTCR; /* Interrupt Control Register */`
128			`volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */`
129			`volatile ITESTSTR _ITEST; /* Interrupt Test Register */`
130			`volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */`
131			`volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */`
132			`volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */`
133			`volatile MODESTR _MODE; /* Mode Register */`
134			`volatile MODRRSTR _MODRR; /* Module Routing Register */`
135			`volatile MTST0STR _MTST0; /* MTST0 */`
136			`volatile MTST1STR _MTST1; /* MTST1 */`
137			`volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */`
138			`volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */`
139			`volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */`
140			`volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */`
141			`volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */`
142			`volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */`
143			`volatile PEARSTR _PEAR; /* Port E Assignment Register */`
144			`volatile PERADSTR _PERAD; /* Port AD Pull Device Enable Register */`
145			`volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */`
146			`volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */`
147			`volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */`
148			`volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */`
149			`volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */`
150			`volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */`
151			`volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */`
152			`volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */`
153			`volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */`
154			`volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */`
155			`volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */`
156			`volatile PORTESTR _PORTE; /* Port E Register */`
157			`volatile PORTKSTR _PORTK; /* Port K Data Register */`
158			`volatile PPAGESTR _PPAGE; /* Page Index Register */`
159			`volatile PPSADSTR _PPSAD; /* Port AD Polarity Select Register */`
160			`volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */`
161			`volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */`
162			`volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */`
163			`volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */`
164			`volatile PPSTSTR _PPST; /* Port T Polarity Select Register */`
165			`volatile PTADSTR _PTAD; /* Port AD I/O Register */`
166			`volatile PTIADSTR _PTIAD; /* Port AD Input Register */`
167			`volatile PTIJSTR _PTIJ; /* Port J Input Register */`
168			`volatile PTIMSTR _PTIM; /* Port M Input */`
169			`volatile PTIPSTR _PTIP; /* Port P Input */`
170			`volatile PTISSTR _PTIS; /* Port S Input */`
171			`volatile PTITSTR _PTIT; /* Port T Input */`
172			`volatile PTJSTR _PTJ; /* Port J I/O Register */`
173			`volatile PTMSTR _PTM; /* Port M I/O Register */`
174			`volatile PTPSTR _PTP; /* Port P I/O Register */`
175			`volatile PTSSTR _PTS; /* Port S I/O Register */`
176			`volatile PTTSTR _PTT; /* Port T I/O Register */`
177			`volatile PUCRSTR _PUCR; /* Pull-Up Control Register */`
178			`volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */`
179			`volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */`
180			`volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */`
181			`volatile PWMESTR _PWME; /* PWM Enable Register */`
182			`volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */`
183			`volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */`
184			`volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */`
185			`volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */`
186			`volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */`
187			`volatile RDRADSTR _RDRAD; /* Port AD Reduced Drive Register */`
188			`volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */`
189			`volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */`
190			`volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */`
191			`volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */`
192			`volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */`
193			`volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */`
194			`volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */`
195			`volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */`
196			`volatile SCICR1STR _SCICR1; /* SCI Control Register 1 */`
197			`volatile SCICR2STR _SCICR2; /* SCI Control Register 2 */`
198			`volatile SCIDRHSTR _SCIDRH; /* SCI Data Register High */`
199			`volatile SCIDRLSTR _SCIDRL; /* SCI Data Register Low */`
200			`volatile SCISR1STR _SCISR1; /* SCI Status Register 1 */`
201			`volatile SCISR2STR _SCISR2; /* SCI Status Register 2 */`
202			`volatile SPIBRSTR _SPIBR; /* SPI Baud Rate Register */`
203			`volatile SPICR1STR _SPICR1; /* SPI Control Register */`
204			`volatile SPICR2STR _SPICR2; /* SPI Control Register 2 */`
205			`volatile SPIDRSTR _SPIDR; /* SPI Data Register */`
206			`volatile SPISRSTR _SPISR; /* SPI Status Register */`
207			`volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */`
208			`volatile TCTL1STR _TCTL1; /* Timer Control Register 1 */`
209			`volatile TCTL2STR _TCTL2; /* Timer Control Register 2 */`
210			`volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */`
211			`volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */`
212			`volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */`
213			`volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */`
214			`volatile TIESTR _TIE; /* Timer Interrupt Enable Register */`
215			`volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */`
216			`volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */`
217			`volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */`
218			`volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */`
219			`volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */`
220			`volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */`
221			`volatile ATDCTL23STR _ATDCTL23; /* ATD Control Register 23 */`
222			`volatile ATDCTL45STR _ATDCTL45; /* ATD Control Register 45 */`
223			`volatile ATDDR0STR _ATDDR0; /* A/D Conversion Result Register 0 */`
224			`volatile ATDDR1STR _ATDDR1; /* A/D Conversion Result Register 1 */`
225			`volatile ATDDR2STR _ATDDR2; /* A/D Conversion Result Register 2 */`
226			`volatile ATDDR3STR _ATDDR3; /* A/D Conversion Result Register 3 */`
227			`volatile ATDDR4STR _ATDDR4; /* A/D Conversion Result Register 4 */`
228			`volatile ATDDR5STR _ATDDR5; /* A/D Conversion Result Register 5 */`
229			`volatile ATDDR6STR _ATDDR6; /* A/D Conversion Result Register 6 */`
230			`volatile ATDDR7STR _ATDDR7; /* A/D Conversion Result Register 7 */`
231			`volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */`
232			`volatile PACNTSTR _PACNT; /* Pulse Accumulators Count Register */`
233			`volatile PORTABSTR _PORTAB; /* Port AB Register */`
234			`volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */`
235			`volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */`
236			`volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */`
237			`volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */`
238			`volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */`
239			`volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */`
240			`volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */`
241			`volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */`
242			`volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */`
243			`volatile SCIBDSTR _SCIBD; /* SCI Baud Rate Register */`
244			`volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */`
245			`volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */`
246			`volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */`
247			`volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */`
248			`volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */`
249			`volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */`
250			`volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */`
251			`volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */`
252			`volatile TCNTSTR _TCNT; /* Timer Count Register */`
253			`/*`
254			`** ###################################################################`
255			`**`
256			`** This file was created by UNIS Processor Expert 03.33 for`
257			`** the Motorola HCS12 series of microcontrollers.`
258			`**`
259			`** ###################################################################`
260			`*/`

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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [HCS12_CodeWarrior_small/] [CODE/] [IO_Map.C] - Blame information for rev 588