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jeremybenn |
/** ###################################################################
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** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
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** Filename : IO_Map.C
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** Project : RTOSDemo
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** Processor : MC9S12C32CFU
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** Beantype : IO_Map
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** Version : Driver 01.01
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** Compiler : Metrowerks HC12 C Compiler
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** Date/Time : 10/05/2005, 11:11
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** Abstract :
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** This bean "IO_Map" implements an IO devices mapping.
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** Settings :
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**
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** Contents :
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** No public methods
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**
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** (c) Copyright UNIS, spol. s r.o. 1997-2002
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** UNIS, spol. s r.o.
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** Jundrovska 33
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** 624 00 Brno
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** Czech Republic
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** http : www.processorexpert.com
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** mail : info@processorexpert.com
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** ###################################################################*/
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/* Based on CPU DB MC9S12C32_80, version 2.87.264 */
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#include "PE_types.h"
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#include "IO_Map.h"
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volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */
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volatile ATDDIENSTR _ATDDIEN; /* ATD Input Enable Mask Register */
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volatile ATDSTAT0STR _ATDSTAT0; /* A/D Status Register 0 */
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volatile ATDSTAT1STR _ATDSTAT1; /* A/D Status Register 1 */
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volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */
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volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */
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volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */
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volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */
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volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */
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volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */
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volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */
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volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */
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volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */
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volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */
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volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */
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volatile CANBTR0STR _CANBTR0; /* MSCAN Bus Timing Register 0 */
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volatile CANBTR1STR _CANBTR1; /* MSCAN Bus Timing Register 1 */
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volatile CANCTL0STR _CANCTL0; /* MSCAN Control 0 Register */
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volatile CANCTL1STR _CANCTL1; /* MSCAN Control 1 Register */
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volatile CANIDACSTR _CANIDAC; /* MSCAN Identifier Acceptance Control Register */
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volatile CANIDAR0STR _CANIDAR0; /* MSCAN Identifier Acceptance Register 0 */
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volatile CANIDAR1STR _CANIDAR1; /* MSCAN Identifier Acceptance Register 1 */
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volatile CANIDAR2STR _CANIDAR2; /* MSCAN Identifier Acceptance Register 2 */
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volatile CANIDAR3STR _CANIDAR3; /* MSCAN Identifier Acceptance Register 3 */
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volatile CANIDAR4STR _CANIDAR4; /* MSCAN Identifier Acceptance Register 4 */
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volatile CANIDAR5STR _CANIDAR5; /* MSCAN Identifier Acceptance Register 5 */
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volatile CANIDAR6STR _CANIDAR6; /* MSCAN Identifier Acceptance Register 6 */
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volatile CANIDAR7STR _CANIDAR7; /* MSCAN Identifier Acceptance Register 7 */
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volatile CANIDMR0STR _CANIDMR0; /* MSCAN Identifier Mask Register 0 */
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volatile CANIDMR1STR _CANIDMR1; /* MSCAN Identifier Mask Register 1 */
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volatile CANIDMR2STR _CANIDMR2; /* MSCAN Identifier Mask Register 2 */
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volatile CANIDMR3STR _CANIDMR3; /* MSCAN Identifier Mask Register 3 */
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volatile CANIDMR4STR _CANIDMR4; /* MSCAN Identifier Mask Register 4 */
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volatile CANIDMR5STR _CANIDMR5; /* MSCAN Identifier Mask Register 5 */
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volatile CANIDMR6STR _CANIDMR6; /* MSCAN Identifier Mask Register 6 */
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volatile CANIDMR7STR _CANIDMR7; /* MSCAN Identifier Mask Register 7 */
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volatile CANRFLGSTR _CANRFLG; /* MSCAN Receiver Flag Register */
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volatile CANRIERSTR _CANRIER; /* MSCAN Receiver Interrupt Enable Register */
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volatile CANRXDLRSTR _CANRXDLR; /* MSCAN Receive Data Length Register */
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volatile CANRXDSR0STR _CANRXDSR0; /* MSCAN Receive Data Segment Register 0 */
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volatile CANRXDSR1STR _CANRXDSR1; /* MSCAN Receive Data Segment Register 1 */
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volatile CANRXDSR2STR _CANRXDSR2; /* MSCAN Receive Data Segment Register 2 */
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volatile CANRXDSR3STR _CANRXDSR3; /* MSCAN Receive Data Segment Register 3 */
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volatile CANRXDSR4STR _CANRXDSR4; /* MSCAN Receive Data Segment Register 4 */
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volatile CANRXDSR5STR _CANRXDSR5; /* MSCAN Receive Data Segment Register 5 */
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volatile CANRXDSR6STR _CANRXDSR6; /* MSCAN Receive Data Segment Register 6 */
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volatile CANRXDSR7STR _CANRXDSR7; /* MSCAN Receive Data Segment Register 7 */
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volatile CANRXERRSTR _CANRXERR; /* MSCAN Receive Error Counter Register */
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volatile CANRXIDR0STR _CANRXIDR0; /* MSCAN Receive Identifier Register 0 */
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volatile CANRXIDR1STR _CANRXIDR1; /* MSCAN Receive Identifier Register 1 */
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volatile CANRXIDR2STR _CANRXIDR2; /* MSCAN Receive Identifier Register 2 */
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volatile CANRXIDR3STR _CANRXIDR3; /* MSCAN Receive Identifier Register 3 */
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volatile CANTAAKSTR _CANTAAK; /* MSCAN Transmitter Message Abort Control */
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volatile CANTARQSTR _CANTARQ; /* MSCAN Transmitter Message Abort Request */
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volatile CANTBSELSTR _CANTBSEL; /* MSCAN Transmit Buffer Selection */
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volatile CANTFLGSTR _CANTFLG; /* MSCAN Transmitter Flag Register */
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volatile CANTIERSTR _CANTIER; /* MSCAN Transmitter Interrupt Enable Register */
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volatile CANTXDLRSTR _CANTXDLR; /* MSCAN Transmit Data Length Register */
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volatile CANTXDSR0STR _CANTXDSR0; /* MSCAN Transmit Data Segment Register 0 */
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volatile CANTXDSR1STR _CANTXDSR1; /* MSCAN Transmit Data Segment Register 1 */
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volatile CANTXDSR2STR _CANTXDSR2; /* MSCAN Transmit Data Segment Register 2 */
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volatile CANTXDSR3STR _CANTXDSR3; /* MSCAN Transmit Data Segment Register 3 */
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volatile CANTXDSR4STR _CANTXDSR4; /* MSCAN Transmit Data Segment Register 4 */
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volatile CANTXDSR5STR _CANTXDSR5; /* MSCAN Transmit Data Segment Register 5 */
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volatile CANTXDSR6STR _CANTXDSR6; /* MSCAN Transmit Data Segment Register 6 */
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volatile CANTXDSR7STR _CANTXDSR7; /* MSCAN Transmit Data Segment Register 7 */
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volatile CANTXERRSTR _CANTXERR; /* MSCAN Transmit Error Counter Register */
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volatile CANTXIDR0STR _CANTXIDR0; /* MSCAN Transmit Identifier Register 0 */
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volatile CANTXIDR1STR _CANTXIDR1; /* MSCAN Transmit Identifier Register 1 */
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volatile CANTXIDR2STR _CANTXIDR2; /* MSCAN Transmit Identifier Register 2 */
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volatile CANTXIDR3STR _CANTXIDR3; /* MSCAN Transmit Identifier Register 3 */
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volatile CANTXTBPRSTR _CANTXTBPR; /* MSCAN Transmit Buffer Priority */
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volatile CFORCSTR _CFORC; /* Timer Compare Force Register */
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volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */
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volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */
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volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */
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volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */
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volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */
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volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */
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volatile DDRADSTR _DDRAD; /* Port AD Data Direction Register */
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volatile DDRESTR _DDRE; /* Port E Data Direction Register */
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volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */
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volatile DDRKSTR _DDRK; /* Port K Data Direction Register */
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volatile DDRMSTR _DDRM; /* Port M Data Direction Register */
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volatile DDRPSTR _DDRP; /* Port P Data Direction Register */
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volatile DDRSSTR _DDRS; /* Port S Data Direction Register */
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volatile DDRTSTR _DDRT; /* Port T Data Direction Register */
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volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */
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volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */
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volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */
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volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */
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volatile FPROTSTR _FPROT; /* Flash Protection Register */
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volatile FSECSTR _FSEC; /* Flash Security Register */
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volatile FSTATSTR _FSTAT; /* Flash Status Register */
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volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */
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volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */
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volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */
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volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */
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volatile INTCRSTR _INTCR; /* Interrupt Control Register */
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volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */
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volatile ITESTSTR _ITEST; /* Interrupt Test Register */
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volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */
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volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */
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volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */
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volatile MODESTR _MODE; /* Mode Register */
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volatile MODRRSTR _MODRR; /* Module Routing Register */
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volatile MTST0STR _MTST0; /* MTST0 */
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volatile MTST1STR _MTST1; /* MTST1 */
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volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */
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volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */
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volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */
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volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */
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volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */
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volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */
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volatile PEARSTR _PEAR; /* Port E Assignment Register */
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volatile PERADSTR _PERAD; /* Port AD Pull Device Enable Register */
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volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */
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volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */
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volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */
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volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */
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volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */
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volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */
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volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */
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volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */
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volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */
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volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */
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volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */
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volatile PORTESTR _PORTE; /* Port E Register */
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volatile PORTKSTR _PORTK; /* Port K Data Register */
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volatile PPAGESTR _PPAGE; /* Page Index Register */
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volatile PPSADSTR _PPSAD; /* Port AD Polarity Select Register */
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volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */
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volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */
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volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */
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volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */
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volatile PPSTSTR _PPST; /* Port T Polarity Select Register */
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volatile PTADSTR _PTAD; /* Port AD I/O Register */
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volatile PTIADSTR _PTIAD; /* Port AD Input Register */
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volatile PTIJSTR _PTIJ; /* Port J Input Register */
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volatile PTIMSTR _PTIM; /* Port M Input */
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volatile PTIPSTR _PTIP; /* Port P Input */
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volatile PTISSTR _PTIS; /* Port S Input */
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volatile PTITSTR _PTIT; /* Port T Input */
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volatile PTJSTR _PTJ; /* Port J I/O Register */
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volatile PTMSTR _PTM; /* Port M I/O Register */
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volatile PTPSTR _PTP; /* Port P I/O Register */
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volatile PTSSTR _PTS; /* Port S I/O Register */
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volatile PTTSTR _PTT; /* Port T I/O Register */
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volatile PUCRSTR _PUCR; /* Pull-Up Control Register */
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volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */
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volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */
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volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */
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volatile PWMESTR _PWME; /* PWM Enable Register */
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volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */
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volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */
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volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */
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volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */
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volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */
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volatile RDRADSTR _RDRAD; /* Port AD Reduced Drive Register */
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volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */
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volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */
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volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */
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volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */
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volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */
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volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */
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volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */
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volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */
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volatile SCICR1STR _SCICR1; /* SCI Control Register 1 */
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volatile SCICR2STR _SCICR2; /* SCI Control Register 2 */
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volatile SCIDRHSTR _SCIDRH; /* SCI Data Register High */
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volatile SCIDRLSTR _SCIDRL; /* SCI Data Register Low */
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volatile SCISR1STR _SCISR1; /* SCI Status Register 1 */
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volatile SCISR2STR _SCISR2; /* SCI Status Register 2 */
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volatile SPIBRSTR _SPIBR; /* SPI Baud Rate Register */
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volatile SPICR1STR _SPICR1; /* SPI Control Register */
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volatile SPICR2STR _SPICR2; /* SPI Control Register 2 */
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volatile SPIDRSTR _SPIDR; /* SPI Data Register */
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volatile SPISRSTR _SPISR; /* SPI Status Register */
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| 207 |
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volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */
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| 208 |
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volatile TCTL1STR _TCTL1; /* Timer Control Register 1 */
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| 209 |
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volatile TCTL2STR _TCTL2; /* Timer Control Register 2 */
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| 210 |
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volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */
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| 211 |
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volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */
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| 212 |
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volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */
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| 213 |
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volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */
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volatile TIESTR _TIE; /* Timer Interrupt Enable Register */
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| 215 |
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volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */
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| 216 |
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volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */
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| 217 |
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volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */
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| 218 |
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volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */
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| 219 |
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volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */
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| 220 |
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volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */
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| 221 |
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volatile ATDCTL23STR _ATDCTL23; /* ATD Control Register 23 */
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| 222 |
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volatile ATDCTL45STR _ATDCTL45; /* ATD Control Register 45 */
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| 223 |
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volatile ATDDR0STR _ATDDR0; /* A/D Conversion Result Register 0 */
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| 224 |
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volatile ATDDR1STR _ATDDR1; /* A/D Conversion Result Register 1 */
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| 225 |
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volatile ATDDR2STR _ATDDR2; /* A/D Conversion Result Register 2 */
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| 226 |
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volatile ATDDR3STR _ATDDR3; /* A/D Conversion Result Register 3 */
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| 227 |
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volatile ATDDR4STR _ATDDR4; /* A/D Conversion Result Register 4 */
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| 228 |
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volatile ATDDR5STR _ATDDR5; /* A/D Conversion Result Register 5 */
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| 229 |
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volatile ATDDR6STR _ATDDR6; /* A/D Conversion Result Register 6 */
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| 230 |
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volatile ATDDR7STR _ATDDR7; /* A/D Conversion Result Register 7 */
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| 231 |
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volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */
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| 232 |
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volatile PACNTSTR _PACNT; /* Pulse Accumulators Count Register */
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| 233 |
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volatile PORTABSTR _PORTAB; /* Port AB Register */
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| 234 |
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volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */
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| 235 |
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volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */
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| 236 |
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volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */
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| 237 |
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volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */
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| 238 |
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volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */
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| 239 |
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volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */
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| 240 |
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volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */
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| 241 |
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volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */
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| 242 |
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volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */
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| 243 |
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volatile SCIBDSTR _SCIBD; /* SCI Baud Rate Register */
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| 244 |
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volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */
|
| 245 |
|
|
volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */
|
| 246 |
|
|
volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */
|
| 247 |
|
|
volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */
|
| 248 |
|
|
volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */
|
| 249 |
|
|
volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */
|
| 250 |
|
|
volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */
|
| 251 |
|
|
volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */
|
| 252 |
|
|
volatile TCNTSTR _TCNT; /* Timer Count Register */
|
| 253 |
|
|
/*
|
| 254 |
|
|
** ###################################################################
|
| 255 |
|
|
**
|
| 256 |
|
|
** This file was created by UNIS Processor Expert 03.33 for
|
| 257 |
|
|
** the Motorola HCS12 series of microcontrollers.
|
| 258 |
|
|
**
|
| 259 |
|
|
** ###################################################################
|
| 260 |
|
|
*/
|
