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jeremybenn |
/** ###################################################################
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** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
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** Filename : IO_Map.H
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** Project : RTOSDemo
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** Processor : MC9S12C32CFU
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** Beantype : IO_Map
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** Version : Driver 01.01
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** Compiler : Metrowerks HC12 C Compiler
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** Date/Time : 10/05/2005, 11:11
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** Abstract :
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** This bean "IO_Map" implements an IO devices mapping.
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** Settings :
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**
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** Contents :
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** No public methods
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**
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** (c) Copyright UNIS, spol. s r.o. 1997-2002
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** UNIS, spol. s r.o.
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** Jundrovska 33
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** 624 00 Brno
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** Czech Republic
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** http : www.processorexpert.com
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** mail : info@processorexpert.com
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** ###################################################################*/
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/* Linker pragmas */
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#pragma LINK_INFO DERIVATIVE "MC9S12C32"
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#pragma LINK_INFO OSCFREQUENCY "16000000"
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#define REG_BASE 0x0000 /* Base address for the I/O register block */
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/* Based on CPU DB MC9S12C32_80, version 2.87.264 (RegistersPrg V1.027) */
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#ifndef _MC9S12C32_80_H
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#define _MC9S12C32_80_H
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#include "PE_Types.h"
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#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */
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/*********************************************/
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/* */
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/* PE I/O map format */
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/* */
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/*********************************************/
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/*** PORTAB - Port AB Register; 0x00000000 ***/
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typedef union {
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word Word;
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/* Overlapped registers: */
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struct {
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/*** PORTA - Port A Register; 0x00000000 ***/
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union {
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byte Byte;
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struct {
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byte BIT0 :1; /* Port A Bit 0 */
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byte BIT1 :1; /* Port A Bit 1 */
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byte BIT2 :1; /* Port A Bit 2 */
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byte BIT3 :1; /* Port A Bit 3 */
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byte BIT4 :1; /* Port A Bit 4 */
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byte BIT5 :1; /* Port A Bit 5 */
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byte BIT6 :1; /* Port A Bit 6 */
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byte BIT7 :1; /* Port A Bit 7 */
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} Bits;
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struct {
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byte grpBIT :8;
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} MergedBits;
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} PORTASTR;
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#define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte
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#define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0
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#define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1
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#define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2
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#define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3
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#define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4
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#define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5
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#define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6
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#define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7
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#define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT
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/*** PORTB - Port B Register; 0x00000001 ***/
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union {
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byte Byte;
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struct {
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byte BIT0 :1; /* Port B Bit 0 */
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byte BIT1 :1; /* Port B Bit 1 */
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byte BIT2 :1; /* Port B Bit 2 */
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byte BIT3 :1; /* Port B Bit 3 */
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byte BIT4 :1; /* Port B Bit 4 */
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byte BIT5 :1; /* Port B Bit 5 */
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byte BIT6 :1; /* Port B Bit 6 */
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byte BIT7 :1; /* Port B Bit 7 */
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} Bits;
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struct {
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byte grpBIT :8;
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} MergedBits;
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} PORTBSTR;
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#define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte
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#define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0
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#define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1
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#define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2
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#define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3
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#define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4
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#define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5
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#define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6
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#define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7
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#define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT
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} Overlap_STR;
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struct {
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word BIT0 :1; /* Port AB Bit 0 */
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word BIT1 :1; /* Port AB Bit 1 */
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word BIT2 :1; /* Port AB Bit 2 */
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word BIT3 :1; /* Port AB Bit 3 */
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word BIT4 :1; /* Port AB Bit 4 */
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word BIT5 :1; /* Port AB Bit 5 */
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word BIT6 :1; /* Port AB Bit 6 */
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word BIT7 :1; /* Port AB Bit 7 */
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word BIT8 :1; /* Port AB Bit 8 */
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word BIT9 :1; /* Port AB Bit 9 */
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word BIT10 :1; /* Port AB Bit 10 */
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word BIT11 :1; /* Port AB Bit 11 */
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word BIT12 :1; /* Port AB Bit 12 */
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word BIT13 :1; /* Port AB Bit 13 */
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word BIT14 :1; /* Port AB Bit 14 */
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word BIT15 :1; /* Port AB Bit 15 */
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} Bits;
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struct {
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word grpBIT :16;
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} MergedBits;
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} PORTABSTR;
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extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000);
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#define PORTAB _PORTAB.Word
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#define PORTAB_BIT0 _PORTAB.Bits.BIT0
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#define PORTAB_BIT1 _PORTAB.Bits.BIT1
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#define PORTAB_BIT2 _PORTAB.Bits.BIT2
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#define PORTAB_BIT3 _PORTAB.Bits.BIT3
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#define PORTAB_BIT4 _PORTAB.Bits.BIT4
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#define PORTAB_BIT5 _PORTAB.Bits.BIT5
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#define PORTAB_BIT6 _PORTAB.Bits.BIT6
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#define PORTAB_BIT7 _PORTAB.Bits.BIT7
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#define PORTAB_BIT8 _PORTAB.Bits.BIT8
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#define PORTAB_BIT9 _PORTAB.Bits.BIT9
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#define PORTAB_BIT10 _PORTAB.Bits.BIT10
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#define PORTAB_BIT11 _PORTAB.Bits.BIT11
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#define PORTAB_BIT12 _PORTAB.Bits.BIT12
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#define PORTAB_BIT13 _PORTAB.Bits.BIT13
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#define PORTAB_BIT14 _PORTAB.Bits.BIT14
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#define PORTAB_BIT15 _PORTAB.Bits.BIT15
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#define PORTAB_BIT _PORTAB.MergedBits.grpBIT
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/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/
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typedef union {
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word Word;
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/* Overlapped registers: */
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struct {
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/*** DDRA - Port A Data Direction Register; 0x00000002 ***/
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union {
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byte Byte;
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struct {
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byte BIT0 :1; /* Data Direction Port A Bit 0 */
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byte BIT1 :1; /* Data Direction Port A Bit 1 */
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byte BIT2 :1; /* Data Direction Port A Bit 2 */
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byte BIT3 :1; /* Data Direction Port A Bit 3 */
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byte BIT4 :1; /* Data Direction Port A Bit 4 */
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byte BIT5 :1; /* Data Direction Port A Bit 5 */
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byte BIT6 :1; /* Data Direction Port A Bit 6 */
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byte BIT7 :1; /* Data Direction Port A Bit 7 */
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} Bits;
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struct {
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byte grpBIT :8;
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} MergedBits;
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} DDRASTR;
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#define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte
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#define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0
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#define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1
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#define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2
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#define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3
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#define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4
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#define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5
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#define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6
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#define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7
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#define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT
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/*** DDRB - Port B Data Direction Register; 0x00000003 ***/
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union {
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byte Byte;
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struct {
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byte BIT0 :1; /* Data Direction Port B Bit 0 */
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byte BIT1 :1; /* Data Direction Port B Bit 1 */
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byte BIT2 :1; /* Data Direction Port B Bit 2 */
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byte BIT3 :1; /* Data Direction Port B Bit 3 */
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byte BIT4 :1; /* Data Direction Port B Bit 4 */
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byte BIT5 :1; /* Data Direction Port B Bit 5 */
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byte BIT6 :1; /* Data Direction Port B Bit 6 */
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byte BIT7 :1; /* Data Direction Port B Bit 7 */
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} Bits;
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struct {
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byte grpBIT :8;
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} MergedBits;
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} DDRBSTR;
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#define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte
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#define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0
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#define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1
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#define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2
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#define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3
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#define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4
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#define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5
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#define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6
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#define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7
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#define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT
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} Overlap_STR;
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struct {
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word BIT0 :1; /* Data Direction Port B Bit 0 */
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word BIT1 :1; /* Data Direction Port B Bit 1 */
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word BIT2 :1; /* Data Direction Port B Bit 2 */
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word BIT3 :1; /* Data Direction Port B Bit 3 */
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word BIT4 :1; /* Data Direction Port B Bit 4 */
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word BIT5 :1; /* Data Direction Port B Bit 5 */
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word BIT6 :1; /* Data Direction Port B Bit 6 */
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word BIT7 :1; /* Data Direction Port B Bit 7 */
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word BIT8 :1; /* Data Direction Port A Bit 8 */
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word BIT9 :1; /* Data Direction Port A Bit 9 */
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word BIT10 :1; /* Data Direction Port A Bit 10 */
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word BIT11 :1; /* Data Direction Port A Bit 11 */
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word BIT12 :1; /* Data Direction Port A Bit 12 */
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word BIT13 :1; /* Data Direction Port A Bit 13 */
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word BIT14 :1; /* Data Direction Port A Bit 14 */
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word BIT15 :1; /* Data Direction Port A Bit 15 */
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} Bits;
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struct {
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word grpBIT :16;
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} MergedBits;
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} DDRABSTR;
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extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);
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#define DDRAB _DDRAB.Word
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#define DDRAB_BIT0 _DDRAB.Bits.BIT0
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#define DDRAB_BIT1 _DDRAB.Bits.BIT1
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#define DDRAB_BIT2 _DDRAB.Bits.BIT2
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#define DDRAB_BIT3 _DDRAB.Bits.BIT3
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#define DDRAB_BIT4 _DDRAB.Bits.BIT4
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#define DDRAB_BIT5 _DDRAB.Bits.BIT5
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#define DDRAB_BIT6 _DDRAB.Bits.BIT6
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#define DDRAB_BIT7 _DDRAB.Bits.BIT7
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#define DDRAB_BIT8 _DDRAB.Bits.BIT8
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#define DDRAB_BIT9 _DDRAB.Bits.BIT9
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#define DDRAB_BIT10 _DDRAB.Bits.BIT10
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#define DDRAB_BIT11 _DDRAB.Bits.BIT11
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#define DDRAB_BIT12 _DDRAB.Bits.BIT12
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#define DDRAB_BIT13 _DDRAB.Bits.BIT13
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#define DDRAB_BIT14 _DDRAB.Bits.BIT14
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#define DDRAB_BIT15 _DDRAB.Bits.BIT15
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#define DDRAB_BIT _DDRAB.MergedBits.grpBIT
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| 258 |
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| 259 |
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/*** TCNT - Timer Count Register; 0x00000044 ***/
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| 260 |
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typedef union {
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| 261 |
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word Word;
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| 262 |
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/* Overlapped registers: */
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| 263 |
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struct {
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| 264 |
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/*** TCNTHi - Timer Count Register High; 0x00000044 ***/
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| 265 |
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union {
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| 266 |
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byte Byte;
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| 267 |
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struct {
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| 268 |
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byte BIT15 :1; /* Timer Count Register Bit 15 */
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| 269 |
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byte BIT14 :1; /* Timer Count Register Bit 14 */
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| 270 |
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byte BIT13 :1; /* Timer Count Register Bit 13 */
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| 271 |
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byte BIT12 :1; /* Timer Count Register Bit 12 */
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| 272 |
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byte BIT11 :1; /* Timer Count Register Bit 11 */
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| 273 |
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byte BIT10 :1; /* Timer Count Register Bit 10 */
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| 274 |
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byte BIT9 :1; /* Timer Count Register Bit 9 */
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| 275 |
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byte BIT8 :1; /* Timer Count Register Bit 8 */
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| 276 |
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} Bits;
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| 277 |
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} TCNTHiSTR;
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| 278 |
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#define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte
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| 279 |
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#define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15
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| 280 |
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#define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14
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| 281 |
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#define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13
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| 282 |
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#define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12
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| 283 |
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#define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11
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| 284 |
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#define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10
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| 285 |
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#define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9
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| 286 |
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#define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8
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| 287 |
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| 288 |
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/*** TCNTLo - Timer Count Register Low; 0x00000045 ***/
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| 289 |
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union {
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| 290 |
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byte Byte;
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| 291 |
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struct {
|
| 292 |
|
|
byte BIT0 :1; /* Timer Count Register Bit 0 */
|
| 293 |
|
|
byte BIT1 :1; /* Timer Count Register Bit 1 */
|
| 294 |
|
|
byte BIT2 :1; /* Timer Count Register Bit 2 */
|
| 295 |
|
|
byte BIT3 :1; /* Timer Count Register Bit 3 */
|
| 296 |
|
|
byte BIT4 :1; /* Timer Count Bit Register 4 */
|
| 297 |
|
|
byte BIT5 :1; /* Timer Count Bit Register 5 */
|
| 298 |
|
|
byte BIT6 :1; /* Timer Count Bit Register 6 */
|
| 299 |
|
|
byte BIT7 :1; /* Timer Count Bit Register 7 */
|
| 300 |
|
|
} Bits;
|
| 301 |
|
|
struct {
|
| 302 |
|
|
byte grpBIT :8;
|
| 303 |
|
|
} MergedBits;
|
| 304 |
|
|
} TCNTLoSTR;
|
| 305 |
|
|
#define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte
|
| 306 |
|
|
#define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0
|
| 307 |
|
|
#define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1
|
| 308 |
|
|
#define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2
|
| 309 |
|
|
#define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3
|
| 310 |
|
|
#define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4
|
| 311 |
|
|
#define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5
|
| 312 |
|
|
#define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6
|
| 313 |
|
|
#define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7
|
| 314 |
|
|
#define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT
|
| 315 |
|
|
|
| 316 |
|
|
} Overlap_STR;
|
| 317 |
|
|
|
| 318 |
|
|
struct {
|
| 319 |
|
|
word grpBIT :16;
|
| 320 |
|
|
} MergedBits;
|
| 321 |
|
|
} TCNTSTR;
|
| 322 |
|
|
extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044);
|
| 323 |
|
|
#define TCNT _TCNT.Word
|
| 324 |
|
|
#define TCNT_BIT _TCNT.MergedBits.grpBIT
|
| 325 |
|
|
|
| 326 |
|
|
|
| 327 |
|
|
/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/
|
| 328 |
|
|
typedef union {
|
| 329 |
|
|
word Word;
|
| 330 |
|
|
/* Overlapped registers: */
|
| 331 |
|
|
struct {
|
| 332 |
|
|
/*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/
|
| 333 |
|
|
union {
|
| 334 |
|
|
byte Byte;
|
| 335 |
|
|
struct {
|
| 336 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */
|
| 337 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */
|
| 338 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */
|
| 339 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */
|
| 340 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */
|
| 341 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */
|
| 342 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */
|
| 343 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */
|
| 344 |
|
|
} Bits;
|
| 345 |
|
|
struct {
|
| 346 |
|
|
byte grpBIT_8 :8;
|
| 347 |
|
|
} MergedBits;
|
| 348 |
|
|
} TC0HiSTR;
|
| 349 |
|
|
#define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte
|
| 350 |
|
|
#define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8
|
| 351 |
|
|
#define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9
|
| 352 |
|
|
#define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10
|
| 353 |
|
|
#define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11
|
| 354 |
|
|
#define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12
|
| 355 |
|
|
#define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13
|
| 356 |
|
|
#define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14
|
| 357 |
|
|
#define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15
|
| 358 |
|
|
#define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8
|
| 359 |
|
|
#define TC0Hi_BIT TC0Hi_BIT_8
|
| 360 |
|
|
|
| 361 |
|
|
/*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/
|
| 362 |
|
|
union {
|
| 363 |
|
|
byte Byte;
|
| 364 |
|
|
struct {
|
| 365 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */
|
| 366 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */
|
| 367 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */
|
| 368 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */
|
| 369 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */
|
| 370 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */
|
| 371 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */
|
| 372 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */
|
| 373 |
|
|
} Bits;
|
| 374 |
|
|
struct {
|
| 375 |
|
|
byte grpBIT :8;
|
| 376 |
|
|
} MergedBits;
|
| 377 |
|
|
} TC0LoSTR;
|
| 378 |
|
|
#define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte
|
| 379 |
|
|
#define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0
|
| 380 |
|
|
#define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1
|
| 381 |
|
|
#define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2
|
| 382 |
|
|
#define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3
|
| 383 |
|
|
#define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4
|
| 384 |
|
|
#define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5
|
| 385 |
|
|
#define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6
|
| 386 |
|
|
#define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7
|
| 387 |
|
|
#define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT
|
| 388 |
|
|
|
| 389 |
|
|
} Overlap_STR;
|
| 390 |
|
|
|
| 391 |
|
|
struct {
|
| 392 |
|
|
word grpBIT :16;
|
| 393 |
|
|
} MergedBits;
|
| 394 |
|
|
} TC0STR;
|
| 395 |
|
|
extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050);
|
| 396 |
|
|
#define TC0 _TC0.Word
|
| 397 |
|
|
#define TC0_BIT _TC0.MergedBits.grpBIT
|
| 398 |
|
|
|
| 399 |
|
|
|
| 400 |
|
|
/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/
|
| 401 |
|
|
typedef union {
|
| 402 |
|
|
word Word;
|
| 403 |
|
|
/* Overlapped registers: */
|
| 404 |
|
|
struct {
|
| 405 |
|
|
/*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/
|
| 406 |
|
|
union {
|
| 407 |
|
|
byte Byte;
|
| 408 |
|
|
struct {
|
| 409 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */
|
| 410 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */
|
| 411 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */
|
| 412 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */
|
| 413 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */
|
| 414 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */
|
| 415 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */
|
| 416 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */
|
| 417 |
|
|
} Bits;
|
| 418 |
|
|
struct {
|
| 419 |
|
|
byte grpBIT_8 :8;
|
| 420 |
|
|
} MergedBits;
|
| 421 |
|
|
} TC1HiSTR;
|
| 422 |
|
|
#define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte
|
| 423 |
|
|
#define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8
|
| 424 |
|
|
#define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9
|
| 425 |
|
|
#define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10
|
| 426 |
|
|
#define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11
|
| 427 |
|
|
#define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12
|
| 428 |
|
|
#define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13
|
| 429 |
|
|
#define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14
|
| 430 |
|
|
#define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15
|
| 431 |
|
|
#define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8
|
| 432 |
|
|
#define TC1Hi_BIT TC1Hi_BIT_8
|
| 433 |
|
|
|
| 434 |
|
|
/*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/
|
| 435 |
|
|
union {
|
| 436 |
|
|
byte Byte;
|
| 437 |
|
|
struct {
|
| 438 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */
|
| 439 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */
|
| 440 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */
|
| 441 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */
|
| 442 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */
|
| 443 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */
|
| 444 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */
|
| 445 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */
|
| 446 |
|
|
} Bits;
|
| 447 |
|
|
struct {
|
| 448 |
|
|
byte grpBIT :8;
|
| 449 |
|
|
} MergedBits;
|
| 450 |
|
|
} TC1LoSTR;
|
| 451 |
|
|
#define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte
|
| 452 |
|
|
#define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0
|
| 453 |
|
|
#define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1
|
| 454 |
|
|
#define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2
|
| 455 |
|
|
#define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3
|
| 456 |
|
|
#define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4
|
| 457 |
|
|
#define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5
|
| 458 |
|
|
#define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6
|
| 459 |
|
|
#define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7
|
| 460 |
|
|
#define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT
|
| 461 |
|
|
|
| 462 |
|
|
} Overlap_STR;
|
| 463 |
|
|
|
| 464 |
|
|
struct {
|
| 465 |
|
|
word grpBIT :16;
|
| 466 |
|
|
} MergedBits;
|
| 467 |
|
|
} TC1STR;
|
| 468 |
|
|
extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052);
|
| 469 |
|
|
#define TC1 _TC1.Word
|
| 470 |
|
|
#define TC1_BIT _TC1.MergedBits.grpBIT
|
| 471 |
|
|
|
| 472 |
|
|
|
| 473 |
|
|
/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/
|
| 474 |
|
|
typedef union {
|
| 475 |
|
|
word Word;
|
| 476 |
|
|
/* Overlapped registers: */
|
| 477 |
|
|
struct {
|
| 478 |
|
|
/*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/
|
| 479 |
|
|
union {
|
| 480 |
|
|
byte Byte;
|
| 481 |
|
|
struct {
|
| 482 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */
|
| 483 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */
|
| 484 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */
|
| 485 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */
|
| 486 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */
|
| 487 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */
|
| 488 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */
|
| 489 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */
|
| 490 |
|
|
} Bits;
|
| 491 |
|
|
struct {
|
| 492 |
|
|
byte grpBIT_8 :8;
|
| 493 |
|
|
} MergedBits;
|
| 494 |
|
|
} TC2HiSTR;
|
| 495 |
|
|
#define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte
|
| 496 |
|
|
#define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8
|
| 497 |
|
|
#define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9
|
| 498 |
|
|
#define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10
|
| 499 |
|
|
#define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11
|
| 500 |
|
|
#define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12
|
| 501 |
|
|
#define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13
|
| 502 |
|
|
#define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14
|
| 503 |
|
|
#define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15
|
| 504 |
|
|
#define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8
|
| 505 |
|
|
#define TC2Hi_BIT TC2Hi_BIT_8
|
| 506 |
|
|
|
| 507 |
|
|
/*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/
|
| 508 |
|
|
union {
|
| 509 |
|
|
byte Byte;
|
| 510 |
|
|
struct {
|
| 511 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */
|
| 512 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */
|
| 513 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */
|
| 514 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */
|
| 515 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */
|
| 516 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */
|
| 517 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */
|
| 518 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */
|
| 519 |
|
|
} Bits;
|
| 520 |
|
|
struct {
|
| 521 |
|
|
byte grpBIT :8;
|
| 522 |
|
|
} MergedBits;
|
| 523 |
|
|
} TC2LoSTR;
|
| 524 |
|
|
#define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte
|
| 525 |
|
|
#define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0
|
| 526 |
|
|
#define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1
|
| 527 |
|
|
#define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2
|
| 528 |
|
|
#define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3
|
| 529 |
|
|
#define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4
|
| 530 |
|
|
#define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5
|
| 531 |
|
|
#define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6
|
| 532 |
|
|
#define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7
|
| 533 |
|
|
#define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT
|
| 534 |
|
|
|
| 535 |
|
|
} Overlap_STR;
|
| 536 |
|
|
|
| 537 |
|
|
struct {
|
| 538 |
|
|
word grpBIT :16;
|
| 539 |
|
|
} MergedBits;
|
| 540 |
|
|
} TC2STR;
|
| 541 |
|
|
extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054);
|
| 542 |
|
|
#define TC2 _TC2.Word
|
| 543 |
|
|
#define TC2_BIT _TC2.MergedBits.grpBIT
|
| 544 |
|
|
|
| 545 |
|
|
|
| 546 |
|
|
/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/
|
| 547 |
|
|
typedef union {
|
| 548 |
|
|
word Word;
|
| 549 |
|
|
/* Overlapped registers: */
|
| 550 |
|
|
struct {
|
| 551 |
|
|
/*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/
|
| 552 |
|
|
union {
|
| 553 |
|
|
byte Byte;
|
| 554 |
|
|
struct {
|
| 555 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */
|
| 556 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */
|
| 557 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */
|
| 558 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */
|
| 559 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */
|
| 560 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */
|
| 561 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */
|
| 562 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */
|
| 563 |
|
|
} Bits;
|
| 564 |
|
|
struct {
|
| 565 |
|
|
byte grpBIT_8 :8;
|
| 566 |
|
|
} MergedBits;
|
| 567 |
|
|
} TC3HiSTR;
|
| 568 |
|
|
#define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte
|
| 569 |
|
|
#define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8
|
| 570 |
|
|
#define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9
|
| 571 |
|
|
#define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10
|
| 572 |
|
|
#define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11
|
| 573 |
|
|
#define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12
|
| 574 |
|
|
#define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13
|
| 575 |
|
|
#define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14
|
| 576 |
|
|
#define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15
|
| 577 |
|
|
#define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8
|
| 578 |
|
|
#define TC3Hi_BIT TC3Hi_BIT_8
|
| 579 |
|
|
|
| 580 |
|
|
/*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/
|
| 581 |
|
|
union {
|
| 582 |
|
|
byte Byte;
|
| 583 |
|
|
struct {
|
| 584 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */
|
| 585 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */
|
| 586 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */
|
| 587 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */
|
| 588 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */
|
| 589 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */
|
| 590 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */
|
| 591 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */
|
| 592 |
|
|
} Bits;
|
| 593 |
|
|
struct {
|
| 594 |
|
|
byte grpBIT :8;
|
| 595 |
|
|
} MergedBits;
|
| 596 |
|
|
} TC3LoSTR;
|
| 597 |
|
|
#define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte
|
| 598 |
|
|
#define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0
|
| 599 |
|
|
#define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1
|
| 600 |
|
|
#define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2
|
| 601 |
|
|
#define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3
|
| 602 |
|
|
#define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4
|
| 603 |
|
|
#define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5
|
| 604 |
|
|
#define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6
|
| 605 |
|
|
#define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7
|
| 606 |
|
|
#define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT
|
| 607 |
|
|
|
| 608 |
|
|
} Overlap_STR;
|
| 609 |
|
|
|
| 610 |
|
|
struct {
|
| 611 |
|
|
word grpBIT :16;
|
| 612 |
|
|
} MergedBits;
|
| 613 |
|
|
} TC3STR;
|
| 614 |
|
|
extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056);
|
| 615 |
|
|
#define TC3 _TC3.Word
|
| 616 |
|
|
#define TC3_BIT _TC3.MergedBits.grpBIT
|
| 617 |
|
|
|
| 618 |
|
|
|
| 619 |
|
|
/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/
|
| 620 |
|
|
typedef union {
|
| 621 |
|
|
word Word;
|
| 622 |
|
|
/* Overlapped registers: */
|
| 623 |
|
|
struct {
|
| 624 |
|
|
/*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/
|
| 625 |
|
|
union {
|
| 626 |
|
|
byte Byte;
|
| 627 |
|
|
struct {
|
| 628 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */
|
| 629 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */
|
| 630 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */
|
| 631 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */
|
| 632 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */
|
| 633 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */
|
| 634 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */
|
| 635 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */
|
| 636 |
|
|
} Bits;
|
| 637 |
|
|
struct {
|
| 638 |
|
|
byte grpBIT_8 :8;
|
| 639 |
|
|
} MergedBits;
|
| 640 |
|
|
} TC4HiSTR;
|
| 641 |
|
|
#define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte
|
| 642 |
|
|
#define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8
|
| 643 |
|
|
#define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9
|
| 644 |
|
|
#define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10
|
| 645 |
|
|
#define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11
|
| 646 |
|
|
#define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12
|
| 647 |
|
|
#define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13
|
| 648 |
|
|
#define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14
|
| 649 |
|
|
#define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15
|
| 650 |
|
|
#define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8
|
| 651 |
|
|
#define TC4Hi_BIT TC4Hi_BIT_8
|
| 652 |
|
|
|
| 653 |
|
|
/*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/
|
| 654 |
|
|
union {
|
| 655 |
|
|
byte Byte;
|
| 656 |
|
|
struct {
|
| 657 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */
|
| 658 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */
|
| 659 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */
|
| 660 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */
|
| 661 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */
|
| 662 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */
|
| 663 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */
|
| 664 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */
|
| 665 |
|
|
} Bits;
|
| 666 |
|
|
struct {
|
| 667 |
|
|
byte grpBIT :8;
|
| 668 |
|
|
} MergedBits;
|
| 669 |
|
|
} TC4LoSTR;
|
| 670 |
|
|
#define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte
|
| 671 |
|
|
#define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0
|
| 672 |
|
|
#define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1
|
| 673 |
|
|
#define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2
|
| 674 |
|
|
#define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3
|
| 675 |
|
|
#define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4
|
| 676 |
|
|
#define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5
|
| 677 |
|
|
#define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6
|
| 678 |
|
|
#define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7
|
| 679 |
|
|
#define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT
|
| 680 |
|
|
|
| 681 |
|
|
} Overlap_STR;
|
| 682 |
|
|
|
| 683 |
|
|
struct {
|
| 684 |
|
|
word grpBIT :16;
|
| 685 |
|
|
} MergedBits;
|
| 686 |
|
|
} TC4STR;
|
| 687 |
|
|
extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058);
|
| 688 |
|
|
#define TC4 _TC4.Word
|
| 689 |
|
|
#define TC4_BIT _TC4.MergedBits.grpBIT
|
| 690 |
|
|
|
| 691 |
|
|
|
| 692 |
|
|
/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/
|
| 693 |
|
|
typedef union {
|
| 694 |
|
|
word Word;
|
| 695 |
|
|
/* Overlapped registers: */
|
| 696 |
|
|
struct {
|
| 697 |
|
|
/*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/
|
| 698 |
|
|
union {
|
| 699 |
|
|
byte Byte;
|
| 700 |
|
|
struct {
|
| 701 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */
|
| 702 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */
|
| 703 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */
|
| 704 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */
|
| 705 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */
|
| 706 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */
|
| 707 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */
|
| 708 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */
|
| 709 |
|
|
} Bits;
|
| 710 |
|
|
struct {
|
| 711 |
|
|
byte grpBIT_8 :8;
|
| 712 |
|
|
} MergedBits;
|
| 713 |
|
|
} TC5HiSTR;
|
| 714 |
|
|
#define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte
|
| 715 |
|
|
#define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8
|
| 716 |
|
|
#define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9
|
| 717 |
|
|
#define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10
|
| 718 |
|
|
#define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11
|
| 719 |
|
|
#define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12
|
| 720 |
|
|
#define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13
|
| 721 |
|
|
#define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14
|
| 722 |
|
|
#define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15
|
| 723 |
|
|
#define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8
|
| 724 |
|
|
#define TC5Hi_BIT TC5Hi_BIT_8
|
| 725 |
|
|
|
| 726 |
|
|
/*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/
|
| 727 |
|
|
union {
|
| 728 |
|
|
byte Byte;
|
| 729 |
|
|
struct {
|
| 730 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */
|
| 731 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */
|
| 732 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */
|
| 733 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */
|
| 734 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */
|
| 735 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */
|
| 736 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */
|
| 737 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */
|
| 738 |
|
|
} Bits;
|
| 739 |
|
|
struct {
|
| 740 |
|
|
byte grpBIT :8;
|
| 741 |
|
|
} MergedBits;
|
| 742 |
|
|
} TC5LoSTR;
|
| 743 |
|
|
#define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte
|
| 744 |
|
|
#define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0
|
| 745 |
|
|
#define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1
|
| 746 |
|
|
#define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2
|
| 747 |
|
|
#define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3
|
| 748 |
|
|
#define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4
|
| 749 |
|
|
#define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5
|
| 750 |
|
|
#define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6
|
| 751 |
|
|
#define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7
|
| 752 |
|
|
#define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT
|
| 753 |
|
|
|
| 754 |
|
|
} Overlap_STR;
|
| 755 |
|
|
|
| 756 |
|
|
struct {
|
| 757 |
|
|
word grpBIT :16;
|
| 758 |
|
|
} MergedBits;
|
| 759 |
|
|
} TC5STR;
|
| 760 |
|
|
extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A);
|
| 761 |
|
|
#define TC5 _TC5.Word
|
| 762 |
|
|
#define TC5_BIT _TC5.MergedBits.grpBIT
|
| 763 |
|
|
|
| 764 |
|
|
|
| 765 |
|
|
/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/
|
| 766 |
|
|
typedef union {
|
| 767 |
|
|
word Word;
|
| 768 |
|
|
/* Overlapped registers: */
|
| 769 |
|
|
struct {
|
| 770 |
|
|
/*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/
|
| 771 |
|
|
union {
|
| 772 |
|
|
byte Byte;
|
| 773 |
|
|
struct {
|
| 774 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */
|
| 775 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */
|
| 776 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */
|
| 777 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */
|
| 778 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */
|
| 779 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */
|
| 780 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */
|
| 781 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */
|
| 782 |
|
|
} Bits;
|
| 783 |
|
|
struct {
|
| 784 |
|
|
byte grpBIT_8 :8;
|
| 785 |
|
|
} MergedBits;
|
| 786 |
|
|
} TC6HiSTR;
|
| 787 |
|
|
#define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte
|
| 788 |
|
|
#define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8
|
| 789 |
|
|
#define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9
|
| 790 |
|
|
#define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10
|
| 791 |
|
|
#define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11
|
| 792 |
|
|
#define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12
|
| 793 |
|
|
#define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13
|
| 794 |
|
|
#define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14
|
| 795 |
|
|
#define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15
|
| 796 |
|
|
#define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8
|
| 797 |
|
|
#define TC6Hi_BIT TC6Hi_BIT_8
|
| 798 |
|
|
|
| 799 |
|
|
/*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/
|
| 800 |
|
|
union {
|
| 801 |
|
|
byte Byte;
|
| 802 |
|
|
struct {
|
| 803 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */
|
| 804 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */
|
| 805 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */
|
| 806 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */
|
| 807 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */
|
| 808 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */
|
| 809 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */
|
| 810 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */
|
| 811 |
|
|
} Bits;
|
| 812 |
|
|
struct {
|
| 813 |
|
|
byte grpBIT :8;
|
| 814 |
|
|
} MergedBits;
|
| 815 |
|
|
} TC6LoSTR;
|
| 816 |
|
|
#define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte
|
| 817 |
|
|
#define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0
|
| 818 |
|
|
#define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1
|
| 819 |
|
|
#define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2
|
| 820 |
|
|
#define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3
|
| 821 |
|
|
#define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4
|
| 822 |
|
|
#define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5
|
| 823 |
|
|
#define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6
|
| 824 |
|
|
#define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7
|
| 825 |
|
|
#define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT
|
| 826 |
|
|
|
| 827 |
|
|
} Overlap_STR;
|
| 828 |
|
|
|
| 829 |
|
|
struct {
|
| 830 |
|
|
word grpBIT :16;
|
| 831 |
|
|
} MergedBits;
|
| 832 |
|
|
} TC6STR;
|
| 833 |
|
|
extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C);
|
| 834 |
|
|
#define TC6 _TC6.Word
|
| 835 |
|
|
#define TC6_BIT _TC6.MergedBits.grpBIT
|
| 836 |
|
|
|
| 837 |
|
|
|
| 838 |
|
|
/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/
|
| 839 |
|
|
typedef union {
|
| 840 |
|
|
word Word;
|
| 841 |
|
|
/* Overlapped registers: */
|
| 842 |
|
|
struct {
|
| 843 |
|
|
/*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/
|
| 844 |
|
|
union {
|
| 845 |
|
|
byte Byte;
|
| 846 |
|
|
struct {
|
| 847 |
|
|
byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */
|
| 848 |
|
|
byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */
|
| 849 |
|
|
byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */
|
| 850 |
|
|
byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */
|
| 851 |
|
|
byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */
|
| 852 |
|
|
byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */
|
| 853 |
|
|
byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */
|
| 854 |
|
|
byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */
|
| 855 |
|
|
} Bits;
|
| 856 |
|
|
struct {
|
| 857 |
|
|
byte grpBIT_8 :8;
|
| 858 |
|
|
} MergedBits;
|
| 859 |
|
|
} TC7HiSTR;
|
| 860 |
|
|
#define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte
|
| 861 |
|
|
#define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8
|
| 862 |
|
|
#define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9
|
| 863 |
|
|
#define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10
|
| 864 |
|
|
#define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11
|
| 865 |
|
|
#define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12
|
| 866 |
|
|
#define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13
|
| 867 |
|
|
#define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14
|
| 868 |
|
|
#define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15
|
| 869 |
|
|
#define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8
|
| 870 |
|
|
#define TC7Hi_BIT TC7Hi_BIT_8
|
| 871 |
|
|
|
| 872 |
|
|
/*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/
|
| 873 |
|
|
union {
|
| 874 |
|
|
byte Byte;
|
| 875 |
|
|
struct {
|
| 876 |
|
|
byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */
|
| 877 |
|
|
byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */
|
| 878 |
|
|
byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */
|
| 879 |
|
|
byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */
|
| 880 |
|
|
byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */
|
| 881 |
|
|
byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */
|
| 882 |
|
|
byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */
|
| 883 |
|
|
byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */
|
| 884 |
|
|
} Bits;
|
| 885 |
|
|
struct {
|
| 886 |
|
|
byte grpBIT :8;
|
| 887 |
|
|
} MergedBits;
|
| 888 |
|
|
} TC7LoSTR;
|
| 889 |
|
|
#define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte
|
| 890 |
|
|
#define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0
|
| 891 |
|
|
#define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1
|
| 892 |
|
|
#define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2
|
| 893 |
|
|
#define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3
|
| 894 |
|
|
#define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4
|
| 895 |
|
|
#define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5
|
| 896 |
|
|
#define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6
|
| 897 |
|
|
#define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7
|
| 898 |
|
|
#define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT
|
| 899 |
|
|
|
| 900 |
|
|
} Overlap_STR;
|
| 901 |
|
|
|
| 902 |
|
|
struct {
|
| 903 |
|
|
word grpBIT :16;
|
| 904 |
|
|
} MergedBits;
|
| 905 |
|
|
} TC7STR;
|
| 906 |
|
|
extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E);
|
| 907 |
|
|
#define TC7 _TC7.Word
|
| 908 |
|
|
#define TC7_BIT _TC7.MergedBits.grpBIT
|
| 909 |
|
|
|
| 910 |
|
|
|
| 911 |
|
|
/*** PACNT - Pulse Accumulators Count Register; 0x00000062 ***/
|
| 912 |
|
|
typedef union {
|
| 913 |
|
|
word Word;
|
| 914 |
|
|
struct {
|
| 915 |
|
|
word grpBIT :16;
|
| 916 |
|
|
} MergedBits;
|
| 917 |
|
|
} PACNTSTR;
|
| 918 |
|
|
extern volatile PACNTSTR _PACNT @(REG_BASE + 0x00000062);
|
| 919 |
|
|
#define PACNT _PACNT.Word
|
| 920 |
|
|
#define PACNT_BIT _PACNT.MergedBits.grpBIT
|
| 921 |
|
|
|
| 922 |
|
|
|
| 923 |
|
|
/*** ATDCTL23 - ATD Control Register 23; 0x00000082 ***/
|
| 924 |
|
|
typedef union {
|
| 925 |
|
|
word Word;
|
| 926 |
|
|
/* Overlapped registers: */
|
| 927 |
|
|
struct {
|
| 928 |
|
|
/*** ATDCTL2 - ATD Control Register 2; 0x00000082 ***/
|
| 929 |
|
|
union {
|
| 930 |
|
|
byte Byte;
|
| 931 |
|
|
struct {
|
| 932 |
|
|
byte ASCIF :1; /* ATD Sequence Complete Interrupt Flag */
|
| 933 |
|
|
byte ASCIE :1; /* ATD Sequence Complete Interrupt Enable */
|
| 934 |
|
|
byte ETRIGE :1; /* External Trigger Mode enable */
|
| 935 |
|
|
byte ETRIGP :1; /* External Trigger Polarity */
|
| 936 |
|
|
byte ETRIGLE :1; /* External Trigger Level/Edge control */
|
| 937 |
|
|
byte AWAI :1; /* ATD Wait Mode */
|
| 938 |
|
|
byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */
|
| 939 |
|
|
byte ADPU :1; /* ATD Disable / Power Down */
|
| 940 |
|
|
} Bits;
|
| 941 |
|
|
} ATDCTL2STR;
|
| 942 |
|
|
#define ATDCTL2 _ATDCTL23.Overlap_STR.ATDCTL2STR.Byte
|
| 943 |
|
|
#define ATDCTL2_ASCIF _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIF
|
| 944 |
|
|
#define ATDCTL2_ASCIE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIE
|
| 945 |
|
|
#define ATDCTL2_ETRIGE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGE
|
| 946 |
|
|
#define ATDCTL2_ETRIGP _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGP
|
| 947 |
|
|
#define ATDCTL2_ETRIGLE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGLE
|
| 948 |
|
|
#define ATDCTL2_AWAI _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AWAI
|
| 949 |
|
|
#define ATDCTL2_AFFC _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AFFC
|
| 950 |
|
|
#define ATDCTL2_ADPU _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ADPU
|
| 951 |
|
|
|
| 952 |
|
|
/*** ATDCTL3 - ATD Control Register 3; 0x00000083 ***/
|
| 953 |
|
|
union {
|
| 954 |
|
|
byte Byte;
|
| 955 |
|
|
struct {
|
| 956 |
|
|
byte FRZ0 :1; /* Background Debug Freeze Enable */
|
| 957 |
|
|
byte FRZ1 :1; /* Background Debug Freeze Enable */
|
| 958 |
|
|
byte FIFO :1; /* Result Register FIFO Mode */
|
| 959 |
|
|
byte S1C :1; /* Conversion Sequence Length 1 */
|
| 960 |
|
|
byte S2C :1; /* Conversion Sequence Length 2 */
|
| 961 |
|
|
byte S4C :1; /* Conversion Sequence Length 4 */
|
| 962 |
|
|
byte S8C :1; /* Conversion Sequence Length 8 */
|
| 963 |
|
|
byte :1;
|
| 964 |
|
|
} Bits;
|
| 965 |
|
|
struct {
|
| 966 |
|
|
byte grpFRZ :2;
|
| 967 |
|
|
byte :1;
|
| 968 |
|
|
byte :1;
|
| 969 |
|
|
byte :1;
|
| 970 |
|
|
byte :1;
|
| 971 |
|
|
byte :1;
|
| 972 |
|
|
byte :1;
|
| 973 |
|
|
} MergedBits;
|
| 974 |
|
|
} ATDCTL3STR;
|
| 975 |
|
|
#define ATDCTL3 _ATDCTL23.Overlap_STR.ATDCTL3STR.Byte
|
| 976 |
|
|
#define ATDCTL3_FRZ0 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ0
|
| 977 |
|
|
#define ATDCTL3_FRZ1 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ1
|
| 978 |
|
|
#define ATDCTL3_FIFO _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FIFO
|
| 979 |
|
|
#define ATDCTL3_S1C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S1C
|
| 980 |
|
|
#define ATDCTL3_S2C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S2C
|
| 981 |
|
|
#define ATDCTL3_S4C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S4C
|
| 982 |
|
|
#define ATDCTL3_S8C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S8C
|
| 983 |
|
|
#define ATDCTL3_FRZ _ATDCTL23.Overlap_STR.ATDCTL3STR.MergedBits.grpFRZ
|
| 984 |
|
|
|
| 985 |
|
|
} Overlap_STR;
|
| 986 |
|
|
|
| 987 |
|
|
struct {
|
| 988 |
|
|
word FRZ0 :1; /* Background Debug Freeze Enable */
|
| 989 |
|
|
word FRZ1 :1; /* Background Debug Freeze Enable */
|
| 990 |
|
|
word FIFO :1; /* Result Register FIFO Mode */
|
| 991 |
|
|
word S1C :1; /* Conversion Sequence Length 1 */
|
| 992 |
|
|
word S2C :1; /* Conversion Sequence Length 2 */
|
| 993 |
|
|
word S4C :1; /* Conversion Sequence Length 4 */
|
| 994 |
|
|
word S8C :1; /* Conversion Sequence Length 8 */
|
| 995 |
|
|
word :1;
|
| 996 |
|
|
word ASCIF :1; /* ATD Sequence Complete Interrupt Flag */
|
| 997 |
|
|
word ASCIE :1; /* ATD Sequence Complete Interrupt Enable */
|
| 998 |
|
|
word ETRIGE :1; /* External Trigger Mode enable */
|
| 999 |
|
|
word ETRIGP :1; /* External Trigger Polarity */
|
| 1000 |
|
|
word ETRIGLE :1; /* External Trigger Level/Edge control */
|
| 1001 |
|
|
word AWAI :1; /* ATD Wait Mode */
|
| 1002 |
|
|
word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */
|
| 1003 |
|
|
word ADPU :1; /* ATD Disable / Power Down */
|
| 1004 |
|
|
} Bits;
|
| 1005 |
|
|
struct {
|
| 1006 |
|
|
word grpFRZ :2;
|
| 1007 |
|
|
word :1;
|
| 1008 |
|
|
word :1;
|
| 1009 |
|
|
word :1;
|
| 1010 |
|
|
word :1;
|
| 1011 |
|
|
word :1;
|
| 1012 |
|
|
word :1;
|
| 1013 |
|
|
word :1;
|
| 1014 |
|
|
word :1;
|
| 1015 |
|
|
word :1;
|
| 1016 |
|
|
word :1;
|
| 1017 |
|
|
word :1;
|
| 1018 |
|
|
word :1;
|
| 1019 |
|
|
word :1;
|
| 1020 |
|
|
word :1;
|
| 1021 |
|
|
} MergedBits;
|
| 1022 |
|
|
} ATDCTL23STR;
|
| 1023 |
|
|
extern volatile ATDCTL23STR _ATDCTL23 @(REG_BASE + 0x00000082);
|
| 1024 |
|
|
#define ATDCTL23 _ATDCTL23.Word
|
| 1025 |
|
|
#define ATDCTL23_FRZ0 _ATDCTL23.Bits.FRZ0
|
| 1026 |
|
|
#define ATDCTL23_FRZ1 _ATDCTL23.Bits.FRZ1
|
| 1027 |
|
|
#define ATDCTL23_FIFO _ATDCTL23.Bits.FIFO
|
| 1028 |
|
|
#define ATDCTL23_S1C _ATDCTL23.Bits.S1C
|
| 1029 |
|
|
#define ATDCTL23_S2C _ATDCTL23.Bits.S2C
|
| 1030 |
|
|
#define ATDCTL23_S4C _ATDCTL23.Bits.S4C
|
| 1031 |
|
|
#define ATDCTL23_S8C _ATDCTL23.Bits.S8C
|
| 1032 |
|
|
#define ATDCTL23_ASCIF _ATDCTL23.Bits.ASCIF
|
| 1033 |
|
|
#define ATDCTL23_ASCIE _ATDCTL23.Bits.ASCIE
|
| 1034 |
|
|
#define ATDCTL23_ETRIGE _ATDCTL23.Bits.ETRIGE
|
| 1035 |
|
|
#define ATDCTL23_ETRIGP _ATDCTL23.Bits.ETRIGP
|
| 1036 |
|
|
#define ATDCTL23_ETRIGLE _ATDCTL23.Bits.ETRIGLE
|
| 1037 |
|
|
#define ATDCTL23_AWAI _ATDCTL23.Bits.AWAI
|
| 1038 |
|
|
#define ATDCTL23_AFFC _ATDCTL23.Bits.AFFC
|
| 1039 |
|
|
#define ATDCTL23_ADPU _ATDCTL23.Bits.ADPU
|
| 1040 |
|
|
#define ATDCTL23_FRZ _ATDCTL23.MergedBits.grpFRZ
|
| 1041 |
|
|
|
| 1042 |
|
|
|
| 1043 |
|
|
/*** ATDCTL45 - ATD Control Register 45; 0x00000084 ***/
|
| 1044 |
|
|
typedef union {
|
| 1045 |
|
|
word Word;
|
| 1046 |
|
|
/* Overlapped registers: */
|
| 1047 |
|
|
struct {
|
| 1048 |
|
|
/*** ATDCTL4 - ATD Control Register 4; 0x00000084 ***/
|
| 1049 |
|
|
union {
|
| 1050 |
|
|
byte Byte;
|
| 1051 |
|
|
struct {
|
| 1052 |
|
|
byte PRS0 :1; /* ATD Clock Prescaler 0 */
|
| 1053 |
|
|
byte PRS1 :1; /* ATD Clock Prescaler 1 */
|
| 1054 |
|
|
byte PRS2 :1; /* ATD Clock Prescaler 2 */
|
| 1055 |
|
|
byte PRS3 :1; /* ATD Clock Prescaler 3 */
|
| 1056 |
|
|
byte PRS4 :1; /* ATD Clock Prescaler 4 */
|
| 1057 |
|
|
byte SMP0 :1; /* Sample Time Select 0 */
|
| 1058 |
|
|
byte SMP1 :1; /* Sample Time Select 1 */
|
| 1059 |
|
|
byte SRES8 :1; /* A/D Resolution Select */
|
| 1060 |
|
|
} Bits;
|
| 1061 |
|
|
struct {
|
| 1062 |
|
|
byte grpPRS :5;
|
| 1063 |
|
|
byte grpSMP :2;
|
| 1064 |
|
|
byte grpSRES_8 :1;
|
| 1065 |
|
|
} MergedBits;
|
| 1066 |
|
|
} ATDCTL4STR;
|
| 1067 |
|
|
#define ATDCTL4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Byte
|
| 1068 |
|
|
#define ATDCTL4_PRS0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS0
|
| 1069 |
|
|
#define ATDCTL4_PRS1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS1
|
| 1070 |
|
|
#define ATDCTL4_PRS2 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS2
|
| 1071 |
|
|
#define ATDCTL4_PRS3 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS3
|
| 1072 |
|
|
#define ATDCTL4_PRS4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS4
|
| 1073 |
|
|
#define ATDCTL4_SMP0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP0
|
| 1074 |
|
|
#define ATDCTL4_SMP1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP1
|
| 1075 |
|
|
#define ATDCTL4_SRES8 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SRES8
|
| 1076 |
|
|
#define ATDCTL4_PRS _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpPRS
|
| 1077 |
|
|
#define ATDCTL4_SMP _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpSMP
|
| 1078 |
|
|
|
| 1079 |
|
|
/*** ATDCTL5 - ATD Control Register 5; 0x00000085 ***/
|
| 1080 |
|
|
union {
|
| 1081 |
|
|
byte Byte;
|
| 1082 |
|
|
struct {
|
| 1083 |
|
|
byte CA :1; /* Analog Input Channel Select Code A */
|
| 1084 |
|
|
byte CB :1; /* Analog Input Channel Select Code B */
|
| 1085 |
|
|
byte CC :1; /* Analog Input Channel Select Code C */
|
| 1086 |
|
|
byte :1;
|
| 1087 |
|
|
byte MULT :1; /* Multi-Channel Sample Mode */
|
| 1088 |
|
|
byte SCAN :1; /* Continuous Conversion Sequence Mode */
|
| 1089 |
|
|
byte DSGN :1; /* Signed/Unsigned Result Data Mode */
|
| 1090 |
|
|
byte DJM :1; /* Result Register Data Justification Mode */
|
| 1091 |
|
|
} Bits;
|
| 1092 |
|
|
} ATDCTL5STR;
|
| 1093 |
|
|
#define ATDCTL5 _ATDCTL45.Overlap_STR.ATDCTL5STR.Byte
|
| 1094 |
|
|
#define ATDCTL5_CA _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CA
|
| 1095 |
|
|
#define ATDCTL5_CB _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CB
|
| 1096 |
|
|
#define ATDCTL5_CC _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CC
|
| 1097 |
|
|
#define ATDCTL5_MULT _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.MULT
|
| 1098 |
|
|
#define ATDCTL5_SCAN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.SCAN
|
| 1099 |
|
|
#define ATDCTL5_DSGN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DSGN
|
| 1100 |
|
|
#define ATDCTL5_DJM _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DJM
|
| 1101 |
|
|
|
| 1102 |
|
|
} Overlap_STR;
|
| 1103 |
|
|
|
| 1104 |
|
|
struct {
|
| 1105 |
|
|
word CA :1; /* Analog Input Channel Select Code A */
|
| 1106 |
|
|
word CB :1; /* Analog Input Channel Select Code B */
|
| 1107 |
|
|
word CC :1; /* Analog Input Channel Select Code C */
|
| 1108 |
|
|
word :1;
|
| 1109 |
|
|
word MULT :1; /* Multi-Channel Sample Mode */
|
| 1110 |
|
|
word SCAN :1; /* Continuous Conversion Sequence Mode */
|
| 1111 |
|
|
word DSGN :1; /* Signed/Unsigned Result Data Mode */
|
| 1112 |
|
|
word DJM :1; /* Result Register Data Justification Mode */
|
| 1113 |
|
|
word PRS0 :1; /* ATD Clock Prescaler 0 */
|
| 1114 |
|
|
word PRS1 :1; /* ATD Clock Prescaler 1 */
|
| 1115 |
|
|
word PRS2 :1; /* ATD Clock Prescaler 2 */
|
| 1116 |
|
|
word PRS3 :1; /* ATD Clock Prescaler 3 */
|
| 1117 |
|
|
word PRS4 :1; /* ATD Clock Prescaler 4 */
|
| 1118 |
|
|
word SMP0 :1; /* Sample Time Select 0 */
|
| 1119 |
|
|
word SMP1 :1; /* Sample Time Select 1 */
|
| 1120 |
|
|
word SRES8 :1; /* A/D Resolution Select */
|
| 1121 |
|
|
} Bits;
|
| 1122 |
|
|
struct {
|
| 1123 |
|
|
word :1;
|
| 1124 |
|
|
word :1;
|
| 1125 |
|
|
word :1;
|
| 1126 |
|
|
word :1;
|
| 1127 |
|
|
word :1;
|
| 1128 |
|
|
word :1;
|
| 1129 |
|
|
word :1;
|
| 1130 |
|
|
word :1;
|
| 1131 |
|
|
word grpPRS :5;
|
| 1132 |
|
|
word grpSMP :2;
|
| 1133 |
|
|
word grpSRES_8 :1;
|
| 1134 |
|
|
} MergedBits;
|
| 1135 |
|
|
} ATDCTL45STR;
|
| 1136 |
|
|
extern volatile ATDCTL45STR _ATDCTL45 @(REG_BASE + 0x00000084);
|
| 1137 |
|
|
#define ATDCTL45 _ATDCTL45.Word
|
| 1138 |
|
|
#define ATDCTL45_CA _ATDCTL45.Bits.CA
|
| 1139 |
|
|
#define ATDCTL45_CB _ATDCTL45.Bits.CB
|
| 1140 |
|
|
#define ATDCTL45_CC _ATDCTL45.Bits.CC
|
| 1141 |
|
|
#define ATDCTL45_MULT _ATDCTL45.Bits.MULT
|
| 1142 |
|
|
#define ATDCTL45_SCAN _ATDCTL45.Bits.SCAN
|
| 1143 |
|
|
#define ATDCTL45_DSGN _ATDCTL45.Bits.DSGN
|
| 1144 |
|
|
#define ATDCTL45_DJM _ATDCTL45.Bits.DJM
|
| 1145 |
|
|
#define ATDCTL45_PRS0 _ATDCTL45.Bits.PRS0
|
| 1146 |
|
|
#define ATDCTL45_PRS1 _ATDCTL45.Bits.PRS1
|
| 1147 |
|
|
#define ATDCTL45_PRS2 _ATDCTL45.Bits.PRS2
|
| 1148 |
|
|
#define ATDCTL45_PRS3 _ATDCTL45.Bits.PRS3
|
| 1149 |
|
|
#define ATDCTL45_PRS4 _ATDCTL45.Bits.PRS4
|
| 1150 |
|
|
#define ATDCTL45_SMP0 _ATDCTL45.Bits.SMP0
|
| 1151 |
|
|
#define ATDCTL45_SMP1 _ATDCTL45.Bits.SMP1
|
| 1152 |
|
|
#define ATDCTL45_SRES8 _ATDCTL45.Bits.SRES8
|
| 1153 |
|
|
#define ATDCTL45_PRS _ATDCTL45.MergedBits.grpPRS
|
| 1154 |
|
|
#define ATDCTL45_SMP _ATDCTL45.MergedBits.grpSMP
|
| 1155 |
|
|
|
| 1156 |
|
|
|
| 1157 |
|
|
/*** ATDDR0 - A/D Conversion Result Register 0; 0x00000090 ***/
|
| 1158 |
|
|
typedef union {
|
| 1159 |
|
|
word Word;
|
| 1160 |
|
|
/* Overlapped registers: */
|
| 1161 |
|
|
struct {
|
| 1162 |
|
|
/*** ATDDR0H - A/D Conversion Result Register 0 High; 0x00000090 ***/
|
| 1163 |
|
|
union {
|
| 1164 |
|
|
byte Byte;
|
| 1165 |
|
|
struct {
|
| 1166 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 1167 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 1168 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 1169 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 1170 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 1171 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 1172 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 1173 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 1174 |
|
|
} Bits;
|
| 1175 |
|
|
struct {
|
| 1176 |
|
|
byte grpBIT_8 :8;
|
| 1177 |
|
|
} MergedBits;
|
| 1178 |
|
|
} ATDDR0HSTR;
|
| 1179 |
|
|
#define ATDDR0H _ATDDR0.Overlap_STR.ATDDR0HSTR.Byte
|
| 1180 |
|
|
#define ATDDR0H_BIT8 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT8
|
| 1181 |
|
|
#define ATDDR0H_BIT9 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT9
|
| 1182 |
|
|
#define ATDDR0H_BIT10 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT10
|
| 1183 |
|
|
#define ATDDR0H_BIT11 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT11
|
| 1184 |
|
|
#define ATDDR0H_BIT12 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT12
|
| 1185 |
|
|
#define ATDDR0H_BIT13 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT13
|
| 1186 |
|
|
#define ATDDR0H_BIT14 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT14
|
| 1187 |
|
|
#define ATDDR0H_BIT15 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT15
|
| 1188 |
|
|
#define ATDDR0H_BIT_8 _ATDDR0.Overlap_STR.ATDDR0HSTR.MergedBits.grpBIT_8
|
| 1189 |
|
|
#define ATDDR0H_BIT ATDDR0H_BIT_8
|
| 1190 |
|
|
|
| 1191 |
|
|
/*** ATDDR0L - A/D Conversion Result Register 0 Low; 0x00000091 ***/
|
| 1192 |
|
|
union {
|
| 1193 |
|
|
byte Byte;
|
| 1194 |
|
|
struct {
|
| 1195 |
|
|
byte :1;
|
| 1196 |
|
|
byte :1;
|
| 1197 |
|
|
byte :1;
|
| 1198 |
|
|
byte :1;
|
| 1199 |
|
|
byte :1;
|
| 1200 |
|
|
byte :1;
|
| 1201 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 1202 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 1203 |
|
|
} Bits;
|
| 1204 |
|
|
struct {
|
| 1205 |
|
|
byte :1;
|
| 1206 |
|
|
byte :1;
|
| 1207 |
|
|
byte :1;
|
| 1208 |
|
|
byte :1;
|
| 1209 |
|
|
byte :1;
|
| 1210 |
|
|
byte :1;
|
| 1211 |
|
|
byte grpBIT_6 :2;
|
| 1212 |
|
|
} MergedBits;
|
| 1213 |
|
|
} ATDDR0LSTR;
|
| 1214 |
|
|
#define ATDDR0L _ATDDR0.Overlap_STR.ATDDR0LSTR.Byte
|
| 1215 |
|
|
#define ATDDR0L_BIT6 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT6
|
| 1216 |
|
|
#define ATDDR0L_BIT7 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT7
|
| 1217 |
|
|
#define ATDDR0L_BIT_6 _ATDDR0.Overlap_STR.ATDDR0LSTR.MergedBits.grpBIT_6
|
| 1218 |
|
|
#define ATDDR0L_BIT ATDDR0L_BIT_6
|
| 1219 |
|
|
|
| 1220 |
|
|
} Overlap_STR;
|
| 1221 |
|
|
|
| 1222 |
|
|
struct {
|
| 1223 |
|
|
word :1;
|
| 1224 |
|
|
word :1;
|
| 1225 |
|
|
word :1;
|
| 1226 |
|
|
word :1;
|
| 1227 |
|
|
word :1;
|
| 1228 |
|
|
word :1;
|
| 1229 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 1230 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 1231 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 1232 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 1233 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 1234 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 1235 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 1236 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 1237 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 1238 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 1239 |
|
|
} Bits;
|
| 1240 |
|
|
struct {
|
| 1241 |
|
|
word :1;
|
| 1242 |
|
|
word :1;
|
| 1243 |
|
|
word :1;
|
| 1244 |
|
|
word :1;
|
| 1245 |
|
|
word :1;
|
| 1246 |
|
|
word :1;
|
| 1247 |
|
|
word grpBIT_6 :10;
|
| 1248 |
|
|
} MergedBits;
|
| 1249 |
|
|
} ATDDR0STR;
|
| 1250 |
|
|
extern volatile ATDDR0STR _ATDDR0 @(REG_BASE + 0x00000090);
|
| 1251 |
|
|
#define ATDDR0 _ATDDR0.Word
|
| 1252 |
|
|
#define ATDDR0_BIT6 _ATDDR0.Bits.BIT6
|
| 1253 |
|
|
#define ATDDR0_BIT7 _ATDDR0.Bits.BIT7
|
| 1254 |
|
|
#define ATDDR0_BIT8 _ATDDR0.Bits.BIT8
|
| 1255 |
|
|
#define ATDDR0_BIT9 _ATDDR0.Bits.BIT9
|
| 1256 |
|
|
#define ATDDR0_BIT10 _ATDDR0.Bits.BIT10
|
| 1257 |
|
|
#define ATDDR0_BIT11 _ATDDR0.Bits.BIT11
|
| 1258 |
|
|
#define ATDDR0_BIT12 _ATDDR0.Bits.BIT12
|
| 1259 |
|
|
#define ATDDR0_BIT13 _ATDDR0.Bits.BIT13
|
| 1260 |
|
|
#define ATDDR0_BIT14 _ATDDR0.Bits.BIT14
|
| 1261 |
|
|
#define ATDDR0_BIT15 _ATDDR0.Bits.BIT15
|
| 1262 |
|
|
#define ATDDR0_BIT_6 _ATDDR0.MergedBits.grpBIT_6
|
| 1263 |
|
|
#define ATDDR0_BIT ATDDR0_BIT_6
|
| 1264 |
|
|
|
| 1265 |
|
|
|
| 1266 |
|
|
/*** ATDDR1 - A/D Conversion Result Register 1; 0x00000092 ***/
|
| 1267 |
|
|
typedef union {
|
| 1268 |
|
|
word Word;
|
| 1269 |
|
|
/* Overlapped registers: */
|
| 1270 |
|
|
struct {
|
| 1271 |
|
|
/*** ATDDR1H - A/D Conversion Result Register 1 High; 0x00000092 ***/
|
| 1272 |
|
|
union {
|
| 1273 |
|
|
byte Byte;
|
| 1274 |
|
|
struct {
|
| 1275 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 1276 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 1277 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 1278 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 1279 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 1280 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 1281 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 1282 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 1283 |
|
|
} Bits;
|
| 1284 |
|
|
struct {
|
| 1285 |
|
|
byte grpBIT_8 :8;
|
| 1286 |
|
|
} MergedBits;
|
| 1287 |
|
|
} ATDDR1HSTR;
|
| 1288 |
|
|
#define ATDDR1H _ATDDR1.Overlap_STR.ATDDR1HSTR.Byte
|
| 1289 |
|
|
#define ATDDR1H_BIT8 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT8
|
| 1290 |
|
|
#define ATDDR1H_BIT9 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT9
|
| 1291 |
|
|
#define ATDDR1H_BIT10 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT10
|
| 1292 |
|
|
#define ATDDR1H_BIT11 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT11
|
| 1293 |
|
|
#define ATDDR1H_BIT12 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT12
|
| 1294 |
|
|
#define ATDDR1H_BIT13 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT13
|
| 1295 |
|
|
#define ATDDR1H_BIT14 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT14
|
| 1296 |
|
|
#define ATDDR1H_BIT15 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT15
|
| 1297 |
|
|
#define ATDDR1H_BIT_8 _ATDDR1.Overlap_STR.ATDDR1HSTR.MergedBits.grpBIT_8
|
| 1298 |
|
|
#define ATDDR1H_BIT ATDDR1H_BIT_8
|
| 1299 |
|
|
|
| 1300 |
|
|
/*** ATDDR1L - A/D Conversion Result Register 1 Low; 0x00000093 ***/
|
| 1301 |
|
|
union {
|
| 1302 |
|
|
byte Byte;
|
| 1303 |
|
|
struct {
|
| 1304 |
|
|
byte :1;
|
| 1305 |
|
|
byte :1;
|
| 1306 |
|
|
byte :1;
|
| 1307 |
|
|
byte :1;
|
| 1308 |
|
|
byte :1;
|
| 1309 |
|
|
byte :1;
|
| 1310 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 1311 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 1312 |
|
|
} Bits;
|
| 1313 |
|
|
struct {
|
| 1314 |
|
|
byte :1;
|
| 1315 |
|
|
byte :1;
|
| 1316 |
|
|
byte :1;
|
| 1317 |
|
|
byte :1;
|
| 1318 |
|
|
byte :1;
|
| 1319 |
|
|
byte :1;
|
| 1320 |
|
|
byte grpBIT_6 :2;
|
| 1321 |
|
|
} MergedBits;
|
| 1322 |
|
|
} ATDDR1LSTR;
|
| 1323 |
|
|
#define ATDDR1L _ATDDR1.Overlap_STR.ATDDR1LSTR.Byte
|
| 1324 |
|
|
#define ATDDR1L_BIT6 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT6
|
| 1325 |
|
|
#define ATDDR1L_BIT7 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT7
|
| 1326 |
|
|
#define ATDDR1L_BIT_6 _ATDDR1.Overlap_STR.ATDDR1LSTR.MergedBits.grpBIT_6
|
| 1327 |
|
|
#define ATDDR1L_BIT ATDDR1L_BIT_6
|
| 1328 |
|
|
|
| 1329 |
|
|
} Overlap_STR;
|
| 1330 |
|
|
|
| 1331 |
|
|
struct {
|
| 1332 |
|
|
word :1;
|
| 1333 |
|
|
word :1;
|
| 1334 |
|
|
word :1;
|
| 1335 |
|
|
word :1;
|
| 1336 |
|
|
word :1;
|
| 1337 |
|
|
word :1;
|
| 1338 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 1339 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 1340 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 1341 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 1342 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 1343 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 1344 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 1345 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 1346 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 1347 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 1348 |
|
|
} Bits;
|
| 1349 |
|
|
struct {
|
| 1350 |
|
|
word :1;
|
| 1351 |
|
|
word :1;
|
| 1352 |
|
|
word :1;
|
| 1353 |
|
|
word :1;
|
| 1354 |
|
|
word :1;
|
| 1355 |
|
|
word :1;
|
| 1356 |
|
|
word grpBIT_6 :10;
|
| 1357 |
|
|
} MergedBits;
|
| 1358 |
|
|
} ATDDR1STR;
|
| 1359 |
|
|
extern volatile ATDDR1STR _ATDDR1 @(REG_BASE + 0x00000092);
|
| 1360 |
|
|
#define ATDDR1 _ATDDR1.Word
|
| 1361 |
|
|
#define ATDDR1_BIT6 _ATDDR1.Bits.BIT6
|
| 1362 |
|
|
#define ATDDR1_BIT7 _ATDDR1.Bits.BIT7
|
| 1363 |
|
|
#define ATDDR1_BIT8 _ATDDR1.Bits.BIT8
|
| 1364 |
|
|
#define ATDDR1_BIT9 _ATDDR1.Bits.BIT9
|
| 1365 |
|
|
#define ATDDR1_BIT10 _ATDDR1.Bits.BIT10
|
| 1366 |
|
|
#define ATDDR1_BIT11 _ATDDR1.Bits.BIT11
|
| 1367 |
|
|
#define ATDDR1_BIT12 _ATDDR1.Bits.BIT12
|
| 1368 |
|
|
#define ATDDR1_BIT13 _ATDDR1.Bits.BIT13
|
| 1369 |
|
|
#define ATDDR1_BIT14 _ATDDR1.Bits.BIT14
|
| 1370 |
|
|
#define ATDDR1_BIT15 _ATDDR1.Bits.BIT15
|
| 1371 |
|
|
#define ATDDR1_BIT_6 _ATDDR1.MergedBits.grpBIT_6
|
| 1372 |
|
|
#define ATDDR1_BIT ATDDR1_BIT_6
|
| 1373 |
|
|
|
| 1374 |
|
|
|
| 1375 |
|
|
/*** ATDDR2 - A/D Conversion Result Register 2; 0x00000094 ***/
|
| 1376 |
|
|
typedef union {
|
| 1377 |
|
|
word Word;
|
| 1378 |
|
|
/* Overlapped registers: */
|
| 1379 |
|
|
struct {
|
| 1380 |
|
|
/*** ATDDR2H - A/D Conversion Result Register 2 High; 0x00000094 ***/
|
| 1381 |
|
|
union {
|
| 1382 |
|
|
byte Byte;
|
| 1383 |
|
|
struct {
|
| 1384 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 1385 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 1386 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 1387 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 1388 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 1389 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 1390 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 1391 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 1392 |
|
|
} Bits;
|
| 1393 |
|
|
struct {
|
| 1394 |
|
|
byte grpBIT_8 :8;
|
| 1395 |
|
|
} MergedBits;
|
| 1396 |
|
|
} ATDDR2HSTR;
|
| 1397 |
|
|
#define ATDDR2H _ATDDR2.Overlap_STR.ATDDR2HSTR.Byte
|
| 1398 |
|
|
#define ATDDR2H_BIT8 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT8
|
| 1399 |
|
|
#define ATDDR2H_BIT9 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT9
|
| 1400 |
|
|
#define ATDDR2H_BIT10 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT10
|
| 1401 |
|
|
#define ATDDR2H_BIT11 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT11
|
| 1402 |
|
|
#define ATDDR2H_BIT12 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT12
|
| 1403 |
|
|
#define ATDDR2H_BIT13 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT13
|
| 1404 |
|
|
#define ATDDR2H_BIT14 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT14
|
| 1405 |
|
|
#define ATDDR2H_BIT15 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT15
|
| 1406 |
|
|
#define ATDDR2H_BIT_8 _ATDDR2.Overlap_STR.ATDDR2HSTR.MergedBits.grpBIT_8
|
| 1407 |
|
|
#define ATDDR2H_BIT ATDDR2H_BIT_8
|
| 1408 |
|
|
|
| 1409 |
|
|
/*** ATDDR2L - A/D Conversion Result Register 2 Low; 0x00000095 ***/
|
| 1410 |
|
|
union {
|
| 1411 |
|
|
byte Byte;
|
| 1412 |
|
|
struct {
|
| 1413 |
|
|
byte :1;
|
| 1414 |
|
|
byte :1;
|
| 1415 |
|
|
byte :1;
|
| 1416 |
|
|
byte :1;
|
| 1417 |
|
|
byte :1;
|
| 1418 |
|
|
byte :1;
|
| 1419 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 1420 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 1421 |
|
|
} Bits;
|
| 1422 |
|
|
struct {
|
| 1423 |
|
|
byte :1;
|
| 1424 |
|
|
byte :1;
|
| 1425 |
|
|
byte :1;
|
| 1426 |
|
|
byte :1;
|
| 1427 |
|
|
byte :1;
|
| 1428 |
|
|
byte :1;
|
| 1429 |
|
|
byte grpBIT_6 :2;
|
| 1430 |
|
|
} MergedBits;
|
| 1431 |
|
|
} ATDDR2LSTR;
|
| 1432 |
|
|
#define ATDDR2L _ATDDR2.Overlap_STR.ATDDR2LSTR.Byte
|
| 1433 |
|
|
#define ATDDR2L_BIT6 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT6
|
| 1434 |
|
|
#define ATDDR2L_BIT7 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT7
|
| 1435 |
|
|
#define ATDDR2L_BIT_6 _ATDDR2.Overlap_STR.ATDDR2LSTR.MergedBits.grpBIT_6
|
| 1436 |
|
|
#define ATDDR2L_BIT ATDDR2L_BIT_6
|
| 1437 |
|
|
|
| 1438 |
|
|
} Overlap_STR;
|
| 1439 |
|
|
|
| 1440 |
|
|
struct {
|
| 1441 |
|
|
word :1;
|
| 1442 |
|
|
word :1;
|
| 1443 |
|
|
word :1;
|
| 1444 |
|
|
word :1;
|
| 1445 |
|
|
word :1;
|
| 1446 |
|
|
word :1;
|
| 1447 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 1448 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 1449 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 1450 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 1451 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 1452 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 1453 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 1454 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 1455 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 1456 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 1457 |
|
|
} Bits;
|
| 1458 |
|
|
struct {
|
| 1459 |
|
|
word :1;
|
| 1460 |
|
|
word :1;
|
| 1461 |
|
|
word :1;
|
| 1462 |
|
|
word :1;
|
| 1463 |
|
|
word :1;
|
| 1464 |
|
|
word :1;
|
| 1465 |
|
|
word grpBIT_6 :10;
|
| 1466 |
|
|
} MergedBits;
|
| 1467 |
|
|
} ATDDR2STR;
|
| 1468 |
|
|
extern volatile ATDDR2STR _ATDDR2 @(REG_BASE + 0x00000094);
|
| 1469 |
|
|
#define ATDDR2 _ATDDR2.Word
|
| 1470 |
|
|
#define ATDDR2_BIT6 _ATDDR2.Bits.BIT6
|
| 1471 |
|
|
#define ATDDR2_BIT7 _ATDDR2.Bits.BIT7
|
| 1472 |
|
|
#define ATDDR2_BIT8 _ATDDR2.Bits.BIT8
|
| 1473 |
|
|
#define ATDDR2_BIT9 _ATDDR2.Bits.BIT9
|
| 1474 |
|
|
#define ATDDR2_BIT10 _ATDDR2.Bits.BIT10
|
| 1475 |
|
|
#define ATDDR2_BIT11 _ATDDR2.Bits.BIT11
|
| 1476 |
|
|
#define ATDDR2_BIT12 _ATDDR2.Bits.BIT12
|
| 1477 |
|
|
#define ATDDR2_BIT13 _ATDDR2.Bits.BIT13
|
| 1478 |
|
|
#define ATDDR2_BIT14 _ATDDR2.Bits.BIT14
|
| 1479 |
|
|
#define ATDDR2_BIT15 _ATDDR2.Bits.BIT15
|
| 1480 |
|
|
#define ATDDR2_BIT_6 _ATDDR2.MergedBits.grpBIT_6
|
| 1481 |
|
|
#define ATDDR2_BIT ATDDR2_BIT_6
|
| 1482 |
|
|
|
| 1483 |
|
|
|
| 1484 |
|
|
/*** ATDDR3 - A/D Conversion Result Register 3; 0x00000096 ***/
|
| 1485 |
|
|
typedef union {
|
| 1486 |
|
|
word Word;
|
| 1487 |
|
|
/* Overlapped registers: */
|
| 1488 |
|
|
struct {
|
| 1489 |
|
|
/*** ATDDR3H - A/D Conversion Result Register 3 High; 0x00000096 ***/
|
| 1490 |
|
|
union {
|
| 1491 |
|
|
byte Byte;
|
| 1492 |
|
|
struct {
|
| 1493 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 1494 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 1495 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 1496 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 1497 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 1498 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 1499 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 1500 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 1501 |
|
|
} Bits;
|
| 1502 |
|
|
struct {
|
| 1503 |
|
|
byte grpBIT_8 :8;
|
| 1504 |
|
|
} MergedBits;
|
| 1505 |
|
|
} ATDDR3HSTR;
|
| 1506 |
|
|
#define ATDDR3H _ATDDR3.Overlap_STR.ATDDR3HSTR.Byte
|
| 1507 |
|
|
#define ATDDR3H_BIT8 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT8
|
| 1508 |
|
|
#define ATDDR3H_BIT9 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT9
|
| 1509 |
|
|
#define ATDDR3H_BIT10 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT10
|
| 1510 |
|
|
#define ATDDR3H_BIT11 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT11
|
| 1511 |
|
|
#define ATDDR3H_BIT12 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT12
|
| 1512 |
|
|
#define ATDDR3H_BIT13 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT13
|
| 1513 |
|
|
#define ATDDR3H_BIT14 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT14
|
| 1514 |
|
|
#define ATDDR3H_BIT15 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT15
|
| 1515 |
|
|
#define ATDDR3H_BIT_8 _ATDDR3.Overlap_STR.ATDDR3HSTR.MergedBits.grpBIT_8
|
| 1516 |
|
|
#define ATDDR3H_BIT ATDDR3H_BIT_8
|
| 1517 |
|
|
|
| 1518 |
|
|
/*** ATDDR3L - A/D Conversion Result Register 3 Low; 0x00000097 ***/
|
| 1519 |
|
|
union {
|
| 1520 |
|
|
byte Byte;
|
| 1521 |
|
|
struct {
|
| 1522 |
|
|
byte :1;
|
| 1523 |
|
|
byte :1;
|
| 1524 |
|
|
byte :1;
|
| 1525 |
|
|
byte :1;
|
| 1526 |
|
|
byte :1;
|
| 1527 |
|
|
byte :1;
|
| 1528 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 1529 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 1530 |
|
|
} Bits;
|
| 1531 |
|
|
struct {
|
| 1532 |
|
|
byte :1;
|
| 1533 |
|
|
byte :1;
|
| 1534 |
|
|
byte :1;
|
| 1535 |
|
|
byte :1;
|
| 1536 |
|
|
byte :1;
|
| 1537 |
|
|
byte :1;
|
| 1538 |
|
|
byte grpBIT_6 :2;
|
| 1539 |
|
|
} MergedBits;
|
| 1540 |
|
|
} ATDDR3LSTR;
|
| 1541 |
|
|
#define ATDDR3L _ATDDR3.Overlap_STR.ATDDR3LSTR.Byte
|
| 1542 |
|
|
#define ATDDR3L_BIT6 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT6
|
| 1543 |
|
|
#define ATDDR3L_BIT7 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT7
|
| 1544 |
|
|
#define ATDDR3L_BIT_6 _ATDDR3.Overlap_STR.ATDDR3LSTR.MergedBits.grpBIT_6
|
| 1545 |
|
|
#define ATDDR3L_BIT ATDDR3L_BIT_6
|
| 1546 |
|
|
|
| 1547 |
|
|
} Overlap_STR;
|
| 1548 |
|
|
|
| 1549 |
|
|
struct {
|
| 1550 |
|
|
word :1;
|
| 1551 |
|
|
word :1;
|
| 1552 |
|
|
word :1;
|
| 1553 |
|
|
word :1;
|
| 1554 |
|
|
word :1;
|
| 1555 |
|
|
word :1;
|
| 1556 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 1557 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 1558 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 1559 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 1560 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 1561 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 1562 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 1563 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 1564 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 1565 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 1566 |
|
|
} Bits;
|
| 1567 |
|
|
struct {
|
| 1568 |
|
|
word :1;
|
| 1569 |
|
|
word :1;
|
| 1570 |
|
|
word :1;
|
| 1571 |
|
|
word :1;
|
| 1572 |
|
|
word :1;
|
| 1573 |
|
|
word :1;
|
| 1574 |
|
|
word grpBIT_6 :10;
|
| 1575 |
|
|
} MergedBits;
|
| 1576 |
|
|
} ATDDR3STR;
|
| 1577 |
|
|
extern volatile ATDDR3STR _ATDDR3 @(REG_BASE + 0x00000096);
|
| 1578 |
|
|
#define ATDDR3 _ATDDR3.Word
|
| 1579 |
|
|
#define ATDDR3_BIT6 _ATDDR3.Bits.BIT6
|
| 1580 |
|
|
#define ATDDR3_BIT7 _ATDDR3.Bits.BIT7
|
| 1581 |
|
|
#define ATDDR3_BIT8 _ATDDR3.Bits.BIT8
|
| 1582 |
|
|
#define ATDDR3_BIT9 _ATDDR3.Bits.BIT9
|
| 1583 |
|
|
#define ATDDR3_BIT10 _ATDDR3.Bits.BIT10
|
| 1584 |
|
|
#define ATDDR3_BIT11 _ATDDR3.Bits.BIT11
|
| 1585 |
|
|
#define ATDDR3_BIT12 _ATDDR3.Bits.BIT12
|
| 1586 |
|
|
#define ATDDR3_BIT13 _ATDDR3.Bits.BIT13
|
| 1587 |
|
|
#define ATDDR3_BIT14 _ATDDR3.Bits.BIT14
|
| 1588 |
|
|
#define ATDDR3_BIT15 _ATDDR3.Bits.BIT15
|
| 1589 |
|
|
#define ATDDR3_BIT_6 _ATDDR3.MergedBits.grpBIT_6
|
| 1590 |
|
|
#define ATDDR3_BIT ATDDR3_BIT_6
|
| 1591 |
|
|
|
| 1592 |
|
|
|
| 1593 |
|
|
/*** ATDDR4 - A/D Conversion Result Register 4; 0x00000098 ***/
|
| 1594 |
|
|
typedef union {
|
| 1595 |
|
|
word Word;
|
| 1596 |
|
|
/* Overlapped registers: */
|
| 1597 |
|
|
struct {
|
| 1598 |
|
|
/*** ATDDR4H - A/D Conversion Result Register 4 High; 0x00000098 ***/
|
| 1599 |
|
|
union {
|
| 1600 |
|
|
byte Byte;
|
| 1601 |
|
|
struct {
|
| 1602 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 1603 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 1604 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 1605 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 1606 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 1607 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 1608 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 1609 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 1610 |
|
|
} Bits;
|
| 1611 |
|
|
struct {
|
| 1612 |
|
|
byte grpBIT_8 :8;
|
| 1613 |
|
|
} MergedBits;
|
| 1614 |
|
|
} ATDDR4HSTR;
|
| 1615 |
|
|
#define ATDDR4H _ATDDR4.Overlap_STR.ATDDR4HSTR.Byte
|
| 1616 |
|
|
#define ATDDR4H_BIT8 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT8
|
| 1617 |
|
|
#define ATDDR4H_BIT9 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT9
|
| 1618 |
|
|
#define ATDDR4H_BIT10 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT10
|
| 1619 |
|
|
#define ATDDR4H_BIT11 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT11
|
| 1620 |
|
|
#define ATDDR4H_BIT12 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT12
|
| 1621 |
|
|
#define ATDDR4H_BIT13 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT13
|
| 1622 |
|
|
#define ATDDR4H_BIT14 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT14
|
| 1623 |
|
|
#define ATDDR4H_BIT15 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT15
|
| 1624 |
|
|
#define ATDDR4H_BIT_8 _ATDDR4.Overlap_STR.ATDDR4HSTR.MergedBits.grpBIT_8
|
| 1625 |
|
|
#define ATDDR4H_BIT ATDDR4H_BIT_8
|
| 1626 |
|
|
|
| 1627 |
|
|
/*** ATDDR4L - A/D Conversion Result Register 4 Low; 0x00000099 ***/
|
| 1628 |
|
|
union {
|
| 1629 |
|
|
byte Byte;
|
| 1630 |
|
|
struct {
|
| 1631 |
|
|
byte :1;
|
| 1632 |
|
|
byte :1;
|
| 1633 |
|
|
byte :1;
|
| 1634 |
|
|
byte :1;
|
| 1635 |
|
|
byte :1;
|
| 1636 |
|
|
byte :1;
|
| 1637 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 1638 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 1639 |
|
|
} Bits;
|
| 1640 |
|
|
struct {
|
| 1641 |
|
|
byte :1;
|
| 1642 |
|
|
byte :1;
|
| 1643 |
|
|
byte :1;
|
| 1644 |
|
|
byte :1;
|
| 1645 |
|
|
byte :1;
|
| 1646 |
|
|
byte :1;
|
| 1647 |
|
|
byte grpBIT_6 :2;
|
| 1648 |
|
|
} MergedBits;
|
| 1649 |
|
|
} ATDDR4LSTR;
|
| 1650 |
|
|
#define ATDDR4L _ATDDR4.Overlap_STR.ATDDR4LSTR.Byte
|
| 1651 |
|
|
#define ATDDR4L_BIT6 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT6
|
| 1652 |
|
|
#define ATDDR4L_BIT7 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT7
|
| 1653 |
|
|
#define ATDDR4L_BIT_6 _ATDDR4.Overlap_STR.ATDDR4LSTR.MergedBits.grpBIT_6
|
| 1654 |
|
|
#define ATDDR4L_BIT ATDDR4L_BIT_6
|
| 1655 |
|
|
|
| 1656 |
|
|
} Overlap_STR;
|
| 1657 |
|
|
|
| 1658 |
|
|
struct {
|
| 1659 |
|
|
word :1;
|
| 1660 |
|
|
word :1;
|
| 1661 |
|
|
word :1;
|
| 1662 |
|
|
word :1;
|
| 1663 |
|
|
word :1;
|
| 1664 |
|
|
word :1;
|
| 1665 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 1666 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 1667 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 1668 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 1669 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 1670 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 1671 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 1672 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 1673 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 1674 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 1675 |
|
|
} Bits;
|
| 1676 |
|
|
struct {
|
| 1677 |
|
|
word :1;
|
| 1678 |
|
|
word :1;
|
| 1679 |
|
|
word :1;
|
| 1680 |
|
|
word :1;
|
| 1681 |
|
|
word :1;
|
| 1682 |
|
|
word :1;
|
| 1683 |
|
|
word grpBIT_6 :10;
|
| 1684 |
|
|
} MergedBits;
|
| 1685 |
|
|
} ATDDR4STR;
|
| 1686 |
|
|
extern volatile ATDDR4STR _ATDDR4 @(REG_BASE + 0x00000098);
|
| 1687 |
|
|
#define ATDDR4 _ATDDR4.Word
|
| 1688 |
|
|
#define ATDDR4_BIT6 _ATDDR4.Bits.BIT6
|
| 1689 |
|
|
#define ATDDR4_BIT7 _ATDDR4.Bits.BIT7
|
| 1690 |
|
|
#define ATDDR4_BIT8 _ATDDR4.Bits.BIT8
|
| 1691 |
|
|
#define ATDDR4_BIT9 _ATDDR4.Bits.BIT9
|
| 1692 |
|
|
#define ATDDR4_BIT10 _ATDDR4.Bits.BIT10
|
| 1693 |
|
|
#define ATDDR4_BIT11 _ATDDR4.Bits.BIT11
|
| 1694 |
|
|
#define ATDDR4_BIT12 _ATDDR4.Bits.BIT12
|
| 1695 |
|
|
#define ATDDR4_BIT13 _ATDDR4.Bits.BIT13
|
| 1696 |
|
|
#define ATDDR4_BIT14 _ATDDR4.Bits.BIT14
|
| 1697 |
|
|
#define ATDDR4_BIT15 _ATDDR4.Bits.BIT15
|
| 1698 |
|
|
#define ATDDR4_BIT_6 _ATDDR4.MergedBits.grpBIT_6
|
| 1699 |
|
|
#define ATDDR4_BIT ATDDR4_BIT_6
|
| 1700 |
|
|
|
| 1701 |
|
|
|
| 1702 |
|
|
/*** ATDDR5 - A/D Conversion Result Register 5; 0x0000009A ***/
|
| 1703 |
|
|
typedef union {
|
| 1704 |
|
|
word Word;
|
| 1705 |
|
|
/* Overlapped registers: */
|
| 1706 |
|
|
struct {
|
| 1707 |
|
|
/*** ATDDR5H - A/D Conversion Result Register 5 High; 0x0000009A ***/
|
| 1708 |
|
|
union {
|
| 1709 |
|
|
byte Byte;
|
| 1710 |
|
|
struct {
|
| 1711 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 1712 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 1713 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 1714 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 1715 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 1716 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 1717 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 1718 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 1719 |
|
|
} Bits;
|
| 1720 |
|
|
struct {
|
| 1721 |
|
|
byte grpBIT_8 :8;
|
| 1722 |
|
|
} MergedBits;
|
| 1723 |
|
|
} ATDDR5HSTR;
|
| 1724 |
|
|
#define ATDDR5H _ATDDR5.Overlap_STR.ATDDR5HSTR.Byte
|
| 1725 |
|
|
#define ATDDR5H_BIT8 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT8
|
| 1726 |
|
|
#define ATDDR5H_BIT9 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT9
|
| 1727 |
|
|
#define ATDDR5H_BIT10 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT10
|
| 1728 |
|
|
#define ATDDR5H_BIT11 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT11
|
| 1729 |
|
|
#define ATDDR5H_BIT12 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT12
|
| 1730 |
|
|
#define ATDDR5H_BIT13 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT13
|
| 1731 |
|
|
#define ATDDR5H_BIT14 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT14
|
| 1732 |
|
|
#define ATDDR5H_BIT15 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT15
|
| 1733 |
|
|
#define ATDDR5H_BIT_8 _ATDDR5.Overlap_STR.ATDDR5HSTR.MergedBits.grpBIT_8
|
| 1734 |
|
|
#define ATDDR5H_BIT ATDDR5H_BIT_8
|
| 1735 |
|
|
|
| 1736 |
|
|
/*** ATDDR5L - A/D Conversion Result Register 5 Low; 0x0000009B ***/
|
| 1737 |
|
|
union {
|
| 1738 |
|
|
byte Byte;
|
| 1739 |
|
|
struct {
|
| 1740 |
|
|
byte :1;
|
| 1741 |
|
|
byte :1;
|
| 1742 |
|
|
byte :1;
|
| 1743 |
|
|
byte :1;
|
| 1744 |
|
|
byte :1;
|
| 1745 |
|
|
byte :1;
|
| 1746 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 1747 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 1748 |
|
|
} Bits;
|
| 1749 |
|
|
struct {
|
| 1750 |
|
|
byte :1;
|
| 1751 |
|
|
byte :1;
|
| 1752 |
|
|
byte :1;
|
| 1753 |
|
|
byte :1;
|
| 1754 |
|
|
byte :1;
|
| 1755 |
|
|
byte :1;
|
| 1756 |
|
|
byte grpBIT_6 :2;
|
| 1757 |
|
|
} MergedBits;
|
| 1758 |
|
|
} ATDDR5LSTR;
|
| 1759 |
|
|
#define ATDDR5L _ATDDR5.Overlap_STR.ATDDR5LSTR.Byte
|
| 1760 |
|
|
#define ATDDR5L_BIT6 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT6
|
| 1761 |
|
|
#define ATDDR5L_BIT7 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT7
|
| 1762 |
|
|
#define ATDDR5L_BIT_6 _ATDDR5.Overlap_STR.ATDDR5LSTR.MergedBits.grpBIT_6
|
| 1763 |
|
|
#define ATDDR5L_BIT ATDDR5L_BIT_6
|
| 1764 |
|
|
|
| 1765 |
|
|
} Overlap_STR;
|
| 1766 |
|
|
|
| 1767 |
|
|
struct {
|
| 1768 |
|
|
word :1;
|
| 1769 |
|
|
word :1;
|
| 1770 |
|
|
word :1;
|
| 1771 |
|
|
word :1;
|
| 1772 |
|
|
word :1;
|
| 1773 |
|
|
word :1;
|
| 1774 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 1775 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 1776 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 1777 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 1778 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 1779 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 1780 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 1781 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 1782 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 1783 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 1784 |
|
|
} Bits;
|
| 1785 |
|
|
struct {
|
| 1786 |
|
|
word :1;
|
| 1787 |
|
|
word :1;
|
| 1788 |
|
|
word :1;
|
| 1789 |
|
|
word :1;
|
| 1790 |
|
|
word :1;
|
| 1791 |
|
|
word :1;
|
| 1792 |
|
|
word grpBIT_6 :10;
|
| 1793 |
|
|
} MergedBits;
|
| 1794 |
|
|
} ATDDR5STR;
|
| 1795 |
|
|
extern volatile ATDDR5STR _ATDDR5 @(REG_BASE + 0x0000009A);
|
| 1796 |
|
|
#define ATDDR5 _ATDDR5.Word
|
| 1797 |
|
|
#define ATDDR5_BIT6 _ATDDR5.Bits.BIT6
|
| 1798 |
|
|
#define ATDDR5_BIT7 _ATDDR5.Bits.BIT7
|
| 1799 |
|
|
#define ATDDR5_BIT8 _ATDDR5.Bits.BIT8
|
| 1800 |
|
|
#define ATDDR5_BIT9 _ATDDR5.Bits.BIT9
|
| 1801 |
|
|
#define ATDDR5_BIT10 _ATDDR5.Bits.BIT10
|
| 1802 |
|
|
#define ATDDR5_BIT11 _ATDDR5.Bits.BIT11
|
| 1803 |
|
|
#define ATDDR5_BIT12 _ATDDR5.Bits.BIT12
|
| 1804 |
|
|
#define ATDDR5_BIT13 _ATDDR5.Bits.BIT13
|
| 1805 |
|
|
#define ATDDR5_BIT14 _ATDDR5.Bits.BIT14
|
| 1806 |
|
|
#define ATDDR5_BIT15 _ATDDR5.Bits.BIT15
|
| 1807 |
|
|
#define ATDDR5_BIT_6 _ATDDR5.MergedBits.grpBIT_6
|
| 1808 |
|
|
#define ATDDR5_BIT ATDDR5_BIT_6
|
| 1809 |
|
|
|
| 1810 |
|
|
|
| 1811 |
|
|
/*** ATDDR6 - A/D Conversion Result Register 6; 0x0000009C ***/
|
| 1812 |
|
|
typedef union {
|
| 1813 |
|
|
word Word;
|
| 1814 |
|
|
/* Overlapped registers: */
|
| 1815 |
|
|
struct {
|
| 1816 |
|
|
/*** ATDDR6H - A/D Conversion Result Register 6 High; 0x0000009C ***/
|
| 1817 |
|
|
union {
|
| 1818 |
|
|
byte Byte;
|
| 1819 |
|
|
struct {
|
| 1820 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 1821 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 1822 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 1823 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 1824 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 1825 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 1826 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 1827 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 1828 |
|
|
} Bits;
|
| 1829 |
|
|
struct {
|
| 1830 |
|
|
byte grpBIT_8 :8;
|
| 1831 |
|
|
} MergedBits;
|
| 1832 |
|
|
} ATDDR6HSTR;
|
| 1833 |
|
|
#define ATDDR6H _ATDDR6.Overlap_STR.ATDDR6HSTR.Byte
|
| 1834 |
|
|
#define ATDDR6H_BIT8 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT8
|
| 1835 |
|
|
#define ATDDR6H_BIT9 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT9
|
| 1836 |
|
|
#define ATDDR6H_BIT10 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT10
|
| 1837 |
|
|
#define ATDDR6H_BIT11 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT11
|
| 1838 |
|
|
#define ATDDR6H_BIT12 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT12
|
| 1839 |
|
|
#define ATDDR6H_BIT13 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT13
|
| 1840 |
|
|
#define ATDDR6H_BIT14 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT14
|
| 1841 |
|
|
#define ATDDR6H_BIT15 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT15
|
| 1842 |
|
|
#define ATDDR6H_BIT_8 _ATDDR6.Overlap_STR.ATDDR6HSTR.MergedBits.grpBIT_8
|
| 1843 |
|
|
#define ATDDR6H_BIT ATDDR6H_BIT_8
|
| 1844 |
|
|
|
| 1845 |
|
|
/*** ATDDR6L - A/D Conversion Result Register 6 Low; 0x0000009D ***/
|
| 1846 |
|
|
union {
|
| 1847 |
|
|
byte Byte;
|
| 1848 |
|
|
struct {
|
| 1849 |
|
|
byte :1;
|
| 1850 |
|
|
byte :1;
|
| 1851 |
|
|
byte :1;
|
| 1852 |
|
|
byte :1;
|
| 1853 |
|
|
byte :1;
|
| 1854 |
|
|
byte :1;
|
| 1855 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 1856 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 1857 |
|
|
} Bits;
|
| 1858 |
|
|
struct {
|
| 1859 |
|
|
byte :1;
|
| 1860 |
|
|
byte :1;
|
| 1861 |
|
|
byte :1;
|
| 1862 |
|
|
byte :1;
|
| 1863 |
|
|
byte :1;
|
| 1864 |
|
|
byte :1;
|
| 1865 |
|
|
byte grpBIT_6 :2;
|
| 1866 |
|
|
} MergedBits;
|
| 1867 |
|
|
} ATDDR6LSTR;
|
| 1868 |
|
|
#define ATDDR6L _ATDDR6.Overlap_STR.ATDDR6LSTR.Byte
|
| 1869 |
|
|
#define ATDDR6L_BIT6 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT6
|
| 1870 |
|
|
#define ATDDR6L_BIT7 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT7
|
| 1871 |
|
|
#define ATDDR6L_BIT_6 _ATDDR6.Overlap_STR.ATDDR6LSTR.MergedBits.grpBIT_6
|
| 1872 |
|
|
#define ATDDR6L_BIT ATDDR6L_BIT_6
|
| 1873 |
|
|
|
| 1874 |
|
|
} Overlap_STR;
|
| 1875 |
|
|
|
| 1876 |
|
|
struct {
|
| 1877 |
|
|
word :1;
|
| 1878 |
|
|
word :1;
|
| 1879 |
|
|
word :1;
|
| 1880 |
|
|
word :1;
|
| 1881 |
|
|
word :1;
|
| 1882 |
|
|
word :1;
|
| 1883 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 1884 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 1885 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 1886 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 1887 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 1888 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 1889 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 1890 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 1891 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 1892 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 1893 |
|
|
} Bits;
|
| 1894 |
|
|
struct {
|
| 1895 |
|
|
word :1;
|
| 1896 |
|
|
word :1;
|
| 1897 |
|
|
word :1;
|
| 1898 |
|
|
word :1;
|
| 1899 |
|
|
word :1;
|
| 1900 |
|
|
word :1;
|
| 1901 |
|
|
word grpBIT_6 :10;
|
| 1902 |
|
|
} MergedBits;
|
| 1903 |
|
|
} ATDDR6STR;
|
| 1904 |
|
|
extern volatile ATDDR6STR _ATDDR6 @(REG_BASE + 0x0000009C);
|
| 1905 |
|
|
#define ATDDR6 _ATDDR6.Word
|
| 1906 |
|
|
#define ATDDR6_BIT6 _ATDDR6.Bits.BIT6
|
| 1907 |
|
|
#define ATDDR6_BIT7 _ATDDR6.Bits.BIT7
|
| 1908 |
|
|
#define ATDDR6_BIT8 _ATDDR6.Bits.BIT8
|
| 1909 |
|
|
#define ATDDR6_BIT9 _ATDDR6.Bits.BIT9
|
| 1910 |
|
|
#define ATDDR6_BIT10 _ATDDR6.Bits.BIT10
|
| 1911 |
|
|
#define ATDDR6_BIT11 _ATDDR6.Bits.BIT11
|
| 1912 |
|
|
#define ATDDR6_BIT12 _ATDDR6.Bits.BIT12
|
| 1913 |
|
|
#define ATDDR6_BIT13 _ATDDR6.Bits.BIT13
|
| 1914 |
|
|
#define ATDDR6_BIT14 _ATDDR6.Bits.BIT14
|
| 1915 |
|
|
#define ATDDR6_BIT15 _ATDDR6.Bits.BIT15
|
| 1916 |
|
|
#define ATDDR6_BIT_6 _ATDDR6.MergedBits.grpBIT_6
|
| 1917 |
|
|
#define ATDDR6_BIT ATDDR6_BIT_6
|
| 1918 |
|
|
|
| 1919 |
|
|
|
| 1920 |
|
|
/*** ATDDR7 - A/D Conversion Result Register 7; 0x0000009E ***/
|
| 1921 |
|
|
typedef union {
|
| 1922 |
|
|
word Word;
|
| 1923 |
|
|
/* Overlapped registers: */
|
| 1924 |
|
|
struct {
|
| 1925 |
|
|
/*** ATDDR7H - A/D Conversion Result Register 7 High; 0x0000009E ***/
|
| 1926 |
|
|
union {
|
| 1927 |
|
|
byte Byte;
|
| 1928 |
|
|
struct {
|
| 1929 |
|
|
byte BIT8 :1; /* Bit 8 */
|
| 1930 |
|
|
byte BIT9 :1; /* Bit 9 */
|
| 1931 |
|
|
byte BIT10 :1; /* Bit 10 */
|
| 1932 |
|
|
byte BIT11 :1; /* Bit 11 */
|
| 1933 |
|
|
byte BIT12 :1; /* Bit 12 */
|
| 1934 |
|
|
byte BIT13 :1; /* Bit 13 */
|
| 1935 |
|
|
byte BIT14 :1; /* Bit 14 */
|
| 1936 |
|
|
byte BIT15 :1; /* Bit 15 */
|
| 1937 |
|
|
} Bits;
|
| 1938 |
|
|
struct {
|
| 1939 |
|
|
byte grpBIT_8 :8;
|
| 1940 |
|
|
} MergedBits;
|
| 1941 |
|
|
} ATDDR7HSTR;
|
| 1942 |
|
|
#define ATDDR7H _ATDDR7.Overlap_STR.ATDDR7HSTR.Byte
|
| 1943 |
|
|
#define ATDDR7H_BIT8 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT8
|
| 1944 |
|
|
#define ATDDR7H_BIT9 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT9
|
| 1945 |
|
|
#define ATDDR7H_BIT10 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT10
|
| 1946 |
|
|
#define ATDDR7H_BIT11 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT11
|
| 1947 |
|
|
#define ATDDR7H_BIT12 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT12
|
| 1948 |
|
|
#define ATDDR7H_BIT13 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT13
|
| 1949 |
|
|
#define ATDDR7H_BIT14 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT14
|
| 1950 |
|
|
#define ATDDR7H_BIT15 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT15
|
| 1951 |
|
|
#define ATDDR7H_BIT_8 _ATDDR7.Overlap_STR.ATDDR7HSTR.MergedBits.grpBIT_8
|
| 1952 |
|
|
#define ATDDR7H_BIT ATDDR7H_BIT_8
|
| 1953 |
|
|
|
| 1954 |
|
|
/*** ATDDR7L - A/D Conversion Result Register 7 Low; 0x0000009F ***/
|
| 1955 |
|
|
union {
|
| 1956 |
|
|
byte Byte;
|
| 1957 |
|
|
struct {
|
| 1958 |
|
|
byte :1;
|
| 1959 |
|
|
byte :1;
|
| 1960 |
|
|
byte :1;
|
| 1961 |
|
|
byte :1;
|
| 1962 |
|
|
byte :1;
|
| 1963 |
|
|
byte :1;
|
| 1964 |
|
|
byte BIT6 :1; /* Bit 6 */
|
| 1965 |
|
|
byte BIT7 :1; /* Bit 7 */
|
| 1966 |
|
|
} Bits;
|
| 1967 |
|
|
struct {
|
| 1968 |
|
|
byte :1;
|
| 1969 |
|
|
byte :1;
|
| 1970 |
|
|
byte :1;
|
| 1971 |
|
|
byte :1;
|
| 1972 |
|
|
byte :1;
|
| 1973 |
|
|
byte :1;
|
| 1974 |
|
|
byte grpBIT_6 :2;
|
| 1975 |
|
|
} MergedBits;
|
| 1976 |
|
|
} ATDDR7LSTR;
|
| 1977 |
|
|
#define ATDDR7L _ATDDR7.Overlap_STR.ATDDR7LSTR.Byte
|
| 1978 |
|
|
#define ATDDR7L_BIT6 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT6
|
| 1979 |
|
|
#define ATDDR7L_BIT7 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT7
|
| 1980 |
|
|
#define ATDDR7L_BIT_6 _ATDDR7.Overlap_STR.ATDDR7LSTR.MergedBits.grpBIT_6
|
| 1981 |
|
|
#define ATDDR7L_BIT ATDDR7L_BIT_6
|
| 1982 |
|
|
|
| 1983 |
|
|
} Overlap_STR;
|
| 1984 |
|
|
|
| 1985 |
|
|
struct {
|
| 1986 |
|
|
word :1;
|
| 1987 |
|
|
word :1;
|
| 1988 |
|
|
word :1;
|
| 1989 |
|
|
word :1;
|
| 1990 |
|
|
word :1;
|
| 1991 |
|
|
word :1;
|
| 1992 |
|
|
word BIT6 :1; /* Bit 6 */
|
| 1993 |
|
|
word BIT7 :1; /* Bit 7 */
|
| 1994 |
|
|
word BIT8 :1; /* Bit 8 */
|
| 1995 |
|
|
word BIT9 :1; /* Bit 9 */
|
| 1996 |
|
|
word BIT10 :1; /* Bit 10 */
|
| 1997 |
|
|
word BIT11 :1; /* Bit 11 */
|
| 1998 |
|
|
word BIT12 :1; /* Bit 12 */
|
| 1999 |
|
|
word BIT13 :1; /* Bit 13 */
|
| 2000 |
|
|
word BIT14 :1; /* Bit 14 */
|
| 2001 |
|
|
word BIT15 :1; /* Bit 15 */
|
| 2002 |
|
|
} Bits;
|
| 2003 |
|
|
struct {
|
| 2004 |
|
|
word :1;
|
| 2005 |
|
|
word :1;
|
| 2006 |
|
|
word :1;
|
| 2007 |
|
|
word :1;
|
| 2008 |
|
|
word :1;
|
| 2009 |
|
|
word :1;
|
| 2010 |
|
|
word grpBIT_6 :10;
|
| 2011 |
|
|
} MergedBits;
|
| 2012 |
|
|
} ATDDR7STR;
|
| 2013 |
|
|
extern volatile ATDDR7STR _ATDDR7 @(REG_BASE + 0x0000009E);
|
| 2014 |
|
|
#define ATDDR7 _ATDDR7.Word
|
| 2015 |
|
|
#define ATDDR7_BIT6 _ATDDR7.Bits.BIT6
|
| 2016 |
|
|
#define ATDDR7_BIT7 _ATDDR7.Bits.BIT7
|
| 2017 |
|
|
#define ATDDR7_BIT8 _ATDDR7.Bits.BIT8
|
| 2018 |
|
|
#define ATDDR7_BIT9 _ATDDR7.Bits.BIT9
|
| 2019 |
|
|
#define ATDDR7_BIT10 _ATDDR7.Bits.BIT10
|
| 2020 |
|
|
#define ATDDR7_BIT11 _ATDDR7.Bits.BIT11
|
| 2021 |
|
|
#define ATDDR7_BIT12 _ATDDR7.Bits.BIT12
|
| 2022 |
|
|
#define ATDDR7_BIT13 _ATDDR7.Bits.BIT13
|
| 2023 |
|
|
#define ATDDR7_BIT14 _ATDDR7.Bits.BIT14
|
| 2024 |
|
|
#define ATDDR7_BIT15 _ATDDR7.Bits.BIT15
|
| 2025 |
|
|
#define ATDDR7_BIT_6 _ATDDR7.MergedBits.grpBIT_6
|
| 2026 |
|
|
#define ATDDR7_BIT ATDDR7_BIT_6
|
| 2027 |
|
|
|
| 2028 |
|
|
|
| 2029 |
|
|
/*** SCIBD - SCI Baud Rate Register; 0x000000C8 ***/
|
| 2030 |
|
|
typedef union {
|
| 2031 |
|
|
word Word;
|
| 2032 |
|
|
/* Overlapped registers: */
|
| 2033 |
|
|
struct {
|
| 2034 |
|
|
/*** SCIBDH - SCI Baud Rate Register High; 0x000000C8 ***/
|
| 2035 |
|
|
union {
|
| 2036 |
|
|
byte Byte;
|
| 2037 |
|
|
struct {
|
| 2038 |
|
|
byte SBR8 :1; /* SCI baud rate Bit 8 */
|
| 2039 |
|
|
byte SBR9 :1; /* SCI baud rate Bit 9 */
|
| 2040 |
|
|
byte SBR10 :1; /* SCI baud rate Bit 10 */
|
| 2041 |
|
|
byte SBR11 :1; /* SCI baud rate Bit 11 */
|
| 2042 |
|
|
byte SBR12 :1; /* SCI baud rate Bit 12 */
|
| 2043 |
|
|
byte :1;
|
| 2044 |
|
|
byte :1;
|
| 2045 |
|
|
byte :1;
|
| 2046 |
|
|
} Bits;
|
| 2047 |
|
|
struct {
|
| 2048 |
|
|
byte grpSBR_8 :5;
|
| 2049 |
|
|
byte :1;
|
| 2050 |
|
|
byte :1;
|
| 2051 |
|
|
byte :1;
|
| 2052 |
|
|
} MergedBits;
|
| 2053 |
|
|
} SCIBDHSTR;
|
| 2054 |
|
|
#define SCIBDH _SCIBD.Overlap_STR.SCIBDHSTR.Byte
|
| 2055 |
|
|
#define SCIBDH_SBR8 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR8
|
| 2056 |
|
|
#define SCIBDH_SBR9 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR9
|
| 2057 |
|
|
#define SCIBDH_SBR10 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR10
|
| 2058 |
|
|
#define SCIBDH_SBR11 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR11
|
| 2059 |
|
|
#define SCIBDH_SBR12 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR12
|
| 2060 |
|
|
#define SCIBDH_SBR_8 _SCIBD.Overlap_STR.SCIBDHSTR.MergedBits.grpSBR_8
|
| 2061 |
|
|
#define SCIBDH_SBR SCIBDH_SBR_8
|
| 2062 |
|
|
|
| 2063 |
|
|
/*** SCIBDL - SCI Baud Rate Register Low; 0x000000C9 ***/
|
| 2064 |
|
|
union {
|
| 2065 |
|
|
byte Byte;
|
| 2066 |
|
|
struct {
|
| 2067 |
|
|
byte SBR0 :1; /* SCI baud rate Bit 0 */
|
| 2068 |
|
|
byte SBR1 :1; /* SCI baud rate Bit 1 */
|
| 2069 |
|
|
byte SBR2 :1; /* SCI baud rate Bit 2 */
|
| 2070 |
|
|
byte SBR3 :1; /* SCI baud rate Bit 3 */
|
| 2071 |
|
|
byte SBR4 :1; /* SCI baud rate Bit 4 */
|
| 2072 |
|
|
byte SBR5 :1; /* SCI baud rate Bit 5 */
|
| 2073 |
|
|
byte SBR6 :1; /* SCI baud rate Bit 6 */
|
| 2074 |
|
|
byte SBR7 :1; /* SCI baud rate Bit 7 */
|
| 2075 |
|
|
} Bits;
|
| 2076 |
|
|
struct {
|
| 2077 |
|
|
byte grpSBR :8;
|
| 2078 |
|
|
} MergedBits;
|
| 2079 |
|
|
} SCIBDLSTR;
|
| 2080 |
|
|
#define SCIBDL _SCIBD.Overlap_STR.SCIBDLSTR.Byte
|
| 2081 |
|
|
#define SCIBDL_SBR0 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR0
|
| 2082 |
|
|
#define SCIBDL_SBR1 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR1
|
| 2083 |
|
|
#define SCIBDL_SBR2 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR2
|
| 2084 |
|
|
#define SCIBDL_SBR3 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR3
|
| 2085 |
|
|
#define SCIBDL_SBR4 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR4
|
| 2086 |
|
|
#define SCIBDL_SBR5 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR5
|
| 2087 |
|
|
#define SCIBDL_SBR6 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR6
|
| 2088 |
|
|
#define SCIBDL_SBR7 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR7
|
| 2089 |
|
|
#define SCIBDL_SBR _SCIBD.Overlap_STR.SCIBDLSTR.MergedBits.grpSBR
|
| 2090 |
|
|
|
| 2091 |
|
|
} Overlap_STR;
|
| 2092 |
|
|
|
| 2093 |
|
|
struct {
|
| 2094 |
|
|
word SBR0 :1; /* SCI baud rate Bit 0 */
|
| 2095 |
|
|
word SBR1 :1; /* SCI baud rate Bit 1 */
|
| 2096 |
|
|
word SBR2 :1; /* SCI baud rate Bit 2 */
|
| 2097 |
|
|
word SBR3 :1; /* SCI baud rate Bit 3 */
|
| 2098 |
|
|
word SBR4 :1; /* SCI baud rate Bit 4 */
|
| 2099 |
|
|
word SBR5 :1; /* SCI baud rate Bit 5 */
|
| 2100 |
|
|
word SBR6 :1; /* SCI baud rate Bit 6 */
|
| 2101 |
|
|
word SBR7 :1; /* SCI baud rate Bit 7 */
|
| 2102 |
|
|
word SBR8 :1; /* SCI baud rate Bit 8 */
|
| 2103 |
|
|
word SBR9 :1; /* SCI baud rate Bit 9 */
|
| 2104 |
|
|
word SBR10 :1; /* SCI baud rate Bit 10 */
|
| 2105 |
|
|
word SBR11 :1; /* SCI baud rate Bit 11 */
|
| 2106 |
|
|
word SBR12 :1; /* SCI baud rate Bit 12 */
|
| 2107 |
|
|
word :1;
|
| 2108 |
|
|
word :1;
|
| 2109 |
|
|
word :1;
|
| 2110 |
|
|
} Bits;
|
| 2111 |
|
|
struct {
|
| 2112 |
|
|
word grpSBR :13;
|
| 2113 |
|
|
word :1;
|
| 2114 |
|
|
word :1;
|
| 2115 |
|
|
word :1;
|
| 2116 |
|
|
} MergedBits;
|
| 2117 |
|
|
} SCIBDSTR;
|
| 2118 |
|
|
extern volatile SCIBDSTR _SCIBD @(REG_BASE + 0x000000C8);
|
| 2119 |
|
|
#define SCIBD _SCIBD.Word
|
| 2120 |
|
|
#define SCIBD_SBR0 _SCIBD.Bits.SBR0
|
| 2121 |
|
|
#define SCIBD_SBR1 _SCIBD.Bits.SBR1
|
| 2122 |
|
|
#define SCIBD_SBR2 _SCIBD.Bits.SBR2
|
| 2123 |
|
|
#define SCIBD_SBR3 _SCIBD.Bits.SBR3
|
| 2124 |
|
|
#define SCIBD_SBR4 _SCIBD.Bits.SBR4
|
| 2125 |
|
|
#define SCIBD_SBR5 _SCIBD.Bits.SBR5
|
| 2126 |
|
|
#define SCIBD_SBR6 _SCIBD.Bits.SBR6
|
| 2127 |
|
|
#define SCIBD_SBR7 _SCIBD.Bits.SBR7
|
| 2128 |
|
|
#define SCIBD_SBR8 _SCIBD.Bits.SBR8
|
| 2129 |
|
|
#define SCIBD_SBR9 _SCIBD.Bits.SBR9
|
| 2130 |
|
|
#define SCIBD_SBR10 _SCIBD.Bits.SBR10
|
| 2131 |
|
|
#define SCIBD_SBR11 _SCIBD.Bits.SBR11
|
| 2132 |
|
|
#define SCIBD_SBR12 _SCIBD.Bits.SBR12
|
| 2133 |
|
|
#define SCIBD_SBR _SCIBD.MergedBits.grpSBR
|
| 2134 |
|
|
|
| 2135 |
|
|
|
| 2136 |
|
|
/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000EC ***/
|
| 2137 |
|
|
typedef union {
|
| 2138 |
|
|
word Word;
|
| 2139 |
|
|
/* Overlapped registers: */
|
| 2140 |
|
|
struct {
|
| 2141 |
|
|
/*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000EC ***/
|
| 2142 |
|
|
union {
|
| 2143 |
|
|
byte Byte;
|
| 2144 |
|
|
struct {
|
| 2145 |
|
|
byte grpBIT :8;
|
| 2146 |
|
|
} MergedBits;
|
| 2147 |
|
|
} PWMCNT0STR;
|
| 2148 |
|
|
#define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte
|
| 2149 |
|
|
#define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT
|
| 2150 |
|
|
|
| 2151 |
|
|
/*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000ED ***/
|
| 2152 |
|
|
union {
|
| 2153 |
|
|
byte Byte;
|
| 2154 |
|
|
struct {
|
| 2155 |
|
|
byte grpBIT :8;
|
| 2156 |
|
|
} MergedBits;
|
| 2157 |
|
|
} PWMCNT1STR;
|
| 2158 |
|
|
#define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte
|
| 2159 |
|
|
#define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT
|
| 2160 |
|
|
|
| 2161 |
|
|
} Overlap_STR;
|
| 2162 |
|
|
|
| 2163 |
|
|
struct {
|
| 2164 |
|
|
word grpBIT :16;
|
| 2165 |
|
|
} MergedBits;
|
| 2166 |
|
|
} PWMCNT01STR;
|
| 2167 |
|
|
extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000EC);
|
| 2168 |
|
|
#define PWMCNT01 _PWMCNT01.Word
|
| 2169 |
|
|
#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT
|
| 2170 |
|
|
|
| 2171 |
|
|
|
| 2172 |
|
|
/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000EE ***/
|
| 2173 |
|
|
typedef union {
|
| 2174 |
|
|
word Word;
|
| 2175 |
|
|
/* Overlapped registers: */
|
| 2176 |
|
|
struct {
|
| 2177 |
|
|
/*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000EE ***/
|
| 2178 |
|
|
union {
|
| 2179 |
|
|
byte Byte;
|
| 2180 |
|
|
struct {
|
| 2181 |
|
|
byte grpBIT :8;
|
| 2182 |
|
|
} MergedBits;
|
| 2183 |
|
|
} PWMCNT2STR;
|
| 2184 |
|
|
#define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte
|
| 2185 |
|
|
#define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT
|
| 2186 |
|
|
|
| 2187 |
|
|
/*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000EF ***/
|
| 2188 |
|
|
union {
|
| 2189 |
|
|
byte Byte;
|
| 2190 |
|
|
struct {
|
| 2191 |
|
|
byte grpBIT :8;
|
| 2192 |
|
|
} MergedBits;
|
| 2193 |
|
|
} PWMCNT3STR;
|
| 2194 |
|
|
#define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte
|
| 2195 |
|
|
#define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT
|
| 2196 |
|
|
|
| 2197 |
|
|
} Overlap_STR;
|
| 2198 |
|
|
|
| 2199 |
|
|
struct {
|
| 2200 |
|
|
word grpBIT :16;
|
| 2201 |
|
|
} MergedBits;
|
| 2202 |
|
|
} PWMCNT23STR;
|
| 2203 |
|
|
extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000EE);
|
| 2204 |
|
|
#define PWMCNT23 _PWMCNT23.Word
|
| 2205 |
|
|
#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT
|
| 2206 |
|
|
|
| 2207 |
|
|
|
| 2208 |
|
|
/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000F0 ***/
|
| 2209 |
|
|
typedef union {
|
| 2210 |
|
|
word Word;
|
| 2211 |
|
|
/* Overlapped registers: */
|
| 2212 |
|
|
struct {
|
| 2213 |
|
|
/*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000F0 ***/
|
| 2214 |
|
|
union {
|
| 2215 |
|
|
byte Byte;
|
| 2216 |
|
|
struct {
|
| 2217 |
|
|
byte grpBIT :8;
|
| 2218 |
|
|
} MergedBits;
|
| 2219 |
|
|
} PWMCNT4STR;
|
| 2220 |
|
|
#define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte
|
| 2221 |
|
|
#define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT
|
| 2222 |
|
|
|
| 2223 |
|
|
/*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000F1 ***/
|
| 2224 |
|
|
union {
|
| 2225 |
|
|
byte Byte;
|
| 2226 |
|
|
struct {
|
| 2227 |
|
|
byte grpBIT :8;
|
| 2228 |
|
|
} MergedBits;
|
| 2229 |
|
|
} PWMCNT5STR;
|
| 2230 |
|
|
#define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte
|
| 2231 |
|
|
#define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT
|
| 2232 |
|
|
|
| 2233 |
|
|
} Overlap_STR;
|
| 2234 |
|
|
|
| 2235 |
|
|
struct {
|
| 2236 |
|
|
word grpBIT :16;
|
| 2237 |
|
|
} MergedBits;
|
| 2238 |
|
|
} PWMCNT45STR;
|
| 2239 |
|
|
extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000F0);
|
| 2240 |
|
|
#define PWMCNT45 _PWMCNT45.Word
|
| 2241 |
|
|
#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT
|
| 2242 |
|
|
|
| 2243 |
|
|
|
| 2244 |
|
|
/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000F2 ***/
|
| 2245 |
|
|
typedef union {
|
| 2246 |
|
|
word Word;
|
| 2247 |
|
|
/* Overlapped registers: */
|
| 2248 |
|
|
struct {
|
| 2249 |
|
|
/*** PWMPER0 - PWM Channel Period 0 Register; 0x000000F2 ***/
|
| 2250 |
|
|
union {
|
| 2251 |
|
|
byte Byte;
|
| 2252 |
|
|
struct {
|
| 2253 |
|
|
byte grpBIT :8;
|
| 2254 |
|
|
} MergedBits;
|
| 2255 |
|
|
} PWMPER0STR;
|
| 2256 |
|
|
#define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte
|
| 2257 |
|
|
#define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT
|
| 2258 |
|
|
|
| 2259 |
|
|
/*** PWMPER1 - PWM Channel Period 1 Register; 0x000000F3 ***/
|
| 2260 |
|
|
union {
|
| 2261 |
|
|
byte Byte;
|
| 2262 |
|
|
struct {
|
| 2263 |
|
|
byte grpBIT :8;
|
| 2264 |
|
|
} MergedBits;
|
| 2265 |
|
|
} PWMPER1STR;
|
| 2266 |
|
|
#define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte
|
| 2267 |
|
|
#define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT
|
| 2268 |
|
|
|
| 2269 |
|
|
} Overlap_STR;
|
| 2270 |
|
|
|
| 2271 |
|
|
struct {
|
| 2272 |
|
|
word grpBIT :16;
|
| 2273 |
|
|
} MergedBits;
|
| 2274 |
|
|
} PWMPER01STR;
|
| 2275 |
|
|
extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000F2);
|
| 2276 |
|
|
#define PWMPER01 _PWMPER01.Word
|
| 2277 |
|
|
#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT
|
| 2278 |
|
|
|
| 2279 |
|
|
|
| 2280 |
|
|
/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000F4 ***/
|
| 2281 |
|
|
typedef union {
|
| 2282 |
|
|
word Word;
|
| 2283 |
|
|
/* Overlapped registers: */
|
| 2284 |
|
|
struct {
|
| 2285 |
|
|
/*** PWMPER2 - PWM Channel Period 2 Register; 0x000000F4 ***/
|
| 2286 |
|
|
union {
|
| 2287 |
|
|
byte Byte;
|
| 2288 |
|
|
struct {
|
| 2289 |
|
|
byte grpBIT :8;
|
| 2290 |
|
|
} MergedBits;
|
| 2291 |
|
|
} PWMPER2STR;
|
| 2292 |
|
|
#define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte
|
| 2293 |
|
|
#define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT
|
| 2294 |
|
|
|
| 2295 |
|
|
/*** PWMPER3 - PWM Channel Period 3 Register; 0x000000F5 ***/
|
| 2296 |
|
|
union {
|
| 2297 |
|
|
byte Byte;
|
| 2298 |
|
|
struct {
|
| 2299 |
|
|
byte grpBIT :8;
|
| 2300 |
|
|
} MergedBits;
|
| 2301 |
|
|
} PWMPER3STR;
|
| 2302 |
|
|
#define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte
|
| 2303 |
|
|
#define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT
|
| 2304 |
|
|
|
| 2305 |
|
|
} Overlap_STR;
|
| 2306 |
|
|
|
| 2307 |
|
|
struct {
|
| 2308 |
|
|
word grpBIT :16;
|
| 2309 |
|
|
} MergedBits;
|
| 2310 |
|
|
} PWMPER23STR;
|
| 2311 |
|
|
extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000F4);
|
| 2312 |
|
|
#define PWMPER23 _PWMPER23.Word
|
| 2313 |
|
|
#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT
|
| 2314 |
|
|
|
| 2315 |
|
|
|
| 2316 |
|
|
/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000F6 ***/
|
| 2317 |
|
|
typedef union {
|
| 2318 |
|
|
word Word;
|
| 2319 |
|
|
/* Overlapped registers: */
|
| 2320 |
|
|
struct {
|
| 2321 |
|
|
/*** PWMPER4 - PWM Channel Period 4 Register; 0x000000F6 ***/
|
| 2322 |
|
|
union {
|
| 2323 |
|
|
byte Byte;
|
| 2324 |
|
|
struct {
|
| 2325 |
|
|
byte grpBIT :8;
|
| 2326 |
|
|
} MergedBits;
|
| 2327 |
|
|
} PWMPER4STR;
|
| 2328 |
|
|
#define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte
|
| 2329 |
|
|
#define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT
|
| 2330 |
|
|
|
| 2331 |
|
|
/*** PWMPER5 - PWM Channel Period 5 Register; 0x000000F7 ***/
|
| 2332 |
|
|
union {
|
| 2333 |
|
|
byte Byte;
|
| 2334 |
|
|
struct {
|
| 2335 |
|
|
byte grpBIT :8;
|
| 2336 |
|
|
} MergedBits;
|
| 2337 |
|
|
} PWMPER5STR;
|
| 2338 |
|
|
#define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte
|
| 2339 |
|
|
#define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT
|
| 2340 |
|
|
|
| 2341 |
|
|
} Overlap_STR;
|
| 2342 |
|
|
|
| 2343 |
|
|
struct {
|
| 2344 |
|
|
word grpBIT :16;
|
| 2345 |
|
|
} MergedBits;
|
| 2346 |
|
|
} PWMPER45STR;
|
| 2347 |
|
|
extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000F6);
|
| 2348 |
|
|
#define PWMPER45 _PWMPER45.Word
|
| 2349 |
|
|
#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT
|
| 2350 |
|
|
|
| 2351 |
|
|
|
| 2352 |
|
|
/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000F8 ***/
|
| 2353 |
|
|
typedef union {
|
| 2354 |
|
|
word Word;
|
| 2355 |
|
|
/* Overlapped registers: */
|
| 2356 |
|
|
struct {
|
| 2357 |
|
|
/*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000F8 ***/
|
| 2358 |
|
|
union {
|
| 2359 |
|
|
byte Byte;
|
| 2360 |
|
|
struct {
|
| 2361 |
|
|
byte grpBIT :8;
|
| 2362 |
|
|
} MergedBits;
|
| 2363 |
|
|
} PWMDTY0STR;
|
| 2364 |
|
|
#define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte
|
| 2365 |
|
|
#define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT
|
| 2366 |
|
|
|
| 2367 |
|
|
/*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000F9 ***/
|
| 2368 |
|
|
union {
|
| 2369 |
|
|
byte Byte;
|
| 2370 |
|
|
struct {
|
| 2371 |
|
|
byte grpBIT :8;
|
| 2372 |
|
|
} MergedBits;
|
| 2373 |
|
|
} PWMDTY1STR;
|
| 2374 |
|
|
#define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte
|
| 2375 |
|
|
#define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT
|
| 2376 |
|
|
|
| 2377 |
|
|
} Overlap_STR;
|
| 2378 |
|
|
|
| 2379 |
|
|
struct {
|
| 2380 |
|
|
word grpBIT :16;
|
| 2381 |
|
|
} MergedBits;
|
| 2382 |
|
|
} PWMDTY01STR;
|
| 2383 |
|
|
extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000F8);
|
| 2384 |
|
|
#define PWMDTY01 _PWMDTY01.Word
|
| 2385 |
|
|
#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT
|
| 2386 |
|
|
|
| 2387 |
|
|
|
| 2388 |
|
|
/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000FA ***/
|
| 2389 |
|
|
typedef union {
|
| 2390 |
|
|
word Word;
|
| 2391 |
|
|
/* Overlapped registers: */
|
| 2392 |
|
|
struct {
|
| 2393 |
|
|
/*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000FA ***/
|
| 2394 |
|
|
union {
|
| 2395 |
|
|
byte Byte;
|
| 2396 |
|
|
struct {
|
| 2397 |
|
|
byte grpBIT :8;
|
| 2398 |
|
|
} MergedBits;
|
| 2399 |
|
|
} PWMDTY2STR;
|
| 2400 |
|
|
#define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte
|
| 2401 |
|
|
#define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT
|
| 2402 |
|
|
|
| 2403 |
|
|
/*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000FB ***/
|
| 2404 |
|
|
union {
|
| 2405 |
|
|
byte Byte;
|
| 2406 |
|
|
struct {
|
| 2407 |
|
|
byte grpBIT :8;
|
| 2408 |
|
|
} MergedBits;
|
| 2409 |
|
|
} PWMDTY3STR;
|
| 2410 |
|
|
#define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte
|
| 2411 |
|
|
#define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT
|
| 2412 |
|
|
|
| 2413 |
|
|
} Overlap_STR;
|
| 2414 |
|
|
|
| 2415 |
|
|
struct {
|
| 2416 |
|
|
word grpBIT :16;
|
| 2417 |
|
|
} MergedBits;
|
| 2418 |
|
|
} PWMDTY23STR;
|
| 2419 |
|
|
extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000FA);
|
| 2420 |
|
|
#define PWMDTY23 _PWMDTY23.Word
|
| 2421 |
|
|
#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT
|
| 2422 |
|
|
|
| 2423 |
|
|
|
| 2424 |
|
|
/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000FC ***/
|
| 2425 |
|
|
typedef union {
|
| 2426 |
|
|
word Word;
|
| 2427 |
|
|
/* Overlapped registers: */
|
| 2428 |
|
|
struct {
|
| 2429 |
|
|
/*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000FC ***/
|
| 2430 |
|
|
union {
|
| 2431 |
|
|
byte Byte;
|
| 2432 |
|
|
struct {
|
| 2433 |
|
|
byte grpBIT :8;
|
| 2434 |
|
|
} MergedBits;
|
| 2435 |
|
|
} PWMDTY4STR;
|
| 2436 |
|
|
#define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte
|
| 2437 |
|
|
#define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT
|
| 2438 |
|
|
|
| 2439 |
|
|
/*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000FD ***/
|
| 2440 |
|
|
union {
|
| 2441 |
|
|
byte Byte;
|
| 2442 |
|
|
struct {
|
| 2443 |
|
|
byte grpBIT :8;
|
| 2444 |
|
|
} MergedBits;
|
| 2445 |
|
|
} PWMDTY5STR;
|
| 2446 |
|
|
#define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte
|
| 2447 |
|
|
#define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT
|
| 2448 |
|
|
|
| 2449 |
|
|
} Overlap_STR;
|
| 2450 |
|
|
|
| 2451 |
|
|
struct {
|
| 2452 |
|
|
word grpBIT :16;
|
| 2453 |
|
|
} MergedBits;
|
| 2454 |
|
|
} PWMDTY45STR;
|
| 2455 |
|
|
extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000FC);
|
| 2456 |
|
|
#define PWMDTY45 _PWMDTY45.Word
|
| 2457 |
|
|
#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT
|
| 2458 |
|
|
|
| 2459 |
|
|
|
| 2460 |
|
|
/*** PORTE - Port E Register; 0x00000008 ***/
|
| 2461 |
|
|
typedef union {
|
| 2462 |
|
|
byte Byte;
|
| 2463 |
|
|
struct {
|
| 2464 |
|
|
byte BIT0 :1; /* Port E Bit 0 */
|
| 2465 |
|
|
byte BIT1 :1; /* Port E Bit 1 */
|
| 2466 |
|
|
byte BIT2 :1; /* Port E Bit 2 */
|
| 2467 |
|
|
byte BIT3 :1; /* Port E Bit 3 */
|
| 2468 |
|
|
byte BIT4 :1; /* Port E Bit 4 */
|
| 2469 |
|
|
byte BIT5 :1; /* Port E Bit 5 */
|
| 2470 |
|
|
byte BIT6 :1; /* Port E Bit 6 */
|
| 2471 |
|
|
byte BIT7 :1; /* Port E Bit 7 */
|
| 2472 |
|
|
} Bits;
|
| 2473 |
|
|
struct {
|
| 2474 |
|
|
byte grpBIT :8;
|
| 2475 |
|
|
} MergedBits;
|
| 2476 |
|
|
} PORTESTR;
|
| 2477 |
|
|
extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);
|
| 2478 |
|
|
#define PORTE _PORTE.Byte
|
| 2479 |
|
|
#define PORTE_BIT0 _PORTE.Bits.BIT0
|
| 2480 |
|
|
#define PORTE_BIT1 _PORTE.Bits.BIT1
|
| 2481 |
|
|
#define PORTE_BIT2 _PORTE.Bits.BIT2
|
| 2482 |
|
|
#define PORTE_BIT3 _PORTE.Bits.BIT3
|
| 2483 |
|
|
#define PORTE_BIT4 _PORTE.Bits.BIT4
|
| 2484 |
|
|
#define PORTE_BIT5 _PORTE.Bits.BIT5
|
| 2485 |
|
|
#define PORTE_BIT6 _PORTE.Bits.BIT6
|
| 2486 |
|
|
#define PORTE_BIT7 _PORTE.Bits.BIT7
|
| 2487 |
|
|
#define PORTE_BIT _PORTE.MergedBits.grpBIT
|
| 2488 |
|
|
|
| 2489 |
|
|
|
| 2490 |
|
|
/*** DDRE - Port E Data Direction Register; 0x00000009 ***/
|
| 2491 |
|
|
typedef union {
|
| 2492 |
|
|
byte Byte;
|
| 2493 |
|
|
struct {
|
| 2494 |
|
|
byte :1;
|
| 2495 |
|
|
byte :1;
|
| 2496 |
|
|
byte BIT2 :1; /* Data Direction Port A Bit 2 */
|
| 2497 |
|
|
byte BIT3 :1; /* Data Direction Port A Bit 3 */
|
| 2498 |
|
|
byte BIT4 :1; /* Data Direction Port A Bit 4 */
|
| 2499 |
|
|
byte BIT5 :1; /* Data Direction Port A Bit 5 */
|
| 2500 |
|
|
byte BIT6 :1; /* Data Direction Port A Bit 6 */
|
| 2501 |
|
|
byte BIT7 :1; /* Data Direction Port A Bit 7 */
|
| 2502 |
|
|
} Bits;
|
| 2503 |
|
|
struct {
|
| 2504 |
|
|
byte :1;
|
| 2505 |
|
|
byte :1;
|
| 2506 |
|
|
byte grpBIT_2 :6;
|
| 2507 |
|
|
} MergedBits;
|
| 2508 |
|
|
} DDRESTR;
|
| 2509 |
|
|
extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);
|
| 2510 |
|
|
#define DDRE _DDRE.Byte
|
| 2511 |
|
|
#define DDRE_BIT2 _DDRE.Bits.BIT2
|
| 2512 |
|
|
#define DDRE_BIT3 _DDRE.Bits.BIT3
|
| 2513 |
|
|
#define DDRE_BIT4 _DDRE.Bits.BIT4
|
| 2514 |
|
|
#define DDRE_BIT5 _DDRE.Bits.BIT5
|
| 2515 |
|
|
#define DDRE_BIT6 _DDRE.Bits.BIT6
|
| 2516 |
|
|
#define DDRE_BIT7 _DDRE.Bits.BIT7
|
| 2517 |
|
|
#define DDRE_BIT_2 _DDRE.MergedBits.grpBIT_2
|
| 2518 |
|
|
#define DDRE_BIT DDRE_BIT_2
|
| 2519 |
|
|
|
| 2520 |
|
|
|
| 2521 |
|
|
/*** PEAR - Port E Assignment Register; 0x0000000A ***/
|
| 2522 |
|
|
typedef union {
|
| 2523 |
|
|
byte Byte;
|
| 2524 |
|
|
struct {
|
| 2525 |
|
|
byte :1;
|
| 2526 |
|
|
byte :1;
|
| 2527 |
|
|
byte RDWE :1; /* Read / Write Enable */
|
| 2528 |
|
|
byte LSTRE :1; /* Low Strobe (LSTRB) Enable */
|
| 2529 |
|
|
byte NECLK :1; /* No External E Clock */
|
| 2530 |
|
|
byte PIPOE :1; /* Pipe Status Signal Output Enable */
|
| 2531 |
|
|
byte :1;
|
| 2532 |
|
|
byte NOACCE :1; /* CPU No Access Output Enable */
|
| 2533 |
|
|
} Bits;
|
| 2534 |
|
|
} PEARSTR;
|
| 2535 |
|
|
extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);
|
| 2536 |
|
|
#define PEAR _PEAR.Byte
|
| 2537 |
|
|
#define PEAR_RDWE _PEAR.Bits.RDWE
|
| 2538 |
|
|
#define PEAR_LSTRE _PEAR.Bits.LSTRE
|
| 2539 |
|
|
#define PEAR_NECLK _PEAR.Bits.NECLK
|
| 2540 |
|
|
#define PEAR_PIPOE _PEAR.Bits.PIPOE
|
| 2541 |
|
|
#define PEAR_NOACCE _PEAR.Bits.NOACCE
|
| 2542 |
|
|
|
| 2543 |
|
|
|
| 2544 |
|
|
/*** MODE - Mode Register; 0x0000000B ***/
|
| 2545 |
|
|
typedef union {
|
| 2546 |
|
|
byte Byte;
|
| 2547 |
|
|
struct {
|
| 2548 |
|
|
byte EME :1; /* Emulate Port E */
|
| 2549 |
|
|
byte EMK :1; /* Emulate Port K */
|
| 2550 |
|
|
byte :1;
|
| 2551 |
|
|
byte IVIS :1; /* Internal Visibility */
|
| 2552 |
|
|
byte :1;
|
| 2553 |
|
|
byte MODA :1; /* Mode Select Bit A */
|
| 2554 |
|
|
byte MODB :1; /* Mode Select Bit B */
|
| 2555 |
|
|
byte MODC :1; /* Mode Select Bit C */
|
| 2556 |
|
|
} Bits;
|
| 2557 |
|
|
} MODESTR;
|
| 2558 |
|
|
extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B);
|
| 2559 |
|
|
#define MODE _MODE.Byte
|
| 2560 |
|
|
#define MODE_EME _MODE.Bits.EME
|
| 2561 |
|
|
#define MODE_EMK _MODE.Bits.EMK
|
| 2562 |
|
|
#define MODE_IVIS _MODE.Bits.IVIS
|
| 2563 |
|
|
#define MODE_MODA _MODE.Bits.MODA
|
| 2564 |
|
|
#define MODE_MODB _MODE.Bits.MODB
|
| 2565 |
|
|
#define MODE_MODC _MODE.Bits.MODC
|
| 2566 |
|
|
|
| 2567 |
|
|
|
| 2568 |
|
|
/*** PUCR - Pull-Up Control Register; 0x0000000C ***/
|
| 2569 |
|
|
typedef union {
|
| 2570 |
|
|
byte Byte;
|
| 2571 |
|
|
struct {
|
| 2572 |
|
|
byte PUPAE :1; /* Pull-Up Port A Enable */
|
| 2573 |
|
|
byte PUPBE :1; /* Pull-Up Port B Enable */
|
| 2574 |
|
|
byte :1;
|
| 2575 |
|
|
byte :1;
|
| 2576 |
|
|
byte PUPEE :1; /* Pull-Up Port E Enable */
|
| 2577 |
|
|
byte :1;
|
| 2578 |
|
|
byte :1;
|
| 2579 |
|
|
byte PUPKE :1; /* Pull-Up Port K Enable */
|
| 2580 |
|
|
} Bits;
|
| 2581 |
|
|
} PUCRSTR;
|
| 2582 |
|
|
extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C);
|
| 2583 |
|
|
#define PUCR _PUCR.Byte
|
| 2584 |
|
|
#define PUCR_PUPAE _PUCR.Bits.PUPAE
|
| 2585 |
|
|
#define PUCR_PUPBE _PUCR.Bits.PUPBE
|
| 2586 |
|
|
#define PUCR_PUPEE _PUCR.Bits.PUPEE
|
| 2587 |
|
|
#define PUCR_PUPKE _PUCR.Bits.PUPKE
|
| 2588 |
|
|
|
| 2589 |
|
|
|
| 2590 |
|
|
/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/
|
| 2591 |
|
|
typedef union {
|
| 2592 |
|
|
byte Byte;
|
| 2593 |
|
|
struct {
|
| 2594 |
|
|
byte RDPA :1; /* Reduced Drive of Port A */
|
| 2595 |
|
|
byte RDPB :1; /* Reduced Drive of Port B */
|
| 2596 |
|
|
byte :1;
|
| 2597 |
|
|
byte :1;
|
| 2598 |
|
|
byte RDPE :1; /* Reduced Drive of Port E */
|
| 2599 |
|
|
byte :1;
|
| 2600 |
|
|
byte :1;
|
| 2601 |
|
|
byte RDPK :1; /* Reduced Drive of Port K */
|
| 2602 |
|
|
} Bits;
|
| 2603 |
|
|
} RDRIVSTR;
|
| 2604 |
|
|
extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);
|
| 2605 |
|
|
#define RDRIV _RDRIV.Byte
|
| 2606 |
|
|
#define RDRIV_RDPA _RDRIV.Bits.RDPA
|
| 2607 |
|
|
#define RDRIV_RDPB _RDRIV.Bits.RDPB
|
| 2608 |
|
|
#define RDRIV_RDPE _RDRIV.Bits.RDPE
|
| 2609 |
|
|
#define RDRIV_RDPK _RDRIV.Bits.RDPK
|
| 2610 |
|
|
|
| 2611 |
|
|
|
| 2612 |
|
|
/*** EBICTL - External Bus Interface Control; 0x0000000E ***/
|
| 2613 |
|
|
typedef union {
|
| 2614 |
|
|
byte Byte;
|
| 2615 |
|
|
struct {
|
| 2616 |
|
|
byte ESTR :1; /* E Stretches */
|
| 2617 |
|
|
byte :1;
|
| 2618 |
|
|
byte :1;
|
| 2619 |
|
|
byte :1;
|
| 2620 |
|
|
byte :1;
|
| 2621 |
|
|
byte :1;
|
| 2622 |
|
|
byte :1;
|
| 2623 |
|
|
byte :1;
|
| 2624 |
|
|
} Bits;
|
| 2625 |
|
|
} EBICTLSTR;
|
| 2626 |
|
|
extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);
|
| 2627 |
|
|
#define EBICTL _EBICTL.Byte
|
| 2628 |
|
|
#define EBICTL_ESTR _EBICTL.Bits.ESTR
|
| 2629 |
|
|
|
| 2630 |
|
|
|
| 2631 |
|
|
/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/
|
| 2632 |
|
|
typedef union {
|
| 2633 |
|
|
byte Byte;
|
| 2634 |
|
|
struct {
|
| 2635 |
|
|
byte RAMHAL :1; /* Internal RAM map alignment */
|
| 2636 |
|
|
byte :1;
|
| 2637 |
|
|
byte :1;
|
| 2638 |
|
|
byte RAM11 :1; /* Internal RAM map position Bit 11 */
|
| 2639 |
|
|
byte RAM12 :1; /* Internal RAM map position Bit 12 */
|
| 2640 |
|
|
byte RAM13 :1; /* Internal RAM map position Bit 13 */
|
| 2641 |
|
|
byte RAM14 :1; /* Internal RAM map position Bit 14 */
|
| 2642 |
|
|
byte RAM15 :1; /* Internal RAM map position Bit 15 */
|
| 2643 |
|
|
} Bits;
|
| 2644 |
|
|
struct {
|
| 2645 |
|
|
byte :1;
|
| 2646 |
|
|
byte :1;
|
| 2647 |
|
|
byte :1;
|
| 2648 |
|
|
byte grpRAM_11 :5;
|
| 2649 |
|
|
} MergedBits;
|
| 2650 |
|
|
} INITRMSTR;
|
| 2651 |
|
|
extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);
|
| 2652 |
|
|
#define INITRM _INITRM.Byte
|
| 2653 |
|
|
#define INITRM_RAMHAL _INITRM.Bits.RAMHAL
|
| 2654 |
|
|
#define INITRM_RAM11 _INITRM.Bits.RAM11
|
| 2655 |
|
|
#define INITRM_RAM12 _INITRM.Bits.RAM12
|
| 2656 |
|
|
#define INITRM_RAM13 _INITRM.Bits.RAM13
|
| 2657 |
|
|
#define INITRM_RAM14 _INITRM.Bits.RAM14
|
| 2658 |
|
|
#define INITRM_RAM15 _INITRM.Bits.RAM15
|
| 2659 |
|
|
#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11
|
| 2660 |
|
|
#define INITRM_RAM INITRM_RAM_11
|
| 2661 |
|
|
|
| 2662 |
|
|
|
| 2663 |
|
|
/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/
|
| 2664 |
|
|
typedef union {
|
| 2665 |
|
|
byte Byte;
|
| 2666 |
|
|
struct {
|
| 2667 |
|
|
byte :1;
|
| 2668 |
|
|
byte :1;
|
| 2669 |
|
|
byte :1;
|
| 2670 |
|
|
byte REG11 :1; /* Internal register map position REG11 */
|
| 2671 |
|
|
byte REG12 :1; /* Internal register map position REG12 */
|
| 2672 |
|
|
byte REG13 :1; /* Internal register map position REG13 */
|
| 2673 |
|
|
byte REG14 :1; /* Internal register map position REG14 */
|
| 2674 |
|
|
byte :1;
|
| 2675 |
|
|
} Bits;
|
| 2676 |
|
|
struct {
|
| 2677 |
|
|
byte :1;
|
| 2678 |
|
|
byte :1;
|
| 2679 |
|
|
byte :1;
|
| 2680 |
|
|
byte grpREG_11 :4;
|
| 2681 |
|
|
byte :1;
|
| 2682 |
|
|
} MergedBits;
|
| 2683 |
|
|
} INITRGSTR;
|
| 2684 |
|
|
extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);
|
| 2685 |
|
|
#define INITRG _INITRG.Byte
|
| 2686 |
|
|
#define INITRG_REG11 _INITRG.Bits.REG11
|
| 2687 |
|
|
#define INITRG_REG12 _INITRG.Bits.REG12
|
| 2688 |
|
|
#define INITRG_REG13 _INITRG.Bits.REG13
|
| 2689 |
|
|
#define INITRG_REG14 _INITRG.Bits.REG14
|
| 2690 |
|
|
#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11
|
| 2691 |
|
|
#define INITRG_REG INITRG_REG_11
|
| 2692 |
|
|
|
| 2693 |
|
|
|
| 2694 |
|
|
/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/
|
| 2695 |
|
|
typedef union {
|
| 2696 |
|
|
byte Byte;
|
| 2697 |
|
|
struct {
|
| 2698 |
|
|
byte EEON :1; /* Internal EEPROM On */
|
| 2699 |
|
|
byte :1;
|
| 2700 |
|
|
byte :1;
|
| 2701 |
|
|
byte :1;
|
| 2702 |
|
|
byte EE12 :1; /* Internal EEPROM map position Bit 12 */
|
| 2703 |
|
|
byte EE13 :1; /* Internal EEPROM map position Bit 13 */
|
| 2704 |
|
|
byte EE14 :1; /* Internal EEPROM map position Bit 14 */
|
| 2705 |
|
|
byte EE15 :1; /* Internal EEPROM map position Bit 15 */
|
| 2706 |
|
|
} Bits;
|
| 2707 |
|
|
struct {
|
| 2708 |
|
|
byte :1;
|
| 2709 |
|
|
byte :1;
|
| 2710 |
|
|
byte :1;
|
| 2711 |
|
|
byte :1;
|
| 2712 |
|
|
byte grpEE_12 :4;
|
| 2713 |
|
|
} MergedBits;
|
| 2714 |
|
|
} INITEESTR;
|
| 2715 |
|
|
extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);
|
| 2716 |
|
|
#define INITEE _INITEE.Byte
|
| 2717 |
|
|
#define INITEE_EEON _INITEE.Bits.EEON
|
| 2718 |
|
|
#define INITEE_EE12 _INITEE.Bits.EE12
|
| 2719 |
|
|
#define INITEE_EE13 _INITEE.Bits.EE13
|
| 2720 |
|
|
#define INITEE_EE14 _INITEE.Bits.EE14
|
| 2721 |
|
|
#define INITEE_EE15 _INITEE.Bits.EE15
|
| 2722 |
|
|
#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12
|
| 2723 |
|
|
#define INITEE_EE INITEE_EE_12
|
| 2724 |
|
|
|
| 2725 |
|
|
|
| 2726 |
|
|
/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/
|
| 2727 |
|
|
typedef union {
|
| 2728 |
|
|
byte Byte;
|
| 2729 |
|
|
struct {
|
| 2730 |
|
|
byte ROMON :1; /* Enable Flash EEPROM */
|
| 2731 |
|
|
byte ROMHM :1; /* Flash EEPROM only in second half of memory map */
|
| 2732 |
|
|
byte EXSTR0 :1; /* External Access Stretch Bit 0 */
|
| 2733 |
|
|
byte EXSTR1 :1; /* External Access Stretch Bit 1 */
|
| 2734 |
|
|
byte :1;
|
| 2735 |
|
|
byte :1;
|
| 2736 |
|
|
byte :1;
|
| 2737 |
|
|
byte :1;
|
| 2738 |
|
|
} Bits;
|
| 2739 |
|
|
struct {
|
| 2740 |
|
|
byte :1;
|
| 2741 |
|
|
byte :1;
|
| 2742 |
|
|
byte grpEXSTR :2;
|
| 2743 |
|
|
byte :1;
|
| 2744 |
|
|
byte :1;
|
| 2745 |
|
|
byte :1;
|
| 2746 |
|
|
byte :1;
|
| 2747 |
|
|
} MergedBits;
|
| 2748 |
|
|
} MISCSTR;
|
| 2749 |
|
|
extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013);
|
| 2750 |
|
|
#define MISC _MISC.Byte
|
| 2751 |
|
|
#define MISC_ROMON _MISC.Bits.ROMON
|
| 2752 |
|
|
#define MISC_ROMHM _MISC.Bits.ROMHM
|
| 2753 |
|
|
#define MISC_EXSTR0 _MISC.Bits.EXSTR0
|
| 2754 |
|
|
#define MISC_EXSTR1 _MISC.Bits.EXSTR1
|
| 2755 |
|
|
#define MISC_EXSTR _MISC.MergedBits.grpEXSTR
|
| 2756 |
|
|
|
| 2757 |
|
|
|
| 2758 |
|
|
/*** MTST0 - MTST0; 0x00000014 ***/
|
| 2759 |
|
|
typedef union {
|
| 2760 |
|
|
byte Byte;
|
| 2761 |
|
|
struct {
|
| 2762 |
|
|
byte BIT0 :1; /* MTST0 Bit 0 */
|
| 2763 |
|
|
byte BIT1 :1; /* MTST0 Bit 1 */
|
| 2764 |
|
|
byte BIT2 :1; /* MTST0 Bit 2 */
|
| 2765 |
|
|
byte BIT3 :1; /* MTST0 Bit 3 */
|
| 2766 |
|
|
byte BIT4 :1; /* MTST0 Bit 4 */
|
| 2767 |
|
|
byte BIT5 :1; /* MTST0 Bit 5 */
|
| 2768 |
|
|
byte BIT6 :1; /* MTST0 Bit 6 */
|
| 2769 |
|
|
byte BIT7 :1; /* MTST0 Bit 7 */
|
| 2770 |
|
|
} Bits;
|
| 2771 |
|
|
struct {
|
| 2772 |
|
|
byte grpBIT :8;
|
| 2773 |
|
|
} MergedBits;
|
| 2774 |
|
|
} MTST0STR;
|
| 2775 |
|
|
extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014);
|
| 2776 |
|
|
#define MTST0 _MTST0.Byte
|
| 2777 |
|
|
#define MTST0_BIT0 _MTST0.Bits.BIT0
|
| 2778 |
|
|
#define MTST0_BIT1 _MTST0.Bits.BIT1
|
| 2779 |
|
|
#define MTST0_BIT2 _MTST0.Bits.BIT2
|
| 2780 |
|
|
#define MTST0_BIT3 _MTST0.Bits.BIT3
|
| 2781 |
|
|
#define MTST0_BIT4 _MTST0.Bits.BIT4
|
| 2782 |
|
|
#define MTST0_BIT5 _MTST0.Bits.BIT5
|
| 2783 |
|
|
#define MTST0_BIT6 _MTST0.Bits.BIT6
|
| 2784 |
|
|
#define MTST0_BIT7 _MTST0.Bits.BIT7
|
| 2785 |
|
|
#define MTST0_BIT _MTST0.MergedBits.grpBIT
|
| 2786 |
|
|
|
| 2787 |
|
|
|
| 2788 |
|
|
/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/
|
| 2789 |
|
|
typedef union {
|
| 2790 |
|
|
byte Byte;
|
| 2791 |
|
|
struct {
|
| 2792 |
|
|
byte ADR0 :1; /* Test register select Bit 0 */
|
| 2793 |
|
|
byte ADR1 :1; /* Test register select Bit 1 */
|
| 2794 |
|
|
byte ADR2 :1; /* Test register select Bit 2 */
|
| 2795 |
|
|
byte ADR3 :1; /* Test register select Bit 3 */
|
| 2796 |
|
|
byte WRTINT :1; /* Write to the Interrupt Test Registers */
|
| 2797 |
|
|
byte :1;
|
| 2798 |
|
|
byte :1;
|
| 2799 |
|
|
byte :1;
|
| 2800 |
|
|
} Bits;
|
| 2801 |
|
|
struct {
|
| 2802 |
|
|
byte grpADR :4;
|
| 2803 |
|
|
byte :1;
|
| 2804 |
|
|
byte :1;
|
| 2805 |
|
|
byte :1;
|
| 2806 |
|
|
byte :1;
|
| 2807 |
|
|
} MergedBits;
|
| 2808 |
|
|
} ITCRSTR;
|
| 2809 |
|
|
extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);
|
| 2810 |
|
|
#define ITCR _ITCR.Byte
|
| 2811 |
|
|
#define ITCR_ADR0 _ITCR.Bits.ADR0
|
| 2812 |
|
|
#define ITCR_ADR1 _ITCR.Bits.ADR1
|
| 2813 |
|
|
#define ITCR_ADR2 _ITCR.Bits.ADR2
|
| 2814 |
|
|
#define ITCR_ADR3 _ITCR.Bits.ADR3
|
| 2815 |
|
|
#define ITCR_WRTINT _ITCR.Bits.WRTINT
|
| 2816 |
|
|
#define ITCR_ADR _ITCR.MergedBits.grpADR
|
| 2817 |
|
|
|
| 2818 |
|
|
|
| 2819 |
|
|
/*** ITEST - Interrupt Test Register; 0x00000016 ***/
|
| 2820 |
|
|
typedef union {
|
| 2821 |
|
|
byte Byte;
|
| 2822 |
|
|
struct {
|
| 2823 |
|
|
byte INT0 :1; /* Interrupt Test Register Bit 0 */
|
| 2824 |
|
|
byte INT2 :1; /* Interrupt Test Register Bit 1 */
|
| 2825 |
|
|
byte INT4 :1; /* Interrupt Test Register Bit 2 */
|
| 2826 |
|
|
byte INT6 :1; /* Interrupt Test Register Bit 3 */
|
| 2827 |
|
|
byte INT8 :1; /* Interrupt Test Register Bit 4 */
|
| 2828 |
|
|
byte INTA :1; /* Interrupt Test Register Bit 5 */
|
| 2829 |
|
|
byte INTC :1; /* Interrupt Test Register Bit 6 */
|
| 2830 |
|
|
byte INTE :1; /* Interrupt Test Register Bit 7 */
|
| 2831 |
|
|
} Bits;
|
| 2832 |
|
|
} ITESTSTR;
|
| 2833 |
|
|
extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);
|
| 2834 |
|
|
#define ITEST _ITEST.Byte
|
| 2835 |
|
|
#define ITEST_INT0 _ITEST.Bits.INT0
|
| 2836 |
|
|
#define ITEST_INT2 _ITEST.Bits.INT2
|
| 2837 |
|
|
#define ITEST_INT4 _ITEST.Bits.INT4
|
| 2838 |
|
|
#define ITEST_INT6 _ITEST.Bits.INT6
|
| 2839 |
|
|
#define ITEST_INT8 _ITEST.Bits.INT8
|
| 2840 |
|
|
#define ITEST_INTA _ITEST.Bits.INTA
|
| 2841 |
|
|
#define ITEST_INTC _ITEST.Bits.INTC
|
| 2842 |
|
|
#define ITEST_INTE _ITEST.Bits.INTE
|
| 2843 |
|
|
|
| 2844 |
|
|
|
| 2845 |
|
|
/*** MTST1 - MTST1; 0x00000017 ***/
|
| 2846 |
|
|
typedef union {
|
| 2847 |
|
|
byte Byte;
|
| 2848 |
|
|
struct {
|
| 2849 |
|
|
byte BIT0 :1; /* MTST1 Bit 0 */
|
| 2850 |
|
|
byte BIT1 :1; /* MTST1 Bit 1 */
|
| 2851 |
|
|
byte BIT2 :1; /* MTST1 Bit 2 */
|
| 2852 |
|
|
byte BIT3 :1; /* MTST1 Bit 3 */
|
| 2853 |
|
|
byte BIT4 :1; /* MTST1 Bit 4 */
|
| 2854 |
|
|
byte BIT5 :1; /* MTST1 Bit 5 */
|
| 2855 |
|
|
byte BIT6 :1; /* MTST1 Bit 6 */
|
| 2856 |
|
|
byte BIT7 :1; /* MTST1 Bit 7 */
|
| 2857 |
|
|
} Bits;
|
| 2858 |
|
|
struct {
|
| 2859 |
|
|
byte grpBIT :8;
|
| 2860 |
|
|
} MergedBits;
|
| 2861 |
|
|
} MTST1STR;
|
| 2862 |
|
|
extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017);
|
| 2863 |
|
|
#define MTST1 _MTST1.Byte
|
| 2864 |
|
|
#define MTST1_BIT0 _MTST1.Bits.BIT0
|
| 2865 |
|
|
#define MTST1_BIT1 _MTST1.Bits.BIT1
|
| 2866 |
|
|
#define MTST1_BIT2 _MTST1.Bits.BIT2
|
| 2867 |
|
|
#define MTST1_BIT3 _MTST1.Bits.BIT3
|
| 2868 |
|
|
#define MTST1_BIT4 _MTST1.Bits.BIT4
|
| 2869 |
|
|
#define MTST1_BIT5 _MTST1.Bits.BIT5
|
| 2870 |
|
|
#define MTST1_BIT6 _MTST1.Bits.BIT6
|
| 2871 |
|
|
#define MTST1_BIT7 _MTST1.Bits.BIT7
|
| 2872 |
|
|
#define MTST1_BIT _MTST1.MergedBits.grpBIT
|
| 2873 |
|
|
|
| 2874 |
|
|
|
| 2875 |
|
|
/*** PARTIDH - Part ID Register High; 0x0000001A ***/
|
| 2876 |
|
|
typedef union {
|
| 2877 |
|
|
byte Byte;
|
| 2878 |
|
|
struct {
|
| 2879 |
|
|
byte ID15 :1; /* Part ID Register Bit 15 */
|
| 2880 |
|
|
byte ID14 :1; /* Part ID Register Bit 14 */
|
| 2881 |
|
|
byte ID13 :1; /* Part ID Register Bit 13 */
|
| 2882 |
|
|
byte ID12 :1; /* Part ID Register Bit 12 */
|
| 2883 |
|
|
byte ID11 :1; /* Part ID Register Bit 11 */
|
| 2884 |
|
|
byte ID10 :1; /* Part ID Register Bit 10 */
|
| 2885 |
|
|
byte ID9 :1; /* Part ID Register Bit 9 */
|
| 2886 |
|
|
byte ID8 :1; /* Part ID Register Bit 8 */
|
| 2887 |
|
|
} Bits;
|
| 2888 |
|
|
} PARTIDHSTR;
|
| 2889 |
|
|
extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A);
|
| 2890 |
|
|
#define PARTIDH _PARTIDH.Byte
|
| 2891 |
|
|
#define PARTIDH_ID15 _PARTIDH.Bits.ID15
|
| 2892 |
|
|
#define PARTIDH_ID14 _PARTIDH.Bits.ID14
|
| 2893 |
|
|
#define PARTIDH_ID13 _PARTIDH.Bits.ID13
|
| 2894 |
|
|
#define PARTIDH_ID12 _PARTIDH.Bits.ID12
|
| 2895 |
|
|
#define PARTIDH_ID11 _PARTIDH.Bits.ID11
|
| 2896 |
|
|
#define PARTIDH_ID10 _PARTIDH.Bits.ID10
|
| 2897 |
|
|
#define PARTIDH_ID9 _PARTIDH.Bits.ID9
|
| 2898 |
|
|
#define PARTIDH_ID8 _PARTIDH.Bits.ID8
|
| 2899 |
|
|
|
| 2900 |
|
|
|
| 2901 |
|
|
/*** PARTIDL - Part ID Register Low; 0x0000001B ***/
|
| 2902 |
|
|
typedef union {
|
| 2903 |
|
|
byte Byte;
|
| 2904 |
|
|
struct {
|
| 2905 |
|
|
byte ID0 :1; /* Part ID Register Bit 0 */
|
| 2906 |
|
|
byte ID1 :1; /* Part ID Register Bit 1 */
|
| 2907 |
|
|
byte ID2 :1; /* Part ID Register Bit 2 */
|
| 2908 |
|
|
byte ID3 :1; /* Part ID Register Bit 3 */
|
| 2909 |
|
|
byte ID4 :1; /* Part ID Register Bit 4 */
|
| 2910 |
|
|
byte ID5 :1; /* Part ID Register Bit 5 */
|
| 2911 |
|
|
byte ID6 :1; /* Part ID Register Bit 6 */
|
| 2912 |
|
|
byte ID7 :1; /* Part ID Register Bit 7 */
|
| 2913 |
|
|
} Bits;
|
| 2914 |
|
|
struct {
|
| 2915 |
|
|
byte grpID :8;
|
| 2916 |
|
|
} MergedBits;
|
| 2917 |
|
|
} PARTIDLSTR;
|
| 2918 |
|
|
extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B);
|
| 2919 |
|
|
#define PARTIDL _PARTIDL.Byte
|
| 2920 |
|
|
#define PARTIDL_ID0 _PARTIDL.Bits.ID0
|
| 2921 |
|
|
#define PARTIDL_ID1 _PARTIDL.Bits.ID1
|
| 2922 |
|
|
#define PARTIDL_ID2 _PARTIDL.Bits.ID2
|
| 2923 |
|
|
#define PARTIDL_ID3 _PARTIDL.Bits.ID3
|
| 2924 |
|
|
#define PARTIDL_ID4 _PARTIDL.Bits.ID4
|
| 2925 |
|
|
#define PARTIDL_ID5 _PARTIDL.Bits.ID5
|
| 2926 |
|
|
#define PARTIDL_ID6 _PARTIDL.Bits.ID6
|
| 2927 |
|
|
#define PARTIDL_ID7 _PARTIDL.Bits.ID7
|
| 2928 |
|
|
#define PARTIDL_ID _PARTIDL.MergedBits.grpID
|
| 2929 |
|
|
|
| 2930 |
|
|
|
| 2931 |
|
|
/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/
|
| 2932 |
|
|
typedef union {
|
| 2933 |
|
|
byte Byte;
|
| 2934 |
|
|
struct {
|
| 2935 |
|
|
byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */
|
| 2936 |
|
|
byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */
|
| 2937 |
|
|
byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */
|
| 2938 |
|
|
byte :1;
|
| 2939 |
|
|
byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */
|
| 2940 |
|
|
byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */
|
| 2941 |
|
|
byte :1;
|
| 2942 |
|
|
byte reg_sw0 :1; /* Allocated System Register Space */
|
| 2943 |
|
|
} Bits;
|
| 2944 |
|
|
struct {
|
| 2945 |
|
|
byte grpram_sw :3;
|
| 2946 |
|
|
byte :1;
|
| 2947 |
|
|
byte grpeep_sw :2;
|
| 2948 |
|
|
byte :1;
|
| 2949 |
|
|
byte grpreg_sw :1;
|
| 2950 |
|
|
} MergedBits;
|
| 2951 |
|
|
} MEMSIZ0STR;
|
| 2952 |
|
|
extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);
|
| 2953 |
|
|
#define MEMSIZ0 _MEMSIZ0.Byte
|
| 2954 |
|
|
#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0
|
| 2955 |
|
|
#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1
|
| 2956 |
|
|
#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2
|
| 2957 |
|
|
#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0
|
| 2958 |
|
|
#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1
|
| 2959 |
|
|
#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0
|
| 2960 |
|
|
#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw
|
| 2961 |
|
|
#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw
|
| 2962 |
|
|
|
| 2963 |
|
|
|
| 2964 |
|
|
/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/
|
| 2965 |
|
|
typedef union {
|
| 2966 |
|
|
byte Byte;
|
| 2967 |
|
|
struct {
|
| 2968 |
|
|
byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */
|
| 2969 |
|
|
byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */
|
| 2970 |
|
|
byte :1;
|
| 2971 |
|
|
byte :1;
|
| 2972 |
|
|
byte :1;
|
| 2973 |
|
|
byte :1;
|
| 2974 |
|
|
byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */
|
| 2975 |
|
|
byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */
|
| 2976 |
|
|
} Bits;
|
| 2977 |
|
|
struct {
|
| 2978 |
|
|
byte grppag_sw :2;
|
| 2979 |
|
|
byte :1;
|
| 2980 |
|
|
byte :1;
|
| 2981 |
|
|
byte :1;
|
| 2982 |
|
|
byte :1;
|
| 2983 |
|
|
byte grprom_sw :2;
|
| 2984 |
|
|
} MergedBits;
|
| 2985 |
|
|
} MEMSIZ1STR;
|
| 2986 |
|
|
extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);
|
| 2987 |
|
|
#define MEMSIZ1 _MEMSIZ1.Byte
|
| 2988 |
|
|
#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0
|
| 2989 |
|
|
#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1
|
| 2990 |
|
|
#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0
|
| 2991 |
|
|
#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1
|
| 2992 |
|
|
#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw
|
| 2993 |
|
|
#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw
|
| 2994 |
|
|
|
| 2995 |
|
|
|
| 2996 |
|
|
/*** INTCR - Interrupt Control Register; 0x0000001E ***/
|
| 2997 |
|
|
typedef union {
|
| 2998 |
|
|
byte Byte;
|
| 2999 |
|
|
struct {
|
| 3000 |
|
|
byte :1;
|
| 3001 |
|
|
byte :1;
|
| 3002 |
|
|
byte :1;
|
| 3003 |
|
|
byte :1;
|
| 3004 |
|
|
byte :1;
|
| 3005 |
|
|
byte :1;
|
| 3006 |
|
|
byte IRQEN :1; /* External IRQ Enable */
|
| 3007 |
|
|
byte IRQE :1; /* IRQ Select Edge Sensitive Only */
|
| 3008 |
|
|
} Bits;
|
| 3009 |
|
|
} INTCRSTR;
|
| 3010 |
|
|
extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);
|
| 3011 |
|
|
#define INTCR _INTCR.Byte
|
| 3012 |
|
|
#define INTCR_IRQEN _INTCR.Bits.IRQEN
|
| 3013 |
|
|
#define INTCR_IRQE _INTCR.Bits.IRQE
|
| 3014 |
|
|
|
| 3015 |
|
|
|
| 3016 |
|
|
/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/
|
| 3017 |
|
|
typedef union {
|
| 3018 |
|
|
byte Byte;
|
| 3019 |
|
|
struct {
|
| 3020 |
|
|
byte :1;
|
| 3021 |
|
|
byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */
|
| 3022 |
|
|
byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */
|
| 3023 |
|
|
byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */
|
| 3024 |
|
|
byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */
|
| 3025 |
|
|
byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */
|
| 3026 |
|
|
byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */
|
| 3027 |
|
|
byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */
|
| 3028 |
|
|
} Bits;
|
| 3029 |
|
|
struct {
|
| 3030 |
|
|
byte :1;
|
| 3031 |
|
|
byte grpPSEL_1 :7;
|
| 3032 |
|
|
} MergedBits;
|
| 3033 |
|
|
} HPRIOSTR;
|
| 3034 |
|
|
extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);
|
| 3035 |
|
|
#define HPRIO _HPRIO.Byte
|
| 3036 |
|
|
#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1
|
| 3037 |
|
|
#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2
|
| 3038 |
|
|
#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3
|
| 3039 |
|
|
#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4
|
| 3040 |
|
|
#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5
|
| 3041 |
|
|
#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6
|
| 3042 |
|
|
#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7
|
| 3043 |
|
|
#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1
|
| 3044 |
|
|
#define HPRIO_PSEL HPRIO_PSEL_1
|
| 3045 |
|
|
|
| 3046 |
|
|
|
| 3047 |
|
|
/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/
|
| 3048 |
|
|
typedef union {
|
| 3049 |
|
|
byte Byte;
|
| 3050 |
|
|
struct {
|
| 3051 |
|
|
byte :1;
|
| 3052 |
|
|
byte :1;
|
| 3053 |
|
|
byte :1;
|
| 3054 |
|
|
byte :1;
|
| 3055 |
|
|
byte BKTAG :1; /* Breakpoint on Tag */
|
| 3056 |
|
|
byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */
|
| 3057 |
|
|
byte BKFULL :1; /* Full Breakpoint Mode Enable */
|
| 3058 |
|
|
byte BKEN :1; /* Breakpoint Enable */
|
| 3059 |
|
|
} Bits;
|
| 3060 |
|
|
} BKPCT0STR;
|
| 3061 |
|
|
extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);
|
| 3062 |
|
|
#define BKPCT0 _BKPCT0.Byte
|
| 3063 |
|
|
#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG
|
| 3064 |
|
|
#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM
|
| 3065 |
|
|
#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL
|
| 3066 |
|
|
#define BKPCT0_BKEN _BKPCT0.Bits.BKEN
|
| 3067 |
|
|
|
| 3068 |
|
|
|
| 3069 |
|
|
/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/
|
| 3070 |
|
|
typedef union {
|
| 3071 |
|
|
byte Byte;
|
| 3072 |
|
|
struct {
|
| 3073 |
|
|
byte BK1RW :1; /* R/W Compare Value 1 */
|
| 3074 |
|
|
byte BK1RWE :1; /* R/W Compare Enable 1 */
|
| 3075 |
|
|
byte BK0RW :1; /* R/W Compare Value 0 */
|
| 3076 |
|
|
byte BK0RWE :1; /* R/W Compare Enable 0 */
|
| 3077 |
|
|
byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */
|
| 3078 |
|
|
byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */
|
| 3079 |
|
|
byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */
|
| 3080 |
|
|
byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */
|
| 3081 |
|
|
} Bits;
|
| 3082 |
|
|
} BKPCT1STR;
|
| 3083 |
|
|
extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);
|
| 3084 |
|
|
#define BKPCT1 _BKPCT1.Byte
|
| 3085 |
|
|
#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW
|
| 3086 |
|
|
#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE
|
| 3087 |
|
|
#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW
|
| 3088 |
|
|
#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE
|
| 3089 |
|
|
#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL
|
| 3090 |
|
|
#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH
|
| 3091 |
|
|
#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL
|
| 3092 |
|
|
#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH
|
| 3093 |
|
|
|
| 3094 |
|
|
|
| 3095 |
|
|
/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/
|
| 3096 |
|
|
typedef union {
|
| 3097 |
|
|
byte Byte;
|
| 3098 |
|
|
struct {
|
| 3099 |
|
|
byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */
|
| 3100 |
|
|
byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */
|
| 3101 |
|
|
byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */
|
| 3102 |
|
|
byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */
|
| 3103 |
|
|
byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */
|
| 3104 |
|
|
byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */
|
| 3105 |
|
|
byte :1;
|
| 3106 |
|
|
byte :1;
|
| 3107 |
|
|
} Bits;
|
| 3108 |
|
|
struct {
|
| 3109 |
|
|
byte grpBK0V :6;
|
| 3110 |
|
|
byte :1;
|
| 3111 |
|
|
byte :1;
|
| 3112 |
|
|
} MergedBits;
|
| 3113 |
|
|
} BKP0XSTR;
|
| 3114 |
|
|
extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);
|
| 3115 |
|
|
#define BKP0X _BKP0X.Byte
|
| 3116 |
|
|
#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0
|
| 3117 |
|
|
#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1
|
| 3118 |
|
|
#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2
|
| 3119 |
|
|
#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3
|
| 3120 |
|
|
#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4
|
| 3121 |
|
|
#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5
|
| 3122 |
|
|
#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V
|
| 3123 |
|
|
|
| 3124 |
|
|
|
| 3125 |
|
|
/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/
|
| 3126 |
|
|
typedef union {
|
| 3127 |
|
|
byte Byte;
|
| 3128 |
|
|
struct {
|
| 3129 |
|
|
byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */
|
| 3130 |
|
|
byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */
|
| 3131 |
|
|
byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */
|
| 3132 |
|
|
byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */
|
| 3133 |
|
|
byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */
|
| 3134 |
|
|
byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */
|
| 3135 |
|
|
byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */
|
| 3136 |
|
|
byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */
|
| 3137 |
|
|
} Bits;
|
| 3138 |
|
|
struct {
|
| 3139 |
|
|
byte grpBIT_8 :8;
|
| 3140 |
|
|
} MergedBits;
|
| 3141 |
|
|
} BKP0HSTR;
|
| 3142 |
|
|
extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B);
|
| 3143 |
|
|
#define BKP0H _BKP0H.Byte
|
| 3144 |
|
|
#define BKP0H_BIT8 _BKP0H.Bits.BIT8
|
| 3145 |
|
|
#define BKP0H_BIT9 _BKP0H.Bits.BIT9
|
| 3146 |
|
|
#define BKP0H_BIT10 _BKP0H.Bits.BIT10
|
| 3147 |
|
|
#define BKP0H_BIT11 _BKP0H.Bits.BIT11
|
| 3148 |
|
|
#define BKP0H_BIT12 _BKP0H.Bits.BIT12
|
| 3149 |
|
|
#define BKP0H_BIT13 _BKP0H.Bits.BIT13
|
| 3150 |
|
|
#define BKP0H_BIT14 _BKP0H.Bits.BIT14
|
| 3151 |
|
|
#define BKP0H_BIT15 _BKP0H.Bits.BIT15
|
| 3152 |
|
|
#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8
|
| 3153 |
|
|
#define BKP0H_BIT BKP0H_BIT_8
|
| 3154 |
|
|
|
| 3155 |
|
|
|
| 3156 |
|
|
/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/
|
| 3157 |
|
|
typedef union {
|
| 3158 |
|
|
byte Byte;
|
| 3159 |
|
|
struct {
|
| 3160 |
|
|
byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */
|
| 3161 |
|
|
byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */
|
| 3162 |
|
|
byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */
|
| 3163 |
|
|
byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */
|
| 3164 |
|
|
byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */
|
| 3165 |
|
|
byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */
|
| 3166 |
|
|
byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */
|
| 3167 |
|
|
byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */
|
| 3168 |
|
|
} Bits;
|
| 3169 |
|
|
struct {
|
| 3170 |
|
|
byte grpBIT :8;
|
| 3171 |
|
|
} MergedBits;
|
| 3172 |
|
|
} BKP0LSTR;
|
| 3173 |
|
|
extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C);
|
| 3174 |
|
|
#define BKP0L _BKP0L.Byte
|
| 3175 |
|
|
#define BKP0L_BIT0 _BKP0L.Bits.BIT0
|
| 3176 |
|
|
#define BKP0L_BIT1 _BKP0L.Bits.BIT1
|
| 3177 |
|
|
#define BKP0L_BIT2 _BKP0L.Bits.BIT2
|
| 3178 |
|
|
#define BKP0L_BIT3 _BKP0L.Bits.BIT3
|
| 3179 |
|
|
#define BKP0L_BIT4 _BKP0L.Bits.BIT4
|
| 3180 |
|
|
#define BKP0L_BIT5 _BKP0L.Bits.BIT5
|
| 3181 |
|
|
#define BKP0L_BIT6 _BKP0L.Bits.BIT6
|
| 3182 |
|
|
#define BKP0L_BIT7 _BKP0L.Bits.BIT7
|
| 3183 |
|
|
#define BKP0L_BIT _BKP0L.MergedBits.grpBIT
|
| 3184 |
|
|
|
| 3185 |
|
|
|
| 3186 |
|
|
/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/
|
| 3187 |
|
|
typedef union {
|
| 3188 |
|
|
byte Byte;
|
| 3189 |
|
|
struct {
|
| 3190 |
|
|
byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */
|
| 3191 |
|
|
byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */
|
| 3192 |
|
|
byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */
|
| 3193 |
|
|
byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */
|
| 3194 |
|
|
byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */
|
| 3195 |
|
|
byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */
|
| 3196 |
|
|
byte :1;
|
| 3197 |
|
|
byte :1;
|
| 3198 |
|
|
} Bits;
|
| 3199 |
|
|
struct {
|
| 3200 |
|
|
byte grpBK1V :6;
|
| 3201 |
|
|
byte :1;
|
| 3202 |
|
|
byte :1;
|
| 3203 |
|
|
} MergedBits;
|
| 3204 |
|
|
} BKP1XSTR;
|
| 3205 |
|
|
extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D);
|
| 3206 |
|
|
#define BKP1X _BKP1X.Byte
|
| 3207 |
|
|
#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0
|
| 3208 |
|
|
#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1
|
| 3209 |
|
|
#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2
|
| 3210 |
|
|
#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3
|
| 3211 |
|
|
#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4
|
| 3212 |
|
|
#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5
|
| 3213 |
|
|
#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V
|
| 3214 |
|
|
|
| 3215 |
|
|
|
| 3216 |
|
|
/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/
|
| 3217 |
|
|
typedef union {
|
| 3218 |
|
|
byte Byte;
|
| 3219 |
|
|
struct {
|
| 3220 |
|
|
byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */
|
| 3221 |
|
|
byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */
|
| 3222 |
|
|
byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */
|
| 3223 |
|
|
byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */
|
| 3224 |
|
|
byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */
|
| 3225 |
|
|
byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */
|
| 3226 |
|
|
byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */
|
| 3227 |
|
|
byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */
|
| 3228 |
|
|
} Bits;
|
| 3229 |
|
|
struct {
|
| 3230 |
|
|
byte grpBIT_8 :8;
|
| 3231 |
|
|
} MergedBits;
|
| 3232 |
|
|
} BKP1HSTR;
|
| 3233 |
|
|
extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E);
|
| 3234 |
|
|
#define BKP1H _BKP1H.Byte
|
| 3235 |
|
|
#define BKP1H_BIT8 _BKP1H.Bits.BIT8
|
| 3236 |
|
|
#define BKP1H_BIT9 _BKP1H.Bits.BIT9
|
| 3237 |
|
|
#define BKP1H_BIT10 _BKP1H.Bits.BIT10
|
| 3238 |
|
|
#define BKP1H_BIT11 _BKP1H.Bits.BIT11
|
| 3239 |
|
|
#define BKP1H_BIT12 _BKP1H.Bits.BIT12
|
| 3240 |
|
|
#define BKP1H_BIT13 _BKP1H.Bits.BIT13
|
| 3241 |
|
|
#define BKP1H_BIT14 _BKP1H.Bits.BIT14
|
| 3242 |
|
|
#define BKP1H_BIT15 _BKP1H.Bits.BIT15
|
| 3243 |
|
|
#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8
|
| 3244 |
|
|
#define BKP1H_BIT BKP1H_BIT_8
|
| 3245 |
|
|
|
| 3246 |
|
|
|
| 3247 |
|
|
/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/
|
| 3248 |
|
|
typedef union {
|
| 3249 |
|
|
byte Byte;
|
| 3250 |
|
|
struct {
|
| 3251 |
|
|
byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */
|
| 3252 |
|
|
byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */
|
| 3253 |
|
|
byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */
|
| 3254 |
|
|
byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */
|
| 3255 |
|
|
byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */
|
| 3256 |
|
|
byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */
|
| 3257 |
|
|
byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */
|
| 3258 |
|
|
byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */
|
| 3259 |
|
|
} Bits;
|
| 3260 |
|
|
struct {
|
| 3261 |
|
|
byte grpBIT :8;
|
| 3262 |
|
|
} MergedBits;
|
| 3263 |
|
|
} BKP1LSTR;
|
| 3264 |
|
|
extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F);
|
| 3265 |
|
|
#define BKP1L _BKP1L.Byte
|
| 3266 |
|
|
#define BKP1L_BIT0 _BKP1L.Bits.BIT0
|
| 3267 |
|
|
#define BKP1L_BIT1 _BKP1L.Bits.BIT1
|
| 3268 |
|
|
#define BKP1L_BIT2 _BKP1L.Bits.BIT2
|
| 3269 |
|
|
#define BKP1L_BIT3 _BKP1L.Bits.BIT3
|
| 3270 |
|
|
#define BKP1L_BIT4 _BKP1L.Bits.BIT4
|
| 3271 |
|
|
#define BKP1L_BIT5 _BKP1L.Bits.BIT5
|
| 3272 |
|
|
#define BKP1L_BIT6 _BKP1L.Bits.BIT6
|
| 3273 |
|
|
#define BKP1L_BIT7 _BKP1L.Bits.BIT7
|
| 3274 |
|
|
#define BKP1L_BIT _BKP1L.MergedBits.grpBIT
|
| 3275 |
|
|
|
| 3276 |
|
|
|
| 3277 |
|
|
/*** PPAGE - Page Index Register; 0x00000030 ***/
|
| 3278 |
|
|
typedef union {
|
| 3279 |
|
|
byte Byte;
|
| 3280 |
|
|
struct {
|
| 3281 |
|
|
byte PIX0 :1; /* Page Index Register Bit 0 */
|
| 3282 |
|
|
byte PIX1 :1; /* Page Index Register Bit 1 */
|
| 3283 |
|
|
byte PIX2 :1; /* Page Index Register Bit 2 */
|
| 3284 |
|
|
byte PIX3 :1; /* Page Index Register Bit 3 */
|
| 3285 |
|
|
byte PIX4 :1; /* Page Index Register Bit 4 */
|
| 3286 |
|
|
byte PIX5 :1; /* Page Index Register Bit 5 */
|
| 3287 |
|
|
byte :1;
|
| 3288 |
|
|
byte :1;
|
| 3289 |
|
|
} Bits;
|
| 3290 |
|
|
struct {
|
| 3291 |
|
|
byte grpPIX :6;
|
| 3292 |
|
|
byte :1;
|
| 3293 |
|
|
byte :1;
|
| 3294 |
|
|
} MergedBits;
|
| 3295 |
|
|
} PPAGESTR;
|
| 3296 |
|
|
extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030);
|
| 3297 |
|
|
#define PPAGE _PPAGE.Byte
|
| 3298 |
|
|
#define PPAGE_PIX0 _PPAGE.Bits.PIX0
|
| 3299 |
|
|
#define PPAGE_PIX1 _PPAGE.Bits.PIX1
|
| 3300 |
|
|
#define PPAGE_PIX2 _PPAGE.Bits.PIX2
|
| 3301 |
|
|
#define PPAGE_PIX3 _PPAGE.Bits.PIX3
|
| 3302 |
|
|
#define PPAGE_PIX4 _PPAGE.Bits.PIX4
|
| 3303 |
|
|
#define PPAGE_PIX5 _PPAGE.Bits.PIX5
|
| 3304 |
|
|
#define PPAGE_PIX _PPAGE.MergedBits.grpPIX
|
| 3305 |
|
|
|
| 3306 |
|
|
|
| 3307 |
|
|
/*** PORTK - Port K Data Register; 0x00000032 ***/
|
| 3308 |
|
|
typedef union {
|
| 3309 |
|
|
byte Byte;
|
| 3310 |
|
|
struct {
|
| 3311 |
|
|
byte BIT0 :1; /* Port K Bit 0, XAB14 */
|
| 3312 |
|
|
byte BIT1 :1; /* Port K Bit 1, XAB15 */
|
| 3313 |
|
|
byte BIT2 :1; /* Port K Bit 2, XAB16 */
|
| 3314 |
|
|
byte BIT3 :1; /* Port K Bit 3, XAB17 */
|
| 3315 |
|
|
byte BIT4 :1; /* Port K Bit 4, XAB18 */
|
| 3316 |
|
|
byte BIT5 :1; /* Port K Bit 5, XAB19 */
|
| 3317 |
|
|
byte BIT6 :1; /* Port K Bit 6 */
|
| 3318 |
|
|
byte BIT7 :1; /* Port K Bit 7, ECS/ROMONE */
|
| 3319 |
|
|
} Bits;
|
| 3320 |
|
|
struct {
|
| 3321 |
|
|
byte grpBIT :8;
|
| 3322 |
|
|
} MergedBits;
|
| 3323 |
|
|
} PORTKSTR;
|
| 3324 |
|
|
extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);
|
| 3325 |
|
|
#define PORTK _PORTK.Byte
|
| 3326 |
|
|
#define PORTK_BIT0 _PORTK.Bits.BIT0
|
| 3327 |
|
|
#define PORTK_BIT1 _PORTK.Bits.BIT1
|
| 3328 |
|
|
#define PORTK_BIT2 _PORTK.Bits.BIT2
|
| 3329 |
|
|
#define PORTK_BIT3 _PORTK.Bits.BIT3
|
| 3330 |
|
|
#define PORTK_BIT4 _PORTK.Bits.BIT4
|
| 3331 |
|
|
#define PORTK_BIT5 _PORTK.Bits.BIT5
|
| 3332 |
|
|
#define PORTK_BIT6 _PORTK.Bits.BIT6
|
| 3333 |
|
|
#define PORTK_BIT7 _PORTK.Bits.BIT7
|
| 3334 |
|
|
#define PORTK_BIT _PORTK.MergedBits.grpBIT
|
| 3335 |
|
|
|
| 3336 |
|
|
|
| 3337 |
|
|
/*** DDRK - Port K Data Direction Register; 0x00000033 ***/
|
| 3338 |
|
|
typedef union {
|
| 3339 |
|
|
byte Byte;
|
| 3340 |
|
|
struct {
|
| 3341 |
|
|
byte DDK0 :1; /* Port K Data Direction Bit 0 */
|
| 3342 |
|
|
byte DDK1 :1; /* Port K Data Direction Bit 1 */
|
| 3343 |
|
|
byte DDK2 :1; /* Port K Data Direction Bit 2 */
|
| 3344 |
|
|
byte DDK3 :1; /* Port K Data Direction Bit 3 */
|
| 3345 |
|
|
byte DDK4 :1; /* Port K Data Direction Bit 4 */
|
| 3346 |
|
|
byte DDK5 :1; /* Port K Data Direction Bit 5 */
|
| 3347 |
|
|
byte :1;
|
| 3348 |
|
|
byte DDK7 :1; /* Port K Data Direction Bit 7 */
|
| 3349 |
|
|
} Bits;
|
| 3350 |
|
|
struct {
|
| 3351 |
|
|
byte grpDDK :6;
|
| 3352 |
|
|
byte :1;
|
| 3353 |
|
|
byte grpDDK_7 :1;
|
| 3354 |
|
|
} MergedBits;
|
| 3355 |
|
|
} DDRKSTR;
|
| 3356 |
|
|
extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);
|
| 3357 |
|
|
#define DDRK _DDRK.Byte
|
| 3358 |
|
|
#define DDRK_DDK0 _DDRK.Bits.DDK0
|
| 3359 |
|
|
#define DDRK_DDK1 _DDRK.Bits.DDK1
|
| 3360 |
|
|
#define DDRK_DDK2 _DDRK.Bits.DDK2
|
| 3361 |
|
|
#define DDRK_DDK3 _DDRK.Bits.DDK3
|
| 3362 |
|
|
#define DDRK_DDK4 _DDRK.Bits.DDK4
|
| 3363 |
|
|
#define DDRK_DDK5 _DDRK.Bits.DDK5
|
| 3364 |
|
|
#define DDRK_DDK7 _DDRK.Bits.DDK7
|
| 3365 |
|
|
#define DDRK_DDK _DDRK.MergedBits.grpDDK
|
| 3366 |
|
|
|
| 3367 |
|
|
|
| 3368 |
|
|
/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/
|
| 3369 |
|
|
typedef union {
|
| 3370 |
|
|
byte Byte;
|
| 3371 |
|
|
struct {
|
| 3372 |
|
|
byte SYN0 :1; /* CRG Synthesizer Bit 0 */
|
| 3373 |
|
|
byte SYN1 :1; /* CRG Synthesizer Bit 1 */
|
| 3374 |
|
|
byte SYN2 :1; /* CRG Synthesizer Bit 2 */
|
| 3375 |
|
|
byte SYN3 :1; /* CRG Synthesizer Bit 3 */
|
| 3376 |
|
|
byte SYN4 :1; /* CRG Synthesizer Bit 4 */
|
| 3377 |
|
|
byte SYN5 :1; /* CRG Synthesizer Bit 5 */
|
| 3378 |
|
|
byte :1;
|
| 3379 |
|
|
byte :1;
|
| 3380 |
|
|
} Bits;
|
| 3381 |
|
|
struct {
|
| 3382 |
|
|
byte grpSYN :6;
|
| 3383 |
|
|
byte :1;
|
| 3384 |
|
|
byte :1;
|
| 3385 |
|
|
} MergedBits;
|
| 3386 |
|
|
} SYNRSTR;
|
| 3387 |
|
|
extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);
|
| 3388 |
|
|
#define SYNR _SYNR.Byte
|
| 3389 |
|
|
#define SYNR_SYN0 _SYNR.Bits.SYN0
|
| 3390 |
|
|
#define SYNR_SYN1 _SYNR.Bits.SYN1
|
| 3391 |
|
|
#define SYNR_SYN2 _SYNR.Bits.SYN2
|
| 3392 |
|
|
#define SYNR_SYN3 _SYNR.Bits.SYN3
|
| 3393 |
|
|
#define SYNR_SYN4 _SYNR.Bits.SYN4
|
| 3394 |
|
|
#define SYNR_SYN5 _SYNR.Bits.SYN5
|
| 3395 |
|
|
#define SYNR_SYN _SYNR.MergedBits.grpSYN
|
| 3396 |
|
|
|
| 3397 |
|
|
|
| 3398 |
|
|
/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/
|
| 3399 |
|
|
typedef union {
|
| 3400 |
|
|
byte Byte;
|
| 3401 |
|
|
struct {
|
| 3402 |
|
|
byte REFDV0 :1; /* CRG Reference Divider Bit 0 */
|
| 3403 |
|
|
byte REFDV1 :1; /* CRG Reference Divider Bit 1 */
|
| 3404 |
|
|
byte REFDV2 :1; /* CRG Reference Divider Bit 2 */
|
| 3405 |
|
|
byte REFDV3 :1; /* CRG Reference Divider Bit 3 */
|
| 3406 |
|
|
byte :1;
|
| 3407 |
|
|
byte :1;
|
| 3408 |
|
|
byte :1;
|
| 3409 |
|
|
byte :1;
|
| 3410 |
|
|
} Bits;
|
| 3411 |
|
|
struct {
|
| 3412 |
|
|
byte grpREFDV :4;
|
| 3413 |
|
|
byte :1;
|
| 3414 |
|
|
byte :1;
|
| 3415 |
|
|
byte :1;
|
| 3416 |
|
|
byte :1;
|
| 3417 |
|
|
} MergedBits;
|
| 3418 |
|
|
} REFDVSTR;
|
| 3419 |
|
|
extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);
|
| 3420 |
|
|
#define REFDV _REFDV.Byte
|
| 3421 |
|
|
#define REFDV_REFDV0 _REFDV.Bits.REFDV0
|
| 3422 |
|
|
#define REFDV_REFDV1 _REFDV.Bits.REFDV1
|
| 3423 |
|
|
#define REFDV_REFDV2 _REFDV.Bits.REFDV2
|
| 3424 |
|
|
#define REFDV_REFDV3 _REFDV.Bits.REFDV3
|
| 3425 |
|
|
#define REFDV_REFDV _REFDV.MergedBits.grpREFDV
|
| 3426 |
|
|
|
| 3427 |
|
|
|
| 3428 |
|
|
/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/
|
| 3429 |
|
|
typedef union {
|
| 3430 |
|
|
byte Byte;
|
| 3431 |
|
|
struct {
|
| 3432 |
|
|
byte TOUT0 :1; /* CRG Test Flags Bit 0 */
|
| 3433 |
|
|
byte TOUT1 :1; /* CRG Test Flags Bit 1 */
|
| 3434 |
|
|
byte TOUT2 :1; /* CRG Test Flags Bit 2 */
|
| 3435 |
|
|
byte TOUT3 :1; /* CRG Test Flags Bit 3 */
|
| 3436 |
|
|
byte TOUT4 :1; /* CRG Test Flags Bit 4 */
|
| 3437 |
|
|
byte TOUT5 :1; /* CRG Test Flags Bit 5 */
|
| 3438 |
|
|
byte TOUT6 :1; /* CRG Test Flags Bit 6 */
|
| 3439 |
|
|
byte TOUT7 :1; /* CRG Test Flags Bit 7 */
|
| 3440 |
|
|
} Bits;
|
| 3441 |
|
|
struct {
|
| 3442 |
|
|
byte grpTOUT :8;
|
| 3443 |
|
|
} MergedBits;
|
| 3444 |
|
|
} CTFLGSTR;
|
| 3445 |
|
|
extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036);
|
| 3446 |
|
|
#define CTFLG _CTFLG.Byte
|
| 3447 |
|
|
#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0
|
| 3448 |
|
|
#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1
|
| 3449 |
|
|
#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2
|
| 3450 |
|
|
#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3
|
| 3451 |
|
|
#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4
|
| 3452 |
|
|
#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5
|
| 3453 |
|
|
#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6
|
| 3454 |
|
|
#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7
|
| 3455 |
|
|
#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT
|
| 3456 |
|
|
|
| 3457 |
|
|
|
| 3458 |
|
|
/*** CRGFLG - CRG Flags Register; 0x00000037 ***/
|
| 3459 |
|
|
typedef union {
|
| 3460 |
|
|
byte Byte;
|
| 3461 |
|
|
struct {
|
| 3462 |
|
|
byte SCM :1; /* Self-clock mode Status */
|
| 3463 |
|
|
byte SCMIF :1; /* Self-clock mode Interrupt Flag */
|
| 3464 |
|
|
byte TRACK :1; /* Track Status */
|
| 3465 |
|
|
byte LOCK :1; /* Lock Status */
|
| 3466 |
|
|
byte LOCKIF :1; /* PLL Lock Interrupt Flag */
|
| 3467 |
|
|
byte :1;
|
| 3468 |
|
|
byte PORF :1; /* Power on Reset Flag */
|
| 3469 |
|
|
byte RTIF :1; /* Real Time Interrupt Flag */
|
| 3470 |
|
|
} Bits;
|
| 3471 |
|
|
} CRGFLGSTR;
|
| 3472 |
|
|
extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);
|
| 3473 |
|
|
#define CRGFLG _CRGFLG.Byte
|
| 3474 |
|
|
#define CRGFLG_SCM _CRGFLG.Bits.SCM
|
| 3475 |
|
|
#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF
|
| 3476 |
|
|
#define CRGFLG_TRACK _CRGFLG.Bits.TRACK
|
| 3477 |
|
|
#define CRGFLG_LOCK _CRGFLG.Bits.LOCK
|
| 3478 |
|
|
#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF
|
| 3479 |
|
|
#define CRGFLG_PORF _CRGFLG.Bits.PORF
|
| 3480 |
|
|
#define CRGFLG_RTIF _CRGFLG.Bits.RTIF
|
| 3481 |
|
|
|
| 3482 |
|
|
|
| 3483 |
|
|
/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/
|
| 3484 |
|
|
typedef union {
|
| 3485 |
|
|
byte Byte;
|
| 3486 |
|
|
struct {
|
| 3487 |
|
|
byte :1;
|
| 3488 |
|
|
byte SCMIE :1; /* Self-clock mode Interrupt Enable */
|
| 3489 |
|
|
byte :1;
|
| 3490 |
|
|
byte :1;
|
| 3491 |
|
|
byte LOCKIE :1; /* Lock Interrupt Enable */
|
| 3492 |
|
|
byte :1;
|
| 3493 |
|
|
byte :1;
|
| 3494 |
|
|
byte RTIE :1; /* Real Time Interrupt Enable */
|
| 3495 |
|
|
} Bits;
|
| 3496 |
|
|
} CRGINTSTR;
|
| 3497 |
|
|
extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038);
|
| 3498 |
|
|
#define CRGINT _CRGINT.Byte
|
| 3499 |
|
|
#define CRGINT_SCMIE _CRGINT.Bits.SCMIE
|
| 3500 |
|
|
#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE
|
| 3501 |
|
|
#define CRGINT_RTIE _CRGINT.Bits.RTIE
|
| 3502 |
|
|
|
| 3503 |
|
|
|
| 3504 |
|
|
/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/
|
| 3505 |
|
|
typedef union {
|
| 3506 |
|
|
byte Byte;
|
| 3507 |
|
|
struct {
|
| 3508 |
|
|
byte COPWAI :1; /* COP stops in WAIT mode */
|
| 3509 |
|
|
byte RTIWAI :1; /* RTI stops in WAIT mode */
|
| 3510 |
|
|
byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */
|
| 3511 |
|
|
byte PLLWAI :1; /* PLL stops in WAIT mode */
|
| 3512 |
|
|
byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */
|
| 3513 |
|
|
byte SYSWAI :1; /* System clocks stop in WAIT mode */
|
| 3514 |
|
|
byte PSTP :1; /* Pseudo Stop */
|
| 3515 |
|
|
byte PLLSEL :1; /* PLL selected for system clock */
|
| 3516 |
|
|
} Bits;
|
| 3517 |
|
|
} CLKSELSTR;
|
| 3518 |
|
|
extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039);
|
| 3519 |
|
|
#define CLKSEL _CLKSEL.Byte
|
| 3520 |
|
|
#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI
|
| 3521 |
|
|
#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI
|
| 3522 |
|
|
#define CLKSEL_CWAI _CLKSEL.Bits.CWAI
|
| 3523 |
|
|
#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI
|
| 3524 |
|
|
#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI
|
| 3525 |
|
|
#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI
|
| 3526 |
|
|
#define CLKSEL_PSTP _CLKSEL.Bits.PSTP
|
| 3527 |
|
|
#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL
|
| 3528 |
|
|
|
| 3529 |
|
|
|
| 3530 |
|
|
/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/
|
| 3531 |
|
|
typedef union {
|
| 3532 |
|
|
byte Byte;
|
| 3533 |
|
|
struct {
|
| 3534 |
|
|
byte SCME :1; /* Self-clock mode enable */
|
| 3535 |
|
|
byte :1;
|
| 3536 |
|
|
byte :1;
|
| 3537 |
|
|
byte :1;
|
| 3538 |
|
|
byte ACQ :1; /* Acquisition */
|
| 3539 |
|
|
byte AUTO :1; /* Automatic Bandwidth Control */
|
| 3540 |
|
|
byte PLLON :1; /* Phase Lock Loop On */
|
| 3541 |
|
|
byte CME :1; /* Crystal Monitor Enable */
|
| 3542 |
|
|
} Bits;
|
| 3543 |
|
|
} PLLCTLSTR;
|
| 3544 |
|
|
extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A);
|
| 3545 |
|
|
#define PLLCTL _PLLCTL.Byte
|
| 3546 |
|
|
#define PLLCTL_SCME _PLLCTL.Bits.SCME
|
| 3547 |
|
|
#define PLLCTL_ACQ _PLLCTL.Bits.ACQ
|
| 3548 |
|
|
#define PLLCTL_AUTO _PLLCTL.Bits.AUTO
|
| 3549 |
|
|
#define PLLCTL_PLLON _PLLCTL.Bits.PLLON
|
| 3550 |
|
|
#define PLLCTL_CME _PLLCTL.Bits.CME
|
| 3551 |
|
|
|
| 3552 |
|
|
|
| 3553 |
|
|
/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/
|
| 3554 |
|
|
typedef union {
|
| 3555 |
|
|
byte Byte;
|
| 3556 |
|
|
struct {
|
| 3557 |
|
|
byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */
|
| 3558 |
|
|
byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */
|
| 3559 |
|
|
byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */
|
| 3560 |
|
|
byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */
|
| 3561 |
|
|
byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */
|
| 3562 |
|
|
byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */
|
| 3563 |
|
|
byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */
|
| 3564 |
|
|
byte :1;
|
| 3565 |
|
|
} Bits;
|
| 3566 |
|
|
struct {
|
| 3567 |
|
|
byte grpRTR :7;
|
| 3568 |
|
|
byte :1;
|
| 3569 |
|
|
} MergedBits;
|
| 3570 |
|
|
} RTICTLSTR;
|
| 3571 |
|
|
extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B);
|
| 3572 |
|
|
#define RTICTL _RTICTL.Byte
|
| 3573 |
|
|
#define RTICTL_RTR0 _RTICTL.Bits.RTR0
|
| 3574 |
|
|
#define RTICTL_RTR1 _RTICTL.Bits.RTR1
|
| 3575 |
|
|
#define RTICTL_RTR2 _RTICTL.Bits.RTR2
|
| 3576 |
|
|
#define RTICTL_RTR3 _RTICTL.Bits.RTR3
|
| 3577 |
|
|
#define RTICTL_RTR4 _RTICTL.Bits.RTR4
|
| 3578 |
|
|
#define RTICTL_RTR5 _RTICTL.Bits.RTR5
|
| 3579 |
|
|
#define RTICTL_RTR6 _RTICTL.Bits.RTR6
|
| 3580 |
|
|
#define RTICTL_RTR _RTICTL.MergedBits.grpRTR
|
| 3581 |
|
|
|
| 3582 |
|
|
|
| 3583 |
|
|
/*** COPCTL - CRG COP Control Register; 0x0000003C ***/
|
| 3584 |
|
|
typedef union {
|
| 3585 |
|
|
byte Byte;
|
| 3586 |
|
|
struct {
|
| 3587 |
|
|
byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */
|
| 3588 |
|
|
byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */
|
| 3589 |
|
|
byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */
|
| 3590 |
|
|
byte :1;
|
| 3591 |
|
|
byte :1;
|
| 3592 |
|
|
byte :1;
|
| 3593 |
|
|
byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */
|
| 3594 |
|
|
byte WCOP :1; /* Window COP mode */
|
| 3595 |
|
|
} Bits;
|
| 3596 |
|
|
struct {
|
| 3597 |
|
|
byte grpCR :3;
|
| 3598 |
|
|
byte :1;
|
| 3599 |
|
|
byte :1;
|
| 3600 |
|
|
byte :1;
|
| 3601 |
|
|
byte :1;
|
| 3602 |
|
|
byte :1;
|
| 3603 |
|
|
} MergedBits;
|
| 3604 |
|
|
} COPCTLSTR;
|
| 3605 |
|
|
extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C);
|
| 3606 |
|
|
#define COPCTL _COPCTL.Byte
|
| 3607 |
|
|
#define COPCTL_CR0 _COPCTL.Bits.CR0
|
| 3608 |
|
|
#define COPCTL_CR1 _COPCTL.Bits.CR1
|
| 3609 |
|
|
#define COPCTL_CR2 _COPCTL.Bits.CR2
|
| 3610 |
|
|
#define COPCTL_RSBCK _COPCTL.Bits.RSBCK
|
| 3611 |
|
|
#define COPCTL_WCOP _COPCTL.Bits.WCOP
|
| 3612 |
|
|
#define COPCTL_CR _COPCTL.MergedBits.grpCR
|
| 3613 |
|
|
|
| 3614 |
|
|
|
| 3615 |
|
|
/*** CTCTL - CRG Test Control Register; 0x0000003E ***/
|
| 3616 |
|
|
typedef union {
|
| 3617 |
|
|
byte Byte;
|
| 3618 |
|
|
struct {
|
| 3619 |
|
|
byte TCTL0 :1; /* CRG Test Control Bit 0 */
|
| 3620 |
|
|
byte TCTL1 :1; /* CRG Test Control Bit 1 */
|
| 3621 |
|
|
byte TCTL2 :1; /* CRG Test Control Bit 2 */
|
| 3622 |
|
|
byte TCTL3 :1; /* CRG Test Control Bit 3 */
|
| 3623 |
|
|
byte TCTL4 :1; /* CRG Test Control Bit 4 */
|
| 3624 |
|
|
byte TCTL5 :1; /* CRG Test Control Bit 5 */
|
| 3625 |
|
|
byte TCTL6 :1; /* CRG Test Control Bit 6 */
|
| 3626 |
|
|
byte TCTL7 :1; /* CRG Test Control Bit 7 */
|
| 3627 |
|
|
} Bits;
|
| 3628 |
|
|
struct {
|
| 3629 |
|
|
byte grpTCTL :8;
|
| 3630 |
|
|
} MergedBits;
|
| 3631 |
|
|
} CTCTLSTR;
|
| 3632 |
|
|
extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E);
|
| 3633 |
|
|
#define CTCTL _CTCTL.Byte
|
| 3634 |
|
|
#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0
|
| 3635 |
|
|
#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1
|
| 3636 |
|
|
#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2
|
| 3637 |
|
|
#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3
|
| 3638 |
|
|
#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4
|
| 3639 |
|
|
#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5
|
| 3640 |
|
|
#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6
|
| 3641 |
|
|
#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7
|
| 3642 |
|
|
#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL
|
| 3643 |
|
|
|
| 3644 |
|
|
|
| 3645 |
|
|
/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/
|
| 3646 |
|
|
typedef union {
|
| 3647 |
|
|
byte Byte;
|
| 3648 |
|
|
struct {
|
| 3649 |
|
|
byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */
|
| 3650 |
|
|
byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */
|
| 3651 |
|
|
byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */
|
| 3652 |
|
|
byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */
|
| 3653 |
|
|
byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */
|
| 3654 |
|
|
byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */
|
| 3655 |
|
|
byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */
|
| 3656 |
|
|
byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */
|
| 3657 |
|
|
} Bits;
|
| 3658 |
|
|
struct {
|
| 3659 |
|
|
byte grpBIT :8;
|
| 3660 |
|
|
} MergedBits;
|
| 3661 |
|
|
} ARMCOPSTR;
|
| 3662 |
|
|
extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F);
|
| 3663 |
|
|
#define ARMCOP _ARMCOP.Byte
|
| 3664 |
|
|
#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0
|
| 3665 |
|
|
#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1
|
| 3666 |
|
|
#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2
|
| 3667 |
|
|
#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3
|
| 3668 |
|
|
#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4
|
| 3669 |
|
|
#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5
|
| 3670 |
|
|
#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6
|
| 3671 |
|
|
#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7
|
| 3672 |
|
|
#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT
|
| 3673 |
|
|
|
| 3674 |
|
|
|
| 3675 |
|
|
/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/
|
| 3676 |
|
|
typedef union {
|
| 3677 |
|
|
byte Byte;
|
| 3678 |
|
|
struct {
|
| 3679 |
|
|
byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */
|
| 3680 |
|
|
byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */
|
| 3681 |
|
|
byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */
|
| 3682 |
|
|
byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */
|
| 3683 |
|
|
byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */
|
| 3684 |
|
|
byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */
|
| 3685 |
|
|
byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */
|
| 3686 |
|
|
byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */
|
| 3687 |
|
|
} Bits;
|
| 3688 |
|
|
struct {
|
| 3689 |
|
|
byte grpIOS :8;
|
| 3690 |
|
|
} MergedBits;
|
| 3691 |
|
|
} TIOSSTR;
|
| 3692 |
|
|
extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040);
|
| 3693 |
|
|
#define TIOS _TIOS.Byte
|
| 3694 |
|
|
#define TIOS_IOS0 _TIOS.Bits.IOS0
|
| 3695 |
|
|
#define TIOS_IOS1 _TIOS.Bits.IOS1
|
| 3696 |
|
|
#define TIOS_IOS2 _TIOS.Bits.IOS2
|
| 3697 |
|
|
#define TIOS_IOS3 _TIOS.Bits.IOS3
|
| 3698 |
|
|
#define TIOS_IOS4 _TIOS.Bits.IOS4
|
| 3699 |
|
|
#define TIOS_IOS5 _TIOS.Bits.IOS5
|
| 3700 |
|
|
#define TIOS_IOS6 _TIOS.Bits.IOS6
|
| 3701 |
|
|
#define TIOS_IOS7 _TIOS.Bits.IOS7
|
| 3702 |
|
|
#define TIOS_IOS _TIOS.MergedBits.grpIOS
|
| 3703 |
|
|
|
| 3704 |
|
|
|
| 3705 |
|
|
/*** CFORC - Timer Compare Force Register; 0x00000041 ***/
|
| 3706 |
|
|
typedef union {
|
| 3707 |
|
|
byte Byte;
|
| 3708 |
|
|
struct {
|
| 3709 |
|
|
byte FOC0 :1; /* Force Output Compare Action for Channel 0 */
|
| 3710 |
|
|
byte FOC1 :1; /* Force Output Compare Action for Channel 1 */
|
| 3711 |
|
|
byte FOC2 :1; /* Force Output Compare Action for Channel 2 */
|
| 3712 |
|
|
byte FOC3 :1; /* Force Output Compare Action for Channel 3 */
|
| 3713 |
|
|
byte FOC4 :1; /* Force Output Compare Action for Channel 4 */
|
| 3714 |
|
|
byte FOC5 :1; /* Force Output Compare Action for Channel 5 */
|
| 3715 |
|
|
byte FOC6 :1; /* Force Output Compare Action for Channel 6 */
|
| 3716 |
|
|
byte FOC7 :1; /* Force Output Compare Action for Channel 7 */
|
| 3717 |
|
|
} Bits;
|
| 3718 |
|
|
struct {
|
| 3719 |
|
|
byte grpFOC :8;
|
| 3720 |
|
|
} MergedBits;
|
| 3721 |
|
|
} CFORCSTR;
|
| 3722 |
|
|
extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041);
|
| 3723 |
|
|
#define CFORC _CFORC.Byte
|
| 3724 |
|
|
#define CFORC_FOC0 _CFORC.Bits.FOC0
|
| 3725 |
|
|
#define CFORC_FOC1 _CFORC.Bits.FOC1
|
| 3726 |
|
|
#define CFORC_FOC2 _CFORC.Bits.FOC2
|
| 3727 |
|
|
#define CFORC_FOC3 _CFORC.Bits.FOC3
|
| 3728 |
|
|
#define CFORC_FOC4 _CFORC.Bits.FOC4
|
| 3729 |
|
|
#define CFORC_FOC5 _CFORC.Bits.FOC5
|
| 3730 |
|
|
#define CFORC_FOC6 _CFORC.Bits.FOC6
|
| 3731 |
|
|
#define CFORC_FOC7 _CFORC.Bits.FOC7
|
| 3732 |
|
|
#define CFORC_FOC _CFORC.MergedBits.grpFOC
|
| 3733 |
|
|
|
| 3734 |
|
|
|
| 3735 |
|
|
/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/
|
| 3736 |
|
|
typedef union {
|
| 3737 |
|
|
byte Byte;
|
| 3738 |
|
|
struct {
|
| 3739 |
|
|
byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */
|
| 3740 |
|
|
byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */
|
| 3741 |
|
|
byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */
|
| 3742 |
|
|
byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */
|
| 3743 |
|
|
byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */
|
| 3744 |
|
|
byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */
|
| 3745 |
|
|
byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */
|
| 3746 |
|
|
byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */
|
| 3747 |
|
|
} Bits;
|
| 3748 |
|
|
struct {
|
| 3749 |
|
|
byte grpOC7M :8;
|
| 3750 |
|
|
} MergedBits;
|
| 3751 |
|
|
} OC7MSTR;
|
| 3752 |
|
|
extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042);
|
| 3753 |
|
|
#define OC7M _OC7M.Byte
|
| 3754 |
|
|
#define OC7M_OC7M0 _OC7M.Bits.OC7M0
|
| 3755 |
|
|
#define OC7M_OC7M1 _OC7M.Bits.OC7M1
|
| 3756 |
|
|
#define OC7M_OC7M2 _OC7M.Bits.OC7M2
|
| 3757 |
|
|
#define OC7M_OC7M3 _OC7M.Bits.OC7M3
|
| 3758 |
|
|
#define OC7M_OC7M4 _OC7M.Bits.OC7M4
|
| 3759 |
|
|
#define OC7M_OC7M5 _OC7M.Bits.OC7M5
|
| 3760 |
|
|
#define OC7M_OC7M6 _OC7M.Bits.OC7M6
|
| 3761 |
|
|
#define OC7M_OC7M7 _OC7M.Bits.OC7M7
|
| 3762 |
|
|
#define OC7M_OC7M _OC7M.MergedBits.grpOC7M
|
| 3763 |
|
|
|
| 3764 |
|
|
|
| 3765 |
|
|
/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/
|
| 3766 |
|
|
typedef union {
|
| 3767 |
|
|
byte Byte;
|
| 3768 |
|
|
struct {
|
| 3769 |
|
|
byte OC7D0 :1; /* Output Compare 7 Bit 0 */
|
| 3770 |
|
|
byte OC7D1 :1; /* Output Compare 7 Bit 1 */
|
| 3771 |
|
|
byte OC7D2 :1; /* Output Compare 7 Bit 2 */
|
| 3772 |
|
|
byte OC7D3 :1; /* Output Compare 7 Bit 3 */
|
| 3773 |
|
|
byte OC7D4 :1; /* Output Compare 7 Bit 4 */
|
| 3774 |
|
|
byte OC7D5 :1; /* Output Compare 7 Bit 5 */
|
| 3775 |
|
|
byte OC7D6 :1; /* Output Compare 7 Bit 6 */
|
| 3776 |
|
|
byte OC7D7 :1; /* Output Compare 7 Bit 7 */
|
| 3777 |
|
|
} Bits;
|
| 3778 |
|
|
struct {
|
| 3779 |
|
|
byte grpOC7D :8;
|
| 3780 |
|
|
} MergedBits;
|
| 3781 |
|
|
} OC7DSTR;
|
| 3782 |
|
|
extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043);
|
| 3783 |
|
|
#define OC7D _OC7D.Byte
|
| 3784 |
|
|
#define OC7D_OC7D0 _OC7D.Bits.OC7D0
|
| 3785 |
|
|
#define OC7D_OC7D1 _OC7D.Bits.OC7D1
|
| 3786 |
|
|
#define OC7D_OC7D2 _OC7D.Bits.OC7D2
|
| 3787 |
|
|
#define OC7D_OC7D3 _OC7D.Bits.OC7D3
|
| 3788 |
|
|
#define OC7D_OC7D4 _OC7D.Bits.OC7D4
|
| 3789 |
|
|
#define OC7D_OC7D5 _OC7D.Bits.OC7D5
|
| 3790 |
|
|
#define OC7D_OC7D6 _OC7D.Bits.OC7D6
|
| 3791 |
|
|
#define OC7D_OC7D7 _OC7D.Bits.OC7D7
|
| 3792 |
|
|
#define OC7D_OC7D _OC7D.MergedBits.grpOC7D
|
| 3793 |
|
|
|
| 3794 |
|
|
|
| 3795 |
|
|
/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/
|
| 3796 |
|
|
typedef union {
|
| 3797 |
|
|
byte Byte;
|
| 3798 |
|
|
struct {
|
| 3799 |
|
|
byte :1;
|
| 3800 |
|
|
byte :1;
|
| 3801 |
|
|
byte :1;
|
| 3802 |
|
|
byte :1;
|
| 3803 |
|
|
byte TFFCA :1; /* Timer Fast Flag Clear All */
|
| 3804 |
|
|
byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */
|
| 3805 |
|
|
byte TSWAI :1; /* Timer Module Stops While in Wait */
|
| 3806 |
|
|
byte TEN :1; /* Timer Enable */
|
| 3807 |
|
|
} Bits;
|
| 3808 |
|
|
} TSCR1STR;
|
| 3809 |
|
|
extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046);
|
| 3810 |
|
|
#define TSCR1 _TSCR1.Byte
|
| 3811 |
|
|
#define TSCR1_TFFCA _TSCR1.Bits.TFFCA
|
| 3812 |
|
|
#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ
|
| 3813 |
|
|
#define TSCR1_TSWAI _TSCR1.Bits.TSWAI
|
| 3814 |
|
|
#define TSCR1_TEN _TSCR1.Bits.TEN
|
| 3815 |
|
|
|
| 3816 |
|
|
|
| 3817 |
|
|
/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/
|
| 3818 |
|
|
typedef union {
|
| 3819 |
|
|
byte Byte;
|
| 3820 |
|
|
struct {
|
| 3821 |
|
|
byte TOV0 :1; /* Toggle On Overflow Bit 0 */
|
| 3822 |
|
|
byte TOV1 :1; /* Toggle On Overflow Bit 1 */
|
| 3823 |
|
|
byte TOV2 :1; /* Toggle On Overflow Bit 2 */
|
| 3824 |
|
|
byte TOV3 :1; /* Toggle On Overflow Bit 3 */
|
| 3825 |
|
|
byte TOV4 :1; /* Toggle On Overflow Bit 4 */
|
| 3826 |
|
|
byte TOV5 :1; /* Toggle On Overflow Bit 5 */
|
| 3827 |
|
|
byte TOV6 :1; /* Toggle On Overflow Bit 6 */
|
| 3828 |
|
|
byte TOV7 :1; /* Toggle On Overflow Bit 7 */
|
| 3829 |
|
|
} Bits;
|
| 3830 |
|
|
struct {
|
| 3831 |
|
|
byte grpTOV :8;
|
| 3832 |
|
|
} MergedBits;
|
| 3833 |
|
|
} TTOVSTR;
|
| 3834 |
|
|
extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047);
|
| 3835 |
|
|
#define TTOV _TTOV.Byte
|
| 3836 |
|
|
#define TTOV_TOV0 _TTOV.Bits.TOV0
|
| 3837 |
|
|
#define TTOV_TOV1 _TTOV.Bits.TOV1
|
| 3838 |
|
|
#define TTOV_TOV2 _TTOV.Bits.TOV2
|
| 3839 |
|
|
#define TTOV_TOV3 _TTOV.Bits.TOV3
|
| 3840 |
|
|
#define TTOV_TOV4 _TTOV.Bits.TOV4
|
| 3841 |
|
|
#define TTOV_TOV5 _TTOV.Bits.TOV5
|
| 3842 |
|
|
#define TTOV_TOV6 _TTOV.Bits.TOV6
|
| 3843 |
|
|
#define TTOV_TOV7 _TTOV.Bits.TOV7
|
| 3844 |
|
|
#define TTOV_TOV _TTOV.MergedBits.grpTOV
|
| 3845 |
|
|
|
| 3846 |
|
|
|
| 3847 |
|
|
/*** TCTL1 - Timer Control Register 1; 0x00000048 ***/
|
| 3848 |
|
|
typedef union {
|
| 3849 |
|
|
byte Byte;
|
| 3850 |
|
|
struct {
|
| 3851 |
|
|
byte OL4 :1; /* Output Level Bit 4 */
|
| 3852 |
|
|
byte OM4 :1; /* Output Mode Bit 4 */
|
| 3853 |
|
|
byte OL5 :1; /* Output Level Bit 5 */
|
| 3854 |
|
|
byte OM5 :1; /* Output Mode Bit 5 */
|
| 3855 |
|
|
byte OL6 :1; /* Output Level Bit 6 */
|
| 3856 |
|
|
byte OM6 :1; /* Output Mode Bit 6 */
|
| 3857 |
|
|
byte OL7 :1; /* Output Level Bit 7 */
|
| 3858 |
|
|
byte OM7 :1; /* Output Mode Bit 7 */
|
| 3859 |
|
|
} Bits;
|
| 3860 |
|
|
} TCTL1STR;
|
| 3861 |
|
|
extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048);
|
| 3862 |
|
|
#define TCTL1 _TCTL1.Byte
|
| 3863 |
|
|
#define TCTL1_OL4 _TCTL1.Bits.OL4
|
| 3864 |
|
|
#define TCTL1_OM4 _TCTL1.Bits.OM4
|
| 3865 |
|
|
#define TCTL1_OL5 _TCTL1.Bits.OL5
|
| 3866 |
|
|
#define TCTL1_OM5 _TCTL1.Bits.OM5
|
| 3867 |
|
|
#define TCTL1_OL6 _TCTL1.Bits.OL6
|
| 3868 |
|
|
#define TCTL1_OM6 _TCTL1.Bits.OM6
|
| 3869 |
|
|
#define TCTL1_OL7 _TCTL1.Bits.OL7
|
| 3870 |
|
|
#define TCTL1_OM7 _TCTL1.Bits.OM7
|
| 3871 |
|
|
|
| 3872 |
|
|
|
| 3873 |
|
|
/*** TCTL2 - Timer Control Register 2; 0x00000049 ***/
|
| 3874 |
|
|
typedef union {
|
| 3875 |
|
|
byte Byte;
|
| 3876 |
|
|
struct {
|
| 3877 |
|
|
byte OL0 :1; /* Output Level Bit 0 */
|
| 3878 |
|
|
byte OM0 :1; /* Output Mode Bit 0 */
|
| 3879 |
|
|
byte OL1 :1; /* Output Level Bit 1 */
|
| 3880 |
|
|
byte OM1 :1; /* Output Mode Bit 1 */
|
| 3881 |
|
|
byte OL2 :1; /* Output Level Bit 2 */
|
| 3882 |
|
|
byte OM2 :1; /* Output Mode Bit 2 */
|
| 3883 |
|
|
byte OL3 :1; /* Output Level Bit 3 */
|
| 3884 |
|
|
byte OM3 :1; /* Output Mode Bit 3 */
|
| 3885 |
|
|
} Bits;
|
| 3886 |
|
|
} TCTL2STR;
|
| 3887 |
|
|
extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049);
|
| 3888 |
|
|
#define TCTL2 _TCTL2.Byte
|
| 3889 |
|
|
#define TCTL2_OL0 _TCTL2.Bits.OL0
|
| 3890 |
|
|
#define TCTL2_OM0 _TCTL2.Bits.OM0
|
| 3891 |
|
|
#define TCTL2_OL1 _TCTL2.Bits.OL1
|
| 3892 |
|
|
#define TCTL2_OM1 _TCTL2.Bits.OM1
|
| 3893 |
|
|
#define TCTL2_OL2 _TCTL2.Bits.OL2
|
| 3894 |
|
|
#define TCTL2_OM2 _TCTL2.Bits.OM2
|
| 3895 |
|
|
#define TCTL2_OL3 _TCTL2.Bits.OL3
|
| 3896 |
|
|
#define TCTL2_OM3 _TCTL2.Bits.OM3
|
| 3897 |
|
|
|
| 3898 |
|
|
|
| 3899 |
|
|
/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/
|
| 3900 |
|
|
typedef union {
|
| 3901 |
|
|
byte Byte;
|
| 3902 |
|
|
struct {
|
| 3903 |
|
|
byte EDG4A :1; /* Input Capture Edge Control 4A */
|
| 3904 |
|
|
byte EDG4B :1; /* Input Capture Edge Control 4B */
|
| 3905 |
|
|
byte EDG5A :1; /* Input Capture Edge Control 5A */
|
| 3906 |
|
|
byte EDG5B :1; /* Input Capture Edge Control 5B */
|
| 3907 |
|
|
byte EDG6A :1; /* Input Capture Edge Control 6A */
|
| 3908 |
|
|
byte EDG6B :1; /* Input Capture Edge Control 6B */
|
| 3909 |
|
|
byte EDG7A :1; /* Input Capture Edge Control 7A */
|
| 3910 |
|
|
byte EDG7B :1; /* Input Capture Edge Control 7B */
|
| 3911 |
|
|
} Bits;
|
| 3912 |
|
|
} TCTL3STR;
|
| 3913 |
|
|
extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A);
|
| 3914 |
|
|
#define TCTL3 _TCTL3.Byte
|
| 3915 |
|
|
#define TCTL3_EDG4A _TCTL3.Bits.EDG4A
|
| 3916 |
|
|
#define TCTL3_EDG4B _TCTL3.Bits.EDG4B
|
| 3917 |
|
|
#define TCTL3_EDG5A _TCTL3.Bits.EDG5A
|
| 3918 |
|
|
#define TCTL3_EDG5B _TCTL3.Bits.EDG5B
|
| 3919 |
|
|
#define TCTL3_EDG6A _TCTL3.Bits.EDG6A
|
| 3920 |
|
|
#define TCTL3_EDG6B _TCTL3.Bits.EDG6B
|
| 3921 |
|
|
#define TCTL3_EDG7A _TCTL3.Bits.EDG7A
|
| 3922 |
|
|
#define TCTL3_EDG7B _TCTL3.Bits.EDG7B
|
| 3923 |
|
|
|
| 3924 |
|
|
|
| 3925 |
|
|
/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/
|
| 3926 |
|
|
typedef union {
|
| 3927 |
|
|
byte Byte;
|
| 3928 |
|
|
struct {
|
| 3929 |
|
|
byte EDG0A :1; /* Input Capture Edge Control 0A */
|
| 3930 |
|
|
byte EDG0B :1; /* Input Capture Edge Control 0B */
|
| 3931 |
|
|
byte EDG1A :1; /* Input Capture Edge Control 1A */
|
| 3932 |
|
|
byte EDG1B :1; /* Input Capture Edge Control 1B */
|
| 3933 |
|
|
byte EDG2A :1; /* Input Capture Edge Control 2A */
|
| 3934 |
|
|
byte EDG2B :1; /* Input Capture Edge Control 2B */
|
| 3935 |
|
|
byte EDG3A :1; /* Input Capture Edge Control 3A */
|
| 3936 |
|
|
byte EDG3B :1; /* Input Capture Edge Control 3B */
|
| 3937 |
|
|
} Bits;
|
| 3938 |
|
|
} TCTL4STR;
|
| 3939 |
|
|
extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B);
|
| 3940 |
|
|
#define TCTL4 _TCTL4.Byte
|
| 3941 |
|
|
#define TCTL4_EDG0A _TCTL4.Bits.EDG0A
|
| 3942 |
|
|
#define TCTL4_EDG0B _TCTL4.Bits.EDG0B
|
| 3943 |
|
|
#define TCTL4_EDG1A _TCTL4.Bits.EDG1A
|
| 3944 |
|
|
#define TCTL4_EDG1B _TCTL4.Bits.EDG1B
|
| 3945 |
|
|
#define TCTL4_EDG2A _TCTL4.Bits.EDG2A
|
| 3946 |
|
|
#define TCTL4_EDG2B _TCTL4.Bits.EDG2B
|
| 3947 |
|
|
#define TCTL4_EDG3A _TCTL4.Bits.EDG3A
|
| 3948 |
|
|
#define TCTL4_EDG3B _TCTL4.Bits.EDG3B
|
| 3949 |
|
|
|
| 3950 |
|
|
|
| 3951 |
|
|
/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/
|
| 3952 |
|
|
typedef union {
|
| 3953 |
|
|
byte Byte;
|
| 3954 |
|
|
struct {
|
| 3955 |
|
|
byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */
|
| 3956 |
|
|
byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */
|
| 3957 |
|
|
byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */
|
| 3958 |
|
|
byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */
|
| 3959 |
|
|
byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */
|
| 3960 |
|
|
byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */
|
| 3961 |
|
|
byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */
|
| 3962 |
|
|
byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */
|
| 3963 |
|
|
} Bits;
|
| 3964 |
|
|
} TIESTR;
|
| 3965 |
|
|
extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C);
|
| 3966 |
|
|
#define TIE _TIE.Byte
|
| 3967 |
|
|
#define TIE_C0I _TIE.Bits.C0I
|
| 3968 |
|
|
#define TIE_C1I _TIE.Bits.C1I
|
| 3969 |
|
|
#define TIE_C2I _TIE.Bits.C2I
|
| 3970 |
|
|
#define TIE_C3I _TIE.Bits.C3I
|
| 3971 |
|
|
#define TIE_C4I _TIE.Bits.C4I
|
| 3972 |
|
|
#define TIE_C5I _TIE.Bits.C5I
|
| 3973 |
|
|
#define TIE_C6I _TIE.Bits.C6I
|
| 3974 |
|
|
#define TIE_C7I _TIE.Bits.C7I
|
| 3975 |
|
|
|
| 3976 |
|
|
|
| 3977 |
|
|
/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/
|
| 3978 |
|
|
typedef union {
|
| 3979 |
|
|
byte Byte;
|
| 3980 |
|
|
struct {
|
| 3981 |
|
|
byte PR0 :1; /* Timer Prescaler Select Bit 0 */
|
| 3982 |
|
|
byte PR1 :1; /* Timer Prescaler Select Bit 1 */
|
| 3983 |
|
|
byte PR2 :1; /* Timer Prescaler Select Bit 2 */
|
| 3984 |
|
|
byte TCRE :1; /* Timer Counter Reset Enable */
|
| 3985 |
|
|
byte :1;
|
| 3986 |
|
|
byte :1;
|
| 3987 |
|
|
byte :1;
|
| 3988 |
|
|
byte TOI :1; /* Timer Overflow Interrupt Enable */
|
| 3989 |
|
|
} Bits;
|
| 3990 |
|
|
struct {
|
| 3991 |
|
|
byte grpPR :3;
|
| 3992 |
|
|
byte :1;
|
| 3993 |
|
|
byte :1;
|
| 3994 |
|
|
byte :1;
|
| 3995 |
|
|
byte :1;
|
| 3996 |
|
|
byte :1;
|
| 3997 |
|
|
} MergedBits;
|
| 3998 |
|
|
} TSCR2STR;
|
| 3999 |
|
|
extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D);
|
| 4000 |
|
|
#define TSCR2 _TSCR2.Byte
|
| 4001 |
|
|
#define TSCR2_PR0 _TSCR2.Bits.PR0
|
| 4002 |
|
|
#define TSCR2_PR1 _TSCR2.Bits.PR1
|
| 4003 |
|
|
#define TSCR2_PR2 _TSCR2.Bits.PR2
|
| 4004 |
|
|
#define TSCR2_TCRE _TSCR2.Bits.TCRE
|
| 4005 |
|
|
#define TSCR2_TOI _TSCR2.Bits.TOI
|
| 4006 |
|
|
#define TSCR2_PR _TSCR2.MergedBits.grpPR
|
| 4007 |
|
|
|
| 4008 |
|
|
|
| 4009 |
|
|
/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/
|
| 4010 |
|
|
typedef union {
|
| 4011 |
|
|
byte Byte;
|
| 4012 |
|
|
struct {
|
| 4013 |
|
|
byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */
|
| 4014 |
|
|
byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */
|
| 4015 |
|
|
byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */
|
| 4016 |
|
|
byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */
|
| 4017 |
|
|
byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */
|
| 4018 |
|
|
byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */
|
| 4019 |
|
|
byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */
|
| 4020 |
|
|
byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */
|
| 4021 |
|
|
} Bits;
|
| 4022 |
|
|
} TFLG1STR;
|
| 4023 |
|
|
extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E);
|
| 4024 |
|
|
#define TFLG1 _TFLG1.Byte
|
| 4025 |
|
|
#define TFLG1_C0F _TFLG1.Bits.C0F
|
| 4026 |
|
|
#define TFLG1_C1F _TFLG1.Bits.C1F
|
| 4027 |
|
|
#define TFLG1_C2F _TFLG1.Bits.C2F
|
| 4028 |
|
|
#define TFLG1_C3F _TFLG1.Bits.C3F
|
| 4029 |
|
|
#define TFLG1_C4F _TFLG1.Bits.C4F
|
| 4030 |
|
|
#define TFLG1_C5F _TFLG1.Bits.C5F
|
| 4031 |
|
|
#define TFLG1_C6F _TFLG1.Bits.C6F
|
| 4032 |
|
|
#define TFLG1_C7F _TFLG1.Bits.C7F
|
| 4033 |
|
|
|
| 4034 |
|
|
|
| 4035 |
|
|
/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/
|
| 4036 |
|
|
typedef union {
|
| 4037 |
|
|
byte Byte;
|
| 4038 |
|
|
struct {
|
| 4039 |
|
|
byte :1;
|
| 4040 |
|
|
byte :1;
|
| 4041 |
|
|
byte :1;
|
| 4042 |
|
|
byte :1;
|
| 4043 |
|
|
byte :1;
|
| 4044 |
|
|
byte :1;
|
| 4045 |
|
|
byte :1;
|
| 4046 |
|
|
byte TOF :1; /* Timer Overflow Flag */
|
| 4047 |
|
|
} Bits;
|
| 4048 |
|
|
} TFLG2STR;
|
| 4049 |
|
|
extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F);
|
| 4050 |
|
|
#define TFLG2 _TFLG2.Byte
|
| 4051 |
|
|
#define TFLG2_TOF _TFLG2.Bits.TOF
|
| 4052 |
|
|
|
| 4053 |
|
|
|
| 4054 |
|
|
/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/
|
| 4055 |
|
|
typedef union {
|
| 4056 |
|
|
byte Byte;
|
| 4057 |
|
|
struct {
|
| 4058 |
|
|
byte PAI :1; /* Pulse Accumulator Input Interrupt enable */
|
| 4059 |
|
|
byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */
|
| 4060 |
|
|
byte CLK0 :1; /* Clock Select Bit 0 */
|
| 4061 |
|
|
byte CLK1 :1; /* Clock Select Bit 1 */
|
| 4062 |
|
|
byte PEDGE :1; /* Pulse Accumulator Edge Control */
|
| 4063 |
|
|
byte PAMOD :1; /* Pulse Accumulator Mode */
|
| 4064 |
|
|
byte PAEN :1; /* Pulse Accumulator A System Enable */
|
| 4065 |
|
|
byte :1;
|
| 4066 |
|
|
} Bits;
|
| 4067 |
|
|
struct {
|
| 4068 |
|
|
byte :1;
|
| 4069 |
|
|
byte :1;
|
| 4070 |
|
|
byte grpCLK :2;
|
| 4071 |
|
|
byte :1;
|
| 4072 |
|
|
byte :1;
|
| 4073 |
|
|
byte :1;
|
| 4074 |
|
|
byte :1;
|
| 4075 |
|
|
} MergedBits;
|
| 4076 |
|
|
} PACTLSTR;
|
| 4077 |
|
|
extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060);
|
| 4078 |
|
|
#define PACTL _PACTL.Byte
|
| 4079 |
|
|
#define PACTL_PAI _PACTL.Bits.PAI
|
| 4080 |
|
|
#define PACTL_PAOVI _PACTL.Bits.PAOVI
|
| 4081 |
|
|
#define PACTL_CLK0 _PACTL.Bits.CLK0
|
| 4082 |
|
|
#define PACTL_CLK1 _PACTL.Bits.CLK1
|
| 4083 |
|
|
#define PACTL_PEDGE _PACTL.Bits.PEDGE
|
| 4084 |
|
|
#define PACTL_PAMOD _PACTL.Bits.PAMOD
|
| 4085 |
|
|
#define PACTL_PAEN _PACTL.Bits.PAEN
|
| 4086 |
|
|
#define PACTL_CLK _PACTL.MergedBits.grpCLK
|
| 4087 |
|
|
|
| 4088 |
|
|
|
| 4089 |
|
|
/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/
|
| 4090 |
|
|
typedef union {
|
| 4091 |
|
|
byte Byte;
|
| 4092 |
|
|
struct {
|
| 4093 |
|
|
byte PAIF :1; /* Pulse Accumulator Input edge Flag */
|
| 4094 |
|
|
byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */
|
| 4095 |
|
|
byte :1;
|
| 4096 |
|
|
byte :1;
|
| 4097 |
|
|
byte :1;
|
| 4098 |
|
|
byte :1;
|
| 4099 |
|
|
byte :1;
|
| 4100 |
|
|
byte :1;
|
| 4101 |
|
|
} Bits;
|
| 4102 |
|
|
} PAFLGSTR;
|
| 4103 |
|
|
extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061);
|
| 4104 |
|
|
#define PAFLG _PAFLG.Byte
|
| 4105 |
|
|
#define PAFLG_PAIF _PAFLG.Bits.PAIF
|
| 4106 |
|
|
#define PAFLG_PAOVF _PAFLG.Bits.PAOVF
|
| 4107 |
|
|
|
| 4108 |
|
|
|
| 4109 |
|
|
/*** ATDSTAT0 - A/D Status Register 0; 0x00000086 ***/
|
| 4110 |
|
|
typedef union {
|
| 4111 |
|
|
byte Byte;
|
| 4112 |
|
|
struct {
|
| 4113 |
|
|
byte CC0 :1; /* Conversion Counter 0 */
|
| 4114 |
|
|
byte CC1 :1; /* Conversion Counter 1 */
|
| 4115 |
|
|
byte CC2 :1; /* Conversion Counter 2 */
|
| 4116 |
|
|
byte :1;
|
| 4117 |
|
|
byte FIFOR :1; /* FIFO Over Run Flag */
|
| 4118 |
|
|
byte ETORF :1; /* External Trigger Overrun Flag */
|
| 4119 |
|
|
byte :1;
|
| 4120 |
|
|
byte SCF :1; /* Sequence Complete Flag */
|
| 4121 |
|
|
} Bits;
|
| 4122 |
|
|
struct {
|
| 4123 |
|
|
byte grpCC :3;
|
| 4124 |
|
|
byte :1;
|
| 4125 |
|
|
byte :1;
|
| 4126 |
|
|
byte :1;
|
| 4127 |
|
|
byte :1;
|
| 4128 |
|
|
byte :1;
|
| 4129 |
|
|
} MergedBits;
|
| 4130 |
|
|
} ATDSTAT0STR;
|
| 4131 |
|
|
extern volatile ATDSTAT0STR _ATDSTAT0 @(REG_BASE + 0x00000086);
|
| 4132 |
|
|
#define ATDSTAT0 _ATDSTAT0.Byte
|
| 4133 |
|
|
#define ATDSTAT0_CC0 _ATDSTAT0.Bits.CC0
|
| 4134 |
|
|
#define ATDSTAT0_CC1 _ATDSTAT0.Bits.CC1
|
| 4135 |
|
|
#define ATDSTAT0_CC2 _ATDSTAT0.Bits.CC2
|
| 4136 |
|
|
#define ATDSTAT0_FIFOR _ATDSTAT0.Bits.FIFOR
|
| 4137 |
|
|
#define ATDSTAT0_ETORF _ATDSTAT0.Bits.ETORF
|
| 4138 |
|
|
#define ATDSTAT0_SCF _ATDSTAT0.Bits.SCF
|
| 4139 |
|
|
#define ATDSTAT0_CC _ATDSTAT0.MergedBits.grpCC
|
| 4140 |
|
|
|
| 4141 |
|
|
|
| 4142 |
|
|
/*** ATDSTAT1 - A/D Status Register 1; 0x0000008B ***/
|
| 4143 |
|
|
typedef union {
|
| 4144 |
|
|
byte Byte;
|
| 4145 |
|
|
struct {
|
| 4146 |
|
|
byte CCF0 :1; /* Conversion Complete Flag 0 */
|
| 4147 |
|
|
byte CCF1 :1; /* Conversion Complete Flag 1 */
|
| 4148 |
|
|
byte CCF2 :1; /* Conversion Complete Flag 2 */
|
| 4149 |
|
|
byte CCF3 :1; /* Conversion Complete Flag 3 */
|
| 4150 |
|
|
byte CCF4 :1; /* Conversion Complete Flag 4 */
|
| 4151 |
|
|
byte CCF5 :1; /* Conversion Complete Flag 5 */
|
| 4152 |
|
|
byte CCF6 :1; /* Conversion Complete Flag 6 */
|
| 4153 |
|
|
byte CCF7 :1; /* Conversion Complete Flag 7 */
|
| 4154 |
|
|
} Bits;
|
| 4155 |
|
|
struct {
|
| 4156 |
|
|
byte grpCCF :8;
|
| 4157 |
|
|
} MergedBits;
|
| 4158 |
|
|
} ATDSTAT1STR;
|
| 4159 |
|
|
extern volatile ATDSTAT1STR _ATDSTAT1 @(REG_BASE + 0x0000008B);
|
| 4160 |
|
|
#define ATDSTAT1 _ATDSTAT1.Byte
|
| 4161 |
|
|
#define ATDSTAT1_CCF0 _ATDSTAT1.Bits.CCF0
|
| 4162 |
|
|
#define ATDSTAT1_CCF1 _ATDSTAT1.Bits.CCF1
|
| 4163 |
|
|
#define ATDSTAT1_CCF2 _ATDSTAT1.Bits.CCF2
|
| 4164 |
|
|
#define ATDSTAT1_CCF3 _ATDSTAT1.Bits.CCF3
|
| 4165 |
|
|
#define ATDSTAT1_CCF4 _ATDSTAT1.Bits.CCF4
|
| 4166 |
|
|
#define ATDSTAT1_CCF5 _ATDSTAT1.Bits.CCF5
|
| 4167 |
|
|
#define ATDSTAT1_CCF6 _ATDSTAT1.Bits.CCF6
|
| 4168 |
|
|
#define ATDSTAT1_CCF7 _ATDSTAT1.Bits.CCF7
|
| 4169 |
|
|
#define ATDSTAT1_CCF _ATDSTAT1.MergedBits.grpCCF
|
| 4170 |
|
|
|
| 4171 |
|
|
|
| 4172 |
|
|
/*** ATDDIEN - ATD Input Enable Mask Register; 0x0000008D ***/
|
| 4173 |
|
|
typedef union {
|
| 4174 |
|
|
byte Byte;
|
| 4175 |
|
|
struct {
|
| 4176 |
|
|
byte BIT0 :1; /* Disable/Enable digital input buffer */
|
| 4177 |
|
|
byte BIT1 :1; /* Disable/Enable digital input buffer */
|
| 4178 |
|
|
byte BIT2 :1; /* Disable/Enable digital input buffer */
|
| 4179 |
|
|
byte BIT3 :1; /* Disable/Enable digital input buffer */
|
| 4180 |
|
|
byte BIT4 :1; /* Disable/Enable digital input buffer */
|
| 4181 |
|
|
byte BIT5 :1; /* Disable/Enable digital input buffer */
|
| 4182 |
|
|
byte BIT6 :1; /* Disable/Enable digital input buffer */
|
| 4183 |
|
|
byte BIT7 :1; /* Disable/Enable digital input buffer */
|
| 4184 |
|
|
} Bits;
|
| 4185 |
|
|
struct {
|
| 4186 |
|
|
byte grpBIT :8;
|
| 4187 |
|
|
} MergedBits;
|
| 4188 |
|
|
} ATDDIENSTR;
|
| 4189 |
|
|
extern volatile ATDDIENSTR _ATDDIEN @(REG_BASE + 0x0000008D);
|
| 4190 |
|
|
#define ATDDIEN _ATDDIEN.Byte
|
| 4191 |
|
|
#define ATDDIEN_BIT0 _ATDDIEN.Bits.BIT0
|
| 4192 |
|
|
#define ATDDIEN_BIT1 _ATDDIEN.Bits.BIT1
|
| 4193 |
|
|
#define ATDDIEN_BIT2 _ATDDIEN.Bits.BIT2
|
| 4194 |
|
|
#define ATDDIEN_BIT3 _ATDDIEN.Bits.BIT3
|
| 4195 |
|
|
#define ATDDIEN_BIT4 _ATDDIEN.Bits.BIT4
|
| 4196 |
|
|
#define ATDDIEN_BIT5 _ATDDIEN.Bits.BIT5
|
| 4197 |
|
|
#define ATDDIEN_BIT6 _ATDDIEN.Bits.BIT6
|
| 4198 |
|
|
#define ATDDIEN_BIT7 _ATDDIEN.Bits.BIT7
|
| 4199 |
|
|
#define ATDDIEN_BIT _ATDDIEN.MergedBits.grpBIT
|
| 4200 |
|
|
|
| 4201 |
|
|
|
| 4202 |
|
|
/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/
|
| 4203 |
|
|
typedef union {
|
| 4204 |
|
|
byte Byte;
|
| 4205 |
|
|
struct {
|
| 4206 |
|
|
byte BIT0 :1; /* AN0 */
|
| 4207 |
|
|
byte BIT1 :1; /* AN1 */
|
| 4208 |
|
|
byte BIT2 :1; /* AN2 */
|
| 4209 |
|
|
byte BIT3 :1; /* AN3 */
|
| 4210 |
|
|
byte BIT4 :1; /* AN4 */
|
| 4211 |
|
|
byte BIT5 :1; /* AN5 */
|
| 4212 |
|
|
byte BIT6 :1; /* AN6 */
|
| 4213 |
|
|
byte BIT7 :1; /* AN7 */
|
| 4214 |
|
|
} Bits;
|
| 4215 |
|
|
struct {
|
| 4216 |
|
|
byte grpBIT :8;
|
| 4217 |
|
|
} MergedBits;
|
| 4218 |
|
|
} PORTAD0STR;
|
| 4219 |
|
|
extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F);
|
| 4220 |
|
|
#define PORTAD0 _PORTAD0.Byte
|
| 4221 |
|
|
#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0
|
| 4222 |
|
|
#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1
|
| 4223 |
|
|
#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2
|
| 4224 |
|
|
#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3
|
| 4225 |
|
|
#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4
|
| 4226 |
|
|
#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5
|
| 4227 |
|
|
#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6
|
| 4228 |
|
|
#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7
|
| 4229 |
|
|
#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT
|
| 4230 |
|
|
|
| 4231 |
|
|
|
| 4232 |
|
|
/*** SCICR1 - SCI Control Register 1; 0x000000CA ***/
|
| 4233 |
|
|
typedef union {
|
| 4234 |
|
|
byte Byte;
|
| 4235 |
|
|
struct {
|
| 4236 |
|
|
byte PT :1; /* Parity Type Bit */
|
| 4237 |
|
|
byte PE :1; /* Parity Enable Bit */
|
| 4238 |
|
|
byte ILT :1; /* Idle Line Type Bit */
|
| 4239 |
|
|
byte WAKE :1; /* Wakeup Condition Bit */
|
| 4240 |
|
|
byte M :1; /* Data Format Mode Bit */
|
| 4241 |
|
|
byte RSRC :1; /* Receiver Source Bit */
|
| 4242 |
|
|
byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */
|
| 4243 |
|
|
byte LOOPS :1; /* Loop Select Bit */
|
| 4244 |
|
|
} Bits;
|
| 4245 |
|
|
} SCICR1STR;
|
| 4246 |
|
|
extern volatile SCICR1STR _SCICR1 @(REG_BASE + 0x000000CA);
|
| 4247 |
|
|
#define SCICR1 _SCICR1.Byte
|
| 4248 |
|
|
#define SCICR1_PT _SCICR1.Bits.PT
|
| 4249 |
|
|
#define SCICR1_PE _SCICR1.Bits.PE
|
| 4250 |
|
|
#define SCICR1_ILT _SCICR1.Bits.ILT
|
| 4251 |
|
|
#define SCICR1_WAKE _SCICR1.Bits.WAKE
|
| 4252 |
|
|
#define SCICR1_M _SCICR1.Bits.M
|
| 4253 |
|
|
#define SCICR1_RSRC _SCICR1.Bits.RSRC
|
| 4254 |
|
|
#define SCICR1_SCISWAI _SCICR1.Bits.SCISWAI
|
| 4255 |
|
|
#define SCICR1_LOOPS _SCICR1.Bits.LOOPS
|
| 4256 |
|
|
|
| 4257 |
|
|
|
| 4258 |
|
|
/*** SCICR2 - SCI Control Register 2; 0x000000CB ***/
|
| 4259 |
|
|
typedef union {
|
| 4260 |
|
|
byte Byte;
|
| 4261 |
|
|
struct {
|
| 4262 |
|
|
byte SBK :1; /* Send Break Bit */
|
| 4263 |
|
|
byte RWU :1; /* Receiver Wakeup Bit */
|
| 4264 |
|
|
byte RE :1; /* Receiver Enable Bit */
|
| 4265 |
|
|
byte TE :1; /* Transmitter Enable Bit */
|
| 4266 |
|
|
byte ILIE :1; /* Idle Line Interrupt Enable Bit */
|
| 4267 |
|
|
byte RIE :1; /* Receiver Full Interrupt Enable Bit */
|
| 4268 |
|
|
byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */
|
| 4269 |
|
|
byte SCTIE :1; /* Transmitter Interrupt Enable Bit */
|
| 4270 |
|
|
} Bits;
|
| 4271 |
|
|
} SCICR2STR;
|
| 4272 |
|
|
extern volatile SCICR2STR _SCICR2 @(REG_BASE + 0x000000CB);
|
| 4273 |
|
|
#define SCICR2 _SCICR2.Byte
|
| 4274 |
|
|
#define SCICR2_SBK _SCICR2.Bits.SBK
|
| 4275 |
|
|
#define SCICR2_RWU _SCICR2.Bits.RWU
|
| 4276 |
|
|
#define SCICR2_RE _SCICR2.Bits.RE
|
| 4277 |
|
|
#define SCICR2_TE _SCICR2.Bits.TE
|
| 4278 |
|
|
#define SCICR2_ILIE _SCICR2.Bits.ILIE
|
| 4279 |
|
|
#define SCICR2_RIE _SCICR2.Bits.RIE
|
| 4280 |
|
|
#define SCICR2_TCIE _SCICR2.Bits.TCIE
|
| 4281 |
|
|
#define SCICR2_SCTIE _SCICR2.Bits.SCTIE
|
| 4282 |
|
|
|
| 4283 |
|
|
|
| 4284 |
|
|
/*** SCISR1 - SCI Status Register 1; 0x000000CC ***/
|
| 4285 |
|
|
typedef union {
|
| 4286 |
|
|
byte Byte;
|
| 4287 |
|
|
struct {
|
| 4288 |
|
|
byte PF :1; /* Parity Error Flag */
|
| 4289 |
|
|
byte FE :1; /* Framing Error Flag */
|
| 4290 |
|
|
byte NF :1; /* Noise Flag */
|
| 4291 |
|
|
byte OR :1; /* Overrun Flag */
|
| 4292 |
|
|
byte IDLE :1; /* Idle Line Flag */
|
| 4293 |
|
|
byte RDRF :1; /* Receive Data Register Full Flag */
|
| 4294 |
|
|
byte TC :1; /* Transmit Complete Flag */
|
| 4295 |
|
|
byte TDRE :1; /* Transmit Data Register Empty Flag */
|
| 4296 |
|
|
} Bits;
|
| 4297 |
|
|
} SCISR1STR;
|
| 4298 |
|
|
extern volatile SCISR1STR _SCISR1 @(REG_BASE + 0x000000CC);
|
| 4299 |
|
|
#define SCISR1 _SCISR1.Byte
|
| 4300 |
|
|
#define SCISR1_PF _SCISR1.Bits.PF
|
| 4301 |
|
|
#define SCISR1_FE _SCISR1.Bits.FE
|
| 4302 |
|
|
#define SCISR1_NF _SCISR1.Bits.NF
|
| 4303 |
|
|
#define SCISR1_OR _SCISR1.Bits.OR
|
| 4304 |
|
|
#define SCISR1_IDLE _SCISR1.Bits.IDLE
|
| 4305 |
|
|
#define SCISR1_RDRF _SCISR1.Bits.RDRF
|
| 4306 |
|
|
#define SCISR1_TC _SCISR1.Bits.TC
|
| 4307 |
|
|
#define SCISR1_TDRE _SCISR1.Bits.TDRE
|
| 4308 |
|
|
|
| 4309 |
|
|
|
| 4310 |
|
|
/*** SCISR2 - SCI Status Register 2; 0x000000CD ***/
|
| 4311 |
|
|
typedef union {
|
| 4312 |
|
|
byte Byte;
|
| 4313 |
|
|
struct {
|
| 4314 |
|
|
byte RAF :1; /* Receiver Active Flag */
|
| 4315 |
|
|
byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */
|
| 4316 |
|
|
byte BRK13 :1; /* Break Transmit character length */
|
| 4317 |
|
|
byte :1;
|
| 4318 |
|
|
byte :1;
|
| 4319 |
|
|
byte :1;
|
| 4320 |
|
|
byte :1;
|
| 4321 |
|
|
byte :1;
|
| 4322 |
|
|
} Bits;
|
| 4323 |
|
|
} SCISR2STR;
|
| 4324 |
|
|
extern volatile SCISR2STR _SCISR2 @(REG_BASE + 0x000000CD);
|
| 4325 |
|
|
#define SCISR2 _SCISR2.Byte
|
| 4326 |
|
|
#define SCISR2_RAF _SCISR2.Bits.RAF
|
| 4327 |
|
|
#define SCISR2_TXDIR _SCISR2.Bits.TXDIR
|
| 4328 |
|
|
#define SCISR2_BRK13 _SCISR2.Bits.BRK13
|
| 4329 |
|
|
|
| 4330 |
|
|
|
| 4331 |
|
|
/*** SCIDRH - SCI Data Register High; 0x000000CE ***/
|
| 4332 |
|
|
typedef union {
|
| 4333 |
|
|
byte Byte;
|
| 4334 |
|
|
struct {
|
| 4335 |
|
|
byte :1;
|
| 4336 |
|
|
byte :1;
|
| 4337 |
|
|
byte :1;
|
| 4338 |
|
|
byte :1;
|
| 4339 |
|
|
byte :1;
|
| 4340 |
|
|
byte :1;
|
| 4341 |
|
|
byte T8 :1; /* Transmit Bit 8 */
|
| 4342 |
|
|
byte R8 :1; /* Received Bit 8 */
|
| 4343 |
|
|
} Bits;
|
| 4344 |
|
|
} SCIDRHSTR;
|
| 4345 |
|
|
extern volatile SCIDRHSTR _SCIDRH @(REG_BASE + 0x000000CE);
|
| 4346 |
|
|
#define SCIDRH _SCIDRH.Byte
|
| 4347 |
|
|
#define SCIDRH_T8 _SCIDRH.Bits.T8
|
| 4348 |
|
|
#define SCIDRH_R8 _SCIDRH.Bits.R8
|
| 4349 |
|
|
|
| 4350 |
|
|
|
| 4351 |
|
|
/*** SCIDRL - SCI Data Register Low; 0x000000CF ***/
|
| 4352 |
|
|
typedef union {
|
| 4353 |
|
|
byte Byte;
|
| 4354 |
|
|
struct {
|
| 4355 |
|
|
byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */
|
| 4356 |
|
|
byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */
|
| 4357 |
|
|
byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */
|
| 4358 |
|
|
byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */
|
| 4359 |
|
|
byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */
|
| 4360 |
|
|
byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */
|
| 4361 |
|
|
byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */
|
| 4362 |
|
|
byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */
|
| 4363 |
|
|
} Bits;
|
| 4364 |
|
|
} SCIDRLSTR;
|
| 4365 |
|
|
extern volatile SCIDRLSTR _SCIDRL @(REG_BASE + 0x000000CF);
|
| 4366 |
|
|
#define SCIDRL _SCIDRL.Byte
|
| 4367 |
|
|
#define SCIDRL_R0_T0 _SCIDRL.Bits.R0_T0
|
| 4368 |
|
|
#define SCIDRL_R1_T1 _SCIDRL.Bits.R1_T1
|
| 4369 |
|
|
#define SCIDRL_R2_T2 _SCIDRL.Bits.R2_T2
|
| 4370 |
|
|
#define SCIDRL_R3_T3 _SCIDRL.Bits.R3_T3
|
| 4371 |
|
|
#define SCIDRL_R4_T4 _SCIDRL.Bits.R4_T4
|
| 4372 |
|
|
#define SCIDRL_R5_T5 _SCIDRL.Bits.R5_T5
|
| 4373 |
|
|
#define SCIDRL_R6_T6 _SCIDRL.Bits.R6_T6
|
| 4374 |
|
|
#define SCIDRL_R7_T7 _SCIDRL.Bits.R7_T7
|
| 4375 |
|
|
|
| 4376 |
|
|
|
| 4377 |
|
|
/*** SPICR1 - SPI Control Register; 0x000000D8 ***/
|
| 4378 |
|
|
typedef union {
|
| 4379 |
|
|
byte Byte;
|
| 4380 |
|
|
struct {
|
| 4381 |
|
|
byte LSBFE :1; /* SPI LSB-First Enable */
|
| 4382 |
|
|
byte SSOE :1; /* Slave Select Output Enable */
|
| 4383 |
|
|
byte CPHA :1; /* SPI Clock Phase Bit */
|
| 4384 |
|
|
byte CPOL :1; /* SPI Clock Polarity Bit */
|
| 4385 |
|
|
byte MSTR :1; /* SPI Master/Slave Mode Select Bit */
|
| 4386 |
|
|
byte SPTIE :1; /* SPI Transmit Interrupt Enable */
|
| 4387 |
|
|
byte SPE :1; /* SPI System Enable Bit */
|
| 4388 |
|
|
byte SPIE :1; /* SPI Interrupt Enable Bit */
|
| 4389 |
|
|
} Bits;
|
| 4390 |
|
|
} SPICR1STR;
|
| 4391 |
|
|
extern volatile SPICR1STR _SPICR1 @(REG_BASE + 0x000000D8);
|
| 4392 |
|
|
#define SPICR1 _SPICR1.Byte
|
| 4393 |
|
|
#define SPICR1_LSBFE _SPICR1.Bits.LSBFE
|
| 4394 |
|
|
#define SPICR1_SSOE _SPICR1.Bits.SSOE
|
| 4395 |
|
|
#define SPICR1_CPHA _SPICR1.Bits.CPHA
|
| 4396 |
|
|
#define SPICR1_CPOL _SPICR1.Bits.CPOL
|
| 4397 |
|
|
#define SPICR1_MSTR _SPICR1.Bits.MSTR
|
| 4398 |
|
|
#define SPICR1_SPTIE _SPICR1.Bits.SPTIE
|
| 4399 |
|
|
#define SPICR1_SPE _SPICR1.Bits.SPE
|
| 4400 |
|
|
#define SPICR1_SPIE _SPICR1.Bits.SPIE
|
| 4401 |
|
|
|
| 4402 |
|
|
|
| 4403 |
|
|
/*** SPICR2 - SPI Control Register 2; 0x000000D9 ***/
|
| 4404 |
|
|
typedef union {
|
| 4405 |
|
|
byte Byte;
|
| 4406 |
|
|
struct {
|
| 4407 |
|
|
byte SPC0 :1; /* Serial Pin Control Bit 0 */
|
| 4408 |
|
|
byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */
|
| 4409 |
|
|
byte :1;
|
| 4410 |
|
|
byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */
|
| 4411 |
|
|
byte MODFEN :1; /* Mode Fault Enable Bit */
|
| 4412 |
|
|
byte :1;
|
| 4413 |
|
|
byte :1;
|
| 4414 |
|
|
byte :1;
|
| 4415 |
|
|
} Bits;
|
| 4416 |
|
|
} SPICR2STR;
|
| 4417 |
|
|
extern volatile SPICR2STR _SPICR2 @(REG_BASE + 0x000000D9);
|
| 4418 |
|
|
#define SPICR2 _SPICR2.Byte
|
| 4419 |
|
|
#define SPICR2_SPC0 _SPICR2.Bits.SPC0
|
| 4420 |
|
|
#define SPICR2_SPISWAI _SPICR2.Bits.SPISWAI
|
| 4421 |
|
|
#define SPICR2_BIDIROE _SPICR2.Bits.BIDIROE
|
| 4422 |
|
|
#define SPICR2_MODFEN _SPICR2.Bits.MODFEN
|
| 4423 |
|
|
|
| 4424 |
|
|
|
| 4425 |
|
|
/*** SPIBR - SPI Baud Rate Register; 0x000000DA ***/
|
| 4426 |
|
|
typedef union {
|
| 4427 |
|
|
byte Byte;
|
| 4428 |
|
|
struct {
|
| 4429 |
|
|
byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */
|
| 4430 |
|
|
byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */
|
| 4431 |
|
|
byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */
|
| 4432 |
|
|
byte :1;
|
| 4433 |
|
|
byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */
|
| 4434 |
|
|
byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */
|
| 4435 |
|
|
byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */
|
| 4436 |
|
|
byte :1;
|
| 4437 |
|
|
} Bits;
|
| 4438 |
|
|
struct {
|
| 4439 |
|
|
byte grpSPR :3;
|
| 4440 |
|
|
byte :1;
|
| 4441 |
|
|
byte grpSPPR :3;
|
| 4442 |
|
|
byte :1;
|
| 4443 |
|
|
} MergedBits;
|
| 4444 |
|
|
} SPIBRSTR;
|
| 4445 |
|
|
extern volatile SPIBRSTR _SPIBR @(REG_BASE + 0x000000DA);
|
| 4446 |
|
|
#define SPIBR _SPIBR.Byte
|
| 4447 |
|
|
#define SPIBR_SPR0 _SPIBR.Bits.SPR0
|
| 4448 |
|
|
#define SPIBR_SPR1 _SPIBR.Bits.SPR1
|
| 4449 |
|
|
#define SPIBR_SPR2 _SPIBR.Bits.SPR2
|
| 4450 |
|
|
#define SPIBR_SPPR0 _SPIBR.Bits.SPPR0
|
| 4451 |
|
|
#define SPIBR_SPPR1 _SPIBR.Bits.SPPR1
|
| 4452 |
|
|
#define SPIBR_SPPR2 _SPIBR.Bits.SPPR2
|
| 4453 |
|
|
#define SPIBR_SPR _SPIBR.MergedBits.grpSPR
|
| 4454 |
|
|
#define SPIBR_SPPR _SPIBR.MergedBits.grpSPPR
|
| 4455 |
|
|
|
| 4456 |
|
|
|
| 4457 |
|
|
/*** SPISR - SPI Status Register; 0x000000DB ***/
|
| 4458 |
|
|
typedef union {
|
| 4459 |
|
|
byte Byte;
|
| 4460 |
|
|
struct {
|
| 4461 |
|
|
byte :1;
|
| 4462 |
|
|
byte :1;
|
| 4463 |
|
|
byte :1;
|
| 4464 |
|
|
byte :1;
|
| 4465 |
|
|
byte MODF :1; /* Mode Fault Flag */
|
| 4466 |
|
|
byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */
|
| 4467 |
|
|
byte :1;
|
| 4468 |
|
|
byte SPIF :1; /* SPIF Receive Interrupt Flag */
|
| 4469 |
|
|
} Bits;
|
| 4470 |
|
|
} SPISRSTR;
|
| 4471 |
|
|
extern volatile SPISRSTR _SPISR @(REG_BASE + 0x000000DB);
|
| 4472 |
|
|
#define SPISR _SPISR.Byte
|
| 4473 |
|
|
#define SPISR_MODF _SPISR.Bits.MODF
|
| 4474 |
|
|
#define SPISR_SPTEF _SPISR.Bits.SPTEF
|
| 4475 |
|
|
#define SPISR_SPIF _SPISR.Bits.SPIF
|
| 4476 |
|
|
|
| 4477 |
|
|
|
| 4478 |
|
|
/*** SPIDR - SPI Data Register; 0x000000DD ***/
|
| 4479 |
|
|
typedef union {
|
| 4480 |
|
|
byte Byte;
|
| 4481 |
|
|
struct {
|
| 4482 |
|
|
byte grpBIT :8;
|
| 4483 |
|
|
} MergedBits;
|
| 4484 |
|
|
} SPIDRSTR;
|
| 4485 |
|
|
extern volatile SPIDRSTR _SPIDR @(REG_BASE + 0x000000DD);
|
| 4486 |
|
|
#define SPIDR _SPIDR.Byte
|
| 4487 |
|
|
#define SPIDR_BIT _SPIDR.MergedBits.grpBIT
|
| 4488 |
|
|
|
| 4489 |
|
|
|
| 4490 |
|
|
/*** PWME - PWM Enable Register; 0x000000E0 ***/
|
| 4491 |
|
|
typedef union {
|
| 4492 |
|
|
byte Byte;
|
| 4493 |
|
|
struct {
|
| 4494 |
|
|
byte PWME0 :1; /* Pulse Width Channel 0 Enable */
|
| 4495 |
|
|
byte PWME1 :1; /* Pulse Width Channel 1 Enable */
|
| 4496 |
|
|
byte PWME2 :1; /* Pulse Width Channel 2 Enable */
|
| 4497 |
|
|
byte PWME3 :1; /* Pulse Width Channel 3 Enable */
|
| 4498 |
|
|
byte PWME4 :1; /* Pulse Width Channel 4 Enable */
|
| 4499 |
|
|
byte PWME5 :1; /* Pulse Width Channel 5 Enable */
|
| 4500 |
|
|
byte PWME6 :1; /* Pulse Width Channel 6 Enable */
|
| 4501 |
|
|
byte PWME7 :1; /* Pulse Width Channel 7 Enable */
|
| 4502 |
|
|
} Bits;
|
| 4503 |
|
|
struct {
|
| 4504 |
|
|
byte grpPWME :8;
|
| 4505 |
|
|
} MergedBits;
|
| 4506 |
|
|
} PWMESTR;
|
| 4507 |
|
|
extern volatile PWMESTR _PWME @(REG_BASE + 0x000000E0);
|
| 4508 |
|
|
#define PWME _PWME.Byte
|
| 4509 |
|
|
#define PWME_PWME0 _PWME.Bits.PWME0
|
| 4510 |
|
|
#define PWME_PWME1 _PWME.Bits.PWME1
|
| 4511 |
|
|
#define PWME_PWME2 _PWME.Bits.PWME2
|
| 4512 |
|
|
#define PWME_PWME3 _PWME.Bits.PWME3
|
| 4513 |
|
|
#define PWME_PWME4 _PWME.Bits.PWME4
|
| 4514 |
|
|
#define PWME_PWME5 _PWME.Bits.PWME5
|
| 4515 |
|
|
#define PWME_PWME6 _PWME.Bits.PWME6
|
| 4516 |
|
|
#define PWME_PWME7 _PWME.Bits.PWME7
|
| 4517 |
|
|
#define PWME_PWME _PWME.MergedBits.grpPWME
|
| 4518 |
|
|
|
| 4519 |
|
|
|
| 4520 |
|
|
/*** PWMPOL - PWM Polarity Register; 0x000000E1 ***/
|
| 4521 |
|
|
typedef union {
|
| 4522 |
|
|
byte Byte;
|
| 4523 |
|
|
struct {
|
| 4524 |
|
|
byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */
|
| 4525 |
|
|
byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */
|
| 4526 |
|
|
byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */
|
| 4527 |
|
|
byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */
|
| 4528 |
|
|
byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */
|
| 4529 |
|
|
byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */
|
| 4530 |
|
|
byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */
|
| 4531 |
|
|
byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */
|
| 4532 |
|
|
} Bits;
|
| 4533 |
|
|
struct {
|
| 4534 |
|
|
byte grpPPOL :8;
|
| 4535 |
|
|
} MergedBits;
|
| 4536 |
|
|
} PWMPOLSTR;
|
| 4537 |
|
|
extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000E1);
|
| 4538 |
|
|
#define PWMPOL _PWMPOL.Byte
|
| 4539 |
|
|
#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0
|
| 4540 |
|
|
#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1
|
| 4541 |
|
|
#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2
|
| 4542 |
|
|
#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3
|
| 4543 |
|
|
#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4
|
| 4544 |
|
|
#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5
|
| 4545 |
|
|
#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6
|
| 4546 |
|
|
#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7
|
| 4547 |
|
|
#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL
|
| 4548 |
|
|
|
| 4549 |
|
|
|
| 4550 |
|
|
/*** PWMCLK - PWM Clock Select Register; 0x000000E2 ***/
|
| 4551 |
|
|
typedef union {
|
| 4552 |
|
|
byte Byte;
|
| 4553 |
|
|
struct {
|
| 4554 |
|
|
byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */
|
| 4555 |
|
|
byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */
|
| 4556 |
|
|
byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */
|
| 4557 |
|
|
byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */
|
| 4558 |
|
|
byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */
|
| 4559 |
|
|
byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */
|
| 4560 |
|
|
byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */
|
| 4561 |
|
|
byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */
|
| 4562 |
|
|
} Bits;
|
| 4563 |
|
|
struct {
|
| 4564 |
|
|
byte grpPCLK :8;
|
| 4565 |
|
|
} MergedBits;
|
| 4566 |
|
|
} PWMCLKSTR;
|
| 4567 |
|
|
extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000E2);
|
| 4568 |
|
|
#define PWMCLK _PWMCLK.Byte
|
| 4569 |
|
|
#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0
|
| 4570 |
|
|
#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1
|
| 4571 |
|
|
#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2
|
| 4572 |
|
|
#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3
|
| 4573 |
|
|
#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4
|
| 4574 |
|
|
#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5
|
| 4575 |
|
|
#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6
|
| 4576 |
|
|
#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7
|
| 4577 |
|
|
#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK
|
| 4578 |
|
|
|
| 4579 |
|
|
|
| 4580 |
|
|
/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000E3 ***/
|
| 4581 |
|
|
typedef union {
|
| 4582 |
|
|
byte Byte;
|
| 4583 |
|
|
struct {
|
| 4584 |
|
|
byte PCKA0 :1; /* Prescaler Select for Clock A 0 */
|
| 4585 |
|
|
byte PCKA1 :1; /* Prescaler Select for Clock A 1 */
|
| 4586 |
|
|
byte PCKA2 :1; /* Prescaler Select for Clock A 2 */
|
| 4587 |
|
|
byte :1;
|
| 4588 |
|
|
byte PCKB0 :1; /* Prescaler Select for Clock B 0 */
|
| 4589 |
|
|
byte PCKB1 :1; /* Prescaler Select for Clock B 1 */
|
| 4590 |
|
|
byte PCKB2 :1; /* Prescaler Select for Clock B 2 */
|
| 4591 |
|
|
byte :1;
|
| 4592 |
|
|
} Bits;
|
| 4593 |
|
|
struct {
|
| 4594 |
|
|
byte grpPCKA :3;
|
| 4595 |
|
|
byte :1;
|
| 4596 |
|
|
byte grpPCKB :3;
|
| 4597 |
|
|
byte :1;
|
| 4598 |
|
|
} MergedBits;
|
| 4599 |
|
|
} PWMPRCLKSTR;
|
| 4600 |
|
|
extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000E3);
|
| 4601 |
|
|
#define PWMPRCLK _PWMPRCLK.Byte
|
| 4602 |
|
|
#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0
|
| 4603 |
|
|
#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1
|
| 4604 |
|
|
#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2
|
| 4605 |
|
|
#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0
|
| 4606 |
|
|
#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1
|
| 4607 |
|
|
#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2
|
| 4608 |
|
|
#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA
|
| 4609 |
|
|
#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB
|
| 4610 |
|
|
|
| 4611 |
|
|
|
| 4612 |
|
|
/*** PWMCAE - PWM Center Align Enable Register; 0x000000E4 ***/
|
| 4613 |
|
|
typedef union {
|
| 4614 |
|
|
byte Byte;
|
| 4615 |
|
|
struct {
|
| 4616 |
|
|
byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */
|
| 4617 |
|
|
byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */
|
| 4618 |
|
|
byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */
|
| 4619 |
|
|
byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */
|
| 4620 |
|
|
byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */
|
| 4621 |
|
|
byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */
|
| 4622 |
|
|
byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */
|
| 4623 |
|
|
byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */
|
| 4624 |
|
|
} Bits;
|
| 4625 |
|
|
struct {
|
| 4626 |
|
|
byte grpCAE :8;
|
| 4627 |
|
|
} MergedBits;
|
| 4628 |
|
|
} PWMCAESTR;
|
| 4629 |
|
|
extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000E4);
|
| 4630 |
|
|
#define PWMCAE _PWMCAE.Byte
|
| 4631 |
|
|
#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0
|
| 4632 |
|
|
#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1
|
| 4633 |
|
|
#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2
|
| 4634 |
|
|
#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3
|
| 4635 |
|
|
#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4
|
| 4636 |
|
|
#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5
|
| 4637 |
|
|
#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6
|
| 4638 |
|
|
#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7
|
| 4639 |
|
|
#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE
|
| 4640 |
|
|
|
| 4641 |
|
|
|
| 4642 |
|
|
/*** PWMCTL - PWM Control Register; 0x000000E5 ***/
|
| 4643 |
|
|
typedef union {
|
| 4644 |
|
|
byte Byte;
|
| 4645 |
|
|
struct {
|
| 4646 |
|
|
byte :1;
|
| 4647 |
|
|
byte :1;
|
| 4648 |
|
|
byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */
|
| 4649 |
|
|
byte PSWAI :1; /* PWM Stops in Wait Mode */
|
| 4650 |
|
|
byte CON01 :1; /* Concatenate channels 0 and 1 */
|
| 4651 |
|
|
byte CON23 :1; /* Concatenate channels 2 and 3 */
|
| 4652 |
|
|
byte CON45 :1; /* Concatenate channels 4 and 5 */
|
| 4653 |
|
|
byte CON67 :1; /* Concatenate channels 6 and 7 */
|
| 4654 |
|
|
} Bits;
|
| 4655 |
|
|
} PWMCTLSTR;
|
| 4656 |
|
|
extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000E5);
|
| 4657 |
|
|
#define PWMCTL _PWMCTL.Byte
|
| 4658 |
|
|
#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ
|
| 4659 |
|
|
#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI
|
| 4660 |
|
|
#define PWMCTL_CON01 _PWMCTL.Bits.CON01
|
| 4661 |
|
|
#define PWMCTL_CON23 _PWMCTL.Bits.CON23
|
| 4662 |
|
|
#define PWMCTL_CON45 _PWMCTL.Bits.CON45
|
| 4663 |
|
|
#define PWMCTL_CON67 _PWMCTL.Bits.CON67
|
| 4664 |
|
|
|
| 4665 |
|
|
|
| 4666 |
|
|
/*** PWMSCLA - PWM Scale A Register; 0x000000E8 ***/
|
| 4667 |
|
|
typedef union {
|
| 4668 |
|
|
byte Byte;
|
| 4669 |
|
|
struct {
|
| 4670 |
|
|
byte BIT0 :1; /* PWM Scale A Bit 0 */
|
| 4671 |
|
|
byte BIT1 :1; /* PWM Scale A Bit 1 */
|
| 4672 |
|
|
byte BIT2 :1; /* PWM Scale A Bit 2 */
|
| 4673 |
|
|
byte BIT3 :1; /* PWM Scale A Bit 3 */
|
| 4674 |
|
|
byte BIT4 :1; /* PWM Scale A Bit 4 */
|
| 4675 |
|
|
byte BIT5 :1; /* PWM Scale A Bit 5 */
|
| 4676 |
|
|
byte BIT6 :1; /* PWM Scale A Bit 6 */
|
| 4677 |
|
|
byte BIT7 :1; /* PWM Scale A Bit 7 */
|
| 4678 |
|
|
} Bits;
|
| 4679 |
|
|
struct {
|
| 4680 |
|
|
byte grpBIT :8;
|
| 4681 |
|
|
} MergedBits;
|
| 4682 |
|
|
} PWMSCLASTR;
|
| 4683 |
|
|
extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000E8);
|
| 4684 |
|
|
#define PWMSCLA _PWMSCLA.Byte
|
| 4685 |
|
|
#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0
|
| 4686 |
|
|
#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1
|
| 4687 |
|
|
#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2
|
| 4688 |
|
|
#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3
|
| 4689 |
|
|
#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4
|
| 4690 |
|
|
#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5
|
| 4691 |
|
|
#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6
|
| 4692 |
|
|
#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7
|
| 4693 |
|
|
#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT
|
| 4694 |
|
|
|
| 4695 |
|
|
|
| 4696 |
|
|
/*** PWMSCLB - PWM Scale B Register; 0x000000E9 ***/
|
| 4697 |
|
|
typedef union {
|
| 4698 |
|
|
byte Byte;
|
| 4699 |
|
|
struct {
|
| 4700 |
|
|
byte BIT0 :1; /* PWM Scale B Bit 0 */
|
| 4701 |
|
|
byte BIT1 :1; /* PWM Scale B Bit 1 */
|
| 4702 |
|
|
byte BIT2 :1; /* PWM Scale B Bit 2 */
|
| 4703 |
|
|
byte BIT3 :1; /* PWM Scale B Bit 3 */
|
| 4704 |
|
|
byte BIT4 :1; /* PWM Scale B Bit 4 */
|
| 4705 |
|
|
byte BIT5 :1; /* PWM Scale B Bit 5 */
|
| 4706 |
|
|
byte BIT6 :1; /* PWM Scale B Bit 6 */
|
| 4707 |
|
|
byte BIT7 :1; /* PWM Scale B Bit 7 */
|
| 4708 |
|
|
} Bits;
|
| 4709 |
|
|
struct {
|
| 4710 |
|
|
byte grpBIT :8;
|
| 4711 |
|
|
} MergedBits;
|
| 4712 |
|
|
} PWMSCLBSTR;
|
| 4713 |
|
|
extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000E9);
|
| 4714 |
|
|
#define PWMSCLB _PWMSCLB.Byte
|
| 4715 |
|
|
#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0
|
| 4716 |
|
|
#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1
|
| 4717 |
|
|
#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2
|
| 4718 |
|
|
#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3
|
| 4719 |
|
|
#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4
|
| 4720 |
|
|
#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5
|
| 4721 |
|
|
#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6
|
| 4722 |
|
|
#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7
|
| 4723 |
|
|
#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT
|
| 4724 |
|
|
|
| 4725 |
|
|
|
| 4726 |
|
|
/*** PWMSDN - PWM Shutdown Register; 0x000000FE ***/
|
| 4727 |
|
|
typedef union {
|
| 4728 |
|
|
byte Byte;
|
| 4729 |
|
|
struct {
|
| 4730 |
|
|
byte PWM7ENA :1; /* PWM emergency shutdown Enable */
|
| 4731 |
|
|
byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */
|
| 4732 |
|
|
byte PWM7IN :1; /* PWM channel 7 input status */
|
| 4733 |
|
|
byte :1;
|
| 4734 |
|
|
byte PWMLVL :1; /* PWM shutdown output Level */
|
| 4735 |
|
|
byte PWMRSTRT :1; /* PWM Restart */
|
| 4736 |
|
|
byte PWMIE :1; /* PWM Interrupt Enable */
|
| 4737 |
|
|
byte PWMIF :1; /* PWM Interrupt Flag */
|
| 4738 |
|
|
} Bits;
|
| 4739 |
|
|
} PWMSDNSTR;
|
| 4740 |
|
|
extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000FE);
|
| 4741 |
|
|
#define PWMSDN _PWMSDN.Byte
|
| 4742 |
|
|
#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA
|
| 4743 |
|
|
#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL
|
| 4744 |
|
|
#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN
|
| 4745 |
|
|
#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL
|
| 4746 |
|
|
#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT
|
| 4747 |
|
|
#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE
|
| 4748 |
|
|
#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF
|
| 4749 |
|
|
|
| 4750 |
|
|
|
| 4751 |
|
|
/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/
|
| 4752 |
|
|
typedef union {
|
| 4753 |
|
|
byte Byte;
|
| 4754 |
|
|
struct {
|
| 4755 |
|
|
byte FDIV0 :1; /* Flash Clock Divider Bit 0 */
|
| 4756 |
|
|
byte FDIV1 :1; /* Flash Clock Divider Bit 1 */
|
| 4757 |
|
|
byte FDIV2 :1; /* Flash Clock Divider Bit 2 */
|
| 4758 |
|
|
byte FDIV3 :1; /* Flash Clock Divider Bit 3 */
|
| 4759 |
|
|
byte FDIV4 :1; /* Flash Clock Divider Bit 4 */
|
| 4760 |
|
|
byte FDIV5 :1; /* Flash Clock Divider Bit 5 */
|
| 4761 |
|
|
byte PRDIV8 :1; /* Enable Prescaler by 8 */
|
| 4762 |
|
|
byte FDIVLD :1; /* Flash Clock Divider Loaded */
|
| 4763 |
|
|
} Bits;
|
| 4764 |
|
|
struct {
|
| 4765 |
|
|
byte grpFDIV :6;
|
| 4766 |
|
|
byte grpPRDIV_8 :1;
|
| 4767 |
|
|
byte :1;
|
| 4768 |
|
|
} MergedBits;
|
| 4769 |
|
|
} FCLKDIVSTR;
|
| 4770 |
|
|
extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100);
|
| 4771 |
|
|
#define FCLKDIV _FCLKDIV.Byte
|
| 4772 |
|
|
#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0
|
| 4773 |
|
|
#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1
|
| 4774 |
|
|
#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2
|
| 4775 |
|
|
#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3
|
| 4776 |
|
|
#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4
|
| 4777 |
|
|
#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5
|
| 4778 |
|
|
#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8
|
| 4779 |
|
|
#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD
|
| 4780 |
|
|
#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV
|
| 4781 |
|
|
|
| 4782 |
|
|
|
| 4783 |
|
|
/*** FSEC - Flash Security Register; 0x00000101 ***/
|
| 4784 |
|
|
typedef union {
|
| 4785 |
|
|
byte Byte;
|
| 4786 |
|
|
struct {
|
| 4787 |
|
|
byte SEC0 :1; /* Memory security bit 0 */
|
| 4788 |
|
|
byte SEC1 :1; /* Memory security bit 1 */
|
| 4789 |
|
|
byte NV2 :1; /* Non Volatile flag bit 2 */
|
| 4790 |
|
|
byte NV3 :1; /* Non Volatile flag bit 3 */
|
| 4791 |
|
|
byte NV4 :1; /* Non Volatile flag bit 4 */
|
| 4792 |
|
|
byte NV5 :1; /* Non Volatile flag bit 5 */
|
| 4793 |
|
|
byte NV6 :1; /* Non Volatile flag bit 6 */
|
| 4794 |
|
|
byte KEYEN :1; /* Enable backdoor key to security */
|
| 4795 |
|
|
} Bits;
|
| 4796 |
|
|
struct {
|
| 4797 |
|
|
byte grpSEC :2;
|
| 4798 |
|
|
byte grpNV_2 :5;
|
| 4799 |
|
|
byte :1;
|
| 4800 |
|
|
} MergedBits;
|
| 4801 |
|
|
} FSECSTR;
|
| 4802 |
|
|
extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101);
|
| 4803 |
|
|
#define FSEC _FSEC.Byte
|
| 4804 |
|
|
#define FSEC_SEC0 _FSEC.Bits.SEC0
|
| 4805 |
|
|
#define FSEC_SEC1 _FSEC.Bits.SEC1
|
| 4806 |
|
|
#define FSEC_NV2 _FSEC.Bits.NV2
|
| 4807 |
|
|
#define FSEC_NV3 _FSEC.Bits.NV3
|
| 4808 |
|
|
#define FSEC_NV4 _FSEC.Bits.NV4
|
| 4809 |
|
|
#define FSEC_NV5 _FSEC.Bits.NV5
|
| 4810 |
|
|
#define FSEC_NV6 _FSEC.Bits.NV6
|
| 4811 |
|
|
#define FSEC_KEYEN _FSEC.Bits.KEYEN
|
| 4812 |
|
|
#define FSEC_SEC _FSEC.MergedBits.grpSEC
|
| 4813 |
|
|
#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2
|
| 4814 |
|
|
#define FSEC_NV FSEC_NV_2
|
| 4815 |
|
|
|
| 4816 |
|
|
|
| 4817 |
|
|
/*** FCNFG - Flash Configuration Register; 0x00000103 ***/
|
| 4818 |
|
|
typedef union {
|
| 4819 |
|
|
byte Byte;
|
| 4820 |
|
|
struct {
|
| 4821 |
|
|
byte BKSEL0 :1; /* Register bank select 0 */
|
| 4822 |
|
|
byte BKSEL1 :1; /* Register bank select 1 */
|
| 4823 |
|
|
byte :1;
|
| 4824 |
|
|
byte :1;
|
| 4825 |
|
|
byte :1;
|
| 4826 |
|
|
byte KEYACC :1; /* Enable Security Key Writing */
|
| 4827 |
|
|
byte CCIE :1; /* Command Complete Interrupt Enable */
|
| 4828 |
|
|
byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */
|
| 4829 |
|
|
} Bits;
|
| 4830 |
|
|
struct {
|
| 4831 |
|
|
byte grpBKSEL :2;
|
| 4832 |
|
|
byte :1;
|
| 4833 |
|
|
byte :1;
|
| 4834 |
|
|
byte :1;
|
| 4835 |
|
|
byte :1;
|
| 4836 |
|
|
byte :1;
|
| 4837 |
|
|
byte :1;
|
| 4838 |
|
|
} MergedBits;
|
| 4839 |
|
|
} FCNFGSTR;
|
| 4840 |
|
|
extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103);
|
| 4841 |
|
|
#define FCNFG _FCNFG.Byte
|
| 4842 |
|
|
#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0
|
| 4843 |
|
|
#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1
|
| 4844 |
|
|
#define FCNFG_KEYACC _FCNFG.Bits.KEYACC
|
| 4845 |
|
|
#define FCNFG_CCIE _FCNFG.Bits.CCIE
|
| 4846 |
|
|
#define FCNFG_CBEIE _FCNFG.Bits.CBEIE
|
| 4847 |
|
|
#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL
|
| 4848 |
|
|
|
| 4849 |
|
|
|
| 4850 |
|
|
/*** FPROT - Flash Protection Register; 0x00000104 ***/
|
| 4851 |
|
|
typedef union {
|
| 4852 |
|
|
byte Byte;
|
| 4853 |
|
|
struct {
|
| 4854 |
|
|
byte FPLS0 :1; /* Flash Protection Lower Address size 0 */
|
| 4855 |
|
|
byte FPLS1 :1; /* Flash Protection Lower Address size 1 */
|
| 4856 |
|
|
byte FPLDIS :1; /* Flash Protection Lower address range disable */
|
| 4857 |
|
|
byte FPHS0 :1; /* Flash Protection Higher address size 0 */
|
| 4858 |
|
|
byte FPHS1 :1; /* Flash Protection Higher address size 1 */
|
| 4859 |
|
|
byte FPHDIS :1; /* Flash Protection Higher address range disable */
|
| 4860 |
|
|
byte NV6 :1; /* Non Volatile Flag Bit */
|
| 4861 |
|
|
byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */
|
| 4862 |
|
|
} Bits;
|
| 4863 |
|
|
struct {
|
| 4864 |
|
|
byte grpFPLS :2;
|
| 4865 |
|
|
byte :1;
|
| 4866 |
|
|
byte grpFPHS :2;
|
| 4867 |
|
|
byte :1;
|
| 4868 |
|
|
byte grpNV_6 :1;
|
| 4869 |
|
|
byte :1;
|
| 4870 |
|
|
} MergedBits;
|
| 4871 |
|
|
} FPROTSTR;
|
| 4872 |
|
|
extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104);
|
| 4873 |
|
|
#define FPROT _FPROT.Byte
|
| 4874 |
|
|
#define FPROT_FPLS0 _FPROT.Bits.FPLS0
|
| 4875 |
|
|
#define FPROT_FPLS1 _FPROT.Bits.FPLS1
|
| 4876 |
|
|
#define FPROT_FPLDIS _FPROT.Bits.FPLDIS
|
| 4877 |
|
|
#define FPROT_FPHS0 _FPROT.Bits.FPHS0
|
| 4878 |
|
|
#define FPROT_FPHS1 _FPROT.Bits.FPHS1
|
| 4879 |
|
|
#define FPROT_FPHDIS _FPROT.Bits.FPHDIS
|
| 4880 |
|
|
#define FPROT_NV6 _FPROT.Bits.NV6
|
| 4881 |
|
|
#define FPROT_FPOPEN _FPROT.Bits.FPOPEN
|
| 4882 |
|
|
#define FPROT_FPLS _FPROT.MergedBits.grpFPLS
|
| 4883 |
|
|
#define FPROT_FPHS _FPROT.MergedBits.grpFPHS
|
| 4884 |
|
|
|
| 4885 |
|
|
|
| 4886 |
|
|
/*** FSTAT - Flash Status Register; 0x00000105 ***/
|
| 4887 |
|
|
typedef union {
|
| 4888 |
|
|
byte Byte;
|
| 4889 |
|
|
struct {
|
| 4890 |
|
|
byte :1;
|
| 4891 |
|
|
byte :1;
|
| 4892 |
|
|
byte BLANK :1; /* Blank Verify Flag */
|
| 4893 |
|
|
byte :1;
|
| 4894 |
|
|
byte ACCERR :1; /* Access error */
|
| 4895 |
|
|
byte PVIOL :1; /* Protection violation */
|
| 4896 |
|
|
byte CCIF :1; /* Command Complete Interrupt Flag */
|
| 4897 |
|
|
byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */
|
| 4898 |
|
|
} Bits;
|
| 4899 |
|
|
} FSTATSTR;
|
| 4900 |
|
|
extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105);
|
| 4901 |
|
|
#define FSTAT _FSTAT.Byte
|
| 4902 |
|
|
#define FSTAT_BLANK _FSTAT.Bits.BLANK
|
| 4903 |
|
|
#define FSTAT_ACCERR _FSTAT.Bits.ACCERR
|
| 4904 |
|
|
#define FSTAT_PVIOL _FSTAT.Bits.PVIOL
|
| 4905 |
|
|
#define FSTAT_CCIF _FSTAT.Bits.CCIF
|
| 4906 |
|
|
#define FSTAT_CBEIF _FSTAT.Bits.CBEIF
|
| 4907 |
|
|
|
| 4908 |
|
|
|
| 4909 |
|
|
/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/
|
| 4910 |
|
|
typedef union {
|
| 4911 |
|
|
byte Byte;
|
| 4912 |
|
|
struct {
|
| 4913 |
|
|
byte CMDB0 :1; /* NVM User Mode Command Bit 0 */
|
| 4914 |
|
|
byte :1;
|
| 4915 |
|
|
byte CMDB2 :1; /* NVM User Mode Command Bit 2 */
|
| 4916 |
|
|
byte :1;
|
| 4917 |
|
|
byte :1;
|
| 4918 |
|
|
byte CMDB5 :1; /* NVM User Mode Command Bit 5 */
|
| 4919 |
|
|
byte CMDB6 :1; /* NVM User Mode Command Bit 6 */
|
| 4920 |
|
|
byte :1;
|
| 4921 |
|
|
} Bits;
|
| 4922 |
|
|
struct {
|
| 4923 |
|
|
byte grpCMDB :1;
|
| 4924 |
|
|
byte :1;
|
| 4925 |
|
|
byte grpCMDB_2 :1;
|
| 4926 |
|
|
byte :1;
|
| 4927 |
|
|
byte :1;
|
| 4928 |
|
|
byte grpCMDB_5 :2;
|
| 4929 |
|
|
byte :1;
|
| 4930 |
|
|
} MergedBits;
|
| 4931 |
|
|
} FCMDSTR;
|
| 4932 |
|
|
extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106);
|
| 4933 |
|
|
#define FCMD _FCMD.Byte
|
| 4934 |
|
|
#define FCMD_CMDB0 _FCMD.Bits.CMDB0
|
| 4935 |
|
|
#define FCMD_CMDB2 _FCMD.Bits.CMDB2
|
| 4936 |
|
|
#define FCMD_CMDB5 _FCMD.Bits.CMDB5
|
| 4937 |
|
|
#define FCMD_CMDB6 _FCMD.Bits.CMDB6
|
| 4938 |
|
|
#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5
|
| 4939 |
|
|
#define FCMD_CMDB FCMD_CMDB_5
|
| 4940 |
|
|
|
| 4941 |
|
|
|
| 4942 |
|
|
/*** CANCTL0 - MSCAN Control 0 Register; 0x00000140 ***/
|
| 4943 |
|
|
typedef union {
|
| 4944 |
|
|
byte Byte;
|
| 4945 |
|
|
struct {
|
| 4946 |
|
|
byte INITRQ :1; /* Initialization Mode Request */
|
| 4947 |
|
|
byte SLPRQ :1; /* Sleep Mode Request */
|
| 4948 |
|
|
byte WUPE :1; /* Wake-Up Enable */
|
| 4949 |
|
|
byte TIME :1; /* Timer Enable */
|
| 4950 |
|
|
byte SYNCH :1; /* Synchronized Status */
|
| 4951 |
|
|
byte CSWAI :1; /* CAN Stops in Wait Mode */
|
| 4952 |
|
|
byte RXACT :1; /* Receiver Active Status */
|
| 4953 |
|
|
byte RXFRM :1; /* Received Frame Flag */
|
| 4954 |
|
|
} Bits;
|
| 4955 |
|
|
} CANCTL0STR;
|
| 4956 |
|
|
extern volatile CANCTL0STR _CANCTL0 @(REG_BASE + 0x00000140);
|
| 4957 |
|
|
#define CANCTL0 _CANCTL0.Byte
|
| 4958 |
|
|
#define CANCTL0_INITRQ _CANCTL0.Bits.INITRQ
|
| 4959 |
|
|
#define CANCTL0_SLPRQ _CANCTL0.Bits.SLPRQ
|
| 4960 |
|
|
#define CANCTL0_WUPE _CANCTL0.Bits.WUPE
|
| 4961 |
|
|
#define CANCTL0_TIME _CANCTL0.Bits.TIME
|
| 4962 |
|
|
#define CANCTL0_SYNCH _CANCTL0.Bits.SYNCH
|
| 4963 |
|
|
#define CANCTL0_CSWAI _CANCTL0.Bits.CSWAI
|
| 4964 |
|
|
#define CANCTL0_RXACT _CANCTL0.Bits.RXACT
|
| 4965 |
|
|
#define CANCTL0_RXFRM _CANCTL0.Bits.RXFRM
|
| 4966 |
|
|
|
| 4967 |
|
|
|
| 4968 |
|
|
/*** CANCTL1 - MSCAN Control 1 Register; 0x00000141 ***/
|
| 4969 |
|
|
typedef union {
|
| 4970 |
|
|
byte Byte;
|
| 4971 |
|
|
struct {
|
| 4972 |
|
|
byte INITAK :1; /* Initialization Mode Acknowledge */
|
| 4973 |
|
|
byte SLPAK :1; /* Sleep Mode Acknowledge */
|
| 4974 |
|
|
byte WUPM :1; /* Wake-Up Mode */
|
| 4975 |
|
|
byte :1;
|
| 4976 |
|
|
byte LISTEN :1; /* Listen Only Mode */
|
| 4977 |
|
|
byte LOOPB :1; /* Loop Back Self Test Mode */
|
| 4978 |
|
|
byte CLKSRC :1; /* MSCAN Clock Source */
|
| 4979 |
|
|
byte CANE :1; /* MSCAN Enable */
|
| 4980 |
|
|
} Bits;
|
| 4981 |
|
|
} CANCTL1STR;
|
| 4982 |
|
|
extern volatile CANCTL1STR _CANCTL1 @(REG_BASE + 0x00000141);
|
| 4983 |
|
|
#define CANCTL1 _CANCTL1.Byte
|
| 4984 |
|
|
#define CANCTL1_INITAK _CANCTL1.Bits.INITAK
|
| 4985 |
|
|
#define CANCTL1_SLPAK _CANCTL1.Bits.SLPAK
|
| 4986 |
|
|
#define CANCTL1_WUPM _CANCTL1.Bits.WUPM
|
| 4987 |
|
|
#define CANCTL1_LISTEN _CANCTL1.Bits.LISTEN
|
| 4988 |
|
|
#define CANCTL1_LOOPB _CANCTL1.Bits.LOOPB
|
| 4989 |
|
|
#define CANCTL1_CLKSRC _CANCTL1.Bits.CLKSRC
|
| 4990 |
|
|
#define CANCTL1_CANE _CANCTL1.Bits.CANE
|
| 4991 |
|
|
|
| 4992 |
|
|
|
| 4993 |
|
|
/*** CANBTR0 - MSCAN Bus Timing Register 0; 0x00000142 ***/
|
| 4994 |
|
|
typedef union {
|
| 4995 |
|
|
byte Byte;
|
| 4996 |
|
|
struct {
|
| 4997 |
|
|
byte BRP0 :1; /* Baud Rate Prescaler 0 */
|
| 4998 |
|
|
byte BRP1 :1; /* Baud Rate Prescaler 1 */
|
| 4999 |
|
|
byte BRP2 :1; /* Baud Rate Prescaler 2 */
|
| 5000 |
|
|
byte BRP3 :1; /* Baud Rate Prescaler 3 */
|
| 5001 |
|
|
byte BRP4 :1; /* Baud Rate Prescaler 4 */
|
| 5002 |
|
|
byte BRP5 :1; /* Baud Rate Prescaler 5 */
|
| 5003 |
|
|
byte SJW0 :1; /* Synchronization Jump Width 0 */
|
| 5004 |
|
|
byte SJW1 :1; /* Synchronization Jump Width 1 */
|
| 5005 |
|
|
} Bits;
|
| 5006 |
|
|
struct {
|
| 5007 |
|
|
byte grpBRP :6;
|
| 5008 |
|
|
byte grpSJW :2;
|
| 5009 |
|
|
} MergedBits;
|
| 5010 |
|
|
} CANBTR0STR;
|
| 5011 |
|
|
extern volatile CANBTR0STR _CANBTR0 @(REG_BASE + 0x00000142);
|
| 5012 |
|
|
#define CANBTR0 _CANBTR0.Byte
|
| 5013 |
|
|
#define CANBTR0_BRP0 _CANBTR0.Bits.BRP0
|
| 5014 |
|
|
#define CANBTR0_BRP1 _CANBTR0.Bits.BRP1
|
| 5015 |
|
|
#define CANBTR0_BRP2 _CANBTR0.Bits.BRP2
|
| 5016 |
|
|
#define CANBTR0_BRP3 _CANBTR0.Bits.BRP3
|
| 5017 |
|
|
#define CANBTR0_BRP4 _CANBTR0.Bits.BRP4
|
| 5018 |
|
|
#define CANBTR0_BRP5 _CANBTR0.Bits.BRP5
|
| 5019 |
|
|
#define CANBTR0_SJW0 _CANBTR0.Bits.SJW0
|
| 5020 |
|
|
#define CANBTR0_SJW1 _CANBTR0.Bits.SJW1
|
| 5021 |
|
|
#define CANBTR0_BRP _CANBTR0.MergedBits.grpBRP
|
| 5022 |
|
|
#define CANBTR0_SJW _CANBTR0.MergedBits.grpSJW
|
| 5023 |
|
|
|
| 5024 |
|
|
|
| 5025 |
|
|
/*** CANBTR1 - MSCAN Bus Timing Register 1; 0x00000143 ***/
|
| 5026 |
|
|
typedef union {
|
| 5027 |
|
|
byte Byte;
|
| 5028 |
|
|
struct {
|
| 5029 |
|
|
byte TSEG10 :1; /* Time Segment 1 */
|
| 5030 |
|
|
byte TSEG11 :1; /* Time Segment 1 */
|
| 5031 |
|
|
byte TSEG12 :1; /* Time Segment 1 */
|
| 5032 |
|
|
byte TSEG13 :1; /* Time Segment 1 */
|
| 5033 |
|
|
byte TSEG20 :1; /* Time Segment 2 */
|
| 5034 |
|
|
byte TSEG21 :1; /* Time Segment 2 */
|
| 5035 |
|
|
byte TSEG22 :1; /* Time Segment 2 */
|
| 5036 |
|
|
byte SAMP :1; /* Sampling */
|
| 5037 |
|
|
} Bits;
|
| 5038 |
|
|
struct {
|
| 5039 |
|
|
byte grpTSEG_10 :4;
|
| 5040 |
|
|
byte grpTSEG_20 :3;
|
| 5041 |
|
|
byte :1;
|
| 5042 |
|
|
} MergedBits;
|
| 5043 |
|
|
} CANBTR1STR;
|
| 5044 |
|
|
extern volatile CANBTR1STR _CANBTR1 @(REG_BASE + 0x00000143);
|
| 5045 |
|
|
#define CANBTR1 _CANBTR1.Byte
|
| 5046 |
|
|
#define CANBTR1_TSEG10 _CANBTR1.Bits.TSEG10
|
| 5047 |
|
|
#define CANBTR1_TSEG11 _CANBTR1.Bits.TSEG11
|
| 5048 |
|
|
#define CANBTR1_TSEG12 _CANBTR1.Bits.TSEG12
|
| 5049 |
|
|
#define CANBTR1_TSEG13 _CANBTR1.Bits.TSEG13
|
| 5050 |
|
|
#define CANBTR1_TSEG20 _CANBTR1.Bits.TSEG20
|
| 5051 |
|
|
#define CANBTR1_TSEG21 _CANBTR1.Bits.TSEG21
|
| 5052 |
|
|
#define CANBTR1_TSEG22 _CANBTR1.Bits.TSEG22
|
| 5053 |
|
|
#define CANBTR1_SAMP _CANBTR1.Bits.SAMP
|
| 5054 |
|
|
#define CANBTR1_TSEG_10 _CANBTR1.MergedBits.grpTSEG_10
|
| 5055 |
|
|
#define CANBTR1_TSEG_20 _CANBTR1.MergedBits.grpTSEG_20
|
| 5056 |
|
|
#define CANBTR1_TSEG CANBTR1_TSEG_10
|
| 5057 |
|
|
|
| 5058 |
|
|
|
| 5059 |
|
|
/*** CANRFLG - MSCAN Receiver Flag Register; 0x00000144 ***/
|
| 5060 |
|
|
typedef union {
|
| 5061 |
|
|
byte Byte;
|
| 5062 |
|
|
struct {
|
| 5063 |
|
|
byte RXF :1; /* Receive Buffer Full */
|
| 5064 |
|
|
byte OVRIF :1; /* Overrun Interrupt Flag */
|
| 5065 |
|
|
byte TSTAT0 :1; /* Transmitter Status Bit 0 */
|
| 5066 |
|
|
byte TSTAT1 :1; /* Transmitter Status Bit 1 */
|
| 5067 |
|
|
byte RSTAT0 :1; /* Receiver Status Bit 0 */
|
| 5068 |
|
|
byte RSTAT1 :1; /* Receiver Status Bit 1 */
|
| 5069 |
|
|
byte CSCIF :1; /* CAN Status Change Interrupt Flag */
|
| 5070 |
|
|
byte WUPIF :1; /* Wake-up Interrupt Flag */
|
| 5071 |
|
|
} Bits;
|
| 5072 |
|
|
struct {
|
| 5073 |
|
|
byte :1;
|
| 5074 |
|
|
byte :1;
|
| 5075 |
|
|
byte grpTSTAT :2;
|
| 5076 |
|
|
byte grpRSTAT :2;
|
| 5077 |
|
|
byte :1;
|
| 5078 |
|
|
byte :1;
|
| 5079 |
|
|
} MergedBits;
|
| 5080 |
|
|
} CANRFLGSTR;
|
| 5081 |
|
|
extern volatile CANRFLGSTR _CANRFLG @(REG_BASE + 0x00000144);
|
| 5082 |
|
|
#define CANRFLG _CANRFLG.Byte
|
| 5083 |
|
|
#define CANRFLG_RXF _CANRFLG.Bits.RXF
|
| 5084 |
|
|
#define CANRFLG_OVRIF _CANRFLG.Bits.OVRIF
|
| 5085 |
|
|
#define CANRFLG_TSTAT0 _CANRFLG.Bits.TSTAT0
|
| 5086 |
|
|
#define CANRFLG_TSTAT1 _CANRFLG.Bits.TSTAT1
|
| 5087 |
|
|
#define CANRFLG_RSTAT0 _CANRFLG.Bits.RSTAT0
|
| 5088 |
|
|
#define CANRFLG_RSTAT1 _CANRFLG.Bits.RSTAT1
|
| 5089 |
|
|
#define CANRFLG_CSCIF _CANRFLG.Bits.CSCIF
|
| 5090 |
|
|
#define CANRFLG_WUPIF _CANRFLG.Bits.WUPIF
|
| 5091 |
|
|
#define CANRFLG_TSTAT _CANRFLG.MergedBits.grpTSTAT
|
| 5092 |
|
|
#define CANRFLG_RSTAT _CANRFLG.MergedBits.grpRSTAT
|
| 5093 |
|
|
|
| 5094 |
|
|
|
| 5095 |
|
|
/*** CANRIER - MSCAN Receiver Interrupt Enable Register; 0x00000145 ***/
|
| 5096 |
|
|
typedef union {
|
| 5097 |
|
|
byte Byte;
|
| 5098 |
|
|
struct {
|
| 5099 |
|
|
byte RXFIE :1; /* Receiver Full Interrupt Enable */
|
| 5100 |
|
|
byte OVRIE :1; /* Overrun Interrupt Enable */
|
| 5101 |
|
|
byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
|
| 5102 |
|
|
byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
|
| 5103 |
|
|
byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
|
| 5104 |
|
|
byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
|
| 5105 |
|
|
byte CSCIE :1; /* CAN Status Change Interrupt Enable */
|
| 5106 |
|
|
byte WUPIE :1; /* Wake-up Interrupt Enable */
|
| 5107 |
|
|
} Bits;
|
| 5108 |
|
|
struct {
|
| 5109 |
|
|
byte :1;
|
| 5110 |
|
|
byte :1;
|
| 5111 |
|
|
byte grpTSTATE :2;
|
| 5112 |
|
|
byte grpRSTATE :2;
|
| 5113 |
|
|
byte :1;
|
| 5114 |
|
|
byte :1;
|
| 5115 |
|
|
} MergedBits;
|
| 5116 |
|
|
} CANRIERSTR;
|
| 5117 |
|
|
extern volatile CANRIERSTR _CANRIER @(REG_BASE + 0x00000145);
|
| 5118 |
|
|
#define CANRIER _CANRIER.Byte
|
| 5119 |
|
|
#define CANRIER_RXFIE _CANRIER.Bits.RXFIE
|
| 5120 |
|
|
#define CANRIER_OVRIE _CANRIER.Bits.OVRIE
|
| 5121 |
|
|
#define CANRIER_TSTATE0 _CANRIER.Bits.TSTATE0
|
| 5122 |
|
|
#define CANRIER_TSTATE1 _CANRIER.Bits.TSTATE1
|
| 5123 |
|
|
#define CANRIER_RSTATE0 _CANRIER.Bits.RSTATE0
|
| 5124 |
|
|
#define CANRIER_RSTATE1 _CANRIER.Bits.RSTATE1
|
| 5125 |
|
|
#define CANRIER_CSCIE _CANRIER.Bits.CSCIE
|
| 5126 |
|
|
#define CANRIER_WUPIE _CANRIER.Bits.WUPIE
|
| 5127 |
|
|
#define CANRIER_TSTATE _CANRIER.MergedBits.grpTSTATE
|
| 5128 |
|
|
#define CANRIER_RSTATE _CANRIER.MergedBits.grpRSTATE
|
| 5129 |
|
|
|
| 5130 |
|
|
|
| 5131 |
|
|
/*** CANTFLG - MSCAN Transmitter Flag Register; 0x00000146 ***/
|
| 5132 |
|
|
typedef union {
|
| 5133 |
|
|
byte Byte;
|
| 5134 |
|
|
struct {
|
| 5135 |
|
|
byte TXE0 :1; /* Transmitter Buffer Empty 0 */
|
| 5136 |
|
|
byte TXE1 :1; /* Transmitter Buffer Empty 1 */
|
| 5137 |
|
|
byte TXE2 :1; /* Transmitter Buffer Empty 2 */
|
| 5138 |
|
|
byte :1;
|
| 5139 |
|
|
byte :1;
|
| 5140 |
|
|
byte :1;
|
| 5141 |
|
|
byte :1;
|
| 5142 |
|
|
byte :1;
|
| 5143 |
|
|
} Bits;
|
| 5144 |
|
|
struct {
|
| 5145 |
|
|
byte grpTXE :3;
|
| 5146 |
|
|
byte :1;
|
| 5147 |
|
|
byte :1;
|
| 5148 |
|
|
byte :1;
|
| 5149 |
|
|
byte :1;
|
| 5150 |
|
|
byte :1;
|
| 5151 |
|
|
} MergedBits;
|
| 5152 |
|
|
} CANTFLGSTR;
|
| 5153 |
|
|
extern volatile CANTFLGSTR _CANTFLG @(REG_BASE + 0x00000146);
|
| 5154 |
|
|
#define CANTFLG _CANTFLG.Byte
|
| 5155 |
|
|
#define CANTFLG_TXE0 _CANTFLG.Bits.TXE0
|
| 5156 |
|
|
#define CANTFLG_TXE1 _CANTFLG.Bits.TXE1
|
| 5157 |
|
|
#define CANTFLG_TXE2 _CANTFLG.Bits.TXE2
|
| 5158 |
|
|
#define CANTFLG_TXE _CANTFLG.MergedBits.grpTXE
|
| 5159 |
|
|
|
| 5160 |
|
|
|
| 5161 |
|
|
/*** CANTIER - MSCAN Transmitter Interrupt Enable Register; 0x00000147 ***/
|
| 5162 |
|
|
typedef union {
|
| 5163 |
|
|
byte Byte;
|
| 5164 |
|
|
struct {
|
| 5165 |
|
|
byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
|
| 5166 |
|
|
byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
|
| 5167 |
|
|
byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
|
| 5168 |
|
|
byte :1;
|
| 5169 |
|
|
byte :1;
|
| 5170 |
|
|
byte :1;
|
| 5171 |
|
|
byte :1;
|
| 5172 |
|
|
byte :1;
|
| 5173 |
|
|
} Bits;
|
| 5174 |
|
|
struct {
|
| 5175 |
|
|
byte grpTXEIE :3;
|
| 5176 |
|
|
byte :1;
|
| 5177 |
|
|
byte :1;
|
| 5178 |
|
|
byte :1;
|
| 5179 |
|
|
byte :1;
|
| 5180 |
|
|
byte :1;
|
| 5181 |
|
|
} MergedBits;
|
| 5182 |
|
|
} CANTIERSTR;
|
| 5183 |
|
|
extern volatile CANTIERSTR _CANTIER @(REG_BASE + 0x00000147);
|
| 5184 |
|
|
#define CANTIER _CANTIER.Byte
|
| 5185 |
|
|
#define CANTIER_TXEIE0 _CANTIER.Bits.TXEIE0
|
| 5186 |
|
|
#define CANTIER_TXEIE1 _CANTIER.Bits.TXEIE1
|
| 5187 |
|
|
#define CANTIER_TXEIE2 _CANTIER.Bits.TXEIE2
|
| 5188 |
|
|
#define CANTIER_TXEIE _CANTIER.MergedBits.grpTXEIE
|
| 5189 |
|
|
|
| 5190 |
|
|
|
| 5191 |
|
|
/*** CANTARQ - MSCAN Transmitter Message Abort Request; 0x00000148 ***/
|
| 5192 |
|
|
typedef union {
|
| 5193 |
|
|
byte Byte;
|
| 5194 |
|
|
struct {
|
| 5195 |
|
|
byte ABTRQ0 :1; /* Abort Request 0 */
|
| 5196 |
|
|
byte ABTRQ1 :1; /* Abort Request 1 */
|
| 5197 |
|
|
byte ABTRQ2 :1; /* Abort Request 2 */
|
| 5198 |
|
|
byte :1;
|
| 5199 |
|
|
byte :1;
|
| 5200 |
|
|
byte :1;
|
| 5201 |
|
|
byte :1;
|
| 5202 |
|
|
byte :1;
|
| 5203 |
|
|
} Bits;
|
| 5204 |
|
|
struct {
|
| 5205 |
|
|
byte grpABTRQ :3;
|
| 5206 |
|
|
byte :1;
|
| 5207 |
|
|
byte :1;
|
| 5208 |
|
|
byte :1;
|
| 5209 |
|
|
byte :1;
|
| 5210 |
|
|
byte :1;
|
| 5211 |
|
|
} MergedBits;
|
| 5212 |
|
|
} CANTARQSTR;
|
| 5213 |
|
|
extern volatile CANTARQSTR _CANTARQ @(REG_BASE + 0x00000148);
|
| 5214 |
|
|
#define CANTARQ _CANTARQ.Byte
|
| 5215 |
|
|
#define CANTARQ_ABTRQ0 _CANTARQ.Bits.ABTRQ0
|
| 5216 |
|
|
#define CANTARQ_ABTRQ1 _CANTARQ.Bits.ABTRQ1
|
| 5217 |
|
|
#define CANTARQ_ABTRQ2 _CANTARQ.Bits.ABTRQ2
|
| 5218 |
|
|
#define CANTARQ_ABTRQ _CANTARQ.MergedBits.grpABTRQ
|
| 5219 |
|
|
|
| 5220 |
|
|
|
| 5221 |
|
|
/*** CANTAAK - MSCAN Transmitter Message Abort Control; 0x00000149 ***/
|
| 5222 |
|
|
typedef union {
|
| 5223 |
|
|
byte Byte;
|
| 5224 |
|
|
struct {
|
| 5225 |
|
|
byte ABTAK0 :1; /* Abort Acknowledge 0 */
|
| 5226 |
|
|
byte ABTAK1 :1; /* Abort Acknowledge 1 */
|
| 5227 |
|
|
byte ABTAK2 :1; /* Abort Acknowledge 2 */
|
| 5228 |
|
|
byte :1;
|
| 5229 |
|
|
byte :1;
|
| 5230 |
|
|
byte :1;
|
| 5231 |
|
|
byte :1;
|
| 5232 |
|
|
byte :1;
|
| 5233 |
|
|
} Bits;
|
| 5234 |
|
|
struct {
|
| 5235 |
|
|
byte grpABTAK :3;
|
| 5236 |
|
|
byte :1;
|
| 5237 |
|
|
byte :1;
|
| 5238 |
|
|
byte :1;
|
| 5239 |
|
|
byte :1;
|
| 5240 |
|
|
byte :1;
|
| 5241 |
|
|
} MergedBits;
|
| 5242 |
|
|
} CANTAAKSTR;
|
| 5243 |
|
|
extern volatile CANTAAKSTR _CANTAAK @(REG_BASE + 0x00000149);
|
| 5244 |
|
|
#define CANTAAK _CANTAAK.Byte
|
| 5245 |
|
|
#define CANTAAK_ABTAK0 _CANTAAK.Bits.ABTAK0
|
| 5246 |
|
|
#define CANTAAK_ABTAK1 _CANTAAK.Bits.ABTAK1
|
| 5247 |
|
|
#define CANTAAK_ABTAK2 _CANTAAK.Bits.ABTAK2
|
| 5248 |
|
|
#define CANTAAK_ABTAK _CANTAAK.MergedBits.grpABTAK
|
| 5249 |
|
|
|
| 5250 |
|
|
|
| 5251 |
|
|
/*** CANTBSEL - MSCAN Transmit Buffer Selection; 0x0000014A ***/
|
| 5252 |
|
|
typedef union {
|
| 5253 |
|
|
byte Byte;
|
| 5254 |
|
|
struct {
|
| 5255 |
|
|
byte TX0 :1; /* Transmit Buffer Select 0 */
|
| 5256 |
|
|
byte TX1 :1; /* Transmit Buffer Select 1 */
|
| 5257 |
|
|
byte TX2 :1; /* Transmit Buffer Select 2 */
|
| 5258 |
|
|
byte :1;
|
| 5259 |
|
|
byte :1;
|
| 5260 |
|
|
byte :1;
|
| 5261 |
|
|
byte :1;
|
| 5262 |
|
|
byte :1;
|
| 5263 |
|
|
} Bits;
|
| 5264 |
|
|
struct {
|
| 5265 |
|
|
byte grpTX :3;
|
| 5266 |
|
|
byte :1;
|
| 5267 |
|
|
byte :1;
|
| 5268 |
|
|
byte :1;
|
| 5269 |
|
|
byte :1;
|
| 5270 |
|
|
byte :1;
|
| 5271 |
|
|
} MergedBits;
|
| 5272 |
|
|
} CANTBSELSTR;
|
| 5273 |
|
|
extern volatile CANTBSELSTR _CANTBSEL @(REG_BASE + 0x0000014A);
|
| 5274 |
|
|
#define CANTBSEL _CANTBSEL.Byte
|
| 5275 |
|
|
#define CANTBSEL_TX0 _CANTBSEL.Bits.TX0
|
| 5276 |
|
|
#define CANTBSEL_TX1 _CANTBSEL.Bits.TX1
|
| 5277 |
|
|
#define CANTBSEL_TX2 _CANTBSEL.Bits.TX2
|
| 5278 |
|
|
#define CANTBSEL_TX _CANTBSEL.MergedBits.grpTX
|
| 5279 |
|
|
|
| 5280 |
|
|
|
| 5281 |
|
|
/*** CANIDAC - MSCAN Identifier Acceptance Control Register; 0x0000014B ***/
|
| 5282 |
|
|
typedef union {
|
| 5283 |
|
|
byte Byte;
|
| 5284 |
|
|
struct {
|
| 5285 |
|
|
byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
|
| 5286 |
|
|
byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
|
| 5287 |
|
|
byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
|
| 5288 |
|
|
byte :1;
|
| 5289 |
|
|
byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
|
| 5290 |
|
|
byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
|
| 5291 |
|
|
byte :1;
|
| 5292 |
|
|
byte :1;
|
| 5293 |
|
|
} Bits;
|
| 5294 |
|
|
struct {
|
| 5295 |
|
|
byte grpIDHIT :3;
|
| 5296 |
|
|
byte :1;
|
| 5297 |
|
|
byte grpIDAM :2;
|
| 5298 |
|
|
byte :1;
|
| 5299 |
|
|
byte :1;
|
| 5300 |
|
|
} MergedBits;
|
| 5301 |
|
|
} CANIDACSTR;
|
| 5302 |
|
|
extern volatile CANIDACSTR _CANIDAC @(REG_BASE + 0x0000014B);
|
| 5303 |
|
|
#define CANIDAC _CANIDAC.Byte
|
| 5304 |
|
|
#define CANIDAC_IDHIT0 _CANIDAC.Bits.IDHIT0
|
| 5305 |
|
|
#define CANIDAC_IDHIT1 _CANIDAC.Bits.IDHIT1
|
| 5306 |
|
|
#define CANIDAC_IDHIT2 _CANIDAC.Bits.IDHIT2
|
| 5307 |
|
|
#define CANIDAC_IDAM0 _CANIDAC.Bits.IDAM0
|
| 5308 |
|
|
#define CANIDAC_IDAM1 _CANIDAC.Bits.IDAM1
|
| 5309 |
|
|
#define CANIDAC_IDHIT _CANIDAC.MergedBits.grpIDHIT
|
| 5310 |
|
|
#define CANIDAC_IDAM _CANIDAC.MergedBits.grpIDAM
|
| 5311 |
|
|
|
| 5312 |
|
|
|
| 5313 |
|
|
/*** CANRXERR - MSCAN Receive Error Counter Register; 0x0000014E ***/
|
| 5314 |
|
|
typedef union {
|
| 5315 |
|
|
byte Byte;
|
| 5316 |
|
|
struct {
|
| 5317 |
|
|
byte RXERR0 :1; /* Bit 0 */
|
| 5318 |
|
|
byte RXERR1 :1; /* Bit 1 */
|
| 5319 |
|
|
byte RXERR2 :1; /* Bit 2 */
|
| 5320 |
|
|
byte RXERR3 :1; /* Bit 3 */
|
| 5321 |
|
|
byte RXERR4 :1; /* Bit 4 */
|
| 5322 |
|
|
byte RXERR5 :1; /* Bit 5 */
|
| 5323 |
|
|
byte RXERR6 :1; /* Bit 6 */
|
| 5324 |
|
|
byte RXERR7 :1; /* Bit 7 */
|
| 5325 |
|
|
} Bits;
|
| 5326 |
|
|
struct {
|
| 5327 |
|
|
byte grpRXERR :8;
|
| 5328 |
|
|
} MergedBits;
|
| 5329 |
|
|
} CANRXERRSTR;
|
| 5330 |
|
|
extern volatile CANRXERRSTR _CANRXERR @(REG_BASE + 0x0000014E);
|
| 5331 |
|
|
#define CANRXERR _CANRXERR.Byte
|
| 5332 |
|
|
#define CANRXERR_RXERR0 _CANRXERR.Bits.RXERR0
|
| 5333 |
|
|
#define CANRXERR_RXERR1 _CANRXERR.Bits.RXERR1
|
| 5334 |
|
|
#define CANRXERR_RXERR2 _CANRXERR.Bits.RXERR2
|
| 5335 |
|
|
#define CANRXERR_RXERR3 _CANRXERR.Bits.RXERR3
|
| 5336 |
|
|
#define CANRXERR_RXERR4 _CANRXERR.Bits.RXERR4
|
| 5337 |
|
|
#define CANRXERR_RXERR5 _CANRXERR.Bits.RXERR5
|
| 5338 |
|
|
#define CANRXERR_RXERR6 _CANRXERR.Bits.RXERR6
|
| 5339 |
|
|
#define CANRXERR_RXERR7 _CANRXERR.Bits.RXERR7
|
| 5340 |
|
|
#define CANRXERR_RXERR _CANRXERR.MergedBits.grpRXERR
|
| 5341 |
|
|
|
| 5342 |
|
|
|
| 5343 |
|
|
/*** CANTXERR - MSCAN Transmit Error Counter Register; 0x0000014F ***/
|
| 5344 |
|
|
typedef union {
|
| 5345 |
|
|
byte Byte;
|
| 5346 |
|
|
struct {
|
| 5347 |
|
|
byte TXERR0 :1; /* Bit 0 */
|
| 5348 |
|
|
byte TXERR1 :1; /* Bit 1 */
|
| 5349 |
|
|
byte TXERR2 :1; /* Bit 2 */
|
| 5350 |
|
|
byte TXERR3 :1; /* Bit 3 */
|
| 5351 |
|
|
byte TXERR4 :1; /* Bit 4 */
|
| 5352 |
|
|
byte TXERR5 :1; /* Bit 5 */
|
| 5353 |
|
|
byte TXERR6 :1; /* Bit 6 */
|
| 5354 |
|
|
byte TXERR7 :1; /* Bit 7 */
|
| 5355 |
|
|
} Bits;
|
| 5356 |
|
|
struct {
|
| 5357 |
|
|
byte grpTXERR :8;
|
| 5358 |
|
|
} MergedBits;
|
| 5359 |
|
|
} CANTXERRSTR;
|
| 5360 |
|
|
extern volatile CANTXERRSTR _CANTXERR @(REG_BASE + 0x0000014F);
|
| 5361 |
|
|
#define CANTXERR _CANTXERR.Byte
|
| 5362 |
|
|
#define CANTXERR_TXERR0 _CANTXERR.Bits.TXERR0
|
| 5363 |
|
|
#define CANTXERR_TXERR1 _CANTXERR.Bits.TXERR1
|
| 5364 |
|
|
#define CANTXERR_TXERR2 _CANTXERR.Bits.TXERR2
|
| 5365 |
|
|
#define CANTXERR_TXERR3 _CANTXERR.Bits.TXERR3
|
| 5366 |
|
|
#define CANTXERR_TXERR4 _CANTXERR.Bits.TXERR4
|
| 5367 |
|
|
#define CANTXERR_TXERR5 _CANTXERR.Bits.TXERR5
|
| 5368 |
|
|
#define CANTXERR_TXERR6 _CANTXERR.Bits.TXERR6
|
| 5369 |
|
|
#define CANTXERR_TXERR7 _CANTXERR.Bits.TXERR7
|
| 5370 |
|
|
#define CANTXERR_TXERR _CANTXERR.MergedBits.grpTXERR
|
| 5371 |
|
|
|
| 5372 |
|
|
|
| 5373 |
|
|
/*** CANIDAR0 - MSCAN Identifier Acceptance Register 0; 0x00000150 ***/
|
| 5374 |
|
|
typedef union {
|
| 5375 |
|
|
byte Byte;
|
| 5376 |
|
|
struct {
|
| 5377 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 5378 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 5379 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 5380 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 5381 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 5382 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 5383 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 5384 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 5385 |
|
|
} Bits;
|
| 5386 |
|
|
struct {
|
| 5387 |
|
|
byte grpAC :8;
|
| 5388 |
|
|
} MergedBits;
|
| 5389 |
|
|
} CANIDAR0STR;
|
| 5390 |
|
|
extern volatile CANIDAR0STR _CANIDAR0 @(REG_BASE + 0x00000150);
|
| 5391 |
|
|
#define CANIDAR0 _CANIDAR0.Byte
|
| 5392 |
|
|
#define CANIDAR0_AC0 _CANIDAR0.Bits.AC0
|
| 5393 |
|
|
#define CANIDAR0_AC1 _CANIDAR0.Bits.AC1
|
| 5394 |
|
|
#define CANIDAR0_AC2 _CANIDAR0.Bits.AC2
|
| 5395 |
|
|
#define CANIDAR0_AC3 _CANIDAR0.Bits.AC3
|
| 5396 |
|
|
#define CANIDAR0_AC4 _CANIDAR0.Bits.AC4
|
| 5397 |
|
|
#define CANIDAR0_AC5 _CANIDAR0.Bits.AC5
|
| 5398 |
|
|
#define CANIDAR0_AC6 _CANIDAR0.Bits.AC6
|
| 5399 |
|
|
#define CANIDAR0_AC7 _CANIDAR0.Bits.AC7
|
| 5400 |
|
|
#define CANIDAR0_AC _CANIDAR0.MergedBits.grpAC
|
| 5401 |
|
|
|
| 5402 |
|
|
|
| 5403 |
|
|
/*** CANIDAR1 - MSCAN Identifier Acceptance Register 1; 0x00000151 ***/
|
| 5404 |
|
|
typedef union {
|
| 5405 |
|
|
byte Byte;
|
| 5406 |
|
|
struct {
|
| 5407 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 5408 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 5409 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 5410 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 5411 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 5412 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 5413 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 5414 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 5415 |
|
|
} Bits;
|
| 5416 |
|
|
struct {
|
| 5417 |
|
|
byte grpAC :8;
|
| 5418 |
|
|
} MergedBits;
|
| 5419 |
|
|
} CANIDAR1STR;
|
| 5420 |
|
|
extern volatile CANIDAR1STR _CANIDAR1 @(REG_BASE + 0x00000151);
|
| 5421 |
|
|
#define CANIDAR1 _CANIDAR1.Byte
|
| 5422 |
|
|
#define CANIDAR1_AC0 _CANIDAR1.Bits.AC0
|
| 5423 |
|
|
#define CANIDAR1_AC1 _CANIDAR1.Bits.AC1
|
| 5424 |
|
|
#define CANIDAR1_AC2 _CANIDAR1.Bits.AC2
|
| 5425 |
|
|
#define CANIDAR1_AC3 _CANIDAR1.Bits.AC3
|
| 5426 |
|
|
#define CANIDAR1_AC4 _CANIDAR1.Bits.AC4
|
| 5427 |
|
|
#define CANIDAR1_AC5 _CANIDAR1.Bits.AC5
|
| 5428 |
|
|
#define CANIDAR1_AC6 _CANIDAR1.Bits.AC6
|
| 5429 |
|
|
#define CANIDAR1_AC7 _CANIDAR1.Bits.AC7
|
| 5430 |
|
|
#define CANIDAR1_AC _CANIDAR1.MergedBits.grpAC
|
| 5431 |
|
|
|
| 5432 |
|
|
|
| 5433 |
|
|
/*** CANIDAR2 - MSCAN Identifier Acceptance Register 2; 0x00000152 ***/
|
| 5434 |
|
|
typedef union {
|
| 5435 |
|
|
byte Byte;
|
| 5436 |
|
|
struct {
|
| 5437 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 5438 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 5439 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 5440 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 5441 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 5442 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 5443 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 5444 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 5445 |
|
|
} Bits;
|
| 5446 |
|
|
struct {
|
| 5447 |
|
|
byte grpAC :8;
|
| 5448 |
|
|
} MergedBits;
|
| 5449 |
|
|
} CANIDAR2STR;
|
| 5450 |
|
|
extern volatile CANIDAR2STR _CANIDAR2 @(REG_BASE + 0x00000152);
|
| 5451 |
|
|
#define CANIDAR2 _CANIDAR2.Byte
|
| 5452 |
|
|
#define CANIDAR2_AC0 _CANIDAR2.Bits.AC0
|
| 5453 |
|
|
#define CANIDAR2_AC1 _CANIDAR2.Bits.AC1
|
| 5454 |
|
|
#define CANIDAR2_AC2 _CANIDAR2.Bits.AC2
|
| 5455 |
|
|
#define CANIDAR2_AC3 _CANIDAR2.Bits.AC3
|
| 5456 |
|
|
#define CANIDAR2_AC4 _CANIDAR2.Bits.AC4
|
| 5457 |
|
|
#define CANIDAR2_AC5 _CANIDAR2.Bits.AC5
|
| 5458 |
|
|
#define CANIDAR2_AC6 _CANIDAR2.Bits.AC6
|
| 5459 |
|
|
#define CANIDAR2_AC7 _CANIDAR2.Bits.AC7
|
| 5460 |
|
|
#define CANIDAR2_AC _CANIDAR2.MergedBits.grpAC
|
| 5461 |
|
|
|
| 5462 |
|
|
|
| 5463 |
|
|
/*** CANIDAR3 - MSCAN Identifier Acceptance Register 3; 0x00000153 ***/
|
| 5464 |
|
|
typedef union {
|
| 5465 |
|
|
byte Byte;
|
| 5466 |
|
|
struct {
|
| 5467 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 5468 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 5469 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 5470 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 5471 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 5472 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 5473 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 5474 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 5475 |
|
|
} Bits;
|
| 5476 |
|
|
struct {
|
| 5477 |
|
|
byte grpAC :8;
|
| 5478 |
|
|
} MergedBits;
|
| 5479 |
|
|
} CANIDAR3STR;
|
| 5480 |
|
|
extern volatile CANIDAR3STR _CANIDAR3 @(REG_BASE + 0x00000153);
|
| 5481 |
|
|
#define CANIDAR3 _CANIDAR3.Byte
|
| 5482 |
|
|
#define CANIDAR3_AC0 _CANIDAR3.Bits.AC0
|
| 5483 |
|
|
#define CANIDAR3_AC1 _CANIDAR3.Bits.AC1
|
| 5484 |
|
|
#define CANIDAR3_AC2 _CANIDAR3.Bits.AC2
|
| 5485 |
|
|
#define CANIDAR3_AC3 _CANIDAR3.Bits.AC3
|
| 5486 |
|
|
#define CANIDAR3_AC4 _CANIDAR3.Bits.AC4
|
| 5487 |
|
|
#define CANIDAR3_AC5 _CANIDAR3.Bits.AC5
|
| 5488 |
|
|
#define CANIDAR3_AC6 _CANIDAR3.Bits.AC6
|
| 5489 |
|
|
#define CANIDAR3_AC7 _CANIDAR3.Bits.AC7
|
| 5490 |
|
|
#define CANIDAR3_AC _CANIDAR3.MergedBits.grpAC
|
| 5491 |
|
|
|
| 5492 |
|
|
|
| 5493 |
|
|
/*** CANIDMR0 - MSCAN Identifier Mask Register 0; 0x00000154 ***/
|
| 5494 |
|
|
typedef union {
|
| 5495 |
|
|
byte Byte;
|
| 5496 |
|
|
struct {
|
| 5497 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 5498 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 5499 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 5500 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 5501 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 5502 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 5503 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 5504 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 5505 |
|
|
} Bits;
|
| 5506 |
|
|
struct {
|
| 5507 |
|
|
byte grpAM :8;
|
| 5508 |
|
|
} MergedBits;
|
| 5509 |
|
|
} CANIDMR0STR;
|
| 5510 |
|
|
extern volatile CANIDMR0STR _CANIDMR0 @(REG_BASE + 0x00000154);
|
| 5511 |
|
|
#define CANIDMR0 _CANIDMR0.Byte
|
| 5512 |
|
|
#define CANIDMR0_AM0 _CANIDMR0.Bits.AM0
|
| 5513 |
|
|
#define CANIDMR0_AM1 _CANIDMR0.Bits.AM1
|
| 5514 |
|
|
#define CANIDMR0_AM2 _CANIDMR0.Bits.AM2
|
| 5515 |
|
|
#define CANIDMR0_AM3 _CANIDMR0.Bits.AM3
|
| 5516 |
|
|
#define CANIDMR0_AM4 _CANIDMR0.Bits.AM4
|
| 5517 |
|
|
#define CANIDMR0_AM5 _CANIDMR0.Bits.AM5
|
| 5518 |
|
|
#define CANIDMR0_AM6 _CANIDMR0.Bits.AM6
|
| 5519 |
|
|
#define CANIDMR0_AM7 _CANIDMR0.Bits.AM7
|
| 5520 |
|
|
#define CANIDMR0_AM _CANIDMR0.MergedBits.grpAM
|
| 5521 |
|
|
|
| 5522 |
|
|
|
| 5523 |
|
|
/*** CANIDMR1 - MSCAN Identifier Mask Register 1; 0x00000155 ***/
|
| 5524 |
|
|
typedef union {
|
| 5525 |
|
|
byte Byte;
|
| 5526 |
|
|
struct {
|
| 5527 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 5528 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 5529 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 5530 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 5531 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 5532 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 5533 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 5534 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 5535 |
|
|
} Bits;
|
| 5536 |
|
|
struct {
|
| 5537 |
|
|
byte grpAM :8;
|
| 5538 |
|
|
} MergedBits;
|
| 5539 |
|
|
} CANIDMR1STR;
|
| 5540 |
|
|
extern volatile CANIDMR1STR _CANIDMR1 @(REG_BASE + 0x00000155);
|
| 5541 |
|
|
#define CANIDMR1 _CANIDMR1.Byte
|
| 5542 |
|
|
#define CANIDMR1_AM0 _CANIDMR1.Bits.AM0
|
| 5543 |
|
|
#define CANIDMR1_AM1 _CANIDMR1.Bits.AM1
|
| 5544 |
|
|
#define CANIDMR1_AM2 _CANIDMR1.Bits.AM2
|
| 5545 |
|
|
#define CANIDMR1_AM3 _CANIDMR1.Bits.AM3
|
| 5546 |
|
|
#define CANIDMR1_AM4 _CANIDMR1.Bits.AM4
|
| 5547 |
|
|
#define CANIDMR1_AM5 _CANIDMR1.Bits.AM5
|
| 5548 |
|
|
#define CANIDMR1_AM6 _CANIDMR1.Bits.AM6
|
| 5549 |
|
|
#define CANIDMR1_AM7 _CANIDMR1.Bits.AM7
|
| 5550 |
|
|
#define CANIDMR1_AM _CANIDMR1.MergedBits.grpAM
|
| 5551 |
|
|
|
| 5552 |
|
|
|
| 5553 |
|
|
/*** CANIDMR2 - MSCAN Identifier Mask Register 2; 0x00000156 ***/
|
| 5554 |
|
|
typedef union {
|
| 5555 |
|
|
byte Byte;
|
| 5556 |
|
|
struct {
|
| 5557 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 5558 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 5559 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 5560 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 5561 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 5562 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 5563 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 5564 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 5565 |
|
|
} Bits;
|
| 5566 |
|
|
struct {
|
| 5567 |
|
|
byte grpAM :8;
|
| 5568 |
|
|
} MergedBits;
|
| 5569 |
|
|
} CANIDMR2STR;
|
| 5570 |
|
|
extern volatile CANIDMR2STR _CANIDMR2 @(REG_BASE + 0x00000156);
|
| 5571 |
|
|
#define CANIDMR2 _CANIDMR2.Byte
|
| 5572 |
|
|
#define CANIDMR2_AM0 _CANIDMR2.Bits.AM0
|
| 5573 |
|
|
#define CANIDMR2_AM1 _CANIDMR2.Bits.AM1
|
| 5574 |
|
|
#define CANIDMR2_AM2 _CANIDMR2.Bits.AM2
|
| 5575 |
|
|
#define CANIDMR2_AM3 _CANIDMR2.Bits.AM3
|
| 5576 |
|
|
#define CANIDMR2_AM4 _CANIDMR2.Bits.AM4
|
| 5577 |
|
|
#define CANIDMR2_AM5 _CANIDMR2.Bits.AM5
|
| 5578 |
|
|
#define CANIDMR2_AM6 _CANIDMR2.Bits.AM6
|
| 5579 |
|
|
#define CANIDMR2_AM7 _CANIDMR2.Bits.AM7
|
| 5580 |
|
|
#define CANIDMR2_AM _CANIDMR2.MergedBits.grpAM
|
| 5581 |
|
|
|
| 5582 |
|
|
|
| 5583 |
|
|
/*** CANIDMR3 - MSCAN Identifier Mask Register 3; 0x00000157 ***/
|
| 5584 |
|
|
typedef union {
|
| 5585 |
|
|
byte Byte;
|
| 5586 |
|
|
struct {
|
| 5587 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 5588 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 5589 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 5590 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 5591 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 5592 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 5593 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 5594 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 5595 |
|
|
} Bits;
|
| 5596 |
|
|
struct {
|
| 5597 |
|
|
byte grpAM :8;
|
| 5598 |
|
|
} MergedBits;
|
| 5599 |
|
|
} CANIDMR3STR;
|
| 5600 |
|
|
extern volatile CANIDMR3STR _CANIDMR3 @(REG_BASE + 0x00000157);
|
| 5601 |
|
|
#define CANIDMR3 _CANIDMR3.Byte
|
| 5602 |
|
|
#define CANIDMR3_AM0 _CANIDMR3.Bits.AM0
|
| 5603 |
|
|
#define CANIDMR3_AM1 _CANIDMR3.Bits.AM1
|
| 5604 |
|
|
#define CANIDMR3_AM2 _CANIDMR3.Bits.AM2
|
| 5605 |
|
|
#define CANIDMR3_AM3 _CANIDMR3.Bits.AM3
|
| 5606 |
|
|
#define CANIDMR3_AM4 _CANIDMR3.Bits.AM4
|
| 5607 |
|
|
#define CANIDMR3_AM5 _CANIDMR3.Bits.AM5
|
| 5608 |
|
|
#define CANIDMR3_AM6 _CANIDMR3.Bits.AM6
|
| 5609 |
|
|
#define CANIDMR3_AM7 _CANIDMR3.Bits.AM7
|
| 5610 |
|
|
#define CANIDMR3_AM _CANIDMR3.MergedBits.grpAM
|
| 5611 |
|
|
|
| 5612 |
|
|
|
| 5613 |
|
|
/*** CANIDAR4 - MSCAN Identifier Acceptance Register 4; 0x00000158 ***/
|
| 5614 |
|
|
typedef union {
|
| 5615 |
|
|
byte Byte;
|
| 5616 |
|
|
struct {
|
| 5617 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 5618 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 5619 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 5620 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 5621 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 5622 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 5623 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 5624 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 5625 |
|
|
} Bits;
|
| 5626 |
|
|
struct {
|
| 5627 |
|
|
byte grpAC :8;
|
| 5628 |
|
|
} MergedBits;
|
| 5629 |
|
|
} CANIDAR4STR;
|
| 5630 |
|
|
extern volatile CANIDAR4STR _CANIDAR4 @(REG_BASE + 0x00000158);
|
| 5631 |
|
|
#define CANIDAR4 _CANIDAR4.Byte
|
| 5632 |
|
|
#define CANIDAR4_AC0 _CANIDAR4.Bits.AC0
|
| 5633 |
|
|
#define CANIDAR4_AC1 _CANIDAR4.Bits.AC1
|
| 5634 |
|
|
#define CANIDAR4_AC2 _CANIDAR4.Bits.AC2
|
| 5635 |
|
|
#define CANIDAR4_AC3 _CANIDAR4.Bits.AC3
|
| 5636 |
|
|
#define CANIDAR4_AC4 _CANIDAR4.Bits.AC4
|
| 5637 |
|
|
#define CANIDAR4_AC5 _CANIDAR4.Bits.AC5
|
| 5638 |
|
|
#define CANIDAR4_AC6 _CANIDAR4.Bits.AC6
|
| 5639 |
|
|
#define CANIDAR4_AC7 _CANIDAR4.Bits.AC7
|
| 5640 |
|
|
#define CANIDAR4_AC _CANIDAR4.MergedBits.grpAC
|
| 5641 |
|
|
|
| 5642 |
|
|
|
| 5643 |
|
|
/*** CANIDAR5 - MSCAN Identifier Acceptance Register 5; 0x00000159 ***/
|
| 5644 |
|
|
typedef union {
|
| 5645 |
|
|
byte Byte;
|
| 5646 |
|
|
struct {
|
| 5647 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 5648 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 5649 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 5650 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 5651 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 5652 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 5653 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 5654 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 5655 |
|
|
} Bits;
|
| 5656 |
|
|
struct {
|
| 5657 |
|
|
byte grpAC :8;
|
| 5658 |
|
|
} MergedBits;
|
| 5659 |
|
|
} CANIDAR5STR;
|
| 5660 |
|
|
extern volatile CANIDAR5STR _CANIDAR5 @(REG_BASE + 0x00000159);
|
| 5661 |
|
|
#define CANIDAR5 _CANIDAR5.Byte
|
| 5662 |
|
|
#define CANIDAR5_AC0 _CANIDAR5.Bits.AC0
|
| 5663 |
|
|
#define CANIDAR5_AC1 _CANIDAR5.Bits.AC1
|
| 5664 |
|
|
#define CANIDAR5_AC2 _CANIDAR5.Bits.AC2
|
| 5665 |
|
|
#define CANIDAR5_AC3 _CANIDAR5.Bits.AC3
|
| 5666 |
|
|
#define CANIDAR5_AC4 _CANIDAR5.Bits.AC4
|
| 5667 |
|
|
#define CANIDAR5_AC5 _CANIDAR5.Bits.AC5
|
| 5668 |
|
|
#define CANIDAR5_AC6 _CANIDAR5.Bits.AC6
|
| 5669 |
|
|
#define CANIDAR5_AC7 _CANIDAR5.Bits.AC7
|
| 5670 |
|
|
#define CANIDAR5_AC _CANIDAR5.MergedBits.grpAC
|
| 5671 |
|
|
|
| 5672 |
|
|
|
| 5673 |
|
|
/*** CANIDAR6 - MSCAN Identifier Acceptance Register 6; 0x0000015A ***/
|
| 5674 |
|
|
typedef union {
|
| 5675 |
|
|
byte Byte;
|
| 5676 |
|
|
struct {
|
| 5677 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 5678 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 5679 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 5680 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 5681 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 5682 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 5683 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 5684 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 5685 |
|
|
} Bits;
|
| 5686 |
|
|
struct {
|
| 5687 |
|
|
byte grpAC :8;
|
| 5688 |
|
|
} MergedBits;
|
| 5689 |
|
|
} CANIDAR6STR;
|
| 5690 |
|
|
extern volatile CANIDAR6STR _CANIDAR6 @(REG_BASE + 0x0000015A);
|
| 5691 |
|
|
#define CANIDAR6 _CANIDAR6.Byte
|
| 5692 |
|
|
#define CANIDAR6_AC0 _CANIDAR6.Bits.AC0
|
| 5693 |
|
|
#define CANIDAR6_AC1 _CANIDAR6.Bits.AC1
|
| 5694 |
|
|
#define CANIDAR6_AC2 _CANIDAR6.Bits.AC2
|
| 5695 |
|
|
#define CANIDAR6_AC3 _CANIDAR6.Bits.AC3
|
| 5696 |
|
|
#define CANIDAR6_AC4 _CANIDAR6.Bits.AC4
|
| 5697 |
|
|
#define CANIDAR6_AC5 _CANIDAR6.Bits.AC5
|
| 5698 |
|
|
#define CANIDAR6_AC6 _CANIDAR6.Bits.AC6
|
| 5699 |
|
|
#define CANIDAR6_AC7 _CANIDAR6.Bits.AC7
|
| 5700 |
|
|
#define CANIDAR6_AC _CANIDAR6.MergedBits.grpAC
|
| 5701 |
|
|
|
| 5702 |
|
|
|
| 5703 |
|
|
/*** CANIDAR7 - MSCAN Identifier Acceptance Register 7; 0x0000015B ***/
|
| 5704 |
|
|
typedef union {
|
| 5705 |
|
|
byte Byte;
|
| 5706 |
|
|
struct {
|
| 5707 |
|
|
byte AC0 :1; /* Acceptance Code Bit 0 */
|
| 5708 |
|
|
byte AC1 :1; /* Acceptance Code Bit 1 */
|
| 5709 |
|
|
byte AC2 :1; /* Acceptance Code Bit 2 */
|
| 5710 |
|
|
byte AC3 :1; /* Acceptance Code Bit 3 */
|
| 5711 |
|
|
byte AC4 :1; /* Acceptance Code Bit 4 */
|
| 5712 |
|
|
byte AC5 :1; /* Acceptance Code Bit 5 */
|
| 5713 |
|
|
byte AC6 :1; /* Acceptance Code Bit 6 */
|
| 5714 |
|
|
byte AC7 :1; /* Acceptance Code Bit 7 */
|
| 5715 |
|
|
} Bits;
|
| 5716 |
|
|
struct {
|
| 5717 |
|
|
byte grpAC :8;
|
| 5718 |
|
|
} MergedBits;
|
| 5719 |
|
|
} CANIDAR7STR;
|
| 5720 |
|
|
extern volatile CANIDAR7STR _CANIDAR7 @(REG_BASE + 0x0000015B);
|
| 5721 |
|
|
#define CANIDAR7 _CANIDAR7.Byte
|
| 5722 |
|
|
#define CANIDAR7_AC0 _CANIDAR7.Bits.AC0
|
| 5723 |
|
|
#define CANIDAR7_AC1 _CANIDAR7.Bits.AC1
|
| 5724 |
|
|
#define CANIDAR7_AC2 _CANIDAR7.Bits.AC2
|
| 5725 |
|
|
#define CANIDAR7_AC3 _CANIDAR7.Bits.AC3
|
| 5726 |
|
|
#define CANIDAR7_AC4 _CANIDAR7.Bits.AC4
|
| 5727 |
|
|
#define CANIDAR7_AC5 _CANIDAR7.Bits.AC5
|
| 5728 |
|
|
#define CANIDAR7_AC6 _CANIDAR7.Bits.AC6
|
| 5729 |
|
|
#define CANIDAR7_AC7 _CANIDAR7.Bits.AC7
|
| 5730 |
|
|
#define CANIDAR7_AC _CANIDAR7.MergedBits.grpAC
|
| 5731 |
|
|
|
| 5732 |
|
|
|
| 5733 |
|
|
/*** CANIDMR4 - MSCAN Identifier Mask Register 4; 0x0000015C ***/
|
| 5734 |
|
|
typedef union {
|
| 5735 |
|
|
byte Byte;
|
| 5736 |
|
|
struct {
|
| 5737 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 5738 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 5739 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 5740 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 5741 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 5742 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 5743 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 5744 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 5745 |
|
|
} Bits;
|
| 5746 |
|
|
struct {
|
| 5747 |
|
|
byte grpAM :8;
|
| 5748 |
|
|
} MergedBits;
|
| 5749 |
|
|
} CANIDMR4STR;
|
| 5750 |
|
|
extern volatile CANIDMR4STR _CANIDMR4 @(REG_BASE + 0x0000015C);
|
| 5751 |
|
|
#define CANIDMR4 _CANIDMR4.Byte
|
| 5752 |
|
|
#define CANIDMR4_AM0 _CANIDMR4.Bits.AM0
|
| 5753 |
|
|
#define CANIDMR4_AM1 _CANIDMR4.Bits.AM1
|
| 5754 |
|
|
#define CANIDMR4_AM2 _CANIDMR4.Bits.AM2
|
| 5755 |
|
|
#define CANIDMR4_AM3 _CANIDMR4.Bits.AM3
|
| 5756 |
|
|
#define CANIDMR4_AM4 _CANIDMR4.Bits.AM4
|
| 5757 |
|
|
#define CANIDMR4_AM5 _CANIDMR4.Bits.AM5
|
| 5758 |
|
|
#define CANIDMR4_AM6 _CANIDMR4.Bits.AM6
|
| 5759 |
|
|
#define CANIDMR4_AM7 _CANIDMR4.Bits.AM7
|
| 5760 |
|
|
#define CANIDMR4_AM _CANIDMR4.MergedBits.grpAM
|
| 5761 |
|
|
|
| 5762 |
|
|
|
| 5763 |
|
|
/*** CANIDMR5 - MSCAN Identifier Mask Register 5; 0x0000015D ***/
|
| 5764 |
|
|
typedef union {
|
| 5765 |
|
|
byte Byte;
|
| 5766 |
|
|
struct {
|
| 5767 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 5768 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 5769 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 5770 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 5771 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 5772 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 5773 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 5774 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 5775 |
|
|
} Bits;
|
| 5776 |
|
|
struct {
|
| 5777 |
|
|
byte grpAM :8;
|
| 5778 |
|
|
} MergedBits;
|
| 5779 |
|
|
} CANIDMR5STR;
|
| 5780 |
|
|
extern volatile CANIDMR5STR _CANIDMR5 @(REG_BASE + 0x0000015D);
|
| 5781 |
|
|
#define CANIDMR5 _CANIDMR5.Byte
|
| 5782 |
|
|
#define CANIDMR5_AM0 _CANIDMR5.Bits.AM0
|
| 5783 |
|
|
#define CANIDMR5_AM1 _CANIDMR5.Bits.AM1
|
| 5784 |
|
|
#define CANIDMR5_AM2 _CANIDMR5.Bits.AM2
|
| 5785 |
|
|
#define CANIDMR5_AM3 _CANIDMR5.Bits.AM3
|
| 5786 |
|
|
#define CANIDMR5_AM4 _CANIDMR5.Bits.AM4
|
| 5787 |
|
|
#define CANIDMR5_AM5 _CANIDMR5.Bits.AM5
|
| 5788 |
|
|
#define CANIDMR5_AM6 _CANIDMR5.Bits.AM6
|
| 5789 |
|
|
#define CANIDMR5_AM7 _CANIDMR5.Bits.AM7
|
| 5790 |
|
|
#define CANIDMR5_AM _CANIDMR5.MergedBits.grpAM
|
| 5791 |
|
|
|
| 5792 |
|
|
|
| 5793 |
|
|
/*** CANIDMR6 - MSCAN Identifier Mask Register 6; 0x0000015E ***/
|
| 5794 |
|
|
typedef union {
|
| 5795 |
|
|
byte Byte;
|
| 5796 |
|
|
struct {
|
| 5797 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 5798 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 5799 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 5800 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 5801 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 5802 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 5803 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 5804 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 5805 |
|
|
} Bits;
|
| 5806 |
|
|
struct {
|
| 5807 |
|
|
byte grpAM :8;
|
| 5808 |
|
|
} MergedBits;
|
| 5809 |
|
|
} CANIDMR6STR;
|
| 5810 |
|
|
extern volatile CANIDMR6STR _CANIDMR6 @(REG_BASE + 0x0000015E);
|
| 5811 |
|
|
#define CANIDMR6 _CANIDMR6.Byte
|
| 5812 |
|
|
#define CANIDMR6_AM0 _CANIDMR6.Bits.AM0
|
| 5813 |
|
|
#define CANIDMR6_AM1 _CANIDMR6.Bits.AM1
|
| 5814 |
|
|
#define CANIDMR6_AM2 _CANIDMR6.Bits.AM2
|
| 5815 |
|
|
#define CANIDMR6_AM3 _CANIDMR6.Bits.AM3
|
| 5816 |
|
|
#define CANIDMR6_AM4 _CANIDMR6.Bits.AM4
|
| 5817 |
|
|
#define CANIDMR6_AM5 _CANIDMR6.Bits.AM5
|
| 5818 |
|
|
#define CANIDMR6_AM6 _CANIDMR6.Bits.AM6
|
| 5819 |
|
|
#define CANIDMR6_AM7 _CANIDMR6.Bits.AM7
|
| 5820 |
|
|
#define CANIDMR6_AM _CANIDMR6.MergedBits.grpAM
|
| 5821 |
|
|
|
| 5822 |
|
|
|
| 5823 |
|
|
/*** CANIDMR7 - MSCAN Identifier Mask Register 7; 0x0000015F ***/
|
| 5824 |
|
|
typedef union {
|
| 5825 |
|
|
byte Byte;
|
| 5826 |
|
|
struct {
|
| 5827 |
|
|
byte AM0 :1; /* Acceptance Mask Bit 0 */
|
| 5828 |
|
|
byte AM1 :1; /* Acceptance Mask Bit 1 */
|
| 5829 |
|
|
byte AM2 :1; /* Acceptance Mask Bit 2 */
|
| 5830 |
|
|
byte AM3 :1; /* Acceptance Mask Bit 3 */
|
| 5831 |
|
|
byte AM4 :1; /* Acceptance Mask Bit 4 */
|
| 5832 |
|
|
byte AM5 :1; /* Acceptance Mask Bit 5 */
|
| 5833 |
|
|
byte AM6 :1; /* Acceptance Mask Bit 6 */
|
| 5834 |
|
|
byte AM7 :1; /* Acceptance Mask Bit 7 */
|
| 5835 |
|
|
} Bits;
|
| 5836 |
|
|
struct {
|
| 5837 |
|
|
byte grpAM :8;
|
| 5838 |
|
|
} MergedBits;
|
| 5839 |
|
|
} CANIDMR7STR;
|
| 5840 |
|
|
extern volatile CANIDMR7STR _CANIDMR7 @(REG_BASE + 0x0000015F);
|
| 5841 |
|
|
#define CANIDMR7 _CANIDMR7.Byte
|
| 5842 |
|
|
#define CANIDMR7_AM0 _CANIDMR7.Bits.AM0
|
| 5843 |
|
|
#define CANIDMR7_AM1 _CANIDMR7.Bits.AM1
|
| 5844 |
|
|
#define CANIDMR7_AM2 _CANIDMR7.Bits.AM2
|
| 5845 |
|
|
#define CANIDMR7_AM3 _CANIDMR7.Bits.AM3
|
| 5846 |
|
|
#define CANIDMR7_AM4 _CANIDMR7.Bits.AM4
|
| 5847 |
|
|
#define CANIDMR7_AM5 _CANIDMR7.Bits.AM5
|
| 5848 |
|
|
#define CANIDMR7_AM6 _CANIDMR7.Bits.AM6
|
| 5849 |
|
|
#define CANIDMR7_AM7 _CANIDMR7.Bits.AM7
|
| 5850 |
|
|
#define CANIDMR7_AM _CANIDMR7.MergedBits.grpAM
|
| 5851 |
|
|
|
| 5852 |
|
|
|
| 5853 |
|
|
/*** CANRXIDR0 - MSCAN Receive Identifier Register 0; 0x00000160 ***/
|
| 5854 |
|
|
typedef union {
|
| 5855 |
|
|
byte Byte;
|
| 5856 |
|
|
struct {
|
| 5857 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 5858 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 5859 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 5860 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 5861 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 5862 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 5863 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 5864 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 5865 |
|
|
} Bits;
|
| 5866 |
|
|
struct {
|
| 5867 |
|
|
byte grpID_21 :8;
|
| 5868 |
|
|
} MergedBits;
|
| 5869 |
|
|
} CANRXIDR0STR;
|
| 5870 |
|
|
extern volatile CANRXIDR0STR _CANRXIDR0 @(REG_BASE + 0x00000160);
|
| 5871 |
|
|
#define CANRXIDR0 _CANRXIDR0.Byte
|
| 5872 |
|
|
#define CANRXIDR0_ID21 _CANRXIDR0.Bits.ID21
|
| 5873 |
|
|
#define CANRXIDR0_ID22 _CANRXIDR0.Bits.ID22
|
| 5874 |
|
|
#define CANRXIDR0_ID23 _CANRXIDR0.Bits.ID23
|
| 5875 |
|
|
#define CANRXIDR0_ID24 _CANRXIDR0.Bits.ID24
|
| 5876 |
|
|
#define CANRXIDR0_ID25 _CANRXIDR0.Bits.ID25
|
| 5877 |
|
|
#define CANRXIDR0_ID26 _CANRXIDR0.Bits.ID26
|
| 5878 |
|
|
#define CANRXIDR0_ID27 _CANRXIDR0.Bits.ID27
|
| 5879 |
|
|
#define CANRXIDR0_ID28 _CANRXIDR0.Bits.ID28
|
| 5880 |
|
|
#define CANRXIDR0_ID_21 _CANRXIDR0.MergedBits.grpID_21
|
| 5881 |
|
|
#define CANRXIDR0_ID CANRXIDR0_ID_21
|
| 5882 |
|
|
|
| 5883 |
|
|
|
| 5884 |
|
|
/*** CANRXIDR1 - MSCAN Receive Identifier Register 1; 0x00000161 ***/
|
| 5885 |
|
|
typedef union {
|
| 5886 |
|
|
byte Byte;
|
| 5887 |
|
|
struct {
|
| 5888 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 5889 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 5890 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 5891 |
|
|
byte IDE :1; /* ID Extended */
|
| 5892 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 5893 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 5894 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 5895 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 5896 |
|
|
} Bits;
|
| 5897 |
|
|
struct {
|
| 5898 |
|
|
byte grpID_15 :3;
|
| 5899 |
|
|
byte :1;
|
| 5900 |
|
|
byte :1;
|
| 5901 |
|
|
byte grpID_18 :3;
|
| 5902 |
|
|
} MergedBits;
|
| 5903 |
|
|
} CANRXIDR1STR;
|
| 5904 |
|
|
extern volatile CANRXIDR1STR _CANRXIDR1 @(REG_BASE + 0x00000161);
|
| 5905 |
|
|
#define CANRXIDR1 _CANRXIDR1.Byte
|
| 5906 |
|
|
#define CANRXIDR1_ID15 _CANRXIDR1.Bits.ID15
|
| 5907 |
|
|
#define CANRXIDR1_ID16 _CANRXIDR1.Bits.ID16
|
| 5908 |
|
|
#define CANRXIDR1_ID17 _CANRXIDR1.Bits.ID17
|
| 5909 |
|
|
#define CANRXIDR1_IDE _CANRXIDR1.Bits.IDE
|
| 5910 |
|
|
#define CANRXIDR1_SRR _CANRXIDR1.Bits.SRR
|
| 5911 |
|
|
#define CANRXIDR1_ID18 _CANRXIDR1.Bits.ID18
|
| 5912 |
|
|
#define CANRXIDR1_ID19 _CANRXIDR1.Bits.ID19
|
| 5913 |
|
|
#define CANRXIDR1_ID20 _CANRXIDR1.Bits.ID20
|
| 5914 |
|
|
#define CANRXIDR1_ID_15 _CANRXIDR1.MergedBits.grpID_15
|
| 5915 |
|
|
#define CANRXIDR1_ID_18 _CANRXIDR1.MergedBits.grpID_18
|
| 5916 |
|
|
#define CANRXIDR1_ID CANRXIDR1_ID_15
|
| 5917 |
|
|
|
| 5918 |
|
|
|
| 5919 |
|
|
/*** CANRXIDR2 - MSCAN Receive Identifier Register 2; 0x00000162 ***/
|
| 5920 |
|
|
typedef union {
|
| 5921 |
|
|
byte Byte;
|
| 5922 |
|
|
struct {
|
| 5923 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 5924 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 5925 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 5926 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 5927 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 5928 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 5929 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 5930 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 5931 |
|
|
} Bits;
|
| 5932 |
|
|
struct {
|
| 5933 |
|
|
byte grpID_7 :8;
|
| 5934 |
|
|
} MergedBits;
|
| 5935 |
|
|
} CANRXIDR2STR;
|
| 5936 |
|
|
extern volatile CANRXIDR2STR _CANRXIDR2 @(REG_BASE + 0x00000162);
|
| 5937 |
|
|
#define CANRXIDR2 _CANRXIDR2.Byte
|
| 5938 |
|
|
#define CANRXIDR2_ID7 _CANRXIDR2.Bits.ID7
|
| 5939 |
|
|
#define CANRXIDR2_ID8 _CANRXIDR2.Bits.ID8
|
| 5940 |
|
|
#define CANRXIDR2_ID9 _CANRXIDR2.Bits.ID9
|
| 5941 |
|
|
#define CANRXIDR2_ID10 _CANRXIDR2.Bits.ID10
|
| 5942 |
|
|
#define CANRXIDR2_ID11 _CANRXIDR2.Bits.ID11
|
| 5943 |
|
|
#define CANRXIDR2_ID12 _CANRXIDR2.Bits.ID12
|
| 5944 |
|
|
#define CANRXIDR2_ID13 _CANRXIDR2.Bits.ID13
|
| 5945 |
|
|
#define CANRXIDR2_ID14 _CANRXIDR2.Bits.ID14
|
| 5946 |
|
|
#define CANRXIDR2_ID_7 _CANRXIDR2.MergedBits.grpID_7
|
| 5947 |
|
|
#define CANRXIDR2_ID CANRXIDR2_ID_7
|
| 5948 |
|
|
|
| 5949 |
|
|
|
| 5950 |
|
|
/*** CANRXIDR3 - MSCAN Receive Identifier Register 3; 0x00000163 ***/
|
| 5951 |
|
|
typedef union {
|
| 5952 |
|
|
byte Byte;
|
| 5953 |
|
|
struct {
|
| 5954 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 5955 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 5956 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 5957 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 5958 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 5959 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 5960 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 5961 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 5962 |
|
|
} Bits;
|
| 5963 |
|
|
struct {
|
| 5964 |
|
|
byte :1;
|
| 5965 |
|
|
byte grpID :7;
|
| 5966 |
|
|
} MergedBits;
|
| 5967 |
|
|
} CANRXIDR3STR;
|
| 5968 |
|
|
extern volatile CANRXIDR3STR _CANRXIDR3 @(REG_BASE + 0x00000163);
|
| 5969 |
|
|
#define CANRXIDR3 _CANRXIDR3.Byte
|
| 5970 |
|
|
#define CANRXIDR3_RTR _CANRXIDR3.Bits.RTR
|
| 5971 |
|
|
#define CANRXIDR3_ID0 _CANRXIDR3.Bits.ID0
|
| 5972 |
|
|
#define CANRXIDR3_ID1 _CANRXIDR3.Bits.ID1
|
| 5973 |
|
|
#define CANRXIDR3_ID2 _CANRXIDR3.Bits.ID2
|
| 5974 |
|
|
#define CANRXIDR3_ID3 _CANRXIDR3.Bits.ID3
|
| 5975 |
|
|
#define CANRXIDR3_ID4 _CANRXIDR3.Bits.ID4
|
| 5976 |
|
|
#define CANRXIDR3_ID5 _CANRXIDR3.Bits.ID5
|
| 5977 |
|
|
#define CANRXIDR3_ID6 _CANRXIDR3.Bits.ID6
|
| 5978 |
|
|
#define CANRXIDR3_ID _CANRXIDR3.MergedBits.grpID
|
| 5979 |
|
|
|
| 5980 |
|
|
|
| 5981 |
|
|
/*** CANRXDSR0 - MSCAN Receive Data Segment Register 0; 0x00000164 ***/
|
| 5982 |
|
|
typedef union {
|
| 5983 |
|
|
byte Byte;
|
| 5984 |
|
|
struct {
|
| 5985 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 5986 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 5987 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 5988 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 5989 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 5990 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 5991 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 5992 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 5993 |
|
|
} Bits;
|
| 5994 |
|
|
struct {
|
| 5995 |
|
|
byte grpDB :8;
|
| 5996 |
|
|
} MergedBits;
|
| 5997 |
|
|
} CANRXDSR0STR;
|
| 5998 |
|
|
extern volatile CANRXDSR0STR _CANRXDSR0 @(REG_BASE + 0x00000164);
|
| 5999 |
|
|
#define CANRXDSR0 _CANRXDSR0.Byte
|
| 6000 |
|
|
#define CANRXDSR0_DB0 _CANRXDSR0.Bits.DB0
|
| 6001 |
|
|
#define CANRXDSR0_DB1 _CANRXDSR0.Bits.DB1
|
| 6002 |
|
|
#define CANRXDSR0_DB2 _CANRXDSR0.Bits.DB2
|
| 6003 |
|
|
#define CANRXDSR0_DB3 _CANRXDSR0.Bits.DB3
|
| 6004 |
|
|
#define CANRXDSR0_DB4 _CANRXDSR0.Bits.DB4
|
| 6005 |
|
|
#define CANRXDSR0_DB5 _CANRXDSR0.Bits.DB5
|
| 6006 |
|
|
#define CANRXDSR0_DB6 _CANRXDSR0.Bits.DB6
|
| 6007 |
|
|
#define CANRXDSR0_DB7 _CANRXDSR0.Bits.DB7
|
| 6008 |
|
|
#define CANRXDSR0_DB _CANRXDSR0.MergedBits.grpDB
|
| 6009 |
|
|
|
| 6010 |
|
|
|
| 6011 |
|
|
/*** CANRXDSR1 - MSCAN Receive Data Segment Register 1; 0x00000165 ***/
|
| 6012 |
|
|
typedef union {
|
| 6013 |
|
|
byte Byte;
|
| 6014 |
|
|
struct {
|
| 6015 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6016 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6017 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6018 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6019 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6020 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6021 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6022 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6023 |
|
|
} Bits;
|
| 6024 |
|
|
struct {
|
| 6025 |
|
|
byte grpDB :8;
|
| 6026 |
|
|
} MergedBits;
|
| 6027 |
|
|
} CANRXDSR1STR;
|
| 6028 |
|
|
extern volatile CANRXDSR1STR _CANRXDSR1 @(REG_BASE + 0x00000165);
|
| 6029 |
|
|
#define CANRXDSR1 _CANRXDSR1.Byte
|
| 6030 |
|
|
#define CANRXDSR1_DB0 _CANRXDSR1.Bits.DB0
|
| 6031 |
|
|
#define CANRXDSR1_DB1 _CANRXDSR1.Bits.DB1
|
| 6032 |
|
|
#define CANRXDSR1_DB2 _CANRXDSR1.Bits.DB2
|
| 6033 |
|
|
#define CANRXDSR1_DB3 _CANRXDSR1.Bits.DB3
|
| 6034 |
|
|
#define CANRXDSR1_DB4 _CANRXDSR1.Bits.DB4
|
| 6035 |
|
|
#define CANRXDSR1_DB5 _CANRXDSR1.Bits.DB5
|
| 6036 |
|
|
#define CANRXDSR1_DB6 _CANRXDSR1.Bits.DB6
|
| 6037 |
|
|
#define CANRXDSR1_DB7 _CANRXDSR1.Bits.DB7
|
| 6038 |
|
|
#define CANRXDSR1_DB _CANRXDSR1.MergedBits.grpDB
|
| 6039 |
|
|
|
| 6040 |
|
|
|
| 6041 |
|
|
/*** CANRXDSR2 - MSCAN Receive Data Segment Register 2; 0x00000166 ***/
|
| 6042 |
|
|
typedef union {
|
| 6043 |
|
|
byte Byte;
|
| 6044 |
|
|
struct {
|
| 6045 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6046 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6047 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6048 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6049 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6050 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6051 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6052 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6053 |
|
|
} Bits;
|
| 6054 |
|
|
struct {
|
| 6055 |
|
|
byte grpDB :8;
|
| 6056 |
|
|
} MergedBits;
|
| 6057 |
|
|
} CANRXDSR2STR;
|
| 6058 |
|
|
extern volatile CANRXDSR2STR _CANRXDSR2 @(REG_BASE + 0x00000166);
|
| 6059 |
|
|
#define CANRXDSR2 _CANRXDSR2.Byte
|
| 6060 |
|
|
#define CANRXDSR2_DB0 _CANRXDSR2.Bits.DB0
|
| 6061 |
|
|
#define CANRXDSR2_DB1 _CANRXDSR2.Bits.DB1
|
| 6062 |
|
|
#define CANRXDSR2_DB2 _CANRXDSR2.Bits.DB2
|
| 6063 |
|
|
#define CANRXDSR2_DB3 _CANRXDSR2.Bits.DB3
|
| 6064 |
|
|
#define CANRXDSR2_DB4 _CANRXDSR2.Bits.DB4
|
| 6065 |
|
|
#define CANRXDSR2_DB5 _CANRXDSR2.Bits.DB5
|
| 6066 |
|
|
#define CANRXDSR2_DB6 _CANRXDSR2.Bits.DB6
|
| 6067 |
|
|
#define CANRXDSR2_DB7 _CANRXDSR2.Bits.DB7
|
| 6068 |
|
|
#define CANRXDSR2_DB _CANRXDSR2.MergedBits.grpDB
|
| 6069 |
|
|
|
| 6070 |
|
|
|
| 6071 |
|
|
/*** CANRXDSR3 - MSCAN Receive Data Segment Register 3; 0x00000167 ***/
|
| 6072 |
|
|
typedef union {
|
| 6073 |
|
|
byte Byte;
|
| 6074 |
|
|
struct {
|
| 6075 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6076 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6077 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6078 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6079 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6080 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6081 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6082 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6083 |
|
|
} Bits;
|
| 6084 |
|
|
struct {
|
| 6085 |
|
|
byte grpDB :8;
|
| 6086 |
|
|
} MergedBits;
|
| 6087 |
|
|
} CANRXDSR3STR;
|
| 6088 |
|
|
extern volatile CANRXDSR3STR _CANRXDSR3 @(REG_BASE + 0x00000167);
|
| 6089 |
|
|
#define CANRXDSR3 _CANRXDSR3.Byte
|
| 6090 |
|
|
#define CANRXDSR3_DB0 _CANRXDSR3.Bits.DB0
|
| 6091 |
|
|
#define CANRXDSR3_DB1 _CANRXDSR3.Bits.DB1
|
| 6092 |
|
|
#define CANRXDSR3_DB2 _CANRXDSR3.Bits.DB2
|
| 6093 |
|
|
#define CANRXDSR3_DB3 _CANRXDSR3.Bits.DB3
|
| 6094 |
|
|
#define CANRXDSR3_DB4 _CANRXDSR3.Bits.DB4
|
| 6095 |
|
|
#define CANRXDSR3_DB5 _CANRXDSR3.Bits.DB5
|
| 6096 |
|
|
#define CANRXDSR3_DB6 _CANRXDSR3.Bits.DB6
|
| 6097 |
|
|
#define CANRXDSR3_DB7 _CANRXDSR3.Bits.DB7
|
| 6098 |
|
|
#define CANRXDSR3_DB _CANRXDSR3.MergedBits.grpDB
|
| 6099 |
|
|
|
| 6100 |
|
|
|
| 6101 |
|
|
/*** CANRXDSR4 - MSCAN Receive Data Segment Register 4; 0x00000168 ***/
|
| 6102 |
|
|
typedef union {
|
| 6103 |
|
|
byte Byte;
|
| 6104 |
|
|
struct {
|
| 6105 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6106 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6107 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6108 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6109 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6110 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6111 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6112 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6113 |
|
|
} Bits;
|
| 6114 |
|
|
struct {
|
| 6115 |
|
|
byte grpDB :8;
|
| 6116 |
|
|
} MergedBits;
|
| 6117 |
|
|
} CANRXDSR4STR;
|
| 6118 |
|
|
extern volatile CANRXDSR4STR _CANRXDSR4 @(REG_BASE + 0x00000168);
|
| 6119 |
|
|
#define CANRXDSR4 _CANRXDSR4.Byte
|
| 6120 |
|
|
#define CANRXDSR4_DB0 _CANRXDSR4.Bits.DB0
|
| 6121 |
|
|
#define CANRXDSR4_DB1 _CANRXDSR4.Bits.DB1
|
| 6122 |
|
|
#define CANRXDSR4_DB2 _CANRXDSR4.Bits.DB2
|
| 6123 |
|
|
#define CANRXDSR4_DB3 _CANRXDSR4.Bits.DB3
|
| 6124 |
|
|
#define CANRXDSR4_DB4 _CANRXDSR4.Bits.DB4
|
| 6125 |
|
|
#define CANRXDSR4_DB5 _CANRXDSR4.Bits.DB5
|
| 6126 |
|
|
#define CANRXDSR4_DB6 _CANRXDSR4.Bits.DB6
|
| 6127 |
|
|
#define CANRXDSR4_DB7 _CANRXDSR4.Bits.DB7
|
| 6128 |
|
|
#define CANRXDSR4_DB _CANRXDSR4.MergedBits.grpDB
|
| 6129 |
|
|
|
| 6130 |
|
|
|
| 6131 |
|
|
/*** CANRXDSR5 - MSCAN Receive Data Segment Register 5; 0x00000169 ***/
|
| 6132 |
|
|
typedef union {
|
| 6133 |
|
|
byte Byte;
|
| 6134 |
|
|
struct {
|
| 6135 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6136 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6137 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6138 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6139 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6140 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6141 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6142 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6143 |
|
|
} Bits;
|
| 6144 |
|
|
struct {
|
| 6145 |
|
|
byte grpDB :8;
|
| 6146 |
|
|
} MergedBits;
|
| 6147 |
|
|
} CANRXDSR5STR;
|
| 6148 |
|
|
extern volatile CANRXDSR5STR _CANRXDSR5 @(REG_BASE + 0x00000169);
|
| 6149 |
|
|
#define CANRXDSR5 _CANRXDSR5.Byte
|
| 6150 |
|
|
#define CANRXDSR5_DB0 _CANRXDSR5.Bits.DB0
|
| 6151 |
|
|
#define CANRXDSR5_DB1 _CANRXDSR5.Bits.DB1
|
| 6152 |
|
|
#define CANRXDSR5_DB2 _CANRXDSR5.Bits.DB2
|
| 6153 |
|
|
#define CANRXDSR5_DB3 _CANRXDSR5.Bits.DB3
|
| 6154 |
|
|
#define CANRXDSR5_DB4 _CANRXDSR5.Bits.DB4
|
| 6155 |
|
|
#define CANRXDSR5_DB5 _CANRXDSR5.Bits.DB5
|
| 6156 |
|
|
#define CANRXDSR5_DB6 _CANRXDSR5.Bits.DB6
|
| 6157 |
|
|
#define CANRXDSR5_DB7 _CANRXDSR5.Bits.DB7
|
| 6158 |
|
|
#define CANRXDSR5_DB _CANRXDSR5.MergedBits.grpDB
|
| 6159 |
|
|
|
| 6160 |
|
|
|
| 6161 |
|
|
/*** CANRXDSR6 - MSCAN Receive Data Segment Register 6; 0x0000016A ***/
|
| 6162 |
|
|
typedef union {
|
| 6163 |
|
|
byte Byte;
|
| 6164 |
|
|
struct {
|
| 6165 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6166 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6167 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6168 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6169 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6170 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6171 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6172 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6173 |
|
|
} Bits;
|
| 6174 |
|
|
struct {
|
| 6175 |
|
|
byte grpDB :8;
|
| 6176 |
|
|
} MergedBits;
|
| 6177 |
|
|
} CANRXDSR6STR;
|
| 6178 |
|
|
extern volatile CANRXDSR6STR _CANRXDSR6 @(REG_BASE + 0x0000016A);
|
| 6179 |
|
|
#define CANRXDSR6 _CANRXDSR6.Byte
|
| 6180 |
|
|
#define CANRXDSR6_DB0 _CANRXDSR6.Bits.DB0
|
| 6181 |
|
|
#define CANRXDSR6_DB1 _CANRXDSR6.Bits.DB1
|
| 6182 |
|
|
#define CANRXDSR6_DB2 _CANRXDSR6.Bits.DB2
|
| 6183 |
|
|
#define CANRXDSR6_DB3 _CANRXDSR6.Bits.DB3
|
| 6184 |
|
|
#define CANRXDSR6_DB4 _CANRXDSR6.Bits.DB4
|
| 6185 |
|
|
#define CANRXDSR6_DB5 _CANRXDSR6.Bits.DB5
|
| 6186 |
|
|
#define CANRXDSR6_DB6 _CANRXDSR6.Bits.DB6
|
| 6187 |
|
|
#define CANRXDSR6_DB7 _CANRXDSR6.Bits.DB7
|
| 6188 |
|
|
#define CANRXDSR6_DB _CANRXDSR6.MergedBits.grpDB
|
| 6189 |
|
|
|
| 6190 |
|
|
|
| 6191 |
|
|
/*** CANRXDSR7 - MSCAN Receive Data Segment Register 7; 0x0000016B ***/
|
| 6192 |
|
|
typedef union {
|
| 6193 |
|
|
byte Byte;
|
| 6194 |
|
|
struct {
|
| 6195 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6196 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6197 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6198 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6199 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6200 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6201 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6202 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6203 |
|
|
} Bits;
|
| 6204 |
|
|
struct {
|
| 6205 |
|
|
byte grpDB :8;
|
| 6206 |
|
|
} MergedBits;
|
| 6207 |
|
|
} CANRXDSR7STR;
|
| 6208 |
|
|
extern volatile CANRXDSR7STR _CANRXDSR7 @(REG_BASE + 0x0000016B);
|
| 6209 |
|
|
#define CANRXDSR7 _CANRXDSR7.Byte
|
| 6210 |
|
|
#define CANRXDSR7_DB0 _CANRXDSR7.Bits.DB0
|
| 6211 |
|
|
#define CANRXDSR7_DB1 _CANRXDSR7.Bits.DB1
|
| 6212 |
|
|
#define CANRXDSR7_DB2 _CANRXDSR7.Bits.DB2
|
| 6213 |
|
|
#define CANRXDSR7_DB3 _CANRXDSR7.Bits.DB3
|
| 6214 |
|
|
#define CANRXDSR7_DB4 _CANRXDSR7.Bits.DB4
|
| 6215 |
|
|
#define CANRXDSR7_DB5 _CANRXDSR7.Bits.DB5
|
| 6216 |
|
|
#define CANRXDSR7_DB6 _CANRXDSR7.Bits.DB6
|
| 6217 |
|
|
#define CANRXDSR7_DB7 _CANRXDSR7.Bits.DB7
|
| 6218 |
|
|
#define CANRXDSR7_DB _CANRXDSR7.MergedBits.grpDB
|
| 6219 |
|
|
|
| 6220 |
|
|
|
| 6221 |
|
|
/*** CANRXDLR - MSCAN Receive Data Length Register; 0x0000016C ***/
|
| 6222 |
|
|
typedef union {
|
| 6223 |
|
|
byte Byte;
|
| 6224 |
|
|
struct {
|
| 6225 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 6226 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 6227 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 6228 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 6229 |
|
|
byte :1;
|
| 6230 |
|
|
byte :1;
|
| 6231 |
|
|
byte :1;
|
| 6232 |
|
|
byte :1;
|
| 6233 |
|
|
} Bits;
|
| 6234 |
|
|
struct {
|
| 6235 |
|
|
byte grpDLC :4;
|
| 6236 |
|
|
byte :1;
|
| 6237 |
|
|
byte :1;
|
| 6238 |
|
|
byte :1;
|
| 6239 |
|
|
byte :1;
|
| 6240 |
|
|
} MergedBits;
|
| 6241 |
|
|
} CANRXDLRSTR;
|
| 6242 |
|
|
extern volatile CANRXDLRSTR _CANRXDLR @(REG_BASE + 0x0000016C);
|
| 6243 |
|
|
#define CANRXDLR _CANRXDLR.Byte
|
| 6244 |
|
|
#define CANRXDLR_DLC0 _CANRXDLR.Bits.DLC0
|
| 6245 |
|
|
#define CANRXDLR_DLC1 _CANRXDLR.Bits.DLC1
|
| 6246 |
|
|
#define CANRXDLR_DLC2 _CANRXDLR.Bits.DLC2
|
| 6247 |
|
|
#define CANRXDLR_DLC3 _CANRXDLR.Bits.DLC3
|
| 6248 |
|
|
#define CANRXDLR_DLC _CANRXDLR.MergedBits.grpDLC
|
| 6249 |
|
|
|
| 6250 |
|
|
|
| 6251 |
|
|
/*** CANTXIDR0 - MSCAN Transmit Identifier Register 0; 0x00000170 ***/
|
| 6252 |
|
|
typedef union {
|
| 6253 |
|
|
byte Byte;
|
| 6254 |
|
|
struct {
|
| 6255 |
|
|
byte ID21 :1; /* Extended format identifier Bit 21 */
|
| 6256 |
|
|
byte ID22 :1; /* Extended format identifier Bit 22 */
|
| 6257 |
|
|
byte ID23 :1; /* Extended format identifier Bit 23 */
|
| 6258 |
|
|
byte ID24 :1; /* Extended format identifier Bit 24 */
|
| 6259 |
|
|
byte ID25 :1; /* Extended format identifier Bit 25 */
|
| 6260 |
|
|
byte ID26 :1; /* Extended format identifier Bit 26 */
|
| 6261 |
|
|
byte ID27 :1; /* Extended format identifier Bit 27 */
|
| 6262 |
|
|
byte ID28 :1; /* Extended format identifier Bit 28 */
|
| 6263 |
|
|
} Bits;
|
| 6264 |
|
|
struct {
|
| 6265 |
|
|
byte grpID_21 :8;
|
| 6266 |
|
|
} MergedBits;
|
| 6267 |
|
|
} CANTXIDR0STR;
|
| 6268 |
|
|
extern volatile CANTXIDR0STR _CANTXIDR0 @(REG_BASE + 0x00000170);
|
| 6269 |
|
|
#define CANTXIDR0 _CANTXIDR0.Byte
|
| 6270 |
|
|
#define CANTXIDR0_ID21 _CANTXIDR0.Bits.ID21
|
| 6271 |
|
|
#define CANTXIDR0_ID22 _CANTXIDR0.Bits.ID22
|
| 6272 |
|
|
#define CANTXIDR0_ID23 _CANTXIDR0.Bits.ID23
|
| 6273 |
|
|
#define CANTXIDR0_ID24 _CANTXIDR0.Bits.ID24
|
| 6274 |
|
|
#define CANTXIDR0_ID25 _CANTXIDR0.Bits.ID25
|
| 6275 |
|
|
#define CANTXIDR0_ID26 _CANTXIDR0.Bits.ID26
|
| 6276 |
|
|
#define CANTXIDR0_ID27 _CANTXIDR0.Bits.ID27
|
| 6277 |
|
|
#define CANTXIDR0_ID28 _CANTXIDR0.Bits.ID28
|
| 6278 |
|
|
#define CANTXIDR0_ID_21 _CANTXIDR0.MergedBits.grpID_21
|
| 6279 |
|
|
#define CANTXIDR0_ID CANTXIDR0_ID_21
|
| 6280 |
|
|
|
| 6281 |
|
|
|
| 6282 |
|
|
/*** CANTXIDR1 - MSCAN Transmit Identifier Register 1; 0x00000171 ***/
|
| 6283 |
|
|
typedef union {
|
| 6284 |
|
|
byte Byte;
|
| 6285 |
|
|
struct {
|
| 6286 |
|
|
byte ID15 :1; /* Extended format identifier Bit 15 */
|
| 6287 |
|
|
byte ID16 :1; /* Extended format identifier Bit 16 */
|
| 6288 |
|
|
byte ID17 :1; /* Extended format identifier Bit 17 */
|
| 6289 |
|
|
byte IDE :1; /* ID Extended */
|
| 6290 |
|
|
byte SRR :1; /* Substitute Remote Request */
|
| 6291 |
|
|
byte ID18 :1; /* Extended format identifier Bit 18 */
|
| 6292 |
|
|
byte ID19 :1; /* Extended format identifier Bit 19 */
|
| 6293 |
|
|
byte ID20 :1; /* Extended format identifier Bit 20 */
|
| 6294 |
|
|
} Bits;
|
| 6295 |
|
|
struct {
|
| 6296 |
|
|
byte grpID_15 :3;
|
| 6297 |
|
|
byte :1;
|
| 6298 |
|
|
byte :1;
|
| 6299 |
|
|
byte grpID_18 :3;
|
| 6300 |
|
|
} MergedBits;
|
| 6301 |
|
|
} CANTXIDR1STR;
|
| 6302 |
|
|
extern volatile CANTXIDR1STR _CANTXIDR1 @(REG_BASE + 0x00000171);
|
| 6303 |
|
|
#define CANTXIDR1 _CANTXIDR1.Byte
|
| 6304 |
|
|
#define CANTXIDR1_ID15 _CANTXIDR1.Bits.ID15
|
| 6305 |
|
|
#define CANTXIDR1_ID16 _CANTXIDR1.Bits.ID16
|
| 6306 |
|
|
#define CANTXIDR1_ID17 _CANTXIDR1.Bits.ID17
|
| 6307 |
|
|
#define CANTXIDR1_IDE _CANTXIDR1.Bits.IDE
|
| 6308 |
|
|
#define CANTXIDR1_SRR _CANTXIDR1.Bits.SRR
|
| 6309 |
|
|
#define CANTXIDR1_ID18 _CANTXIDR1.Bits.ID18
|
| 6310 |
|
|
#define CANTXIDR1_ID19 _CANTXIDR1.Bits.ID19
|
| 6311 |
|
|
#define CANTXIDR1_ID20 _CANTXIDR1.Bits.ID20
|
| 6312 |
|
|
#define CANTXIDR1_ID_15 _CANTXIDR1.MergedBits.grpID_15
|
| 6313 |
|
|
#define CANTXIDR1_ID_18 _CANTXIDR1.MergedBits.grpID_18
|
| 6314 |
|
|
#define CANTXIDR1_ID CANTXIDR1_ID_15
|
| 6315 |
|
|
|
| 6316 |
|
|
|
| 6317 |
|
|
/*** CANTXIDR2 - MSCAN Transmit Identifier Register 2; 0x00000172 ***/
|
| 6318 |
|
|
typedef union {
|
| 6319 |
|
|
byte Byte;
|
| 6320 |
|
|
struct {
|
| 6321 |
|
|
byte ID7 :1; /* Extended format identifier Bit 7 */
|
| 6322 |
|
|
byte ID8 :1; /* Extended format identifier Bit 8 */
|
| 6323 |
|
|
byte ID9 :1; /* Extended format identifier Bit 9 */
|
| 6324 |
|
|
byte ID10 :1; /* Extended format identifier Bit 10 */
|
| 6325 |
|
|
byte ID11 :1; /* Extended format identifier Bit 11 */
|
| 6326 |
|
|
byte ID12 :1; /* Extended format identifier Bit 12 */
|
| 6327 |
|
|
byte ID13 :1; /* Extended format identifier Bit 13 */
|
| 6328 |
|
|
byte ID14 :1; /* Extended format identifier Bit 14 */
|
| 6329 |
|
|
} Bits;
|
| 6330 |
|
|
struct {
|
| 6331 |
|
|
byte grpID_7 :8;
|
| 6332 |
|
|
} MergedBits;
|
| 6333 |
|
|
} CANTXIDR2STR;
|
| 6334 |
|
|
extern volatile CANTXIDR2STR _CANTXIDR2 @(REG_BASE + 0x00000172);
|
| 6335 |
|
|
#define CANTXIDR2 _CANTXIDR2.Byte
|
| 6336 |
|
|
#define CANTXIDR2_ID7 _CANTXIDR2.Bits.ID7
|
| 6337 |
|
|
#define CANTXIDR2_ID8 _CANTXIDR2.Bits.ID8
|
| 6338 |
|
|
#define CANTXIDR2_ID9 _CANTXIDR2.Bits.ID9
|
| 6339 |
|
|
#define CANTXIDR2_ID10 _CANTXIDR2.Bits.ID10
|
| 6340 |
|
|
#define CANTXIDR2_ID11 _CANTXIDR2.Bits.ID11
|
| 6341 |
|
|
#define CANTXIDR2_ID12 _CANTXIDR2.Bits.ID12
|
| 6342 |
|
|
#define CANTXIDR2_ID13 _CANTXIDR2.Bits.ID13
|
| 6343 |
|
|
#define CANTXIDR2_ID14 _CANTXIDR2.Bits.ID14
|
| 6344 |
|
|
#define CANTXIDR2_ID_7 _CANTXIDR2.MergedBits.grpID_7
|
| 6345 |
|
|
#define CANTXIDR2_ID CANTXIDR2_ID_7
|
| 6346 |
|
|
|
| 6347 |
|
|
|
| 6348 |
|
|
/*** CANTXIDR3 - MSCAN Transmit Identifier Register 3; 0x00000173 ***/
|
| 6349 |
|
|
typedef union {
|
| 6350 |
|
|
byte Byte;
|
| 6351 |
|
|
struct {
|
| 6352 |
|
|
byte RTR :1; /* Remote Transmission Request */
|
| 6353 |
|
|
byte ID0 :1; /* Extended format identifier Bit 0 */
|
| 6354 |
|
|
byte ID1 :1; /* Extended format identifier Bit 1 */
|
| 6355 |
|
|
byte ID2 :1; /* Extended format identifier Bit 2 */
|
| 6356 |
|
|
byte ID3 :1; /* Extended format identifier Bit 3 */
|
| 6357 |
|
|
byte ID4 :1; /* Extended format identifier Bit 4 */
|
| 6358 |
|
|
byte ID5 :1; /* Extended format identifier Bit 5 */
|
| 6359 |
|
|
byte ID6 :1; /* Extended format identifier Bit 6 */
|
| 6360 |
|
|
} Bits;
|
| 6361 |
|
|
struct {
|
| 6362 |
|
|
byte :1;
|
| 6363 |
|
|
byte grpID :7;
|
| 6364 |
|
|
} MergedBits;
|
| 6365 |
|
|
} CANTXIDR3STR;
|
| 6366 |
|
|
extern volatile CANTXIDR3STR _CANTXIDR3 @(REG_BASE + 0x00000173);
|
| 6367 |
|
|
#define CANTXIDR3 _CANTXIDR3.Byte
|
| 6368 |
|
|
#define CANTXIDR3_RTR _CANTXIDR3.Bits.RTR
|
| 6369 |
|
|
#define CANTXIDR3_ID0 _CANTXIDR3.Bits.ID0
|
| 6370 |
|
|
#define CANTXIDR3_ID1 _CANTXIDR3.Bits.ID1
|
| 6371 |
|
|
#define CANTXIDR3_ID2 _CANTXIDR3.Bits.ID2
|
| 6372 |
|
|
#define CANTXIDR3_ID3 _CANTXIDR3.Bits.ID3
|
| 6373 |
|
|
#define CANTXIDR3_ID4 _CANTXIDR3.Bits.ID4
|
| 6374 |
|
|
#define CANTXIDR3_ID5 _CANTXIDR3.Bits.ID5
|
| 6375 |
|
|
#define CANTXIDR3_ID6 _CANTXIDR3.Bits.ID6
|
| 6376 |
|
|
#define CANTXIDR3_ID _CANTXIDR3.MergedBits.grpID
|
| 6377 |
|
|
|
| 6378 |
|
|
|
| 6379 |
|
|
/*** CANTXDSR0 - MSCAN Transmit Data Segment Register 0; 0x00000174 ***/
|
| 6380 |
|
|
typedef union {
|
| 6381 |
|
|
byte Byte;
|
| 6382 |
|
|
struct {
|
| 6383 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6384 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6385 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6386 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6387 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6388 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6389 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6390 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6391 |
|
|
} Bits;
|
| 6392 |
|
|
struct {
|
| 6393 |
|
|
byte grpDB :8;
|
| 6394 |
|
|
} MergedBits;
|
| 6395 |
|
|
} CANTXDSR0STR;
|
| 6396 |
|
|
extern volatile CANTXDSR0STR _CANTXDSR0 @(REG_BASE + 0x00000174);
|
| 6397 |
|
|
#define CANTXDSR0 _CANTXDSR0.Byte
|
| 6398 |
|
|
#define CANTXDSR0_DB0 _CANTXDSR0.Bits.DB0
|
| 6399 |
|
|
#define CANTXDSR0_DB1 _CANTXDSR0.Bits.DB1
|
| 6400 |
|
|
#define CANTXDSR0_DB2 _CANTXDSR0.Bits.DB2
|
| 6401 |
|
|
#define CANTXDSR0_DB3 _CANTXDSR0.Bits.DB3
|
| 6402 |
|
|
#define CANTXDSR0_DB4 _CANTXDSR0.Bits.DB4
|
| 6403 |
|
|
#define CANTXDSR0_DB5 _CANTXDSR0.Bits.DB5
|
| 6404 |
|
|
#define CANTXDSR0_DB6 _CANTXDSR0.Bits.DB6
|
| 6405 |
|
|
#define CANTXDSR0_DB7 _CANTXDSR0.Bits.DB7
|
| 6406 |
|
|
#define CANTXDSR0_DB _CANTXDSR0.MergedBits.grpDB
|
| 6407 |
|
|
|
| 6408 |
|
|
|
| 6409 |
|
|
/*** CANTXDSR1 - MSCAN Transmit Data Segment Register 1; 0x00000175 ***/
|
| 6410 |
|
|
typedef union {
|
| 6411 |
|
|
byte Byte;
|
| 6412 |
|
|
struct {
|
| 6413 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6414 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6415 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6416 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6417 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6418 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6419 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6420 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6421 |
|
|
} Bits;
|
| 6422 |
|
|
struct {
|
| 6423 |
|
|
byte grpDB :8;
|
| 6424 |
|
|
} MergedBits;
|
| 6425 |
|
|
} CANTXDSR1STR;
|
| 6426 |
|
|
extern volatile CANTXDSR1STR _CANTXDSR1 @(REG_BASE + 0x00000175);
|
| 6427 |
|
|
#define CANTXDSR1 _CANTXDSR1.Byte
|
| 6428 |
|
|
#define CANTXDSR1_DB0 _CANTXDSR1.Bits.DB0
|
| 6429 |
|
|
#define CANTXDSR1_DB1 _CANTXDSR1.Bits.DB1
|
| 6430 |
|
|
#define CANTXDSR1_DB2 _CANTXDSR1.Bits.DB2
|
| 6431 |
|
|
#define CANTXDSR1_DB3 _CANTXDSR1.Bits.DB3
|
| 6432 |
|
|
#define CANTXDSR1_DB4 _CANTXDSR1.Bits.DB4
|
| 6433 |
|
|
#define CANTXDSR1_DB5 _CANTXDSR1.Bits.DB5
|
| 6434 |
|
|
#define CANTXDSR1_DB6 _CANTXDSR1.Bits.DB6
|
| 6435 |
|
|
#define CANTXDSR1_DB7 _CANTXDSR1.Bits.DB7
|
| 6436 |
|
|
#define CANTXDSR1_DB _CANTXDSR1.MergedBits.grpDB
|
| 6437 |
|
|
|
| 6438 |
|
|
|
| 6439 |
|
|
/*** CANTXDSR2 - MSCAN Transmit Data Segment Register 2; 0x00000176 ***/
|
| 6440 |
|
|
typedef union {
|
| 6441 |
|
|
byte Byte;
|
| 6442 |
|
|
struct {
|
| 6443 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6444 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6445 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6446 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6447 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6448 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6449 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6450 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6451 |
|
|
} Bits;
|
| 6452 |
|
|
struct {
|
| 6453 |
|
|
byte grpDB :8;
|
| 6454 |
|
|
} MergedBits;
|
| 6455 |
|
|
} CANTXDSR2STR;
|
| 6456 |
|
|
extern volatile CANTXDSR2STR _CANTXDSR2 @(REG_BASE + 0x00000176);
|
| 6457 |
|
|
#define CANTXDSR2 _CANTXDSR2.Byte
|
| 6458 |
|
|
#define CANTXDSR2_DB0 _CANTXDSR2.Bits.DB0
|
| 6459 |
|
|
#define CANTXDSR2_DB1 _CANTXDSR2.Bits.DB1
|
| 6460 |
|
|
#define CANTXDSR2_DB2 _CANTXDSR2.Bits.DB2
|
| 6461 |
|
|
#define CANTXDSR2_DB3 _CANTXDSR2.Bits.DB3
|
| 6462 |
|
|
#define CANTXDSR2_DB4 _CANTXDSR2.Bits.DB4
|
| 6463 |
|
|
#define CANTXDSR2_DB5 _CANTXDSR2.Bits.DB5
|
| 6464 |
|
|
#define CANTXDSR2_DB6 _CANTXDSR2.Bits.DB6
|
| 6465 |
|
|
#define CANTXDSR2_DB7 _CANTXDSR2.Bits.DB7
|
| 6466 |
|
|
#define CANTXDSR2_DB _CANTXDSR2.MergedBits.grpDB
|
| 6467 |
|
|
|
| 6468 |
|
|
|
| 6469 |
|
|
/*** CANTXDSR3 - MSCAN Transmit Data Segment Register 3; 0x00000177 ***/
|
| 6470 |
|
|
typedef union {
|
| 6471 |
|
|
byte Byte;
|
| 6472 |
|
|
struct {
|
| 6473 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6474 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6475 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6476 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6477 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6478 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6479 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6480 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6481 |
|
|
} Bits;
|
| 6482 |
|
|
struct {
|
| 6483 |
|
|
byte grpDB :8;
|
| 6484 |
|
|
} MergedBits;
|
| 6485 |
|
|
} CANTXDSR3STR;
|
| 6486 |
|
|
extern volatile CANTXDSR3STR _CANTXDSR3 @(REG_BASE + 0x00000177);
|
| 6487 |
|
|
#define CANTXDSR3 _CANTXDSR3.Byte
|
| 6488 |
|
|
#define CANTXDSR3_DB0 _CANTXDSR3.Bits.DB0
|
| 6489 |
|
|
#define CANTXDSR3_DB1 _CANTXDSR3.Bits.DB1
|
| 6490 |
|
|
#define CANTXDSR3_DB2 _CANTXDSR3.Bits.DB2
|
| 6491 |
|
|
#define CANTXDSR3_DB3 _CANTXDSR3.Bits.DB3
|
| 6492 |
|
|
#define CANTXDSR3_DB4 _CANTXDSR3.Bits.DB4
|
| 6493 |
|
|
#define CANTXDSR3_DB5 _CANTXDSR3.Bits.DB5
|
| 6494 |
|
|
#define CANTXDSR3_DB6 _CANTXDSR3.Bits.DB6
|
| 6495 |
|
|
#define CANTXDSR3_DB7 _CANTXDSR3.Bits.DB7
|
| 6496 |
|
|
#define CANTXDSR3_DB _CANTXDSR3.MergedBits.grpDB
|
| 6497 |
|
|
|
| 6498 |
|
|
|
| 6499 |
|
|
/*** CANTXDSR4 - MSCAN Transmit Data Segment Register 4; 0x00000178 ***/
|
| 6500 |
|
|
typedef union {
|
| 6501 |
|
|
byte Byte;
|
| 6502 |
|
|
struct {
|
| 6503 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6504 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6505 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6506 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6507 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6508 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6509 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6510 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6511 |
|
|
} Bits;
|
| 6512 |
|
|
struct {
|
| 6513 |
|
|
byte grpDB :8;
|
| 6514 |
|
|
} MergedBits;
|
| 6515 |
|
|
} CANTXDSR4STR;
|
| 6516 |
|
|
extern volatile CANTXDSR4STR _CANTXDSR4 @(REG_BASE + 0x00000178);
|
| 6517 |
|
|
#define CANTXDSR4 _CANTXDSR4.Byte
|
| 6518 |
|
|
#define CANTXDSR4_DB0 _CANTXDSR4.Bits.DB0
|
| 6519 |
|
|
#define CANTXDSR4_DB1 _CANTXDSR4.Bits.DB1
|
| 6520 |
|
|
#define CANTXDSR4_DB2 _CANTXDSR4.Bits.DB2
|
| 6521 |
|
|
#define CANTXDSR4_DB3 _CANTXDSR4.Bits.DB3
|
| 6522 |
|
|
#define CANTXDSR4_DB4 _CANTXDSR4.Bits.DB4
|
| 6523 |
|
|
#define CANTXDSR4_DB5 _CANTXDSR4.Bits.DB5
|
| 6524 |
|
|
#define CANTXDSR4_DB6 _CANTXDSR4.Bits.DB6
|
| 6525 |
|
|
#define CANTXDSR4_DB7 _CANTXDSR4.Bits.DB7
|
| 6526 |
|
|
#define CANTXDSR4_DB _CANTXDSR4.MergedBits.grpDB
|
| 6527 |
|
|
|
| 6528 |
|
|
|
| 6529 |
|
|
/*** CANTXDSR5 - MSCAN Transmit Data Segment Register 5; 0x00000179 ***/
|
| 6530 |
|
|
typedef union {
|
| 6531 |
|
|
byte Byte;
|
| 6532 |
|
|
struct {
|
| 6533 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6534 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6535 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6536 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6537 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6538 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6539 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6540 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6541 |
|
|
} Bits;
|
| 6542 |
|
|
struct {
|
| 6543 |
|
|
byte grpDB :8;
|
| 6544 |
|
|
} MergedBits;
|
| 6545 |
|
|
} CANTXDSR5STR;
|
| 6546 |
|
|
extern volatile CANTXDSR5STR _CANTXDSR5 @(REG_BASE + 0x00000179);
|
| 6547 |
|
|
#define CANTXDSR5 _CANTXDSR5.Byte
|
| 6548 |
|
|
#define CANTXDSR5_DB0 _CANTXDSR5.Bits.DB0
|
| 6549 |
|
|
#define CANTXDSR5_DB1 _CANTXDSR5.Bits.DB1
|
| 6550 |
|
|
#define CANTXDSR5_DB2 _CANTXDSR5.Bits.DB2
|
| 6551 |
|
|
#define CANTXDSR5_DB3 _CANTXDSR5.Bits.DB3
|
| 6552 |
|
|
#define CANTXDSR5_DB4 _CANTXDSR5.Bits.DB4
|
| 6553 |
|
|
#define CANTXDSR5_DB5 _CANTXDSR5.Bits.DB5
|
| 6554 |
|
|
#define CANTXDSR5_DB6 _CANTXDSR5.Bits.DB6
|
| 6555 |
|
|
#define CANTXDSR5_DB7 _CANTXDSR5.Bits.DB7
|
| 6556 |
|
|
#define CANTXDSR5_DB _CANTXDSR5.MergedBits.grpDB
|
| 6557 |
|
|
|
| 6558 |
|
|
|
| 6559 |
|
|
/*** CANTXDSR6 - MSCAN Transmit Data Segment Register 6; 0x0000017A ***/
|
| 6560 |
|
|
typedef union {
|
| 6561 |
|
|
byte Byte;
|
| 6562 |
|
|
struct {
|
| 6563 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6564 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6565 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6566 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6567 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6568 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6569 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6570 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6571 |
|
|
} Bits;
|
| 6572 |
|
|
struct {
|
| 6573 |
|
|
byte grpDB :8;
|
| 6574 |
|
|
} MergedBits;
|
| 6575 |
|
|
} CANTXDSR6STR;
|
| 6576 |
|
|
extern volatile CANTXDSR6STR _CANTXDSR6 @(REG_BASE + 0x0000017A);
|
| 6577 |
|
|
#define CANTXDSR6 _CANTXDSR6.Byte
|
| 6578 |
|
|
#define CANTXDSR6_DB0 _CANTXDSR6.Bits.DB0
|
| 6579 |
|
|
#define CANTXDSR6_DB1 _CANTXDSR6.Bits.DB1
|
| 6580 |
|
|
#define CANTXDSR6_DB2 _CANTXDSR6.Bits.DB2
|
| 6581 |
|
|
#define CANTXDSR6_DB3 _CANTXDSR6.Bits.DB3
|
| 6582 |
|
|
#define CANTXDSR6_DB4 _CANTXDSR6.Bits.DB4
|
| 6583 |
|
|
#define CANTXDSR6_DB5 _CANTXDSR6.Bits.DB5
|
| 6584 |
|
|
#define CANTXDSR6_DB6 _CANTXDSR6.Bits.DB6
|
| 6585 |
|
|
#define CANTXDSR6_DB7 _CANTXDSR6.Bits.DB7
|
| 6586 |
|
|
#define CANTXDSR6_DB _CANTXDSR6.MergedBits.grpDB
|
| 6587 |
|
|
|
| 6588 |
|
|
|
| 6589 |
|
|
/*** CANTXDSR7 - MSCAN Transmit Data Segment Register 7; 0x0000017B ***/
|
| 6590 |
|
|
typedef union {
|
| 6591 |
|
|
byte Byte;
|
| 6592 |
|
|
struct {
|
| 6593 |
|
|
byte DB0 :1; /* Data Bit 0 */
|
| 6594 |
|
|
byte DB1 :1; /* Data Bit 1 */
|
| 6595 |
|
|
byte DB2 :1; /* Data Bit 2 */
|
| 6596 |
|
|
byte DB3 :1; /* Data Bit 3 */
|
| 6597 |
|
|
byte DB4 :1; /* Data Bit 4 */
|
| 6598 |
|
|
byte DB5 :1; /* Data Bit 5 */
|
| 6599 |
|
|
byte DB6 :1; /* Data Bit 6 */
|
| 6600 |
|
|
byte DB7 :1; /* Data Bit 7 */
|
| 6601 |
|
|
} Bits;
|
| 6602 |
|
|
struct {
|
| 6603 |
|
|
byte grpDB :8;
|
| 6604 |
|
|
} MergedBits;
|
| 6605 |
|
|
} CANTXDSR7STR;
|
| 6606 |
|
|
extern volatile CANTXDSR7STR _CANTXDSR7 @(REG_BASE + 0x0000017B);
|
| 6607 |
|
|
#define CANTXDSR7 _CANTXDSR7.Byte
|
| 6608 |
|
|
#define CANTXDSR7_DB0 _CANTXDSR7.Bits.DB0
|
| 6609 |
|
|
#define CANTXDSR7_DB1 _CANTXDSR7.Bits.DB1
|
| 6610 |
|
|
#define CANTXDSR7_DB2 _CANTXDSR7.Bits.DB2
|
| 6611 |
|
|
#define CANTXDSR7_DB3 _CANTXDSR7.Bits.DB3
|
| 6612 |
|
|
#define CANTXDSR7_DB4 _CANTXDSR7.Bits.DB4
|
| 6613 |
|
|
#define CANTXDSR7_DB5 _CANTXDSR7.Bits.DB5
|
| 6614 |
|
|
#define CANTXDSR7_DB6 _CANTXDSR7.Bits.DB6
|
| 6615 |
|
|
#define CANTXDSR7_DB7 _CANTXDSR7.Bits.DB7
|
| 6616 |
|
|
#define CANTXDSR7_DB _CANTXDSR7.MergedBits.grpDB
|
| 6617 |
|
|
|
| 6618 |
|
|
|
| 6619 |
|
|
/*** CANTXDLR - MSCAN Transmit Data Length Register; 0x0000017C ***/
|
| 6620 |
|
|
typedef union {
|
| 6621 |
|
|
byte Byte;
|
| 6622 |
|
|
struct {
|
| 6623 |
|
|
byte DLC0 :1; /* Data Length Code Bit 0 */
|
| 6624 |
|
|
byte DLC1 :1; /* Data Length Code Bit 1 */
|
| 6625 |
|
|
byte DLC2 :1; /* Data Length Code Bit 2 */
|
| 6626 |
|
|
byte DLC3 :1; /* Data Length Code Bit 3 */
|
| 6627 |
|
|
byte :1;
|
| 6628 |
|
|
byte :1;
|
| 6629 |
|
|
byte :1;
|
| 6630 |
|
|
byte :1;
|
| 6631 |
|
|
} Bits;
|
| 6632 |
|
|
struct {
|
| 6633 |
|
|
byte grpDLC :4;
|
| 6634 |
|
|
byte :1;
|
| 6635 |
|
|
byte :1;
|
| 6636 |
|
|
byte :1;
|
| 6637 |
|
|
byte :1;
|
| 6638 |
|
|
} MergedBits;
|
| 6639 |
|
|
} CANTXDLRSTR;
|
| 6640 |
|
|
extern volatile CANTXDLRSTR _CANTXDLR @(REG_BASE + 0x0000017C);
|
| 6641 |
|
|
#define CANTXDLR _CANTXDLR.Byte
|
| 6642 |
|
|
#define CANTXDLR_DLC0 _CANTXDLR.Bits.DLC0
|
| 6643 |
|
|
#define CANTXDLR_DLC1 _CANTXDLR.Bits.DLC1
|
| 6644 |
|
|
#define CANTXDLR_DLC2 _CANTXDLR.Bits.DLC2
|
| 6645 |
|
|
#define CANTXDLR_DLC3 _CANTXDLR.Bits.DLC3
|
| 6646 |
|
|
#define CANTXDLR_DLC _CANTXDLR.MergedBits.grpDLC
|
| 6647 |
|
|
|
| 6648 |
|
|
|
| 6649 |
|
|
/*** CANTXTBPR - MSCAN Transmit Buffer Priority; 0x0000017F ***/
|
| 6650 |
|
|
typedef union {
|
| 6651 |
|
|
byte Byte;
|
| 6652 |
|
|
struct {
|
| 6653 |
|
|
byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
|
| 6654 |
|
|
byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
|
| 6655 |
|
|
byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
|
| 6656 |
|
|
byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
|
| 6657 |
|
|
byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
|
| 6658 |
|
|
byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
|
| 6659 |
|
|
byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
|
| 6660 |
|
|
byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
|
| 6661 |
|
|
} Bits;
|
| 6662 |
|
|
struct {
|
| 6663 |
|
|
byte grpPRIO :8;
|
| 6664 |
|
|
} MergedBits;
|
| 6665 |
|
|
} CANTXTBPRSTR;
|
| 6666 |
|
|
extern volatile CANTXTBPRSTR _CANTXTBPR @(REG_BASE + 0x0000017F);
|
| 6667 |
|
|
#define CANTXTBPR _CANTXTBPR.Byte
|
| 6668 |
|
|
#define CANTXTBPR_PRIO0 _CANTXTBPR.Bits.PRIO0
|
| 6669 |
|
|
#define CANTXTBPR_PRIO1 _CANTXTBPR.Bits.PRIO1
|
| 6670 |
|
|
#define CANTXTBPR_PRIO2 _CANTXTBPR.Bits.PRIO2
|
| 6671 |
|
|
#define CANTXTBPR_PRIO3 _CANTXTBPR.Bits.PRIO3
|
| 6672 |
|
|
#define CANTXTBPR_PRIO4 _CANTXTBPR.Bits.PRIO4
|
| 6673 |
|
|
#define CANTXTBPR_PRIO5 _CANTXTBPR.Bits.PRIO5
|
| 6674 |
|
|
#define CANTXTBPR_PRIO6 _CANTXTBPR.Bits.PRIO6
|
| 6675 |
|
|
#define CANTXTBPR_PRIO7 _CANTXTBPR.Bits.PRIO7
|
| 6676 |
|
|
#define CANTXTBPR_PRIO _CANTXTBPR.MergedBits.grpPRIO
|
| 6677 |
|
|
|
| 6678 |
|
|
|
| 6679 |
|
|
/*** PTT - Port T I/O Register; 0x00000240 ***/
|
| 6680 |
|
|
typedef union {
|
| 6681 |
|
|
byte Byte;
|
| 6682 |
|
|
struct {
|
| 6683 |
|
|
byte PTT0 :1; /* Port T Bit 0 */
|
| 6684 |
|
|
byte PTT1 :1; /* Port T Bit 1 */
|
| 6685 |
|
|
byte PTT2 :1; /* Port T Bit 2 */
|
| 6686 |
|
|
byte PTT3 :1; /* Port T Bit 3 */
|
| 6687 |
|
|
byte PTT4 :1; /* Port T Bit 4 */
|
| 6688 |
|
|
byte PTT5 :1; /* Port T Bit 5 */
|
| 6689 |
|
|
byte PTT6 :1; /* Port T Bit 6 */
|
| 6690 |
|
|
byte PTT7 :1; /* Port T Bit 7 */
|
| 6691 |
|
|
} Bits;
|
| 6692 |
|
|
struct {
|
| 6693 |
|
|
byte grpPTT :8;
|
| 6694 |
|
|
} MergedBits;
|
| 6695 |
|
|
} PTTSTR;
|
| 6696 |
|
|
extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240);
|
| 6697 |
|
|
#define PTT _PTT.Byte
|
| 6698 |
|
|
#define PTT_PTT0 _PTT.Bits.PTT0
|
| 6699 |
|
|
#define PTT_PTT1 _PTT.Bits.PTT1
|
| 6700 |
|
|
#define PTT_PTT2 _PTT.Bits.PTT2
|
| 6701 |
|
|
#define PTT_PTT3 _PTT.Bits.PTT3
|
| 6702 |
|
|
#define PTT_PTT4 _PTT.Bits.PTT4
|
| 6703 |
|
|
#define PTT_PTT5 _PTT.Bits.PTT5
|
| 6704 |
|
|
#define PTT_PTT6 _PTT.Bits.PTT6
|
| 6705 |
|
|
#define PTT_PTT7 _PTT.Bits.PTT7
|
| 6706 |
|
|
#define PTT_PTT _PTT.MergedBits.grpPTT
|
| 6707 |
|
|
|
| 6708 |
|
|
|
| 6709 |
|
|
/*** PTIT - Port T Input; 0x00000241 ***/
|
| 6710 |
|
|
typedef union {
|
| 6711 |
|
|
byte Byte;
|
| 6712 |
|
|
struct {
|
| 6713 |
|
|
byte PTIT0 :1; /* Port T Bit 0 */
|
| 6714 |
|
|
byte PTIT1 :1; /* Port T Bit 1 */
|
| 6715 |
|
|
byte PTIT2 :1; /* Port T Bit 2 */
|
| 6716 |
|
|
byte PTIT3 :1; /* Port T Bit 3 */
|
| 6717 |
|
|
byte PTIT4 :1; /* Port T Bit 4 */
|
| 6718 |
|
|
byte PTIT5 :1; /* Port T Bit 5 */
|
| 6719 |
|
|
byte PTIT6 :1; /* Port T Bit 6 */
|
| 6720 |
|
|
byte PTIT7 :1; /* Port T Bit 7 */
|
| 6721 |
|
|
} Bits;
|
| 6722 |
|
|
struct {
|
| 6723 |
|
|
byte grpPTIT :8;
|
| 6724 |
|
|
} MergedBits;
|
| 6725 |
|
|
} PTITSTR;
|
| 6726 |
|
|
extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241);
|
| 6727 |
|
|
#define PTIT _PTIT.Byte
|
| 6728 |
|
|
#define PTIT_PTIT0 _PTIT.Bits.PTIT0
|
| 6729 |
|
|
#define PTIT_PTIT1 _PTIT.Bits.PTIT1
|
| 6730 |
|
|
#define PTIT_PTIT2 _PTIT.Bits.PTIT2
|
| 6731 |
|
|
#define PTIT_PTIT3 _PTIT.Bits.PTIT3
|
| 6732 |
|
|
#define PTIT_PTIT4 _PTIT.Bits.PTIT4
|
| 6733 |
|
|
#define PTIT_PTIT5 _PTIT.Bits.PTIT5
|
| 6734 |
|
|
#define PTIT_PTIT6 _PTIT.Bits.PTIT6
|
| 6735 |
|
|
#define PTIT_PTIT7 _PTIT.Bits.PTIT7
|
| 6736 |
|
|
#define PTIT_PTIT _PTIT.MergedBits.grpPTIT
|
| 6737 |
|
|
|
| 6738 |
|
|
|
| 6739 |
|
|
/*** DDRT - Port T Data Direction Register; 0x00000242 ***/
|
| 6740 |
|
|
typedef union {
|
| 6741 |
|
|
byte Byte;
|
| 6742 |
|
|
struct {
|
| 6743 |
|
|
byte DDRT0 :1; /* Data Direction Port T Bit 0 */
|
| 6744 |
|
|
byte DDRT1 :1; /* Data Direction Port T Bit 1 */
|
| 6745 |
|
|
byte DDRT2 :1; /* Data Direction Port T Bit 2 */
|
| 6746 |
|
|
byte DDRT3 :1; /* Data Direction Port T Bit 3 */
|
| 6747 |
|
|
byte DDRT4 :1; /* Data Direction Port T Bit 4 */
|
| 6748 |
|
|
byte DDRT5 :1; /* Data Direction Port T Bit 5 */
|
| 6749 |
|
|
byte DDRT6 :1; /* Data Direction Port T Bit 6 */
|
| 6750 |
|
|
byte DDRT7 :1; /* Data Direction Port T Bit 7 */
|
| 6751 |
|
|
} Bits;
|
| 6752 |
|
|
struct {
|
| 6753 |
|
|
byte grpDDRT :8;
|
| 6754 |
|
|
} MergedBits;
|
| 6755 |
|
|
} DDRTSTR;
|
| 6756 |
|
|
extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242);
|
| 6757 |
|
|
#define DDRT _DDRT.Byte
|
| 6758 |
|
|
#define DDRT_DDRT0 _DDRT.Bits.DDRT0
|
| 6759 |
|
|
#define DDRT_DDRT1 _DDRT.Bits.DDRT1
|
| 6760 |
|
|
#define DDRT_DDRT2 _DDRT.Bits.DDRT2
|
| 6761 |
|
|
#define DDRT_DDRT3 _DDRT.Bits.DDRT3
|
| 6762 |
|
|
#define DDRT_DDRT4 _DDRT.Bits.DDRT4
|
| 6763 |
|
|
#define DDRT_DDRT5 _DDRT.Bits.DDRT5
|
| 6764 |
|
|
#define DDRT_DDRT6 _DDRT.Bits.DDRT6
|
| 6765 |
|
|
#define DDRT_DDRT7 _DDRT.Bits.DDRT7
|
| 6766 |
|
|
#define DDRT_DDRT _DDRT.MergedBits.grpDDRT
|
| 6767 |
|
|
|
| 6768 |
|
|
|
| 6769 |
|
|
/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/
|
| 6770 |
|
|
typedef union {
|
| 6771 |
|
|
byte Byte;
|
| 6772 |
|
|
struct {
|
| 6773 |
|
|
byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */
|
| 6774 |
|
|
byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */
|
| 6775 |
|
|
byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */
|
| 6776 |
|
|
byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */
|
| 6777 |
|
|
byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */
|
| 6778 |
|
|
byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */
|
| 6779 |
|
|
byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */
|
| 6780 |
|
|
byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */
|
| 6781 |
|
|
} Bits;
|
| 6782 |
|
|
struct {
|
| 6783 |
|
|
byte grpRDRT :8;
|
| 6784 |
|
|
} MergedBits;
|
| 6785 |
|
|
} RDRTSTR;
|
| 6786 |
|
|
extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243);
|
| 6787 |
|
|
#define RDRT _RDRT.Byte
|
| 6788 |
|
|
#define RDRT_RDRT0 _RDRT.Bits.RDRT0
|
| 6789 |
|
|
#define RDRT_RDRT1 _RDRT.Bits.RDRT1
|
| 6790 |
|
|
#define RDRT_RDRT2 _RDRT.Bits.RDRT2
|
| 6791 |
|
|
#define RDRT_RDRT3 _RDRT.Bits.RDRT3
|
| 6792 |
|
|
#define RDRT_RDRT4 _RDRT.Bits.RDRT4
|
| 6793 |
|
|
#define RDRT_RDRT5 _RDRT.Bits.RDRT5
|
| 6794 |
|
|
#define RDRT_RDRT6 _RDRT.Bits.RDRT6
|
| 6795 |
|
|
#define RDRT_RDRT7 _RDRT.Bits.RDRT7
|
| 6796 |
|
|
#define RDRT_RDRT _RDRT.MergedBits.grpRDRT
|
| 6797 |
|
|
|
| 6798 |
|
|
|
| 6799 |
|
|
/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/
|
| 6800 |
|
|
typedef union {
|
| 6801 |
|
|
byte Byte;
|
| 6802 |
|
|
struct {
|
| 6803 |
|
|
byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */
|
| 6804 |
|
|
byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */
|
| 6805 |
|
|
byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */
|
| 6806 |
|
|
byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */
|
| 6807 |
|
|
byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */
|
| 6808 |
|
|
byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */
|
| 6809 |
|
|
byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */
|
| 6810 |
|
|
byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */
|
| 6811 |
|
|
} Bits;
|
| 6812 |
|
|
struct {
|
| 6813 |
|
|
byte grpPERT :8;
|
| 6814 |
|
|
} MergedBits;
|
| 6815 |
|
|
} PERTSTR;
|
| 6816 |
|
|
extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244);
|
| 6817 |
|
|
#define PERT _PERT.Byte
|
| 6818 |
|
|
#define PERT_PERT0 _PERT.Bits.PERT0
|
| 6819 |
|
|
#define PERT_PERT1 _PERT.Bits.PERT1
|
| 6820 |
|
|
#define PERT_PERT2 _PERT.Bits.PERT2
|
| 6821 |
|
|
#define PERT_PERT3 _PERT.Bits.PERT3
|
| 6822 |
|
|
#define PERT_PERT4 _PERT.Bits.PERT4
|
| 6823 |
|
|
#define PERT_PERT5 _PERT.Bits.PERT5
|
| 6824 |
|
|
#define PERT_PERT6 _PERT.Bits.PERT6
|
| 6825 |
|
|
#define PERT_PERT7 _PERT.Bits.PERT7
|
| 6826 |
|
|
#define PERT_PERT _PERT.MergedBits.grpPERT
|
| 6827 |
|
|
|
| 6828 |
|
|
|
| 6829 |
|
|
/*** PPST - Port T Polarity Select Register; 0x00000245 ***/
|
| 6830 |
|
|
typedef union {
|
| 6831 |
|
|
byte Byte;
|
| 6832 |
|
|
struct {
|
| 6833 |
|
|
byte PPST0 :1; /* Pull Select Port T Bit 0 */
|
| 6834 |
|
|
byte PPST1 :1; /* Pull Select Port T Bit 1 */
|
| 6835 |
|
|
byte PPST2 :1; /* Pull Select Port T Bit 2 */
|
| 6836 |
|
|
byte PPST3 :1; /* Pull Select Port T Bit 3 */
|
| 6837 |
|
|
byte PPST4 :1; /* Pull Select Port T Bit 4 */
|
| 6838 |
|
|
byte PPST5 :1; /* Pull Select Port T Bit 5 */
|
| 6839 |
|
|
byte PPST6 :1; /* Pull Select Port T Bit 6 */
|
| 6840 |
|
|
byte PPST7 :1; /* Pull Select Port T Bit 7 */
|
| 6841 |
|
|
} Bits;
|
| 6842 |
|
|
struct {
|
| 6843 |
|
|
byte grpPPST :8;
|
| 6844 |
|
|
} MergedBits;
|
| 6845 |
|
|
} PPSTSTR;
|
| 6846 |
|
|
extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245);
|
| 6847 |
|
|
#define PPST _PPST.Byte
|
| 6848 |
|
|
#define PPST_PPST0 _PPST.Bits.PPST0
|
| 6849 |
|
|
#define PPST_PPST1 _PPST.Bits.PPST1
|
| 6850 |
|
|
#define PPST_PPST2 _PPST.Bits.PPST2
|
| 6851 |
|
|
#define PPST_PPST3 _PPST.Bits.PPST3
|
| 6852 |
|
|
#define PPST_PPST4 _PPST.Bits.PPST4
|
| 6853 |
|
|
#define PPST_PPST5 _PPST.Bits.PPST5
|
| 6854 |
|
|
#define PPST_PPST6 _PPST.Bits.PPST6
|
| 6855 |
|
|
#define PPST_PPST7 _PPST.Bits.PPST7
|
| 6856 |
|
|
#define PPST_PPST _PPST.MergedBits.grpPPST
|
| 6857 |
|
|
|
| 6858 |
|
|
|
| 6859 |
|
|
/*** MODRR - Module Routing Register; 0x00000247 ***/
|
| 6860 |
|
|
typedef union {
|
| 6861 |
|
|
byte Byte;
|
| 6862 |
|
|
struct {
|
| 6863 |
|
|
byte MODRR0 :1; /* Module Routing Bit 0 */
|
| 6864 |
|
|
byte MODRR1 :1; /* Module Routing Bit 1 */
|
| 6865 |
|
|
byte MODRR2 :1; /* Module Routing Bit 2 */
|
| 6866 |
|
|
byte MODRR3 :1; /* Module Routing Bit 3 */
|
| 6867 |
|
|
byte MODRR4 :1; /* Module Routing Bit 4 */
|
| 6868 |
|
|
byte :1;
|
| 6869 |
|
|
byte :1;
|
| 6870 |
|
|
byte :1;
|
| 6871 |
|
|
} Bits;
|
| 6872 |
|
|
struct {
|
| 6873 |
|
|
byte grpMODRR :5;
|
| 6874 |
|
|
byte :1;
|
| 6875 |
|
|
byte :1;
|
| 6876 |
|
|
byte :1;
|
| 6877 |
|
|
} MergedBits;
|
| 6878 |
|
|
} MODRRSTR;
|
| 6879 |
|
|
extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000247);
|
| 6880 |
|
|
#define MODRR _MODRR.Byte
|
| 6881 |
|
|
#define MODRR_MODRR0 _MODRR.Bits.MODRR0
|
| 6882 |
|
|
#define MODRR_MODRR1 _MODRR.Bits.MODRR1
|
| 6883 |
|
|
#define MODRR_MODRR2 _MODRR.Bits.MODRR2
|
| 6884 |
|
|
#define MODRR_MODRR3 _MODRR.Bits.MODRR3
|
| 6885 |
|
|
#define MODRR_MODRR4 _MODRR.Bits.MODRR4
|
| 6886 |
|
|
#define MODRR_MODRR _MODRR.MergedBits.grpMODRR
|
| 6887 |
|
|
|
| 6888 |
|
|
|
| 6889 |
|
|
/*** PTS - Port S I/O Register; 0x00000248 ***/
|
| 6890 |
|
|
typedef union {
|
| 6891 |
|
|
byte Byte;
|
| 6892 |
|
|
struct {
|
| 6893 |
|
|
byte PTS0 :1; /* Port S Bit 0 */
|
| 6894 |
|
|
byte PTS1 :1; /* Port S Bit 1 */
|
| 6895 |
|
|
byte PTS2 :1; /* Port S Bit 2 */
|
| 6896 |
|
|
byte PTS3 :1; /* Port S Bit 3 */
|
| 6897 |
|
|
byte :1;
|
| 6898 |
|
|
byte :1;
|
| 6899 |
|
|
byte :1;
|
| 6900 |
|
|
byte :1;
|
| 6901 |
|
|
} Bits;
|
| 6902 |
|
|
struct {
|
| 6903 |
|
|
byte grpPTS :4;
|
| 6904 |
|
|
byte :1;
|
| 6905 |
|
|
byte :1;
|
| 6906 |
|
|
byte :1;
|
| 6907 |
|
|
byte :1;
|
| 6908 |
|
|
} MergedBits;
|
| 6909 |
|
|
} PTSSTR;
|
| 6910 |
|
|
extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248);
|
| 6911 |
|
|
#define PTS _PTS.Byte
|
| 6912 |
|
|
#define PTS_PTS0 _PTS.Bits.PTS0
|
| 6913 |
|
|
#define PTS_PTS1 _PTS.Bits.PTS1
|
| 6914 |
|
|
#define PTS_PTS2 _PTS.Bits.PTS2
|
| 6915 |
|
|
#define PTS_PTS3 _PTS.Bits.PTS3
|
| 6916 |
|
|
#define PTS_PTS _PTS.MergedBits.grpPTS
|
| 6917 |
|
|
|
| 6918 |
|
|
|
| 6919 |
|
|
/*** PTIS - Port S Input; 0x00000249 ***/
|
| 6920 |
|
|
typedef union {
|
| 6921 |
|
|
byte Byte;
|
| 6922 |
|
|
struct {
|
| 6923 |
|
|
byte PTIS0 :1; /* Port S Bit 0 */
|
| 6924 |
|
|
byte PTIS1 :1; /* Port S Bit 1 */
|
| 6925 |
|
|
byte PTIS2 :1; /* Port S Bit 2 */
|
| 6926 |
|
|
byte PTIS3 :1; /* Port S Bit 3 */
|
| 6927 |
|
|
byte :1;
|
| 6928 |
|
|
byte :1;
|
| 6929 |
|
|
byte :1;
|
| 6930 |
|
|
byte :1;
|
| 6931 |
|
|
} Bits;
|
| 6932 |
|
|
struct {
|
| 6933 |
|
|
byte grpPTIS :4;
|
| 6934 |
|
|
byte :1;
|
| 6935 |
|
|
byte :1;
|
| 6936 |
|
|
byte :1;
|
| 6937 |
|
|
byte :1;
|
| 6938 |
|
|
} MergedBits;
|
| 6939 |
|
|
} PTISSTR;
|
| 6940 |
|
|
extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249);
|
| 6941 |
|
|
#define PTIS _PTIS.Byte
|
| 6942 |
|
|
#define PTIS_PTIS0 _PTIS.Bits.PTIS0
|
| 6943 |
|
|
#define PTIS_PTIS1 _PTIS.Bits.PTIS1
|
| 6944 |
|
|
#define PTIS_PTIS2 _PTIS.Bits.PTIS2
|
| 6945 |
|
|
#define PTIS_PTIS3 _PTIS.Bits.PTIS3
|
| 6946 |
|
|
#define PTIS_PTIS _PTIS.MergedBits.grpPTIS
|
| 6947 |
|
|
|
| 6948 |
|
|
|
| 6949 |
|
|
/*** DDRS - Port S Data Direction Register; 0x0000024A ***/
|
| 6950 |
|
|
typedef union {
|
| 6951 |
|
|
byte Byte;
|
| 6952 |
|
|
struct {
|
| 6953 |
|
|
byte DDRS0 :1; /* Data Direction Port S Bit 0 */
|
| 6954 |
|
|
byte DDRS1 :1; /* Data Direction Port S Bit 1 */
|
| 6955 |
|
|
byte DDRS2 :1; /* Data Direction Port S Bit 2 */
|
| 6956 |
|
|
byte DDRS3 :1; /* Data Direction Port S Bit 3 */
|
| 6957 |
|
|
byte :1;
|
| 6958 |
|
|
byte :1;
|
| 6959 |
|
|
byte :1;
|
| 6960 |
|
|
byte :1;
|
| 6961 |
|
|
} Bits;
|
| 6962 |
|
|
struct {
|
| 6963 |
|
|
byte grpDDRS :4;
|
| 6964 |
|
|
byte :1;
|
| 6965 |
|
|
byte :1;
|
| 6966 |
|
|
byte :1;
|
| 6967 |
|
|
byte :1;
|
| 6968 |
|
|
} MergedBits;
|
| 6969 |
|
|
} DDRSSTR;
|
| 6970 |
|
|
extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A);
|
| 6971 |
|
|
#define DDRS _DDRS.Byte
|
| 6972 |
|
|
#define DDRS_DDRS0 _DDRS.Bits.DDRS0
|
| 6973 |
|
|
#define DDRS_DDRS1 _DDRS.Bits.DDRS1
|
| 6974 |
|
|
#define DDRS_DDRS2 _DDRS.Bits.DDRS2
|
| 6975 |
|
|
#define DDRS_DDRS3 _DDRS.Bits.DDRS3
|
| 6976 |
|
|
#define DDRS_DDRS _DDRS.MergedBits.grpDDRS
|
| 6977 |
|
|
|
| 6978 |
|
|
|
| 6979 |
|
|
/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/
|
| 6980 |
|
|
typedef union {
|
| 6981 |
|
|
byte Byte;
|
| 6982 |
|
|
struct {
|
| 6983 |
|
|
byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */
|
| 6984 |
|
|
byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */
|
| 6985 |
|
|
byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */
|
| 6986 |
|
|
byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */
|
| 6987 |
|
|
byte :1;
|
| 6988 |
|
|
byte :1;
|
| 6989 |
|
|
byte :1;
|
| 6990 |
|
|
byte :1;
|
| 6991 |
|
|
} Bits;
|
| 6992 |
|
|
struct {
|
| 6993 |
|
|
byte grpRDRS :4;
|
| 6994 |
|
|
byte :1;
|
| 6995 |
|
|
byte :1;
|
| 6996 |
|
|
byte :1;
|
| 6997 |
|
|
byte :1;
|
| 6998 |
|
|
} MergedBits;
|
| 6999 |
|
|
} RDRSSTR;
|
| 7000 |
|
|
extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B);
|
| 7001 |
|
|
#define RDRS _RDRS.Byte
|
| 7002 |
|
|
#define RDRS_RDRS0 _RDRS.Bits.RDRS0
|
| 7003 |
|
|
#define RDRS_RDRS1 _RDRS.Bits.RDRS1
|
| 7004 |
|
|
#define RDRS_RDRS2 _RDRS.Bits.RDRS2
|
| 7005 |
|
|
#define RDRS_RDRS3 _RDRS.Bits.RDRS3
|
| 7006 |
|
|
#define RDRS_RDRS _RDRS.MergedBits.grpRDRS
|
| 7007 |
|
|
|
| 7008 |
|
|
|
| 7009 |
|
|
/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/
|
| 7010 |
|
|
typedef union {
|
| 7011 |
|
|
byte Byte;
|
| 7012 |
|
|
struct {
|
| 7013 |
|
|
byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */
|
| 7014 |
|
|
byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */
|
| 7015 |
|
|
byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */
|
| 7016 |
|
|
byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */
|
| 7017 |
|
|
byte :1;
|
| 7018 |
|
|
byte :1;
|
| 7019 |
|
|
byte :1;
|
| 7020 |
|
|
byte :1;
|
| 7021 |
|
|
} Bits;
|
| 7022 |
|
|
struct {
|
| 7023 |
|
|
byte grpPERS :4;
|
| 7024 |
|
|
byte :1;
|
| 7025 |
|
|
byte :1;
|
| 7026 |
|
|
byte :1;
|
| 7027 |
|
|
byte :1;
|
| 7028 |
|
|
} MergedBits;
|
| 7029 |
|
|
} PERSSTR;
|
| 7030 |
|
|
extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C);
|
| 7031 |
|
|
#define PERS _PERS.Byte
|
| 7032 |
|
|
#define PERS_PERS0 _PERS.Bits.PERS0
|
| 7033 |
|
|
#define PERS_PERS1 _PERS.Bits.PERS1
|
| 7034 |
|
|
#define PERS_PERS2 _PERS.Bits.PERS2
|
| 7035 |
|
|
#define PERS_PERS3 _PERS.Bits.PERS3
|
| 7036 |
|
|
#define PERS_PERS _PERS.MergedBits.grpPERS
|
| 7037 |
|
|
|
| 7038 |
|
|
|
| 7039 |
|
|
/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/
|
| 7040 |
|
|
typedef union {
|
| 7041 |
|
|
byte Byte;
|
| 7042 |
|
|
struct {
|
| 7043 |
|
|
byte PPSS0 :1; /* Pull Select Port S Bit 0 */
|
| 7044 |
|
|
byte PPSS1 :1; /* Pull Select Port S Bit 1 */
|
| 7045 |
|
|
byte PPSS2 :1; /* Pull Select Port S Bit 2 */
|
| 7046 |
|
|
byte PPSS3 :1; /* Pull Select Port S Bit 3 */
|
| 7047 |
|
|
byte :1;
|
| 7048 |
|
|
byte :1;
|
| 7049 |
|
|
byte :1;
|
| 7050 |
|
|
byte :1;
|
| 7051 |
|
|
} Bits;
|
| 7052 |
|
|
struct {
|
| 7053 |
|
|
byte grpPPSS :4;
|
| 7054 |
|
|
byte :1;
|
| 7055 |
|
|
byte :1;
|
| 7056 |
|
|
byte :1;
|
| 7057 |
|
|
byte :1;
|
| 7058 |
|
|
} MergedBits;
|
| 7059 |
|
|
} PPSSSTR;
|
| 7060 |
|
|
extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D);
|
| 7061 |
|
|
#define PPSS _PPSS.Byte
|
| 7062 |
|
|
#define PPSS_PPSS0 _PPSS.Bits.PPSS0
|
| 7063 |
|
|
#define PPSS_PPSS1 _PPSS.Bits.PPSS1
|
| 7064 |
|
|
#define PPSS_PPSS2 _PPSS.Bits.PPSS2
|
| 7065 |
|
|
#define PPSS_PPSS3 _PPSS.Bits.PPSS3
|
| 7066 |
|
|
#define PPSS_PPSS _PPSS.MergedBits.grpPPSS
|
| 7067 |
|
|
|
| 7068 |
|
|
|
| 7069 |
|
|
/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/
|
| 7070 |
|
|
typedef union {
|
| 7071 |
|
|
byte Byte;
|
| 7072 |
|
|
struct {
|
| 7073 |
|
|
byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */
|
| 7074 |
|
|
byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */
|
| 7075 |
|
|
byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */
|
| 7076 |
|
|
byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */
|
| 7077 |
|
|
byte :1;
|
| 7078 |
|
|
byte :1;
|
| 7079 |
|
|
byte :1;
|
| 7080 |
|
|
byte :1;
|
| 7081 |
|
|
} Bits;
|
| 7082 |
|
|
struct {
|
| 7083 |
|
|
byte grpWOMS :4;
|
| 7084 |
|
|
byte :1;
|
| 7085 |
|
|
byte :1;
|
| 7086 |
|
|
byte :1;
|
| 7087 |
|
|
byte :1;
|
| 7088 |
|
|
} MergedBits;
|
| 7089 |
|
|
} WOMSSTR;
|
| 7090 |
|
|
extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E);
|
| 7091 |
|
|
#define WOMS _WOMS.Byte
|
| 7092 |
|
|
#define WOMS_WOMS0 _WOMS.Bits.WOMS0
|
| 7093 |
|
|
#define WOMS_WOMS1 _WOMS.Bits.WOMS1
|
| 7094 |
|
|
#define WOMS_WOMS2 _WOMS.Bits.WOMS2
|
| 7095 |
|
|
#define WOMS_WOMS3 _WOMS.Bits.WOMS3
|
| 7096 |
|
|
#define WOMS_WOMS _WOMS.MergedBits.grpWOMS
|
| 7097 |
|
|
|
| 7098 |
|
|
|
| 7099 |
|
|
/*** PTM - Port M I/O Register; 0x00000250 ***/
|
| 7100 |
|
|
typedef union {
|
| 7101 |
|
|
byte Byte;
|
| 7102 |
|
|
struct {
|
| 7103 |
|
|
byte PTM0 :1; /* Port T Bit 0 */
|
| 7104 |
|
|
byte PTM1 :1; /* Port T Bit 1 */
|
| 7105 |
|
|
byte PTM2 :1; /* Port T Bit 2 */
|
| 7106 |
|
|
byte PTM3 :1; /* Port T Bit 3 */
|
| 7107 |
|
|
byte PTM4 :1; /* Port T Bit 4 */
|
| 7108 |
|
|
byte PTM5 :1; /* Port T Bit 5 */
|
| 7109 |
|
|
byte :1;
|
| 7110 |
|
|
byte :1;
|
| 7111 |
|
|
} Bits;
|
| 7112 |
|
|
struct {
|
| 7113 |
|
|
byte grpPTM :6;
|
| 7114 |
|
|
byte :1;
|
| 7115 |
|
|
byte :1;
|
| 7116 |
|
|
} MergedBits;
|
| 7117 |
|
|
} PTMSTR;
|
| 7118 |
|
|
extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250);
|
| 7119 |
|
|
#define PTM _PTM.Byte
|
| 7120 |
|
|
#define PTM_PTM0 _PTM.Bits.PTM0
|
| 7121 |
|
|
#define PTM_PTM1 _PTM.Bits.PTM1
|
| 7122 |
|
|
#define PTM_PTM2 _PTM.Bits.PTM2
|
| 7123 |
|
|
#define PTM_PTM3 _PTM.Bits.PTM3
|
| 7124 |
|
|
#define PTM_PTM4 _PTM.Bits.PTM4
|
| 7125 |
|
|
#define PTM_PTM5 _PTM.Bits.PTM5
|
| 7126 |
|
|
#define PTM_PTM _PTM.MergedBits.grpPTM
|
| 7127 |
|
|
|
| 7128 |
|
|
|
| 7129 |
|
|
/*** PTIM - Port M Input; 0x00000251 ***/
|
| 7130 |
|
|
typedef union {
|
| 7131 |
|
|
byte Byte;
|
| 7132 |
|
|
struct {
|
| 7133 |
|
|
byte PTIM0 :1; /* Port M Bit 0 */
|
| 7134 |
|
|
byte PTIM1 :1; /* Port M Bit 1 */
|
| 7135 |
|
|
byte PTIM2 :1; /* Port M Bit 2 */
|
| 7136 |
|
|
byte PTIM3 :1; /* Port M Bit 3 */
|
| 7137 |
|
|
byte PTIM4 :1; /* Port M Bit 4 */
|
| 7138 |
|
|
byte PTIM5 :1; /* Port M Bit 5 */
|
| 7139 |
|
|
byte :1;
|
| 7140 |
|
|
byte :1;
|
| 7141 |
|
|
} Bits;
|
| 7142 |
|
|
struct {
|
| 7143 |
|
|
byte grpPTIM :6;
|
| 7144 |
|
|
byte :1;
|
| 7145 |
|
|
byte :1;
|
| 7146 |
|
|
} MergedBits;
|
| 7147 |
|
|
} PTIMSTR;
|
| 7148 |
|
|
extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251);
|
| 7149 |
|
|
#define PTIM _PTIM.Byte
|
| 7150 |
|
|
#define PTIM_PTIM0 _PTIM.Bits.PTIM0
|
| 7151 |
|
|
#define PTIM_PTIM1 _PTIM.Bits.PTIM1
|
| 7152 |
|
|
#define PTIM_PTIM2 _PTIM.Bits.PTIM2
|
| 7153 |
|
|
#define PTIM_PTIM3 _PTIM.Bits.PTIM3
|
| 7154 |
|
|
#define PTIM_PTIM4 _PTIM.Bits.PTIM4
|
| 7155 |
|
|
#define PTIM_PTIM5 _PTIM.Bits.PTIM5
|
| 7156 |
|
|
#define PTIM_PTIM _PTIM.MergedBits.grpPTIM
|
| 7157 |
|
|
|
| 7158 |
|
|
|
| 7159 |
|
|
/*** DDRM - Port M Data Direction Register; 0x00000252 ***/
|
| 7160 |
|
|
typedef union {
|
| 7161 |
|
|
byte Byte;
|
| 7162 |
|
|
struct {
|
| 7163 |
|
|
byte DDRM0 :1; /* Data Direction Port M Bit 0 */
|
| 7164 |
|
|
byte DDRM1 :1; /* Data Direction Port M Bit 1 */
|
| 7165 |
|
|
byte DDRM2 :1; /* Data Direction Port M Bit 2 */
|
| 7166 |
|
|
byte DDRM3 :1; /* Data Direction Port M Bit 3 */
|
| 7167 |
|
|
byte DDRM4 :1; /* Data Direction Port M Bit 4 */
|
| 7168 |
|
|
byte DDRM5 :1; /* Data Direction Port M Bit 5 */
|
| 7169 |
|
|
byte :1;
|
| 7170 |
|
|
byte :1;
|
| 7171 |
|
|
} Bits;
|
| 7172 |
|
|
struct {
|
| 7173 |
|
|
byte grpDDRM :6;
|
| 7174 |
|
|
byte :1;
|
| 7175 |
|
|
byte :1;
|
| 7176 |
|
|
} MergedBits;
|
| 7177 |
|
|
} DDRMSTR;
|
| 7178 |
|
|
extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252);
|
| 7179 |
|
|
#define DDRM _DDRM.Byte
|
| 7180 |
|
|
#define DDRM_DDRM0 _DDRM.Bits.DDRM0
|
| 7181 |
|
|
#define DDRM_DDRM1 _DDRM.Bits.DDRM1
|
| 7182 |
|
|
#define DDRM_DDRM2 _DDRM.Bits.DDRM2
|
| 7183 |
|
|
#define DDRM_DDRM3 _DDRM.Bits.DDRM3
|
| 7184 |
|
|
#define DDRM_DDRM4 _DDRM.Bits.DDRM4
|
| 7185 |
|
|
#define DDRM_DDRM5 _DDRM.Bits.DDRM5
|
| 7186 |
|
|
#define DDRM_DDRM _DDRM.MergedBits.grpDDRM
|
| 7187 |
|
|
|
| 7188 |
|
|
|
| 7189 |
|
|
/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/
|
| 7190 |
|
|
typedef union {
|
| 7191 |
|
|
byte Byte;
|
| 7192 |
|
|
struct {
|
| 7193 |
|
|
byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */
|
| 7194 |
|
|
byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */
|
| 7195 |
|
|
byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */
|
| 7196 |
|
|
byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */
|
| 7197 |
|
|
byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */
|
| 7198 |
|
|
byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */
|
| 7199 |
|
|
byte :1;
|
| 7200 |
|
|
byte :1;
|
| 7201 |
|
|
} Bits;
|
| 7202 |
|
|
struct {
|
| 7203 |
|
|
byte grpRDRM :6;
|
| 7204 |
|
|
byte :1;
|
| 7205 |
|
|
byte :1;
|
| 7206 |
|
|
} MergedBits;
|
| 7207 |
|
|
} RDRMSTR;
|
| 7208 |
|
|
extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253);
|
| 7209 |
|
|
#define RDRM _RDRM.Byte
|
| 7210 |
|
|
#define RDRM_RDRM0 _RDRM.Bits.RDRM0
|
| 7211 |
|
|
#define RDRM_RDRM1 _RDRM.Bits.RDRM1
|
| 7212 |
|
|
#define RDRM_RDRM2 _RDRM.Bits.RDRM2
|
| 7213 |
|
|
#define RDRM_RDRM3 _RDRM.Bits.RDRM3
|
| 7214 |
|
|
#define RDRM_RDRM4 _RDRM.Bits.RDRM4
|
| 7215 |
|
|
#define RDRM_RDRM5 _RDRM.Bits.RDRM5
|
| 7216 |
|
|
#define RDRM_RDRM _RDRM.MergedBits.grpRDRM
|
| 7217 |
|
|
|
| 7218 |
|
|
|
| 7219 |
|
|
/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/
|
| 7220 |
|
|
typedef union {
|
| 7221 |
|
|
byte Byte;
|
| 7222 |
|
|
struct {
|
| 7223 |
|
|
byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */
|
| 7224 |
|
|
byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */
|
| 7225 |
|
|
byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */
|
| 7226 |
|
|
byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */
|
| 7227 |
|
|
byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */
|
| 7228 |
|
|
byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */
|
| 7229 |
|
|
byte :1;
|
| 7230 |
|
|
byte :1;
|
| 7231 |
|
|
} Bits;
|
| 7232 |
|
|
struct {
|
| 7233 |
|
|
byte grpPERM :6;
|
| 7234 |
|
|
byte :1;
|
| 7235 |
|
|
byte :1;
|
| 7236 |
|
|
} MergedBits;
|
| 7237 |
|
|
} PERMSTR;
|
| 7238 |
|
|
extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254);
|
| 7239 |
|
|
#define PERM _PERM.Byte
|
| 7240 |
|
|
#define PERM_PERM0 _PERM.Bits.PERM0
|
| 7241 |
|
|
#define PERM_PERM1 _PERM.Bits.PERM1
|
| 7242 |
|
|
#define PERM_PERM2 _PERM.Bits.PERM2
|
| 7243 |
|
|
#define PERM_PERM3 _PERM.Bits.PERM3
|
| 7244 |
|
|
#define PERM_PERM4 _PERM.Bits.PERM4
|
| 7245 |
|
|
#define PERM_PERM5 _PERM.Bits.PERM5
|
| 7246 |
|
|
#define PERM_PERM _PERM.MergedBits.grpPERM
|
| 7247 |
|
|
|
| 7248 |
|
|
|
| 7249 |
|
|
/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/
|
| 7250 |
|
|
typedef union {
|
| 7251 |
|
|
byte Byte;
|
| 7252 |
|
|
struct {
|
| 7253 |
|
|
byte PPSM0 :1; /* Pull Select Port M Bit 0 */
|
| 7254 |
|
|
byte PPSM1 :1; /* Pull Select Port M Bit 1 */
|
| 7255 |
|
|
byte PPSM2 :1; /* Pull Select Port M Bit 2 */
|
| 7256 |
|
|
byte PPSM3 :1; /* Pull Select Port M Bit 3 */
|
| 7257 |
|
|
byte PPSM4 :1; /* Pull Select Port M Bit 4 */
|
| 7258 |
|
|
byte PPSM5 :1; /* Pull Select Port M Bit 5 */
|
| 7259 |
|
|
byte :1;
|
| 7260 |
|
|
byte :1;
|
| 7261 |
|
|
} Bits;
|
| 7262 |
|
|
struct {
|
| 7263 |
|
|
byte grpPPSM :6;
|
| 7264 |
|
|
byte :1;
|
| 7265 |
|
|
byte :1;
|
| 7266 |
|
|
} MergedBits;
|
| 7267 |
|
|
} PPSMSTR;
|
| 7268 |
|
|
extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255);
|
| 7269 |
|
|
#define PPSM _PPSM.Byte
|
| 7270 |
|
|
#define PPSM_PPSM0 _PPSM.Bits.PPSM0
|
| 7271 |
|
|
#define PPSM_PPSM1 _PPSM.Bits.PPSM1
|
| 7272 |
|
|
#define PPSM_PPSM2 _PPSM.Bits.PPSM2
|
| 7273 |
|
|
#define PPSM_PPSM3 _PPSM.Bits.PPSM3
|
| 7274 |
|
|
#define PPSM_PPSM4 _PPSM.Bits.PPSM4
|
| 7275 |
|
|
#define PPSM_PPSM5 _PPSM.Bits.PPSM5
|
| 7276 |
|
|
#define PPSM_PPSM _PPSM.MergedBits.grpPPSM
|
| 7277 |
|
|
|
| 7278 |
|
|
|
| 7279 |
|
|
/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/
|
| 7280 |
|
|
typedef union {
|
| 7281 |
|
|
byte Byte;
|
| 7282 |
|
|
struct {
|
| 7283 |
|
|
byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */
|
| 7284 |
|
|
byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */
|
| 7285 |
|
|
byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */
|
| 7286 |
|
|
byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */
|
| 7287 |
|
|
byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */
|
| 7288 |
|
|
byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */
|
| 7289 |
|
|
byte :1;
|
| 7290 |
|
|
byte :1;
|
| 7291 |
|
|
} Bits;
|
| 7292 |
|
|
struct {
|
| 7293 |
|
|
byte grpWOMM :6;
|
| 7294 |
|
|
byte :1;
|
| 7295 |
|
|
byte :1;
|
| 7296 |
|
|
} MergedBits;
|
| 7297 |
|
|
} WOMMSTR;
|
| 7298 |
|
|
extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256);
|
| 7299 |
|
|
#define WOMM _WOMM.Byte
|
| 7300 |
|
|
#define WOMM_WOMM0 _WOMM.Bits.WOMM0
|
| 7301 |
|
|
#define WOMM_WOMM1 _WOMM.Bits.WOMM1
|
| 7302 |
|
|
#define WOMM_WOMM2 _WOMM.Bits.WOMM2
|
| 7303 |
|
|
#define WOMM_WOMM3 _WOMM.Bits.WOMM3
|
| 7304 |
|
|
#define WOMM_WOMM4 _WOMM.Bits.WOMM4
|
| 7305 |
|
|
#define WOMM_WOMM5 _WOMM.Bits.WOMM5
|
| 7306 |
|
|
#define WOMM_WOMM _WOMM.MergedBits.grpWOMM
|
| 7307 |
|
|
|
| 7308 |
|
|
|
| 7309 |
|
|
/*** PTP - Port P I/O Register; 0x00000258 ***/
|
| 7310 |
|
|
typedef union {
|
| 7311 |
|
|
byte Byte;
|
| 7312 |
|
|
struct {
|
| 7313 |
|
|
byte PTP0 :1; /* Port P Bit 0 */
|
| 7314 |
|
|
byte PTP1 :1; /* Port P Bit 1 */
|
| 7315 |
|
|
byte PTP2 :1; /* Port P Bit 2 */
|
| 7316 |
|
|
byte PTP3 :1; /* Port P Bit 3 */
|
| 7317 |
|
|
byte PTP4 :1; /* Port P Bit 4 */
|
| 7318 |
|
|
byte PTP5 :1; /* Port P Bit 5 */
|
| 7319 |
|
|
byte PTP6 :1; /* Port P Bit 6 */
|
| 7320 |
|
|
byte PTP7 :1; /* Port P Bit 7 */
|
| 7321 |
|
|
} Bits;
|
| 7322 |
|
|
struct {
|
| 7323 |
|
|
byte grpPTP :8;
|
| 7324 |
|
|
} MergedBits;
|
| 7325 |
|
|
} PTPSTR;
|
| 7326 |
|
|
extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258);
|
| 7327 |
|
|
#define PTP _PTP.Byte
|
| 7328 |
|
|
#define PTP_PTP0 _PTP.Bits.PTP0
|
| 7329 |
|
|
#define PTP_PTP1 _PTP.Bits.PTP1
|
| 7330 |
|
|
#define PTP_PTP2 _PTP.Bits.PTP2
|
| 7331 |
|
|
#define PTP_PTP3 _PTP.Bits.PTP3
|
| 7332 |
|
|
#define PTP_PTP4 _PTP.Bits.PTP4
|
| 7333 |
|
|
#define PTP_PTP5 _PTP.Bits.PTP5
|
| 7334 |
|
|
#define PTP_PTP6 _PTP.Bits.PTP6
|
| 7335 |
|
|
#define PTP_PTP7 _PTP.Bits.PTP7
|
| 7336 |
|
|
#define PTP_PTP _PTP.MergedBits.grpPTP
|
| 7337 |
|
|
|
| 7338 |
|
|
|
| 7339 |
|
|
/*** PTIP - Port P Input; 0x00000259 ***/
|
| 7340 |
|
|
typedef union {
|
| 7341 |
|
|
byte Byte;
|
| 7342 |
|
|
struct {
|
| 7343 |
|
|
byte PTIP0 :1; /* Port P Bit 0 */
|
| 7344 |
|
|
byte PTIP1 :1; /* Port P Bit 1 */
|
| 7345 |
|
|
byte PTIP2 :1; /* Port P Bit 2 */
|
| 7346 |
|
|
byte PTIP3 :1; /* Port P Bit 3 */
|
| 7347 |
|
|
byte PTIP4 :1; /* Port P Bit 4 */
|
| 7348 |
|
|
byte PTIP5 :1; /* Port P Bit 5 */
|
| 7349 |
|
|
byte PTIP6 :1; /* Port P Bit 6 */
|
| 7350 |
|
|
byte PTIP7 :1; /* Port P Bit 7 */
|
| 7351 |
|
|
} Bits;
|
| 7352 |
|
|
struct {
|
| 7353 |
|
|
byte grpPTIP :8;
|
| 7354 |
|
|
} MergedBits;
|
| 7355 |
|
|
} PTIPSTR;
|
| 7356 |
|
|
extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259);
|
| 7357 |
|
|
#define PTIP _PTIP.Byte
|
| 7358 |
|
|
#define PTIP_PTIP0 _PTIP.Bits.PTIP0
|
| 7359 |
|
|
#define PTIP_PTIP1 _PTIP.Bits.PTIP1
|
| 7360 |
|
|
#define PTIP_PTIP2 _PTIP.Bits.PTIP2
|
| 7361 |
|
|
#define PTIP_PTIP3 _PTIP.Bits.PTIP3
|
| 7362 |
|
|
#define PTIP_PTIP4 _PTIP.Bits.PTIP4
|
| 7363 |
|
|
#define PTIP_PTIP5 _PTIP.Bits.PTIP5
|
| 7364 |
|
|
#define PTIP_PTIP6 _PTIP.Bits.PTIP6
|
| 7365 |
|
|
#define PTIP_PTIP7 _PTIP.Bits.PTIP7
|
| 7366 |
|
|
#define PTIP_PTIP _PTIP.MergedBits.grpPTIP
|
| 7367 |
|
|
|
| 7368 |
|
|
|
| 7369 |
|
|
/*** DDRP - Port P Data Direction Register; 0x0000025A ***/
|
| 7370 |
|
|
typedef union {
|
| 7371 |
|
|
byte Byte;
|
| 7372 |
|
|
struct {
|
| 7373 |
|
|
byte DDRP0 :1; /* Data Direction Port P Bit 0 */
|
| 7374 |
|
|
byte DDRP1 :1; /* Data Direction Port P Bit 1 */
|
| 7375 |
|
|
byte DDRP2 :1; /* Data Direction Port P Bit 2 */
|
| 7376 |
|
|
byte DDRP3 :1; /* Data Direction Port P Bit 3 */
|
| 7377 |
|
|
byte DDRP4 :1; /* Data Direction Port P Bit 4 */
|
| 7378 |
|
|
byte DDRP5 :1; /* Data Direction Port P Bit 5 */
|
| 7379 |
|
|
byte DDRP6 :1; /* Data Direction Port P Bit 6 */
|
| 7380 |
|
|
byte DDRP7 :1; /* Data Direction Port P Bit 7 */
|
| 7381 |
|
|
} Bits;
|
| 7382 |
|
|
struct {
|
| 7383 |
|
|
byte grpDDRP :8;
|
| 7384 |
|
|
} MergedBits;
|
| 7385 |
|
|
} DDRPSTR;
|
| 7386 |
|
|
extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A);
|
| 7387 |
|
|
#define DDRP _DDRP.Byte
|
| 7388 |
|
|
#define DDRP_DDRP0 _DDRP.Bits.DDRP0
|
| 7389 |
|
|
#define DDRP_DDRP1 _DDRP.Bits.DDRP1
|
| 7390 |
|
|
#define DDRP_DDRP2 _DDRP.Bits.DDRP2
|
| 7391 |
|
|
#define DDRP_DDRP3 _DDRP.Bits.DDRP3
|
| 7392 |
|
|
#define DDRP_DDRP4 _DDRP.Bits.DDRP4
|
| 7393 |
|
|
#define DDRP_DDRP5 _DDRP.Bits.DDRP5
|
| 7394 |
|
|
#define DDRP_DDRP6 _DDRP.Bits.DDRP6
|
| 7395 |
|
|
#define DDRP_DDRP7 _DDRP.Bits.DDRP7
|
| 7396 |
|
|
#define DDRP_DDRP _DDRP.MergedBits.grpDDRP
|
| 7397 |
|
|
|
| 7398 |
|
|
|
| 7399 |
|
|
/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/
|
| 7400 |
|
|
typedef union {
|
| 7401 |
|
|
byte Byte;
|
| 7402 |
|
|
struct {
|
| 7403 |
|
|
byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */
|
| 7404 |
|
|
byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */
|
| 7405 |
|
|
byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */
|
| 7406 |
|
|
byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */
|
| 7407 |
|
|
byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */
|
| 7408 |
|
|
byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */
|
| 7409 |
|
|
byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */
|
| 7410 |
|
|
byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */
|
| 7411 |
|
|
} Bits;
|
| 7412 |
|
|
struct {
|
| 7413 |
|
|
byte grpRDRP :8;
|
| 7414 |
|
|
} MergedBits;
|
| 7415 |
|
|
} RDRPSTR;
|
| 7416 |
|
|
extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B);
|
| 7417 |
|
|
#define RDRP _RDRP.Byte
|
| 7418 |
|
|
#define RDRP_RDRP0 _RDRP.Bits.RDRP0
|
| 7419 |
|
|
#define RDRP_RDRP1 _RDRP.Bits.RDRP1
|
| 7420 |
|
|
#define RDRP_RDRP2 _RDRP.Bits.RDRP2
|
| 7421 |
|
|
#define RDRP_RDRP3 _RDRP.Bits.RDRP3
|
| 7422 |
|
|
#define RDRP_RDRP4 _RDRP.Bits.RDRP4
|
| 7423 |
|
|
#define RDRP_RDRP5 _RDRP.Bits.RDRP5
|
| 7424 |
|
|
#define RDRP_RDRP6 _RDRP.Bits.RDRP6
|
| 7425 |
|
|
#define RDRP_RDRP7 _RDRP.Bits.RDRP7
|
| 7426 |
|
|
#define RDRP_RDRP _RDRP.MergedBits.grpRDRP
|
| 7427 |
|
|
|
| 7428 |
|
|
|
| 7429 |
|
|
/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/
|
| 7430 |
|
|
typedef union {
|
| 7431 |
|
|
byte Byte;
|
| 7432 |
|
|
struct {
|
| 7433 |
|
|
byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */
|
| 7434 |
|
|
byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */
|
| 7435 |
|
|
byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */
|
| 7436 |
|
|
byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */
|
| 7437 |
|
|
byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */
|
| 7438 |
|
|
byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */
|
| 7439 |
|
|
byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */
|
| 7440 |
|
|
byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */
|
| 7441 |
|
|
} Bits;
|
| 7442 |
|
|
struct {
|
| 7443 |
|
|
byte grpPERP :8;
|
| 7444 |
|
|
} MergedBits;
|
| 7445 |
|
|
} PERPSTR;
|
| 7446 |
|
|
extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C);
|
| 7447 |
|
|
#define PERP _PERP.Byte
|
| 7448 |
|
|
#define PERP_PERP0 _PERP.Bits.PERP0
|
| 7449 |
|
|
#define PERP_PERP1 _PERP.Bits.PERP1
|
| 7450 |
|
|
#define PERP_PERP2 _PERP.Bits.PERP2
|
| 7451 |
|
|
#define PERP_PERP3 _PERP.Bits.PERP3
|
| 7452 |
|
|
#define PERP_PERP4 _PERP.Bits.PERP4
|
| 7453 |
|
|
#define PERP_PERP5 _PERP.Bits.PERP5
|
| 7454 |
|
|
#define PERP_PERP6 _PERP.Bits.PERP6
|
| 7455 |
|
|
#define PERP_PERP7 _PERP.Bits.PERP7
|
| 7456 |
|
|
#define PERP_PERP _PERP.MergedBits.grpPERP
|
| 7457 |
|
|
|
| 7458 |
|
|
|
| 7459 |
|
|
/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/
|
| 7460 |
|
|
typedef union {
|
| 7461 |
|
|
byte Byte;
|
| 7462 |
|
|
struct {
|
| 7463 |
|
|
byte PPSP0 :1; /* Pull Select Port P Bit 0 */
|
| 7464 |
|
|
byte PPSP1 :1; /* Pull Select Port P Bit 1 */
|
| 7465 |
|
|
byte PPSP2 :1; /* Pull Select Port P Bit 2 */
|
| 7466 |
|
|
byte PPSP3 :1; /* Pull Select Port P Bit 3 */
|
| 7467 |
|
|
byte PPSP4 :1; /* Pull Select Port P Bit 4 */
|
| 7468 |
|
|
byte PPSP5 :1; /* Pull Select Port P Bit 5 */
|
| 7469 |
|
|
byte PPSP6 :1; /* Pull Select Port P Bit 6 */
|
| 7470 |
|
|
byte PPSP7 :1; /* Pull Select Port P Bit 7 */
|
| 7471 |
|
|
} Bits;
|
| 7472 |
|
|
struct {
|
| 7473 |
|
|
byte grpPPSP :8;
|
| 7474 |
|
|
} MergedBits;
|
| 7475 |
|
|
} PPSPSTR;
|
| 7476 |
|
|
extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D);
|
| 7477 |
|
|
#define PPSP _PPSP.Byte
|
| 7478 |
|
|
#define PPSP_PPSP0 _PPSP.Bits.PPSP0
|
| 7479 |
|
|
#define PPSP_PPSP1 _PPSP.Bits.PPSP1
|
| 7480 |
|
|
#define PPSP_PPSP2 _PPSP.Bits.PPSP2
|
| 7481 |
|
|
#define PPSP_PPSP3 _PPSP.Bits.PPSP3
|
| 7482 |
|
|
#define PPSP_PPSP4 _PPSP.Bits.PPSP4
|
| 7483 |
|
|
#define PPSP_PPSP5 _PPSP.Bits.PPSP5
|
| 7484 |
|
|
#define PPSP_PPSP6 _PPSP.Bits.PPSP6
|
| 7485 |
|
|
#define PPSP_PPSP7 _PPSP.Bits.PPSP7
|
| 7486 |
|
|
#define PPSP_PPSP _PPSP.MergedBits.grpPPSP
|
| 7487 |
|
|
|
| 7488 |
|
|
|
| 7489 |
|
|
/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/
|
| 7490 |
|
|
typedef union {
|
| 7491 |
|
|
byte Byte;
|
| 7492 |
|
|
struct {
|
| 7493 |
|
|
byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */
|
| 7494 |
|
|
byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */
|
| 7495 |
|
|
byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */
|
| 7496 |
|
|
byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */
|
| 7497 |
|
|
byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */
|
| 7498 |
|
|
byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */
|
| 7499 |
|
|
byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */
|
| 7500 |
|
|
byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */
|
| 7501 |
|
|
} Bits;
|
| 7502 |
|
|
struct {
|
| 7503 |
|
|
byte grpPIEP :8;
|
| 7504 |
|
|
} MergedBits;
|
| 7505 |
|
|
} PIEPSTR;
|
| 7506 |
|
|
extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E);
|
| 7507 |
|
|
#define PIEP _PIEP.Byte
|
| 7508 |
|
|
#define PIEP_PIEP0 _PIEP.Bits.PIEP0
|
| 7509 |
|
|
#define PIEP_PIEP1 _PIEP.Bits.PIEP1
|
| 7510 |
|
|
#define PIEP_PIEP2 _PIEP.Bits.PIEP2
|
| 7511 |
|
|
#define PIEP_PIEP3 _PIEP.Bits.PIEP3
|
| 7512 |
|
|
#define PIEP_PIEP4 _PIEP.Bits.PIEP4
|
| 7513 |
|
|
#define PIEP_PIEP5 _PIEP.Bits.PIEP5
|
| 7514 |
|
|
#define PIEP_PIEP6 _PIEP.Bits.PIEP6
|
| 7515 |
|
|
#define PIEP_PIEP7 _PIEP.Bits.PIEP7
|
| 7516 |
|
|
#define PIEP_PIEP _PIEP.MergedBits.grpPIEP
|
| 7517 |
|
|
|
| 7518 |
|
|
|
| 7519 |
|
|
/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/
|
| 7520 |
|
|
typedef union {
|
| 7521 |
|
|
byte Byte;
|
| 7522 |
|
|
struct {
|
| 7523 |
|
|
byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */
|
| 7524 |
|
|
byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */
|
| 7525 |
|
|
byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */
|
| 7526 |
|
|
byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */
|
| 7527 |
|
|
byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */
|
| 7528 |
|
|
byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */
|
| 7529 |
|
|
byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */
|
| 7530 |
|
|
byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */
|
| 7531 |
|
|
} Bits;
|
| 7532 |
|
|
struct {
|
| 7533 |
|
|
byte grpPIFP :8;
|
| 7534 |
|
|
} MergedBits;
|
| 7535 |
|
|
} PIFPSTR;
|
| 7536 |
|
|
extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F);
|
| 7537 |
|
|
#define PIFP _PIFP.Byte
|
| 7538 |
|
|
#define PIFP_PIFP0 _PIFP.Bits.PIFP0
|
| 7539 |
|
|
#define PIFP_PIFP1 _PIFP.Bits.PIFP1
|
| 7540 |
|
|
#define PIFP_PIFP2 _PIFP.Bits.PIFP2
|
| 7541 |
|
|
#define PIFP_PIFP3 _PIFP.Bits.PIFP3
|
| 7542 |
|
|
#define PIFP_PIFP4 _PIFP.Bits.PIFP4
|
| 7543 |
|
|
#define PIFP_PIFP5 _PIFP.Bits.PIFP5
|
| 7544 |
|
|
#define PIFP_PIFP6 _PIFP.Bits.PIFP6
|
| 7545 |
|
|
#define PIFP_PIFP7 _PIFP.Bits.PIFP7
|
| 7546 |
|
|
#define PIFP_PIFP _PIFP.MergedBits.grpPIFP
|
| 7547 |
|
|
|
| 7548 |
|
|
|
| 7549 |
|
|
/*** PTJ - Port J I/O Register; 0x00000268 ***/
|
| 7550 |
|
|
typedef union {
|
| 7551 |
|
|
byte Byte;
|
| 7552 |
|
|
struct {
|
| 7553 |
|
|
byte :1;
|
| 7554 |
|
|
byte :1;
|
| 7555 |
|
|
byte :1;
|
| 7556 |
|
|
byte :1;
|
| 7557 |
|
|
byte :1;
|
| 7558 |
|
|
byte :1;
|
| 7559 |
|
|
byte PTJ6 :1; /* Port J Bit 6 */
|
| 7560 |
|
|
byte PTJ7 :1; /* Port J Bit 7 */
|
| 7561 |
|
|
} Bits;
|
| 7562 |
|
|
struct {
|
| 7563 |
|
|
byte :1;
|
| 7564 |
|
|
byte :1;
|
| 7565 |
|
|
byte :1;
|
| 7566 |
|
|
byte :1;
|
| 7567 |
|
|
byte :1;
|
| 7568 |
|
|
byte :1;
|
| 7569 |
|
|
byte grpPTJ_6 :2;
|
| 7570 |
|
|
} MergedBits;
|
| 7571 |
|
|
} PTJSTR;
|
| 7572 |
|
|
extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268);
|
| 7573 |
|
|
#define PTJ _PTJ.Byte
|
| 7574 |
|
|
#define PTJ_PTJ6 _PTJ.Bits.PTJ6
|
| 7575 |
|
|
#define PTJ_PTJ7 _PTJ.Bits.PTJ7
|
| 7576 |
|
|
#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6
|
| 7577 |
|
|
|
| 7578 |
|
|
|
| 7579 |
|
|
/*** PTIJ - Port J Input Register; 0x00000269 ***/
|
| 7580 |
|
|
typedef union {
|
| 7581 |
|
|
byte Byte;
|
| 7582 |
|
|
struct {
|
| 7583 |
|
|
byte :1;
|
| 7584 |
|
|
byte :1;
|
| 7585 |
|
|
byte :1;
|
| 7586 |
|
|
byte :1;
|
| 7587 |
|
|
byte :1;
|
| 7588 |
|
|
byte :1;
|
| 7589 |
|
|
byte PTIJ6 :1; /* Port J Bit 6 */
|
| 7590 |
|
|
byte PTIJ7 :1; /* Port J Bit 7 */
|
| 7591 |
|
|
} Bits;
|
| 7592 |
|
|
struct {
|
| 7593 |
|
|
byte :1;
|
| 7594 |
|
|
byte :1;
|
| 7595 |
|
|
byte :1;
|
| 7596 |
|
|
byte :1;
|
| 7597 |
|
|
byte :1;
|
| 7598 |
|
|
byte :1;
|
| 7599 |
|
|
byte grpPTIJ_6 :2;
|
| 7600 |
|
|
} MergedBits;
|
| 7601 |
|
|
} PTIJSTR;
|
| 7602 |
|
|
extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269);
|
| 7603 |
|
|
#define PTIJ _PTIJ.Byte
|
| 7604 |
|
|
#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6
|
| 7605 |
|
|
#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7
|
| 7606 |
|
|
#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6
|
| 7607 |
|
|
|
| 7608 |
|
|
|
| 7609 |
|
|
/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/
|
| 7610 |
|
|
typedef union {
|
| 7611 |
|
|
byte Byte;
|
| 7612 |
|
|
struct {
|
| 7613 |
|
|
byte :1;
|
| 7614 |
|
|
byte :1;
|
| 7615 |
|
|
byte :1;
|
| 7616 |
|
|
byte :1;
|
| 7617 |
|
|
byte :1;
|
| 7618 |
|
|
byte :1;
|
| 7619 |
|
|
byte DDRJ6 :1; /* Data Direction Port J Bit 6 */
|
| 7620 |
|
|
byte DDRJ7 :1; /* Data Direction Port J Bit 7 */
|
| 7621 |
|
|
} Bits;
|
| 7622 |
|
|
struct {
|
| 7623 |
|
|
byte :1;
|
| 7624 |
|
|
byte :1;
|
| 7625 |
|
|
byte :1;
|
| 7626 |
|
|
byte :1;
|
| 7627 |
|
|
byte :1;
|
| 7628 |
|
|
byte :1;
|
| 7629 |
|
|
byte grpDDRJ_6 :2;
|
| 7630 |
|
|
} MergedBits;
|
| 7631 |
|
|
} DDRJSTR;
|
| 7632 |
|
|
extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A);
|
| 7633 |
|
|
#define DDRJ _DDRJ.Byte
|
| 7634 |
|
|
#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6
|
| 7635 |
|
|
#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7
|
| 7636 |
|
|
#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6
|
| 7637 |
|
|
|
| 7638 |
|
|
|
| 7639 |
|
|
/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/
|
| 7640 |
|
|
typedef union {
|
| 7641 |
|
|
byte Byte;
|
| 7642 |
|
|
struct {
|
| 7643 |
|
|
byte :1;
|
| 7644 |
|
|
byte :1;
|
| 7645 |
|
|
byte :1;
|
| 7646 |
|
|
byte :1;
|
| 7647 |
|
|
byte :1;
|
| 7648 |
|
|
byte :1;
|
| 7649 |
|
|
byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */
|
| 7650 |
|
|
byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */
|
| 7651 |
|
|
} Bits;
|
| 7652 |
|
|
struct {
|
| 7653 |
|
|
byte :1;
|
| 7654 |
|
|
byte :1;
|
| 7655 |
|
|
byte :1;
|
| 7656 |
|
|
byte :1;
|
| 7657 |
|
|
byte :1;
|
| 7658 |
|
|
byte :1;
|
| 7659 |
|
|
byte grpRDRJ_6 :2;
|
| 7660 |
|
|
} MergedBits;
|
| 7661 |
|
|
} RDRJSTR;
|
| 7662 |
|
|
extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B);
|
| 7663 |
|
|
#define RDRJ _RDRJ.Byte
|
| 7664 |
|
|
#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6
|
| 7665 |
|
|
#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7
|
| 7666 |
|
|
#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6
|
| 7667 |
|
|
|
| 7668 |
|
|
|
| 7669 |
|
|
/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/
|
| 7670 |
|
|
typedef union {
|
| 7671 |
|
|
byte Byte;
|
| 7672 |
|
|
struct {
|
| 7673 |
|
|
byte :1;
|
| 7674 |
|
|
byte :1;
|
| 7675 |
|
|
byte :1;
|
| 7676 |
|
|
byte :1;
|
| 7677 |
|
|
byte :1;
|
| 7678 |
|
|
byte :1;
|
| 7679 |
|
|
byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */
|
| 7680 |
|
|
byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */
|
| 7681 |
|
|
} Bits;
|
| 7682 |
|
|
struct {
|
| 7683 |
|
|
byte :1;
|
| 7684 |
|
|
byte :1;
|
| 7685 |
|
|
byte :1;
|
| 7686 |
|
|
byte :1;
|
| 7687 |
|
|
byte :1;
|
| 7688 |
|
|
byte :1;
|
| 7689 |
|
|
byte grpPERJ_6 :2;
|
| 7690 |
|
|
} MergedBits;
|
| 7691 |
|
|
} PERJSTR;
|
| 7692 |
|
|
extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C);
|
| 7693 |
|
|
#define PERJ _PERJ.Byte
|
| 7694 |
|
|
#define PERJ_PERJ6 _PERJ.Bits.PERJ6
|
| 7695 |
|
|
#define PERJ_PERJ7 _PERJ.Bits.PERJ7
|
| 7696 |
|
|
#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6
|
| 7697 |
|
|
|
| 7698 |
|
|
|
| 7699 |
|
|
/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/
|
| 7700 |
|
|
typedef union {
|
| 7701 |
|
|
byte Byte;
|
| 7702 |
|
|
struct {
|
| 7703 |
|
|
byte :1;
|
| 7704 |
|
|
byte :1;
|
| 7705 |
|
|
byte :1;
|
| 7706 |
|
|
byte :1;
|
| 7707 |
|
|
byte :1;
|
| 7708 |
|
|
byte :1;
|
| 7709 |
|
|
byte PPSJ6 :1; /* Pull Select Port J Bit 6 */
|
| 7710 |
|
|
byte PPSJ7 :1; /* Pull Select Port J Bit 7 */
|
| 7711 |
|
|
} Bits;
|
| 7712 |
|
|
struct {
|
| 7713 |
|
|
byte :1;
|
| 7714 |
|
|
byte :1;
|
| 7715 |
|
|
byte :1;
|
| 7716 |
|
|
byte :1;
|
| 7717 |
|
|
byte :1;
|
| 7718 |
|
|
byte :1;
|
| 7719 |
|
|
byte grpPPSJ_6 :2;
|
| 7720 |
|
|
} MergedBits;
|
| 7721 |
|
|
} PPSJSTR;
|
| 7722 |
|
|
extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D);
|
| 7723 |
|
|
#define PPSJ _PPSJ.Byte
|
| 7724 |
|
|
#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6
|
| 7725 |
|
|
#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7
|
| 7726 |
|
|
#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6
|
| 7727 |
|
|
|
| 7728 |
|
|
|
| 7729 |
|
|
/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/
|
| 7730 |
|
|
typedef union {
|
| 7731 |
|
|
byte Byte;
|
| 7732 |
|
|
struct {
|
| 7733 |
|
|
byte :1;
|
| 7734 |
|
|
byte :1;
|
| 7735 |
|
|
byte :1;
|
| 7736 |
|
|
byte :1;
|
| 7737 |
|
|
byte :1;
|
| 7738 |
|
|
byte :1;
|
| 7739 |
|
|
byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */
|
| 7740 |
|
|
byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */
|
| 7741 |
|
|
} Bits;
|
| 7742 |
|
|
struct {
|
| 7743 |
|
|
byte :1;
|
| 7744 |
|
|
byte :1;
|
| 7745 |
|
|
byte :1;
|
| 7746 |
|
|
byte :1;
|
| 7747 |
|
|
byte :1;
|
| 7748 |
|
|
byte :1;
|
| 7749 |
|
|
byte grpPIEJ_6 :2;
|
| 7750 |
|
|
} MergedBits;
|
| 7751 |
|
|
} PIEJSTR;
|
| 7752 |
|
|
extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E);
|
| 7753 |
|
|
#define PIEJ _PIEJ.Byte
|
| 7754 |
|
|
#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6
|
| 7755 |
|
|
#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7
|
| 7756 |
|
|
#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6
|
| 7757 |
|
|
|
| 7758 |
|
|
|
| 7759 |
|
|
/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/
|
| 7760 |
|
|
typedef union {
|
| 7761 |
|
|
byte Byte;
|
| 7762 |
|
|
struct {
|
| 7763 |
|
|
byte :1;
|
| 7764 |
|
|
byte :1;
|
| 7765 |
|
|
byte :1;
|
| 7766 |
|
|
byte :1;
|
| 7767 |
|
|
byte :1;
|
| 7768 |
|
|
byte :1;
|
| 7769 |
|
|
byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */
|
| 7770 |
|
|
byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */
|
| 7771 |
|
|
} Bits;
|
| 7772 |
|
|
struct {
|
| 7773 |
|
|
byte :1;
|
| 7774 |
|
|
byte :1;
|
| 7775 |
|
|
byte :1;
|
| 7776 |
|
|
byte :1;
|
| 7777 |
|
|
byte :1;
|
| 7778 |
|
|
byte :1;
|
| 7779 |
|
|
byte grpPIFJ_6 :2;
|
| 7780 |
|
|
} MergedBits;
|
| 7781 |
|
|
} PIFJSTR;
|
| 7782 |
|
|
extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F);
|
| 7783 |
|
|
#define PIFJ _PIFJ.Byte
|
| 7784 |
|
|
#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6
|
| 7785 |
|
|
#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7
|
| 7786 |
|
|
#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6
|
| 7787 |
|
|
|
| 7788 |
|
|
|
| 7789 |
|
|
/*** PTAD - Port AD I/O Register; 0x00000270 ***/
|
| 7790 |
|
|
typedef union {
|
| 7791 |
|
|
byte Byte;
|
| 7792 |
|
|
struct {
|
| 7793 |
|
|
byte PTAD0 :1; /* Port AD Bit 0 */
|
| 7794 |
|
|
byte PTAD1 :1; /* Port AD Bit 1 */
|
| 7795 |
|
|
byte PTAD2 :1; /* Port AD Bit 2 */
|
| 7796 |
|
|
byte PTAD3 :1; /* Port AD Bit 3 */
|
| 7797 |
|
|
byte PTAD4 :1; /* Port AD Bit 4 */
|
| 7798 |
|
|
byte PTAD5 :1; /* Port AD Bit 5 */
|
| 7799 |
|
|
byte PTAD6 :1; /* Port AD Bit 6 */
|
| 7800 |
|
|
byte PTAD7 :1; /* Port AD Bit 7 */
|
| 7801 |
|
|
} Bits;
|
| 7802 |
|
|
struct {
|
| 7803 |
|
|
byte grpPTAD :8;
|
| 7804 |
|
|
} MergedBits;
|
| 7805 |
|
|
} PTADSTR;
|
| 7806 |
|
|
extern volatile PTADSTR _PTAD @(REG_BASE + 0x00000270);
|
| 7807 |
|
|
#define PTAD _PTAD.Byte
|
| 7808 |
|
|
#define PTAD_PTAD0 _PTAD.Bits.PTAD0
|
| 7809 |
|
|
#define PTAD_PTAD1 _PTAD.Bits.PTAD1
|
| 7810 |
|
|
#define PTAD_PTAD2 _PTAD.Bits.PTAD2
|
| 7811 |
|
|
#define PTAD_PTAD3 _PTAD.Bits.PTAD3
|
| 7812 |
|
|
#define PTAD_PTAD4 _PTAD.Bits.PTAD4
|
| 7813 |
|
|
#define PTAD_PTAD5 _PTAD.Bits.PTAD5
|
| 7814 |
|
|
#define PTAD_PTAD6 _PTAD.Bits.PTAD6
|
| 7815 |
|
|
#define PTAD_PTAD7 _PTAD.Bits.PTAD7
|
| 7816 |
|
|
#define PTAD_PTAD _PTAD.MergedBits.grpPTAD
|
| 7817 |
|
|
|
| 7818 |
|
|
|
| 7819 |
|
|
/*** PTIAD - Port AD Input Register; 0x00000271 ***/
|
| 7820 |
|
|
typedef union {
|
| 7821 |
|
|
byte Byte;
|
| 7822 |
|
|
struct {
|
| 7823 |
|
|
byte PTIAD0 :1; /* Port AD Bit 0 */
|
| 7824 |
|
|
byte PTIAD1 :1; /* Port AD Bit 1 */
|
| 7825 |
|
|
byte PTIAD2 :1; /* Port AD Bit 2 */
|
| 7826 |
|
|
byte PTIAD3 :1; /* Port AD Bit 3 */
|
| 7827 |
|
|
byte PTIAD4 :1; /* Port AD Bit 4 */
|
| 7828 |
|
|
byte PTIAD5 :1; /* Port AD Bit 5 */
|
| 7829 |
|
|
byte PTIAD6 :1; /* Port AD Bit 6 */
|
| 7830 |
|
|
byte PTIAD7 :1; /* Port AD Bit 7 */
|
| 7831 |
|
|
} Bits;
|
| 7832 |
|
|
struct {
|
| 7833 |
|
|
byte grpPTIAD :8;
|
| 7834 |
|
|
} MergedBits;
|
| 7835 |
|
|
} PTIADSTR;
|
| 7836 |
|
|
extern volatile PTIADSTR _PTIAD @(REG_BASE + 0x00000271);
|
| 7837 |
|
|
#define PTIAD _PTIAD.Byte
|
| 7838 |
|
|
#define PTIAD_PTIAD0 _PTIAD.Bits.PTIAD0
|
| 7839 |
|
|
#define PTIAD_PTIAD1 _PTIAD.Bits.PTIAD1
|
| 7840 |
|
|
#define PTIAD_PTIAD2 _PTIAD.Bits.PTIAD2
|
| 7841 |
|
|
#define PTIAD_PTIAD3 _PTIAD.Bits.PTIAD3
|
| 7842 |
|
|
#define PTIAD_PTIAD4 _PTIAD.Bits.PTIAD4
|
| 7843 |
|
|
#define PTIAD_PTIAD5 _PTIAD.Bits.PTIAD5
|
| 7844 |
|
|
#define PTIAD_PTIAD6 _PTIAD.Bits.PTIAD6
|
| 7845 |
|
|
#define PTIAD_PTIAD7 _PTIAD.Bits.PTIAD7
|
| 7846 |
|
|
#define PTIAD_PTIAD _PTIAD.MergedBits.grpPTIAD
|
| 7847 |
|
|
|
| 7848 |
|
|
|
| 7849 |
|
|
/*** DDRAD - Port AD Data Direction Register; 0x00000272 ***/
|
| 7850 |
|
|
typedef union {
|
| 7851 |
|
|
byte Byte;
|
| 7852 |
|
|
struct {
|
| 7853 |
|
|
byte DDRAD0 :1; /* Port AD Data Direction Bit 0 */
|
| 7854 |
|
|
byte DDRAD1 :1; /* Port AD Data Direction Bit 1 */
|
| 7855 |
|
|
byte DDRAD2 :1; /* Port AD Data Direction Bit 2 */
|
| 7856 |
|
|
byte DDRAD3 :1; /* Port AD Data Direction Bit 3 */
|
| 7857 |
|
|
byte DDRAD4 :1; /* Port AD Data Direction Bit 4 */
|
| 7858 |
|
|
byte DDRAD5 :1; /* Port AD Data Direction Bit 5 */
|
| 7859 |
|
|
byte DDRAD6 :1; /* Port AD Data Direction Bit 6 */
|
| 7860 |
|
|
byte DDRAD7 :1; /* Port AD Data Direction Bit 7 */
|
| 7861 |
|
|
} Bits;
|
| 7862 |
|
|
struct {
|
| 7863 |
|
|
byte grpDDRAD :8;
|
| 7864 |
|
|
} MergedBits;
|
| 7865 |
|
|
} DDRADSTR;
|
| 7866 |
|
|
extern volatile DDRADSTR _DDRAD @(REG_BASE + 0x00000272);
|
| 7867 |
|
|
#define DDRAD _DDRAD.Byte
|
| 7868 |
|
|
#define DDRAD_DDRAD0 _DDRAD.Bits.DDRAD0
|
| 7869 |
|
|
#define DDRAD_DDRAD1 _DDRAD.Bits.DDRAD1
|
| 7870 |
|
|
#define DDRAD_DDRAD2 _DDRAD.Bits.DDRAD2
|
| 7871 |
|
|
#define DDRAD_DDRAD3 _DDRAD.Bits.DDRAD3
|
| 7872 |
|
|
#define DDRAD_DDRAD4 _DDRAD.Bits.DDRAD4
|
| 7873 |
|
|
#define DDRAD_DDRAD5 _DDRAD.Bits.DDRAD5
|
| 7874 |
|
|
#define DDRAD_DDRAD6 _DDRAD.Bits.DDRAD6
|
| 7875 |
|
|
#define DDRAD_DDRAD7 _DDRAD.Bits.DDRAD7
|
| 7876 |
|
|
#define DDRAD_DDRAD _DDRAD.MergedBits.grpDDRAD
|
| 7877 |
|
|
|
| 7878 |
|
|
|
| 7879 |
|
|
/*** RDRAD - Port AD Reduced Drive Register; 0x00000273 ***/
|
| 7880 |
|
|
typedef union {
|
| 7881 |
|
|
byte Byte;
|
| 7882 |
|
|
struct {
|
| 7883 |
|
|
byte RDRAD0 :1; /* Port AD Reduced Drive Bit 0 */
|
| 7884 |
|
|
byte RDRAD1 :1; /* Port AD Reduced Drive Bit 1 */
|
| 7885 |
|
|
byte RDRAD2 :1; /* Port AD Reduced Drive Bit 2 */
|
| 7886 |
|
|
byte RDRAD3 :1; /* Port AD Reduced Drive Bit 3 */
|
| 7887 |
|
|
byte RDRAD4 :1; /* Port AD Reduced Drive Bit 4 */
|
| 7888 |
|
|
byte RDRAD5 :1; /* Port AD Reduced Drive Bit 5 */
|
| 7889 |
|
|
byte RDRAD6 :1; /* Port AD Reduced Drive Bit 6 */
|
| 7890 |
|
|
byte RDRAD7 :1; /* Port AD Reduced Drive Bit 7 */
|
| 7891 |
|
|
} Bits;
|
| 7892 |
|
|
struct {
|
| 7893 |
|
|
byte grpRDRAD :8;
|
| 7894 |
|
|
} MergedBits;
|
| 7895 |
|
|
} RDRADSTR;
|
| 7896 |
|
|
extern volatile RDRADSTR _RDRAD @(REG_BASE + 0x00000273);
|
| 7897 |
|
|
#define RDRAD _RDRAD.Byte
|
| 7898 |
|
|
#define RDRAD_RDRAD0 _RDRAD.Bits.RDRAD0
|
| 7899 |
|
|
#define RDRAD_RDRAD1 _RDRAD.Bits.RDRAD1
|
| 7900 |
|
|
#define RDRAD_RDRAD2 _RDRAD.Bits.RDRAD2
|
| 7901 |
|
|
#define RDRAD_RDRAD3 _RDRAD.Bits.RDRAD3
|
| 7902 |
|
|
#define RDRAD_RDRAD4 _RDRAD.Bits.RDRAD4
|
| 7903 |
|
|
#define RDRAD_RDRAD5 _RDRAD.Bits.RDRAD5
|
| 7904 |
|
|
#define RDRAD_RDRAD6 _RDRAD.Bits.RDRAD6
|
| 7905 |
|
|
#define RDRAD_RDRAD7 _RDRAD.Bits.RDRAD7
|
| 7906 |
|
|
#define RDRAD_RDRAD _RDRAD.MergedBits.grpRDRAD
|
| 7907 |
|
|
|
| 7908 |
|
|
|
| 7909 |
|
|
/*** PERAD - Port AD Pull Device Enable Register; 0x00000274 ***/
|
| 7910 |
|
|
typedef union {
|
| 7911 |
|
|
byte Byte;
|
| 7912 |
|
|
struct {
|
| 7913 |
|
|
byte PERAD0 :1; /* Port AD Pull Device Enable Bit 0 */
|
| 7914 |
|
|
byte PERAD1 :1; /* Port AD Pull Device Enable Bit 1 */
|
| 7915 |
|
|
byte PERAD2 :1; /* Port AD Pull Device Enable Bit 2 */
|
| 7916 |
|
|
byte PERAD3 :1; /* Port AD Pull Device Enable Bit 3 */
|
| 7917 |
|
|
byte PERAD4 :1; /* Port AD Pull Device Enable Bit 4 */
|
| 7918 |
|
|
byte PERAD5 :1; /* Port AD Pull Device Enable Bit 5 */
|
| 7919 |
|
|
byte PERAD6 :1; /* Port AD Pull Device Enable Bit 6 */
|
| 7920 |
|
|
byte PERAD7 :1; /* Port AD Pull Device Enable Bit 7 */
|
| 7921 |
|
|
} Bits;
|
| 7922 |
|
|
struct {
|
| 7923 |
|
|
byte grpPERAD :8;
|
| 7924 |
|
|
} MergedBits;
|
| 7925 |
|
|
} PERADSTR;
|
| 7926 |
|
|
extern volatile PERADSTR _PERAD @(REG_BASE + 0x00000274);
|
| 7927 |
|
|
#define PERAD _PERAD.Byte
|
| 7928 |
|
|
#define PERAD_PERAD0 _PERAD.Bits.PERAD0
|
| 7929 |
|
|
#define PERAD_PERAD1 _PERAD.Bits.PERAD1
|
| 7930 |
|
|
#define PERAD_PERAD2 _PERAD.Bits.PERAD2
|
| 7931 |
|
|
#define PERAD_PERAD3 _PERAD.Bits.PERAD3
|
| 7932 |
|
|
#define PERAD_PERAD4 _PERAD.Bits.PERAD4
|
| 7933 |
|
|
#define PERAD_PERAD5 _PERAD.Bits.PERAD5
|
| 7934 |
|
|
#define PERAD_PERAD6 _PERAD.Bits.PERAD6
|
| 7935 |
|
|
#define PERAD_PERAD7 _PERAD.Bits.PERAD7
|
| 7936 |
|
|
#define PERAD_PERAD _PERAD.MergedBits.grpPERAD
|
| 7937 |
|
|
|
| 7938 |
|
|
|
| 7939 |
|
|
/*** PPSAD - Port AD Polarity Select Register; 0x00000275 ***/
|
| 7940 |
|
|
typedef union {
|
| 7941 |
|
|
byte Byte;
|
| 7942 |
|
|
struct {
|
| 7943 |
|
|
byte PPSAD0 :1; /* Port AD Polarity Select Bit 0 */
|
| 7944 |
|
|
byte PPSAD1 :1; /* Port AD Polarity Select Bit 1 */
|
| 7945 |
|
|
byte PPSAD2 :1; /* Port AD Polarity Select Bit 2 */
|
| 7946 |
|
|
byte PPSAD3 :1; /* Port AD Polarity Select Bit 3 */
|
| 7947 |
|
|
byte PPSAD4 :1; /* Port AD Polarity Select Bit 4 */
|
| 7948 |
|
|
byte PPSAD5 :1; /* Port AD Polarity Select Bit 5 */
|
| 7949 |
|
|
byte PPSAD6 :1; /* Port AD Polarity Select Bit 6 */
|
| 7950 |
|
|
byte PPSAD7 :1; /* Port AD Polarity Select Bit 7 */
|
| 7951 |
|
|
} Bits;
|
| 7952 |
|
|
struct {
|
| 7953 |
|
|
byte grpPPSAD :8;
|
| 7954 |
|
|
} MergedBits;
|
| 7955 |
|
|
} PPSADSTR;
|
| 7956 |
|
|
extern volatile PPSADSTR _PPSAD @(REG_BASE + 0x00000275);
|
| 7957 |
|
|
#define PPSAD _PPSAD.Byte
|
| 7958 |
|
|
#define PPSAD_PPSAD0 _PPSAD.Bits.PPSAD0
|
| 7959 |
|
|
#define PPSAD_PPSAD1 _PPSAD.Bits.PPSAD1
|
| 7960 |
|
|
#define PPSAD_PPSAD2 _PPSAD.Bits.PPSAD2
|
| 7961 |
|
|
#define PPSAD_PPSAD3 _PPSAD.Bits.PPSAD3
|
| 7962 |
|
|
#define PPSAD_PPSAD4 _PPSAD.Bits.PPSAD4
|
| 7963 |
|
|
#define PPSAD_PPSAD5 _PPSAD.Bits.PPSAD5
|
| 7964 |
|
|
#define PPSAD_PPSAD6 _PPSAD.Bits.PPSAD6
|
| 7965 |
|
|
#define PPSAD_PPSAD7 _PPSAD.Bits.PPSAD7
|
| 7966 |
|
|
#define PPSAD_PPSAD _PPSAD.MergedBits.grpPPSAD
|
| 7967 |
|
|
|
| 7968 |
|
|
|
| 7969 |
|
|
/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/
|
| 7970 |
|
|
typedef union {
|
| 7971 |
|
|
byte Byte;
|
| 7972 |
|
|
struct {
|
| 7973 |
|
|
byte :1;
|
| 7974 |
|
|
byte UNSEC :1; /* Unsecure */
|
| 7975 |
|
|
byte CLKSW :1; /* Clock switch */
|
| 7976 |
|
|
byte TRACE :1; /* TRACE1 BDM firmware command is being executed */
|
| 7977 |
|
|
byte SDV :1; /* Shift data valid */
|
| 7978 |
|
|
byte ENTAG :1; /* Tagging enable */
|
| 7979 |
|
|
byte BDMACT :1; /* BDM active status */
|
| 7980 |
|
|
byte ENBDM :1; /* Enable BDM */
|
| 7981 |
|
|
} Bits;
|
| 7982 |
|
|
} BDMSTSSTR;
|
| 7983 |
|
|
extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01);
|
| 7984 |
|
|
#define BDMSTS _BDMSTS.Byte
|
| 7985 |
|
|
#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC
|
| 7986 |
|
|
#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW
|
| 7987 |
|
|
#define BDMSTS_TRACE _BDMSTS.Bits.TRACE
|
| 7988 |
|
|
#define BDMSTS_SDV _BDMSTS.Bits.SDV
|
| 7989 |
|
|
#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG
|
| 7990 |
|
|
#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT
|
| 7991 |
|
|
#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM
|
| 7992 |
|
|
|
| 7993 |
|
|
|
| 7994 |
|
|
/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/
|
| 7995 |
|
|
typedef union {
|
| 7996 |
|
|
byte Byte;
|
| 7997 |
|
|
struct {
|
| 7998 |
|
|
byte CCR0 :1; /* BDM CCR Holding Bit 0 */
|
| 7999 |
|
|
byte CCR1 :1; /* BDM CCR Holding Bit 1 */
|
| 8000 |
|
|
byte CCR2 :1; /* BDM CCR Holding Bit 2 */
|
| 8001 |
|
|
byte CCR3 :1; /* BDM CCR Holding Bit 3 */
|
| 8002 |
|
|
byte CCR4 :1; /* BDM CCR Holding Bit 4 */
|
| 8003 |
|
|
byte CCR5 :1; /* BDM CCR Holding Bit 5 */
|
| 8004 |
|
|
byte CCR6 :1; /* BDM CCR Holding Bit 6 */
|
| 8005 |
|
|
byte CCR7 :1; /* BDM CCR Holding Bit 7 */
|
| 8006 |
|
|
} Bits;
|
| 8007 |
|
|
struct {
|
| 8008 |
|
|
byte grpCCR :8;
|
| 8009 |
|
|
} MergedBits;
|
| 8010 |
|
|
} BDMCCRSTR;
|
| 8011 |
|
|
extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06);
|
| 8012 |
|
|
#define BDMCCR _BDMCCR.Byte
|
| 8013 |
|
|
#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0
|
| 8014 |
|
|
#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1
|
| 8015 |
|
|
#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2
|
| 8016 |
|
|
#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3
|
| 8017 |
|
|
#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4
|
| 8018 |
|
|
#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5
|
| 8019 |
|
|
#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6
|
| 8020 |
|
|
#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7
|
| 8021 |
|
|
#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR
|
| 8022 |
|
|
|
| 8023 |
|
|
|
| 8024 |
|
|
/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/
|
| 8025 |
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typedef union {
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| 8026 |
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byte Byte;
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| 8027 |
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struct {
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| 8028 |
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byte :1;
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| 8029 |
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byte :1;
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| 8030 |
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byte :1;
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| 8031 |
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byte REG11 :1; /* Internal register map position */
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| 8032 |
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byte REG12 :1; /* Internal register map position */
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| 8033 |
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byte REG13 :1; /* Internal register map position */
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| 8034 |
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byte REG14 :1; /* Internal register map position */
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| 8035 |
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byte REG15 :1; /* Internal register map position */
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| 8036 |
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} Bits;
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| 8037 |
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struct {
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| 8038 |
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byte :1;
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| 8039 |
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byte :1;
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| 8040 |
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byte :1;
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| 8041 |
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byte grpREG_11 :5;
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| 8042 |
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} MergedBits;
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| 8043 |
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} BDMINRSTR;
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| 8044 |
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extern volatile BDMINRSTR _BDMINR @(0x0000FF07);
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| 8045 |
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#define BDMINR _BDMINR.Byte
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| 8046 |
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#define BDMINR_REG11 _BDMINR.Bits.REG11
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| 8047 |
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#define BDMINR_REG12 _BDMINR.Bits.REG12
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| 8048 |
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#define BDMINR_REG13 _BDMINR.Bits.REG13
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| 8049 |
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#define BDMINR_REG14 _BDMINR.Bits.REG14
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| 8050 |
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#define BDMINR_REG15 _BDMINR.Bits.REG15
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| 8051 |
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#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11
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| 8052 |
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#define BDMINR_REG BDMINR_REG_11
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| 8053 |
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| 8054 |
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| 8055 |
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/* Watchdog reset macro */
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| 8056 |
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#ifdef _lint
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| 8057 |
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#define __RESET_WATCHDOG() /* empty */
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| 8058 |
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#else
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| 8059 |
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#define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */
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| 8060 |
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#endif
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| 8061 |
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| 8062 |
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#endif
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| 8063 |
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| 8064 |
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/*
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** ###################################################################
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| 8066 |
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**
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| 8067 |
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** This file was created by UNIS Processor Expert 03.33 for
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| 8068 |
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** the Motorola HCS12 series of microcontrollers.
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| 8069 |
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**
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| 8070 |
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** ###################################################################
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| 8071 |
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*/
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| 8072 |
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