OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [HCS12_GCC_banked/] [asm-m68hcs12/] [ports.h] - Blame information for rev 621

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 588 jeremybenn
/* m68hc11/ports.h -- Definition of 68HC11 ports
2
   Copyright 1999, 2000, 2003 Free Software Foundation, Inc.
3
   Written by Stephane Carrez (stcarrez@nerim.fr)
4
 
5
   Modified by Jefferson L Smith, Robotronics Inc.
6
 
7
This file is part of GDB, GAS, and the GNU binutils.
8
 
9
GDB, GAS, and the GNU binutils are free software; you can redistribute
10
them and/or modify them under the terms of the GNU General Public
11
License as published by the Free Software Foundation; either version
12
1, or (at your option) any later version.
13
 
14
GDB, GAS, and the GNU binutils are distributed in the hope that they
15
will be useful, but WITHOUT ANY WARRANTY; without even the implied
16
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
17
the GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with this file; see the file COPYING.  If not, write to the Free
21
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
22
 
23
#ifndef _M68HC11_PORTS_H
24
#define _M68HC11_PORTS_H
25
 
26
#include "ports_def.h"
27
 
28
/** Define default SCI port registers */
29
#if defined(M6812_DEF_SCI)
30
 
31
#if M6812_DEF_SCI==2
32
# define SCI_BASE       SCI2_BASE
33
#elif M6812_DEF_SCI==1
34
# define SCI_BASE       SCI1_BASE
35
#else /* default M6812_DEF_SCI==0 */
36
# define SCI_BASE       SCI0_BASE
37
#endif /* default M6812_DEF_SCI==0 */
38
 
39
#else  /* M6812_DEF_SCI not defined */
40
# define SCI_BASE       SCI0_BASE
41
#endif /* M6812_DEF_SCI */
42
 
43
# define SCIBD          PORTIO_16(SCI_BASE + _SCIBD)
44
# define SCICR1         PORTIO_8(SCI_BASE + _SCICR1)
45
# define SCICR2         PORTIO_8(SCI_BASE + _SCICR2)
46
# define SCISR1         PORTIO_8(SCI_BASE + _SCISR1)
47
# define SCISR2         PORTIO_8(SCI_BASE + _SCISR2)
48
# define SCIDRL         PORTIO_8(SCI_BASE + _SCIDRL)
49
 
50
extern inline unsigned short
51
get_timer_counter (void)
52
{
53
  return TCNT;
54
}
55
 
56
extern inline void
57
set_timer_counter (unsigned short value)
58
{
59
  TCNT = value;
60
}
61
#if 0
62
extern inline unsigned short
63
get_input_capture_1 (void)
64
{
65
  return ((unsigned volatile short*) &_io_ports[M6811_TIC1_H])[0];
66
}
67
 
68
extern inline void
69
set_input_capture_1 (unsigned short value)
70
{
71
  ((unsigned volatile short*) &_io_ports[M6811_TIC1_H])[0] = value;
72
}
73
 
74
extern inline unsigned short
75
get_input_capture_2 (void)
76
{
77
  return ((unsigned volatile short*) &_io_ports[M6811_TIC2_H])[0];
78
}
79
 
80
extern inline void
81
set_input_capture_2 (unsigned short value)
82
{
83
  ((unsigned volatile short*) &_io_ports[M6811_TIC2_H])[0] = value;
84
}
85
 
86
extern inline unsigned short
87
get_input_capture_3 (void)
88
{
89
  return ((unsigned volatile short*) &_io_ports[M6811_TIC3_H])[0];
90
}
91
 
92
extern inline void
93
set_input_capture_3 (unsigned short value)
94
{
95
  ((unsigned volatile short*) &_io_ports[M6811_TIC3_H])[0] = value;
96
}
97
 
98
/* Get output compare 16-bit register.  */
99
extern inline unsigned short
100
get_output_compare_1 (void)
101
{
102
  return ((unsigned volatile short*) &_io_ports[M6811_TOC1_H])[0];
103
}
104
 
105
extern inline void
106
set_output_compare_1 (unsigned short value)
107
{
108
  ((unsigned volatile short*) &_io_ports[M6811_TOC1_H])[0] = value;
109
}
110
 
111
extern inline unsigned short
112
get_output_compare_2 (void)
113
{
114
  return ((unsigned volatile short*) &_io_ports[M6811_TOC2_H])[0];
115
}
116
 
117
extern inline void
118
set_output_compare_2 (unsigned short value)
119
{
120
  ((unsigned volatile short*) &_io_ports[M6811_TOC2_H])[0] = value;
121
}
122
 
123
extern inline unsigned short
124
get_output_compare_3 (void)
125
{
126
  return ((unsigned volatile short*) &_io_ports[M6811_TOC3_H])[0];
127
}
128
 
129
extern inline void
130
set_output_compare_3 (unsigned short value)
131
{
132
  ((unsigned volatile short*) &_io_ports[M6811_TOC3_H])[0] = value;
133
}
134
 
135
extern inline unsigned short
136
get_output_compare_4 (void)
137
{
138
  return ((unsigned volatile short*) &_io_ports[M6811_TOC4_H])[0];
139
}
140
 
141
extern inline void
142
set_output_compare_4 (unsigned short value)
143
{
144
  ((unsigned volatile short*) &_io_ports[M6811_TOC4_H])[0] = value;
145
}
146
 
147
extern inline unsigned short
148
get_output_compare_5 (void)
149
{
150
  return ((unsigned volatile short*) &_io_ports[M6811_TOC5_H])[0];
151
}
152
 
153
extern inline void
154
set_output_compare_5 (unsigned short value)
155
{
156
  ((unsigned volatile short*) &_io_ports[M6811_TOC5_H])[0] = value;
157
}
158
 
159
#endif
160
 
161
/* Reset the COP.  */
162
extern inline void
163
cop_reset (void)
164
{
165
  ARMCOP = 0x55;
166
  ARMCOP = 0xAA;
167
}
168
 
169
extern inline void
170
cop_optional_reset (void)
171
{
172
#if defined(M6811_USE_COP) && M6811_USE_COP == 1
173
  cop_reset ();
174
#endif
175
}
176
 
177
/* Acknowledge the timer interrupt.  */
178
extern inline void
179
timer_acknowledge (void)
180
{
181
  CRGFLG = RTIF;
182
}
183
 
184
/* Initialize the timer.  */
185
extern inline void
186
timer_initialize_rate (unsigned char divisor)
187
{
188
  RTICTL = divisor;
189
}
190
 
191
#endif /* _M68HC11_PORTS_H */
192
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.