OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [HCS12_GCC_banked/] [memory.x] - Blame information for rev 866

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 588 jeremybenn
/* Flash Memory Banks
2
   For Wytec Dragon12, Technological Arts Adapt9S12DP256
3
   with DBug12 v4 bootloader
4
 
5
   Author Jefferson L Smith; Robotronics, Inc.
6
  */
7
 
8
MEMORY
9
{
10
  page0 (rwx) : ORIGIN = 0x0, LENGTH = 256
11
 
12
  /* RAM */
13
  data (rwx)  : ORIGIN = 0x1000, LENGTH = 12k
14
 
15
  eeprom (rx): ORIGIN = 0x0400, LENGTH = 3k
16
  text (rx)  : ORIGIN = 0x4000, LENGTH = 16k
17
 
18
  /* high fixed bank, reserve 0x100 vectors and security. */
19
  text_h (rx)  : ORIGIN = 0xc000, LENGTH = 16k-0x100
20
 
21
  /* Flash memory banks */
22
  bank0  (rx)   : ORIGIN = 0x0d0000, LENGTH = 16k
23
  bank1  (rx)   : ORIGIN = 0x0d4000, LENGTH = 16k
24
  bank2  (rx)   : ORIGIN = 0x0d8000, LENGTH = 16k
25
  bank3  (rx)   : ORIGIN = 0x0dc000, LENGTH = 16k
26
  bank4  (rx)   : ORIGIN = 0x0e0000, LENGTH = 16k
27
  bank5  (rx)   : ORIGIN = 0x0e4000, LENGTH = 16k
28
  bank6  (rx)   : ORIGIN = 0x0e8000, LENGTH = 16k
29
  bank7  (rx)   : ORIGIN = 0x0ec000, LENGTH = 16k
30
  bank8  (rx)   : ORIGIN = 0x0f0000, LENGTH = 16k
31
  bank9  (rx)   : ORIGIN = 0x0f4000, LENGTH = 16k
32
  bank10 (rx)   : ORIGIN = 0x0f8000, LENGTH = 16k
33
  bank11 (rx)   : ORIGIN = 0x0fc000, LENGTH = 16k
34
  bank12 (rx)   : ORIGIN = 0x100000, LENGTH = 16k
35
  bank13 (rx)   : ORIGIN = 0x104000, LENGTH = 16k
36
 
37
  bank14 (rx)   : ORIGIN = 0x108000, LENGTH = 16k
38
  bank15 (rx)   : ORIGIN = 0x10c000, LENGTH = 16k-0x100
39
}
40
/* Setup the stack on the top of the data memory bank.  */
41
PROVIDE (_stack = 0x1000+12k);
42
 
43
/* interrupt/reset vectors*/
44
vectors_addr = 0x10ff80;
45
 
46
SECTIONS
47
{
48
  /* PPAGE memory banks */
49
 
50
  .bank2 :
51
  {
52
    ../Common/Minimal/flash.o(.text .rodata)
53
    *(.bank2)
54
  } > bank2
55
 
56
  .bank3 :
57
  {
58
    ParTest.o(.text .rodata)
59
    *(.bank3)
60
  } > bank3
61
 
62
}
63
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.