OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [HCS12_GCC_banked/] [sci.h] - Blame information for rev 617

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 588 jeremybenn
/**
2
 * sci.h controls SCI for GCC/HCS12 version of FreeRTOS Demo
3
 * Parts taken from the CodeWarrior Demo in order to work similar.
4
 *
5
 * Author Jefferson L Smith, Robotronics Inc.
6
 */
7
 
8
#ifndef __SCI
9
#define __SCI
10
 
11
#include "cpu.h"
12
 
13
#define COM0_Bm_38400baud         0    /* Constant for switch to mode 0 */
14
#define COM0_Bm_19200baud         1    /* Constant for switch to mode 1 */
15
#define COM0_Bm_9600baud          2    /* Constant for switch to mode 2 */
16
#define COM0_Bm_4800baud          3    /* Constant for switch to mode 3 */
17
 
18
 
19
/**
20
 * SCI_SetBaudRateMode
21
 *
22
 * Changes the speed (baud rate).
23
 */
24
byte SCI_SetBaudRateMode(byte Mod);
25
 
26
 
27
/**
28
 * SCI_Init (bean AsynchroSerial)
29
 *
30
 * This enables SCI.
31
 */
32
void SCI_Init(void);
33
 
34
#endif /* ifndef __SCI */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.