URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MB91460_Softune/] [PRC/] [set_SIMULATE.prc] - Blame information for rev 773

Go to most recent revision | Details | Compare with Previous | View Log


# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
# ELIGIBILITY FOR ANY PURPOSES.                                             */
#                 (C) Fujitsu Microelectronics Europe GmbH                  */
 
# Environment and memory manioulation after program upload
 
 
 
 
print "patch reset vector to \"__start\"\n";
SET MEMORY/WORD 0xFFFFC=__start
 

Line No.	Rev	Author	Line
1	584	jeremybenn	`# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */`
2			`# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */`
3			`# ELIGIBILITY FOR ANY PURPOSES. */`
4			`# (C) Fujitsu Microelectronics Europe GmbH */`
5
6			`# Environment and memory manioulation after program upload`
7
8
9
10
11			`print "patch reset vector to \"__start\"\n";`
12			`SET MEMORY/WORD 0xFFFFC=__start`
13

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MB91460_Softune/] [PRC/] [set_SIMULATE.prc] - Blame information for rev 773