Subversion Repositories openrisc_2011-10-31

/*      THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU       */

/*      MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR       */

/*      ELIGIBILITY FOR ANY PURPOSES.                                                   */

/*      (C) 2007,2008 Fujitsu Microelectronics Europe GmbH                              */

;=========================================================================================

; 1  Contents

;=========================================================================================

; 1       Contents

; 2       Disclaimer

;

; 3       History

;

; 4       Settings

; 4.1     Controller device

; 4.2     Boot / flash security

; 4.3     Stack type and stack size

; 4.4     Copy code from flash to I-RAM

; 4.5     C++ start-up

; 4.6     Low-level library interface

; 4.7     Clock Configuration

; 4.7.1   Clock selection

; 4.7.2   Select Clock Modulator

; 4.8     External bus interface

; 4.8.1   Select chipselect

; 4.8.2   Set memory addressing for chipselects

; 4.8.3   Configure chipselect area

; 4.8.4   Set wait cycles for chipselects

; 4.8.5   Configure chipselects SDRAM memory only

; 4.8.6   Referesh control register RCR

; 4.8.7   Terminal and timing control register

; 4.8.8   Enable / disable I-cache

; 4.8.9   Enable CACHE for chipselect

; 4.8.10  Select external bus mode (data lines)

; 4.8.11  Select external bus mode (address lines)

; 4.8.12  Select external bus mode (control signals)

;

; 5       Definitions of Configurations

;

; 6       Section and data declaration

; 6.1     Define stack size

; 6.2     Define sections

;

; 7.      S T A R T

; 7.1     Initialise stack pointer and table base register

; 7.2     Check for CSV reset and set CSV

; 7.3     Check clock condition

; 7.4     Restore default settings after reset

; 7.4.1   Disable clock modulator

; 7.4.2   Check if running on sub clock, change to main clock

; 7.4.3   Disable sub clock

; 7.4.4   Check if running on PLL, gear down PLL

; 7.4.5   Disable PLL

; 7.4.6   Set to main clock

; 7.5     Set memory controller

; 7.6     Clock startup

; 7.6.1   Set Voltage Regulator Settings

; 7.6.2   Power on clock modulator - clock modulator part I

; 7.6.3   Set CLKR register w/o clock mode

; 7.6.4   Start PLLs

; 7.6.5   Wait for PLL oscillation stabilisation

; 7.6.6   Set clocks

; 7.6.6.1 Set CPU and peripheral clock

; 7.6.6.2 Set external bus interface clock

; 7.6.6.3 Set CAN clock prescaler

; 7.6.6.4 Switch main clock mode

; 7.6.6.5 Switch sub clock mode

; 7.6.6.6 Switch to PLL mode

; 7.6.7   Enable frequncy modulation - clock modulator part II

; 7.7     Set BusInterface

; 7.7.1   Disable all CS

; 7.7.2   Clear TCR register

; 7.7.3   Set CS0

; 7.7.4   Set CS1

; 7.7.5   Set CS2

; 7.7.6   Set CS3

; 7.7.7   Set CS4

; 7.7.8   Set CS5

; 7.7.9   Set CS6

; 7.7.10  Set CS7

; 7.7.11  Set special SDRAM config register

; 7.7.12  set Port function register

; 7.7.13  Set TCR register

; 7.7.14  Enable cache for selected CS

; 7.7.15  Set SDRAM referesh control register

; 7.7.16  Enable used CS

; 7.7.17  I-cache on/off

; 7.7.18  Set port function register to general as I/O-port

; 7.8     Copy code from flash to I-RAM

; 7.9     Fill stacks

; 7.10    Clear data

; 7.11    Copy Init section from ROM to RAM

; 7.12    C library initialization

; 7.13    Call C++ constructors

; 7.14    Call main routine

; 7.15    Return from main function

;

;=========================================================================================

; 2  Disclaimer

;=========================================================================================

;                    Fujitsu Microelectronics Europe GmbH

;                http://emea.fujitsu.com/microelectronics

;

;    The  following  software  is for  demonstration  purposes only. It  is not fully

;    tested, nor  validated  in order to fullfill its task under  all  circumstances.

;    Therefore,  this software or  any part of it must only  be used in an evaluation

;    laboratory environment.

;    This  software  is  subject to  the  rules of  our  standard DISCLAIMER, that is

;    delivered with our  SW-tools on  the  Fujitsu  Microcontrollers  CD/DVD (V3.4 or

;    higher "\START.HTM") or on our Internet Pages:

;    http://www.fme.gsdc.de/gsdc.htm

;    http://emea.fujitsu.com/microelectronics

;

;=========================================================================================

; 3  History

;=========================================================================================

;

;=========================================================================================

;       MB914xx (FR60 CORE ONLY) Series C Compiler's

;

;       Startup file for memory and basic controller initialisation

;=========================================================================================

;History:

;

; 2005-04-18 V1.0 UMa  Release first version

; 2005-06-17 V1.1 UMa  Added bus interface, modified c++ startup

; 2005-06-28 V1.2 UMa  minor changes

; 2005-07-27 V1.3 UMa  default values changed

; 2005-10-04 V1.4 UMa  changed code 'Call main Routine'

;                      Added secutiy section for MB91F467D

;                      Added Flash Access Read Timing setting section;

; 2005-10-04 V1.5 UMa  Added Flash Controller Section

; 2005-10-28 V1.6 UMa  Check for CSV reset

; 2005-11.16 V1.7 UMa  Monitor Debugger support added: Copy of intvect Table

;                      Ext. Int 0 as abort function

;                      Changed PLL-Startup, Reset HWWD added

; 2005-11-16 V1.7 UMa  Examples for MUL_G changed

; 2006-02-14 V1.8 UMa  mb91464a added

;                      Settings for Clock Spervisor added

;                      Name of Section SECURITY changed to SECURITY_VECTORS

;                      Example values for gear-up changed

; 2006-03-17 V1.9 UMa  Changed Startup for Monitor Debugger

; 2006-04-24 v2.0 UMa  Added MB91465K and MB91469G

; 2006-05-03 v2.1 UMa  Added MB91461R; removed MB91V460A

;                      Added settings for the external bus-interface

; 2006-07-28 v2.2 UMa  Added I-RAM copy function (ROM -> IRAM)

;                      Added default settings for FLASH Access Read Timing

;                      Settings

;                      Changed default settings for FLASH cache configuration

;                      Register

;                      Changed check for clock startup

; 2006-08-16 v2.3 MVo  Corrected Boot Security Sector Addresses for MB91469G

; 2006-10-06 v2.4 UMa  Added new devices

;                      Corrected typo in I_RAM to flash copy function

;                      Changed default settings for flash cache configuration

;                      Changed comments for SDRAM bus interface configuration

;                      Changed comments and default setting of CAN Prescaler

;                      Added Stack filler

;                      Added Settings for REGSEL Register

; 2007-02-13 v2.5 UMa  Introduction of default configurations

;                      Changed I_RAM to flash copy function

;

;

;=========================================================================================

; 4  Settings

;=========================================================================================

;

; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION;

;

; Configure this startup file in the "Settings" section. Search for

; comments with leading "; <<<". This points to the items to be set.

;=========================================================================================

;

#set    OFF             0

#set    ON              1

#set    DEFAULT         2

#set    LOW_PRIOR       31

;

;=========================================================================================

; 4.1  Controller Device

;=========================================================================================

#set    MB91464A        2                       ; MB91460 series

;

#set    MB91467B       10                       ; MB91460 series

;

#set    MB91467C       11                       ; MB91460 series

;

#set    MB91467D        4                       ; MB91460 series

;

#set    MB91469G        6                       ; MB91460 series

;

#set    MB91465K        3                       ; MB91460 series

;

#set    MB91463N        8                       ; MB91460 series

;

#set    MB91461R        1                       ; MB91460 series

#set    MB91467R        5                       ; MB91460 series

;

#set    MB91465X        9                       ; MB91460 series

;

#set    others          7                       ; MB91460 series

;

;

;

#set    DEVICE          MB91467D                ; <<< select device

;

;=========================================================================================

; 4.2  Boot / Flash Security

;=========================================================================================

;

#set    BOOT_FLASH_SEC  OFF                     ; <<< BOOT and Flash Security Vector

;

; The flash devices have two flash and two boot security vectors.  It is important to set

; the four vectors correctly.  Otherwise it might be possible,  that the flash device is

; not accessible any more via the bootrom. Please read carefully the hardware manual.

;

; OFF:  The security feature is switch off. The section SECURITY_VECTORS is reserved and

;       the vectors are set.

; ON:   IMPORTANT! The  security vectors are  not set. But the  section SECURITY_VECTORS

;       is reserved.

;

; Note: This feature is not supported by every device. Please check the data sheet. This

;       feature is not available on MB91461R.

;

;=========================================================================================

; 4.3  Stack Type and Stack Size

;=========================================================================================

;

#set    USRSTACK        0                       ; user stack:   for main program

#set    SYSSTACK        1                       ; system stack: for main program and

;                                               ;               interrupts

;

;

#set    STACKUSE        SYSSTACK                ; <<< set active stack

;

#set    STACK_RESERVE   ON                      ; <<< reserve stack area in

;                                               ;     this module

#set    STACK_SYS_SIZE  1000                    ; <<< byte size of System stack

#set    STACK_USR_SIZE  4                       ; <<< byte size of User stack

;

#set    STACK_FILL      ON                     ; <<< fills the stack area with pattern

#set    STACK_PATTERN   0x55AA55AA              ; <<< the pattern to write to stack

;

; - If the active stack is set to SYSSTACK,  it is used for main program and interrupts.

;   In this case,  the user stack  could be set to a dummy size.  If the active stack is

;   set  to  user  stack,  it is  used  for the  main  program  but the  system stack is

;   automatically activated,  if an interrupt is serviced.  Both stack areas must have a

;   reasonable size.

; - If STACK_RESERVE is ON,  the sections USTACK and SSTACK are reserved in this module.

;   Otherwise, they have to be reserved in other modules.  If STACK_RESERVE is OFF,  the

;   size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning.

; - Even if  they  are reverved  in other modules,  they are  still initialised  in this

;   start-up file.

;

; Note: Several library functions require quite a big stack (due to ANSI).

;       Check the stack information files (*.stk) in the LIB\911 directory.

;

;=========================================================================================

; 4.4  Copy code from Flash to I-RAM

;=========================================================================================

;

#set    I_RAM           OFF                     ; <<< select  if  code  in  section IRAM

;                                                     should be copied

;

; If this option is activated code located in the  section IRAM is copied during startup

; from ROM to the instruction-RAM. The code is linked for the instruction-RAM.

;

;=========================================================================================

; 4.5  Low-Level Library Interface

;=========================================================================================

;

#set    CLIBINIT        OFF                     ; <<< select ext. libray usage

;

; This option has only to be set,  if  stream-IO/standard-IO function  of the C-libraray

; have to be used (printf(), fopen()...).  This also requires  low-level functions to be

; defined by the application software.

; For other library functions like (e.g. sprintf()) all this is not necessary.  However,

; several functions consume a large amount of stack.

;

;=========================================================================================

; 4.6  C++ start-up

;=========================================================================================

;

#set    CPLUSPLUS       OFF                     ; <<< activate if c++ files are used

;

; In the  C++ specifications,  when external  or static objects are used,  a constructor

; must be called followed by  the main function.  Because four-byte pointers to the main

; function are stored in the EXT_CTOR_DTOR section, call a constructor sequentially from

; the  lower  address  of  the four  addresses  in that  section.  If using C++ sources,

; activate this function to create the section EXT_CTOR_DTOR.

;

;=========================================================================================

; 4.7  Clock Configuration

;=========================================================================================

;=========================================================================================

; 4.7.1  Clock Selection

;=========================================================================================

;

; No clock settings

#set    NO_CLOCK                                               0x01

;

; Sub-oscillation input: 32 kHz

#set    SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ     0x11

;

; Oscillation input: 4 MHz

#set    MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ     0x21

#set    PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ     0x22

#set    PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ     0x23

#set    PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ     0x24

#set    PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ     0x25

#set    PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ     0x26  ;not MB91V460, ...

#set    PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ     0x27  ;not MB91V460, ...

;

; MB91461R only: Oscillation input: 10 MHz

#set    PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ     0x41

;

; MB91461R only: Oscillation input: 20 MHz

#set    PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ     0x51

;

; User settings

#set    CLOCK_USER                                             0x61

;

;

;

#set    CLOCKSPEED      PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ

;                                               ; <<< Select clock configuration

;

; There are different default configurations available, where all necessary settings for

; clocks and the related  registers are made.  Beside this configurations,  there is the

; possibility   to  define  a  user   configuration   in  the  chapter   "Definition  of

; Configurations"

;

; - NO_CLOCK means:

;   The clock registers are not set by the start-up file.

;

; - PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ means:

;   Main oszillation        =  4 MHz, PLL is activated

;   CPU clock (CLKB)        = 64 MHZ

;   Peripheral clock (CLKP) = 16 MHZ

;   Ext. bus clock (CLKT)   = 32 MHZ

;   CAN clock (CLKCAN)      = 16 MHz, using PLLx

;

; - CLOCK_USER:

;   The user configuration definded in the chapter "Definition of Configurations" is set.

;

; Note: Not all  frequencies  are supported  by every device.  Please see  the  hardware

;       manual.

;

;=========================================================================================

; 4.7.2  Select Clock Modulator

;=========================================================================================

;

#set    CLOMO           OFF                     ; <<< Enable /disable clock modulator

;

#set    CMPR            0x026F                  ; <<< Ref. to the data sheet, CMPR

;

; Please  refer  to the data sheet  of the device  if you  enable clock modulation.  The

; register CMPR dependant on the PLL-Clock.

;

; Note: If the CLKCAN source is set either to main oscillator or to PLL  output then the

;       clock  for  the CAN  is not influenced by  the clock  modulation.  If the CLKCAN

;       source is set CPU clock (CLKB) then the clock for the CAN is also modulated  (if

;       the clock modulator is enabled).

;

; Note: If the clock modulator is enabled,  the wait states  of the  internal flash wait

;       states  must  be  adapted  to  maximum frequency.  Please check the  wait states

;       settings.

;

; Note: This feature  is not supported by every device,  e.g. MB91461.  Please check the

;       data sheet.

;

;=========================================================================================

; 4.8  External Bus Interface

;

;      The rest of the configuration is only applicable for devices with an external bus

;      interface.

;

;      If the device does not offer an external bus interface,  the configuration can be

;      stoped at this point.

;

;=========================================================================================

;

#set    EXTBUS          DEFAULT                 ; <<< Ext. Bus on/off

;

;                       ON      - The ext. bus interface is enabled and is configured as

;                                 set below.

;

;                       OFF     - The ext. bus interface is  diabled.  The port function

;                                 registers  are set to  general I/O.  The registers  of

;                                 ext. bus interface will not be touched by the start-up

;                                 file.

;                                 Be aware, that the device  might be conifgured in ext.

;                                 bus mode by default after reset.

;

;                       DEFAULT - Neither the register nor the respective  port function

;                                 registers are touched by the start-up file.

;                                 Be aware, that the device  might be conifgured in ext.

;                                 bus mode by default after reset.

;

;

; Note: This feature is not supported by every device. Please check the data sheet.  The

;       following devices for example do not offer an external bus interface:  MB91464A,

;       MB91467C, MB91465K, MB91463N, MB91465X.

;

;=========================================================================================

; 4.8.1  Select Chipselect (Only EXTBUS == ON)

;=========================================================================================

;

#set    CS0             OFF                     ; <<< select CS (ON/OFF)

#set    CS1             OFF                     ; <<< select CS (ON/OFF)

#set    CS2             OFF                     ; <<< select CS (ON/OFF)

#set    CS3             OFF                     ; <<< select CS (ON/OFF)

#set    CS4             OFF                     ; <<< select CS (ON/OFF)

#set    CS5             OFF                     ; <<< select CS (ON/OFF)

#set    CS6             OFF                     ; <<< select CS (ON/OFF)

#set    CS7             OFF                     ; <<< select CS (ON/OFF)

#set    SDRAM           OFF                     ; <<< select if a SDRAM is connected

;

;

#set    ENACSX          B'00000000              ; <<< set CS, ENACSX

;                         ||||||||

;                         ||||||||__ CS0 bit, enable/disable CS0 (1/0)

;                         |||||||___ CS1 bit, enable/disable CS1 (1/0)

;                         ||||||____ CS2 bit, enable/disable CS2 (1/0)

;                         |||||_____ CS3 bit, enable/disable CS3 (1/0)

;                         ||||______ CS4 bit, enable/disable CS4 (1/0)

;                         |||_______ CS5 bit, enable/disable CS5 (1/0)

;                         ||________ CS6 bit, enable/disable CS6 (1/0)

;                         |_________ CS7 bit, enable/disable CS7 (1/0)

;

; Note: If the SWB Monitor Debugger is used,  set the CS1 (external RAM only) or CS0 and

;       CS 1 (external RAM and flash) to off.

;

; Note: Not all Chipselects  are supported by  the different devices.  Please check  the

;       data sheet.

;

;=========================================================================================

; 4.8.2  Set memory addressing for Chipselects (only EXTBUS == ON)

;=========================================================================================

;

#set    AREASEL0        0x0000                  ; <<< set start add. for CS0, ASR0

#set    AREASEL1        0x0000                  ; <<< set start add. for CS1, ASR1

#set    AREASEL2        0x0000                  ; <<< set start add. for CS2, ASR2

#set    AREASEL3        0x0000                  ; <<< set start add. for CS3, ASR3

#set    AREASEL4        0x0000                  ; <<< set start add. for CS4, ASR4

#set    AREASEL5        0x0000                  ; <<< set start add. for CS5, ASR5

#set    AREASEL6        0x0000                  ; <<< set start add. for CS6, ASR6

#set    AREASEL7        0x0000                  ; <<< set start add. for CS7, ASR7

;

; Configure the starting address of each used Chipselect. Chipselects which are not used

; (not set to ON in "Select Chipselect") need not be set (setting ignored).

;

; NOTE: Just  the upper 16-bit  of the start address must be set,  e.g. when using start

;       address 0x00080000 set 0x0008.

;

;=========================================================================================

; 4.8.3  Configure Chipselect Area (only EXTBUS == ON)

;=========================================================================================

;

#set    CONFIGCS0       B'0000000000000000      ; <<< Config. CS0, ACR0

#set    CONFIGCS1       B'0000000000000000      ; <<< Config. CS1, ACR1

#set    CONFIGCS2       B'0000000000000000      ; <<< Config. CS2, ACR2

#set    CONFIGCS3       B'0000000000000000      ; <<< Config. CS3, ACR3

#set    CONFIGCS4       B'0000000000000000      ; <<< Config. CS4, ACR4

#set    CONFIGCS5       B'0000000000000000      ; <<< Config. CS5, ACR5

#set    CONFIGCS6       B'0000000000000000      ; <<< Config. CS6, ACR6

#set    CONFIGCS7       B'0000000000000000      ; <<< Config. CS7, ACR7

;                         ||||||||||||||||

;                         ||||||||||||||||__ TYP0 bit, TYP0-4 bits select access type

;                         |||||||||||||||___ TYP1 bit

;                         ||||||||||||||____ TYP2 bit

;                         |||||||||||||_____ TYP3 bit

;                         ||||||||||||______ LEND bit, select little '1' or big endian '0'

;                         |||||||||||_______ WREN bit, en-/disable (1/0) Write access

;                         ||||||||||________ PFEN bit, en-/disable (1/0) pre-fetch

;                         |||||||||_________ SREN bit, en-/disable (1/0) share of BRQ & BGRNTX

;                         ||||||||__________ BST0 bit, BSTx bits select burst size

;                         |||||||___________ BST1 bit

;                         ||||||____________ DBW0 bit, DBWx select data bus width

;                         |||||_____________ DBW1 bit

;                         ||||______________ ASZ0 bit, ASZx bits select address size of CS

;                         |||_______________ ASZ1 bit

;                         ||________________ ASZ2 bit

;                         |_________________ ASZ3 bit

;

; Bit description:

;

; TYP3 TYP2 TYP1 TYP0  : Select access type of each CS

; 0    0    X    X     : Normal access (asynchronous SRAM, I/O,

;                        single/page/busrt-ROM/FLASH)

; 0    1    X    X     : Address/data multiplexed (8bit / 16bit bus width only)

; 0    X    X    0     : WAIT insertion by RDY disabled

; 0    X    X    1     : WAIT insertion by RDY enabled

; 0    X    0    X     : The WR0X pin to the WR3X pin are used as write strobes

;                        (WRX is fixed at H-Level)

; 0    X    1    X     : The WRX pin is used as write strobe

; 1    0    0    0     : Memory type A: SDRAM/FCRAM (Auto pre-charge used)

; 1    0    0    1     : Memory type B: FCRAM (Auto pre-charge used)

; 1    0    1    0     : setting not allowed

; 1    0    1    1     : setting not allowed

; 1    1    0    0     : setting not allowed

; 1    1    0    1     : setting not allowed

; 1    1    1    0     : setting not allowed

; 1    1    1    1     : mask area setting

;

;               LEND   : select BYTE ordering

;                0     : Big endian

;                1     : Little endian

;

;               WREN   : enable or disable write access

;                0     : disabled

;                1     : enabled,

;

;               PFEN   : Enable or disable the pre-fetch

;                0     : disabled

;                1     : enabled,

;

;               SREN   : Enable or disable the sharing of BRQ and BGRNTX

;                0     : disabled

;                1     : enabled (CSx pin High-Z)

;

;          BST1 BST0   : set burst size of chip select area

;            0   0     : 1 burst (single access)

;            0   1     : 2 bursts (Address boundary 1 bit)

;            1   0     : 4 bursts (Address boundary 2 bit)

;            1   1     : 8 bursts (Address boundary 3 bit)

;

;          DBW1 DBW0   : Set data bus width

;            0   0     : 8-bit (BYTE access)

;            0   1     : 16-bit (HALF-WORD access)

;            1   0     : 32-bit (WORD access)

;            1   1     : Reserved

;

; ASZ3 ASZ2 ASZ1 ASZ0  :  Select memory size of each chipselect

; 0    0    0    0     : 64 Kbyte  (0x01.0000 bytes; use ASR A[31:16] bits)

; 0    0    0    1     : 128 Kbyte (0x02.0000 bytes; use ASR A[31:17] bits)

; 0    0    1    0     : 256 Kbyte (0x04.0000 bytes; use ASR A[31:18] bits)

; 0    0    1    1     : 512 Kbyte (0x08.0000 bytes; use ASR A[31:19] bits)

; 0    1    0    0     : 1 Mbyte   (0x10.0000 bytes; use ASR A[31:20] bits)

; 0    1    0    1     : 2 Mbyte   (0x20.0000 bytes; use ASR A[31:21] bits)

; 0    1    1    0     : 4 Mbyte   (0x40.0000 bytes; use ASR A[31:22] bits)

; 0    1    1    1     : 8 Mbyte   (0x80.0000 bytes; use ASR A[31:23] bits)

; 1    0    0    0     : 16 Mbyte  (0x100.0000 bytes; use ASR A[31:24] bits)

; 1    0    0    1     : 32 Mbyte  (0x200.0000 bytes; use ASR A[31:25] bits)

; 1    0    1    0     : 64 Mbyte  (0x400.0000 bytes; use ASR A[31:26] bits)

; 1    0    1    1     : 128 Mbyte (0x800.0000 bytes; use ASR A[31:27] bits)

; 1    1    0    0     : 256 Mbyte (0x1000.0000 bytes; use ASR A[31:28] bits)

; 1    1    0    1     : 512 Mbyte (0x2000.0000 bytes; use ASR A[31:29] bits)

; 1    1    1    0     : 1024 Mbyte(0x4000.0000 bytes; use ASR A[31:30] bits)

; 1    1    1    1     : 2048 Mbyte(0x8000.0000 bytes; use ASR A[31] bit)

;

;=========================================================================================

; 4.8.4  Set Wait cycles for Chipselects for ordinary businterface (only EXTBUS == ON)

;=========================================================================================

;

; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)

;

#set    WAITREG0        B'0000000000000000      ; <<< CS0 Waitstates, AWR0

#set    WAITREG1        B'0000000000000000      ; <<< CS1 Waitstates, AWR1

#set    WAITREG2        B'0000000000000000      ; <<< CS2 Waitstates, AWR2

#set    WAITREG3        B'0000000000000000      ; <<< CS3 Waitstates, AWR3

#set    WAITREG4        B'0000000000000000      ; <<< CS4 Waitstates, AWR4

#set    WAITREG5        B'0000000000000000      ; <<< CS5 Waitstates, AWR5

;                         ||||||||||||||||

;                         ||||||||||||||||__ W00 bit, RDY/WRY-> CSX hold cycle

;                         |||||||||||||||___ W01 bit, CSX->RDX/WRX setup extension cycle

;                         ||||||||||||||____ W02 bit, Address -> CSX Delay selection

;                         |||||||||||||_____ W03 bit, WR0X to WR3X/WRX outout timing

;                         ||||||||||||______ W04 bit, W04/W05 Write recovery cycle

;                         |||||||||||_______ W05 bit

;                         ||||||||||________ W06 bit, W06/07 Read -> Write idle cycle

;                         |||||||||_________ W07 bit          selection

;                         ||||||||__________ W08 bit, W08-W11 Intra-page access cycle

;                         |||||||___________ W09 bit          select (0-15 cycles)

;                         ||||||____________ W10 bit

;                         |||||_____________ W11 bit

;                         ||||______________ W12 bit, W12-W15 First access wait cycle

;                         |||_______________ W13 bit          select (0-15 cycles)

;                         ||________________ W14 bit

;                         |_________________ W15 bit

;

;

; SDRAM and FRAM bus interface (ACRx_Type = 100x)

;

#set    WAITREG6        B'0000000000000000      ; <<< CS6 Waitstates, AWR6

#set    WAITREG7        B'0000000000000000      ; <<< CS7 Waitstates, AWR7

;                         ||||||||||||||||

;                         ||||||||||||||||__ W00 bit, W0-W1 RAS precharge cycles

;                         |||||||||||||||___ W01 bit

;                         ||||||||||||||____ W02 bit, W2-W3 RAS active Time

;                         |||||||||||||_____ W03 bit

;                         ||||||||||||______ W04 bit, W4-W5 Write recovery cycle

;                         |||||||||||_______ W05 bit

;                         ||||||||||________ W06 bit, W6-W7 Read->Write idle cycle

;                         |||||||||_________ W07 bit

;                         ||||||||__________ W08 bit, W8-W10 CAS latency

;                         |||||||___________ W09 bit

;                         ||||||____________ W10 bit

;                         |||||_____________ W11 bit, reserved

;                         ||||______________ W12 bit, W12-W16 RAS-CAS delay

;                         |||_______________ W13 bit

;                         ||________________ W14 bit

;                         |_________________ W15 bit, reserved

;

;

; The bit meaning depends on the configured bus interface type. The bus interface can be

; configured for different memory types. Depending on the memory type, the wait register

; bits have a differnt meaning.  CS0-5 should  be configurable as ordinary bus interface

; (w/o SDRAM and FRAM)  and CS6-7 should be configurable as  SDRAM and FRAM.  It is also

; possible and for some devices neccessary to configure  other two chip selects as SDRAM

; or FRAM interface. In such a case be aware of the bit meanings.

;

;

; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)

; --------------------------------------------------------------

;

; Bit description:

;

;                W00   : RDY/WRX -> CSX hold extension cycle

;                0     : 0 cycle

;                1     : 1 cycle

;

;                W01   : CSX -> RDX/WRX setup extention cycle

;                0     : 0 cycle

;                1     : 1 cycle

;

;                W02   : Address -> CSX Delay selection

;                0     : no delay selected

;                1     : delay selected

;

;                W03   : WR0X to WR3X/WRX outout timing selection

;                0     : MCLK synchronous write output enable (ASX=L)

;                1     : Asynchronous write strobe output (norma operation)

;

;           W05  W04   : select Write recovery cycle

;           0    0     : 0 cycle

;           0    1     : 1 cycle

;           1    0     : 2 cycles

;           1    1     : 3 cycles

;

;           W07  W06   : Read -> Write idle cycle selection

;           0    0     : 0 cycle

;           0    1     : 1 cycle

;           1    0     : 2 cycles

;           1    1     : 3 cycles

;

; W11  W10  W09  W08   :  Intra-page access cycle select (0-15 cycles)

; 0    0    0    0     :  0 Wait state

; 0    0    0    1     :  1 Auto-wait cycle

; 0    0    1    0     :  2 Auto-wait cycle

; ....

; 1    1    1    1     :  15 Auto wait cycles

;

; W15  W14  W13  W12   :  First access wait cycle can be set (0-15 cycles)

; 0    0    0    0     :  0 Wait state

; 0    0    0    1     :  1 Auto-wait cycle

; 0    0    1    0     :  2 Auto-wait cycle

; ....

; 1    1    1    1     :  15 Auto wait cycles

;

;

;

; SDRAM and FRAM bus interface (ACRx_Type = 100x)

; -----------------------------------------------

;

; Bit description:

;

;           W01  W00   : RAS precharge cycles.

;           0    0     : 1 cycle

;           0    1     : 2 cycles

;           1    0     : 5 cycles

;           1    1     : 6 cycles

;

;           W03  W02   : RAS active Time

;           0    0     : 1 cycle

;           0    1     : 2 cycles

;           1    0     : 5 cycles

;           1    1     : 6 cycles

;

;           W05  W04   : set Write recovery cycle (1 - 4 cycles)

;           0    0     : Prohibited

;           0    1     : 2 cycles

;           1    0     : 3 cycles

;           1    1     : 4 cycles

;

;           W07  W06   : set Read -> Write idle Cycle (1 - 4 cycles)

;           0    0     : 1 cycle

;           0    1     : 2 cycles

;           1    0     : 3 cycles

;           1    1     : 4 cycles

;

;      W10  W09  W08   : set CAS latency (1 - 8 cycles)

;      0    0    0     : 1 cycle

;      0    0    1     : 2 cycle

;      ...

;      1    1    1     : 8 cycle

;

;                W11   : RESERVED, ALWAYS WRITE 0 !

;

;      W14  W13  W12   : set RAS-CAS delay (1 - 8 cycles)

;      0    0    0     : 1 cycle

;      0    0    1     : 2 cycle

;      ...

;      1    1    1     : 8 cycle

;

;                W15   : RESERVED, ALWAYS WRITE 0 !

;

; The bit meaning depends on the configured bus interface type

;

;=========================================================================================

; 4.8.5  Configure Chipselects for SDRAM memory only (only EXTBUS == ON and SDRAM)

;=========================================================================================

;

#set    MEMCON           B'00000111             ; <<< set special SDRAM register, MCRA

;                          ||||||||

;                          ||||||||__ ABS0 bit, set max. active banks (ABS1,0)

;                          |||||||___ ABS1 bit

;                          ||||||____ BANK bit, set number of banks connected to CS

;                          |||||_____ WBST bit, Write burst enable/disable

;                          ||||______ PSZ0 bit, Set page size (PSZ2-0)

;                          |||_______ PSZ1 bit

;                          ||________ PSZ2 bit

;                          |_________ reserved, always write 0

;

; When connecting  SDRAM/FCRAM TYP3-0=1000  in ACRx register the following register must

; be setup.

;

; Bit description:

;

;           ABS1  ABS0 : Set maximum number of bank, active at same time

;            0     0   : 1 bank

;            0     1   : 2 banks

;            1     0   : 3 banks

;            1     1   : 4 banks

;

;                 BANK : Set number of connected SDRAM banks

;                  0   : 2 banks

;                  1   : 4 banks

;

;                 WBST : Write burst enable

;                  0   : Single Write

;                  1   : Busrt Write

;

;      PSZ2  PSZ1  PS0 : Select page size of connected memory

;      0     0     0   : 8-bit column address = A0 to A7

;      0     0     1   : 9-bit column address = A0 to A8

;      0     1     0   : 10-bit column address = A0 to A9

;      0     1     1   : 11-bit column address = A0 to A9, A11

;      1     X     X   : setting disabled

;

;

;=========================================================================================

; 4.8.6  Referesh Control Register RCR (only EXTBUS == ON and SDRAM)

;=========================================================================================

;

#set    REFRESH         B'1110001001000111      ; <<< set Refresh Control Register, RCR

;                         ||||||||||||||||

;                         ||||||||||||||||__ TRC0 bit, set refresh cycle (TRC2-0)

;                         |||||||||||||||___ TRC1 bit

;                         ||||||||||||||____ TRC2 bit

;                         |||||||||||||_____ PON bit, set power-on control

;                         ||||||||||||______ RFC0 bit, set refresh count (RFC2-0)

;                         |||||||||||_______ RFC1 bit

;                         ||||||||||________ RFC2 bit

;                         |||||||||_________ BRST bit, set burst refresh control

;                         ||||||||__________ RFINT0 bit, set auto refresh interval

;                         |||||||___________ RFINT1 bit, (RFINT5-0)

;                         ||||||____________ RFINT2 bit

;                         |||||_____________ RFINT3 bit

;                         ||||______________ RFINT4 bit

;                         |||_______________ RFINT5 bit

;                         ||________________ RRLD bit, counter refresh strat control

;                         |_________________ SELF bit, self refresh control

;

;

; This register sets various SDRAM refresh controls.  When SDRAM control is not set  for

; any area, the setting of this register is meaningless,  but do not change the register

; value  at  initial   state.   When  a  read is  performed   using  a read-modify-write

; instruction, 0 always returns from the SELF, RRLD, and PON bits.

;

; Bit description:

;

;

;    TRC2  TRC1  TRC0  : Refresh Cycle

;      0     0     0   : 4

;      0     0     1   : 5

;      0     1     0   : 6

;      0     1     1   : 7

;      1     0     0   : 8

;      1     0     1   : 9

;      1     1     0   : 10

;      1     1     1   : 11

;

;                 PON  : Power-on control

;                  0   : disabled

;                  1   : power-on sequence started

;

;     RFC2  RFC1  RFC0 : Refresh Count

;      0     0     0   : 256

;      0     0     1   : 512

;      0     1     0   : 1024

;      0     1     1   : 2048

;      1     0     0   : 4096

;      1     0     1   : 8192

;      1     1     0   : Setting disabled

;      1     1     1   : Refresh disabled

;

;                 BRST : Burst refresh control

;                  0   : Decentralised refresh

;                  1   : burst refresh

;

;           RFINT[5-0] : auto refresh interval

;

;                 RRLD : Refresh counter Activation Control

;                  0   : Disabled,

;                  1   : Autorefresh performed once, then value of RFINT reloaded

;

;                 SELF : Self refresh control

;                  0   : auto refresh or power down

;                  1   : Transitions to self-refresch mode

;

; NOTE: PON bit is set after the above setting. Do not set PON bit to 1 in the

;       above setting. Otherwise the settings are not correct set.

;

;=========================================================================================

; 4.8.7  Terminal and Timing Control Register (only EXTBUS == ON)

;=========================================================================================

;

#set    TIMECONTR        B'00000000             ; <<< set TCR register, TCR

;                          ||||||||

;                          ||||||||__ RDW0 bit, set wait cycle reduction (RDW0,1)

;                          |||||||___ RDW1 bit

;                          ||||||____ OHT0 bit, set output hold delay (OHT1,0)

;                          |||||_____ OHT1 bit

;                          ||||______ reserved, always write 0

;                          |||_______ PCLR bit, prefetch buffer clear

;                          ||________ PSUS bit, prefetch suspend

;                          |_________ BREN bit, BRQ input enable

;

; This register controls the general functions  of the external bus interface controller

; such as the common-pin function setting and timing control.

;

; Bit description:

;

;          RDW1  RDW0  : Wait cycle reduction

;            0     0   : Normal Wait (AWR0 - 7 setting)

;            0     1   : 1/2 of AWR0 - 7 setting value

;            1     0   : 1/4 of AWR0 - 7 setting value

;            1     1   : 1/8 of AWR0 - 7 setting value

;

;          OHT1  OHT0  : Output hold selection bit

;            0     0   : Output performed at falling edge of SYSCLK/MCLK

;            0     1   : Output performed about 3ns after falling edge of SYSCLK/MCLK

;            1     0   : Output performed about 4ns after falling edge of SYSCLK/MCLK

;            1     1   : Output performed about 5ns after falling edge of SYSCLK/MCLK

;

;                PCLR  : Prefetch buffer all clear

;                  0   : normal state

;                  1   : Prefetch buffer cleared

;

;                PSUS  : prefetch suspension bit

;                  0   : Prefetch enabled

;                  1   : Prefetch disabled

;

;                BREN  : BRQ input enable

;                  0   : disabled,

;                  1   : enabled, Bus sharing of BRQ/BGRNTX performed

;

; Note: This function is used to prevent an  excessive access cycle wait while operating

;       at  a low-speed  clock  (such as  while  base  clock  operating at low  speed or

;       high frequency division rate for external bus clock).

;

;=========================================================================================

; 4.8.8  Enable/Disable I-CACHE (only EXTBUS == ON)

;=========================================================================================

;

#set    C1024           1                       ; CACHE Size: 1024 BYTE

#set    C2048           2                       ; CACHE Size: 2048 BYTE

#set    C4096           3                       ; CACHE Size: 4096 BYTE

;

;

#set    CACHE           OFF                     ; <<< Select use of cache

#set    CACHE_SIZE      C4096                   ; <<< Select size of cache, ISIZE

;

; It is possible  to use cache  functionality on  the I-Bus on  several devices.  Please

; check the  corresponidng data sheet  if this feature is  available on a certain device

; and for the size of the cache. This is the general cache configuration. It is possible

; to configure for each CS area, if the cache should be used.

;

; Note: This feature is not supported by every device. Please check the data  sheet. The

;       feature is for example supported by MB91461R, MB91469G.

;

;=========================================================================================

; 4.8.9  Enable CACHE for chipselect (only EXTBUS == ON)

;=========================================================================================

;

#set    CHEENA          B'11111111              ; <<< en-/disable cache, CHER

;                         ||||||||

;                         ||||||||__ CHE0 bit, CS0 area

;                         |||||||___ CHE1 bit, CS1 area

;                         ||||||____ CHE2 bit, CS2 area

;                         |||||_____ CHE3 bit, CS3 area

;                         ||||______ CHE4 bit, CS4 area

;                         |||_______ CHE5 bit, CS5 area

;                         ||________ CHE6 bit, CS6 area

;                         |_________ CHE7 bit, CS7 area

;

; Additional to  the general cache enable setting,  select which CS  area should be used

; with cache functionality.

;

; Note: Not all  Chipselects are  supported by the  different devices.  Please check the

;       data sheet.

;

; Note: This feature is not supported by every device.  Please check the data sheet. The

;       Feature is supported by MB91461R, MB91469G.

;

;=========================================================================================

; 4.8.10  Select External bus mode (Data lines) (only EXTBUS == ON)

;=========================================================================================

;

#set    PFUNC0          B'11111111              ;<<< Data lines or GIO, PFR00

;                         ||||||||

;                         ||||||||__ D24 / P00_0

;                         |||||||___ D25 / P00_1

;                         ||||||____ D26 / P00_2

;                         |||||_____ D27 / P00_3

;                         ||||______ D28 / P00_4

;                         |||_______ D29 / P00_5

;                         ||________ D30 / P00_6

;                         |_________ D31 / P00_7

;

#set    PFUNC1          B'11111111              ;<<< Data lines or GIO, PFR01

;                         ||||||||

;                         ||||||||__ D16 / P01_0

;                         |||||||___ D17 / P01_1

;                         ||||||____ D18 / P01_2

;                         |||||_____ D19 / P01_3

;                         ||||______ D20 / P01_4