OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MB91460_Softune/] [SRC/] [serial/] [serial.c] - Blame information for rev 600

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 584 jeremybenn
/*
2
    FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
3
 
4
    ***************************************************************************
5
    *                                                                         *
6
    * If you are:                                                             *
7
    *                                                                         *
8
    *    + New to FreeRTOS,                                                   *
9
    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
10
    *    + Looking for basic training,                                        *
11
    *    + Wanting to improve your FreeRTOS skills and productivity           *
12
    *                                                                         *
13
    * then take a look at the FreeRTOS books - available as PDF or paperback  *
14
    *                                                                         *
15
    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
16
    *                  http://www.FreeRTOS.org/Documentation                  *
17
    *                                                                         *
18
    * A pdf reference manual is also available.  Both are usually delivered   *
19
    * to your inbox within 20 minutes to two hours when purchased between 8am *
20
    * and 8pm GMT (although please allow up to 24 hours in case of            *
21
    * exceptional circumstances).  Thank you for your support!                *
22
    *                                                                         *
23
    ***************************************************************************
24
 
25
    This file is part of the FreeRTOS distribution.
26
 
27
    FreeRTOS is free software; you can redistribute it and/or modify it under
28
    the terms of the GNU General Public License (version 2) as published by the
29
    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
30
    ***NOTE*** The exception to the GPL is included to allow you to distribute
31
    a combined work that includes FreeRTOS without being obliged to provide the
32
    source code for proprietary components outside of the FreeRTOS kernel.
33
    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
34
    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35
    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
36
    more details. You should have received a copy of the GNU General Public
37
    License and the FreeRTOS license exception along with FreeRTOS; if not it
38
    can be viewed here: http://www.freertos.org/a00114.html and also obtained
39
    by writing to Richard Barry, contact details for whom are available on the
40
    FreeRTOS WEB site.
41
 
42
    1 tab == 4 spaces!
43
 
44
    http://www.FreeRTOS.org - Documentation, latest information, license and
45
    contact details.
46
 
47
    http://www.SafeRTOS.com - A version that is certified for use in safety
48
    critical systems.
49
 
50
    http://www.OpenRTOS.com - Commercial support, development, porting,
51
    licensing and training services.
52
*/
53
 
54
 
55
/*
56
 * BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.
57
 *
58
 * This file only supports UART 2
59
 */
60
 
61
/* Standard includes. */
62
#include <stdlib.h>
63
 
64
/* Scheduler includes. */
65
#include "FreeRTOS.h"
66
#include "queue.h"
67
#include "task.h"
68
 
69
/* Demo application includes. */
70
#include "serial.h"
71
 
72
/* The queue used to hold received characters. */
73
static xQueueHandle xRxedChars;
74
 
75
/* The queue used to hold characters waiting transmission. */
76
static xQueueHandle xCharsForTx;
77
 
78
static volatile portSHORT sTHREEmpty;
79
 
80
/*-----------------------------------------------------------*/
81
 
82
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
83
{
84
        portENTER_CRITICAL();
85
        {
86
                /* Create the queues used by the com test task. */
87
                xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
88
                xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
89
 
90
                 /* Initialize UART asynchronous mode */
91
                BGR02 = configPER_CLOCK_HZ / ulWantedBaud;
92
 
93
                SCR02 = 0x17;   /* 8N1 */
94
                SMR02 = 0x0d;   /* enable SOT3, Reset, normal mode */
95
                SSR02 = 0x02;   /* LSB first, enable receive interrupts */
96
 
97
                PFR20_D0 = 1;   /* enable UART */
98
                PFR20_D1 = 1;   /* enable UART */
99
 
100
                EPFR20_D1 = 0;  /* enable UART */
101
        }
102
        portEXIT_CRITICAL();
103
 
104
        /* Unlike other ports, this serial code does not allow for more than one
105
        com port.  We therefore don't return a pointer to a port structure and can
106
        instead just return NULL. */
107
        return NULL;
108
}
109
/*-----------------------------------------------------------*/
110
 
111
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
112
{
113
        /* Get the next character from the buffer.  Return false if no characters
114
        are available, or arrive before xBlockTime expires. */
115
        if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
116
        {
117
                return pdTRUE;
118
        }
119
        else
120
        {
121
                return pdFALSE;
122
        }
123
}
124
/*-----------------------------------------------------------*/
125
 
126
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
127
{
128
signed portBASE_TYPE xReturn;
129
 
130
        /* Transmit a character. */
131
        portENTER_CRITICAL();
132
        {
133
                if( sTHREEmpty == pdTRUE )
134
                {
135
                        /* If sTHREEmpty is true then the UART Tx ISR has indicated that
136
                        there are no characters queued to be transmitted - so we can
137
                        write the character directly to the shift Tx register. */
138
                        sTHREEmpty = pdFALSE;
139
                        TDR02 = cOutChar;
140
                        xReturn = pdPASS;
141
                }
142
                else
143
                {
144
                        /* sTHREEmpty is false, so there are still characters waiting to be
145
                        transmitted.  We have to queue this character so it gets
146
                        transmitted     in turn. */
147
 
148
                        /* Return false if after the block time there is no room on the Tx
149
                        queue.  It is ok to block inside a critical section as each task
150
                        maintains it's own critical section status. */
151
                        if (xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdTRUE)
152
                        {
153
                                xReturn = pdPASS;
154
                        }
155
                        else
156
                        {
157
                                xReturn = pdFAIL;
158
                        }
159
                }
160
 
161
                if (pdPASS == xReturn)
162
                {
163
                        /* Turn on the Tx interrupt so the ISR will remove the character from the
164
                        queue and send it.   This does not need to be in a critical section as
165
                        if the interrupt has already removed the character the next interrupt
166
                        will simply turn off the Tx interrupt again. */
167
                        SSR02_TIE = 1;
168
                }
169
 
170
        }
171
        portEXIT_CRITICAL();
172
 
173
        return pdPASS;
174
}
175
/*-----------------------------------------------------------*/
176
 
177
/*
178
 * UART RX interrupt service routine.
179
 */
180
 __interrupt void UART2_RxISR (void)
181
{
182
        signed portCHAR cChar;
183
        portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
184
 
185
        /* Get the character from the UART and post it on the queue of Rxed
186
        characters. */
187
        cChar = RDR02;
188
 
189
        xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
190
 
191
        if( xHigherPriorityTaskWoken )
192
        {
193
                /*If the post causes a task to wake force a context switch
194
                as the woken task may have a higher priority than the task we have
195
                interrupted. */
196
                portYIELD_FROM_ISR();
197
        }
198
}
199
 
200
/*-----------------------------------------------------------*/
201
 
202
/*
203
 * UART Tx interrupt service routine.
204
 */
205
__interrupt void UART2_TxISR (void)
206
{
207
        signed portCHAR cChar;
208
        signed portBASE_TYPE xTaskWoken = pdFALSE;
209
 
210
        /* The previous character has been transmitted.  See if there are any
211
        further characters waiting transmission. */
212
        if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
213
        {
214
                /* There was another character queued - transmit it now. */
215
                TDR02 = cChar;
216
        }
217
        else
218
        {
219
                /* There were no other characters to transmit. */
220
                sTHREEmpty = pdTRUE;
221
 
222
                /* Disable transmit interrupts */
223
                SSR02_TIE = 0;
224
        }
225
}
226
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.