OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MB91460_Softune/] [SRC/] [vectors.c] - Blame information for rev 745

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 584 jeremybenn 
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
2 
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
3 
/* ELIGIBILITY FOR ANY PURPOSES.                                                                                         */
4 
/*                               (C) Fujitsu Microelectronics Europe GmbH                                 */
5 
/*------------------------------------------------------------------------
6 
  VECTORS.C
7 
  - Interrupt level (priority) setting
8 
  - Interrupt vector definition
9 
 
10 
  31.04.05  1.00   UMa  Initial Version
11 
  08.11.05  1.01   MSt  SWB Mondeb switch for ICR00 Register added
12 
  27.02.06  1.02   UMa  added comment in DefaultIRQHandler
13 
  17.03.06  1.03   UMa  comment out ICR01
14 
  28.07.06  1.04   UMa  changed comment
15 
  06.10.06  1.05   UMa  changed DefaultIRQHandler
16 
-------------------------------------------------------------------------*/
17 
 
18 
#include "mb91467d.h"
19 
#include "watchdog.h"
20 
#include "FreeRTOSConfig.h"
21 
 
22 
/*------------------------------------------------------------------------
23 
  InitIrqLevels()
24 
 
25 
  This function  pre-sets all interrupt control registers. It can be used
26 
  to set all interrupt priorities in static applications. If this file
27 
  contains assignments to dedicated resources, verify  that the
28 
  appropriate controller is used. Not all devices of the MB91460 Series
29 
  offer all recources.
30 
 
31 
  NOTE: value 31 disables the interrupt and value 16 sets highest priority.
32 
-------------------------------------------------------------------------*/
33 
void InitIrqLevels(void)
34 
{
35 
        /*  ICRxx */
36 
        /* Softune Workbench Monitor Debugger is using ext int0 for abort function */
37 
        /*  ICR00 = 31;  *//* External Interrupt 0               */
38 
                                                                                                /* External Interrupt 1         */
39 
        ICR01 = 31;                                                                     /* External Interrupt 2         */
40 
                                                                                                /* External Interrupt 3         */
41 
        ICR02 = 31;                                                                     /* External Interrupt 4         */
42 
                                                                                                /* External Interrupt 5         */
43 
        ICR03 = 31;                                                                     /* External Interrupt 6         */
44 
                                                                                                /* External Interrupt 7         */
45 
        ICR04 = 31;                                                                     /* External Interrupt 8         */
46 
                                                                                                /* External Interrupt 9         */
47 
        ICR05 = 31;                                                                     /* External Interrupt 10        */
48 
                                                                                                /* External Interrupt 11        */
49 
        ICR06 = 31;                                                                     /* External Interrupt 12        */
50 
                                                                                                /* External Interrupt 13        */
51 
        ICR07 = 31;                                                                     /* External Interrupt 14        */
52 
                                                                                                /* External Interrupt 15        */
53 
        ICR08 = configKERNEL_INTERRUPT_PRIORITY;        /* Reload Timer 0                       */
54 
                                                                                                /* Reload Timer 1                       */
55 
        ICR09 = 31;                                                                     /* Reload Timer 2                       */
56 
                                                                                                /* Reload Timer 3                       */
57 
        ICR10 = 31;                                                                     /* Reload Timer 4                       */
58 
                                                                                                /* Reload Timer 5                       */
59 
        ICR11 = 31;                                                                     /* Reload Timer 6                       */
60 
                                                                                                /* Reload Timer 7                       */
61 
        ICR12 = 31;                                                                     /* Free Run Timer 0                     */
62 
                                                                                                /* Free Run Timer 1                     */
63 
        ICR13 = 31;                                                                     /* Free Run Timer 2                     */
64 
                                                                                                /* Free Run Timer 3                     */
65 
        ICR14 = 31;                                                                     /* Free Run Timer 4                     */
66 
                                                                                                /* Free Run Timer 5                     */
67 
        ICR15 = 31;                                                                     /* Free Run Timer 6                     */
68 
                                                                                                /* Free Run Timer 7                     */
69 
        ICR16 = 31;                                                                     /* CAN 0                                        */
70 
                                                                                                /* CAN 1                                        */
71 
        ICR17 = 31;                                                                     /* CAN 2                                        */
72 
                                                                                                /* CAN 3                                        */
73 
        ICR18 = 31;                                                                     /* CAN 4                                        */
74 
                                                                                                /* CAN 5                                        */
75 
        ICR19 = 31;                                                                     /* USART (LIN) 0 RX                     */
76 
                                                                                                /* USART (LIN) 0 TX                     */
77 
        ICR20 = 31;                                                                     /* USART (LIN) 1 RX                     */
78 
                                                                                                /* USART (LIN) 1 TX                     */
79 
        ICR21 = configKERNEL_INTERRUPT_PRIORITY;        /* USART (LIN) 2 RX                     */
80 
                                                                                                /* USART (LIN) 2 TX                     */
81 
        ICR22 = 31;                                                                     /* USART (LIN) 3 RX                     */
82 
                                                                                                /* USART (LIN) 3 TX                     */
83 
        ICR23 = configKERNEL_INTERRUPT_PRIORITY;        /* System Reserved                      */
84 
                                                                                                /* Delayed Interrupt            */
85 
        ICR24 = 31;                                                                     /* System Reserved                      */
86 
                                                                                                /* System Reserved                      */
87 
        ICR25 = 31;                                                                     /* USART (LIN, FIFO) 4 RX       */
88 
                                                                                                /* USART (LIN, FIFO) 4 TX       */
89 
        ICR26 = configKERNEL_INTERRUPT_PRIORITY;        /* USART (LIN, FIFO) 5 RX       */
90 
                                                                                                /* USART (LIN, FIFO) 5 TX       */
91 
        ICR27 = 31;                                                                     /* USART (LIN, FIFO) 6 RX       */
92 
                                                                                                /* USART (LIN, FIFO) 6 TX       */
93 
        ICR28 = 31;                                                                     /* USART (LIN, FIFO) 7 RX       */
94 
                                                                                                /* USART (LIN, FIFO) 7 TX       */
95 
        ICR29 = 31;                                                                     /* I2C 0 / I2C 2                        */
96 
                                                                                                /* I2C 1 / I2C 3                        */
97 
        ICR30 = 31;                                                                     /* USART (LIN, FIFO) 8 RX       */
98 
                                                                                                /* USART (LIN, FIFO) 8 TX       */
99 
        ICR31 = 31;                                                                     /* USART (LIN, FIFO) 9 RX       */
100 
                                                                                                /* USART (LIN, FIFO) 9 TX       */
101 
        ICR32 = 31;                                                                     /* USART (LIN, FIFO) 10 RX      */
102 
                                                                                                /* USART (LIN, FIFO) 10 TX      */
103 
        ICR33 = 31;                                                                     /* USART (LIN, FIFO) 11 RX      */
104 
                                                                                                /* USART (LIN, FIFO) 11 TX      */
105 
        ICR34 = 31;                                                                     /* USART (LIN, FIFO) 12 RX      */
106 
                                                                                                /* USART (LIN, FIFO) 12 TX      */
107 
        ICR35 = 31;                                                                     /* USART (LIN, FIFO) 13 RX      */
108 
                                                                                                /* USART (LIN, FIFO) 13 TX      */
109 
        ICR36 = 31;                                                                     /* USART (LIN, FIFO) 14 RX      */
110 
                                                                                                /* USART (LIN, FIFO) 14 TX      */
111 
        ICR37 = 31;                                                                     /* USART (LIN, FIFO) 15 RX      */
112 
                                                                                                /* USART (LIN, FIFO) 15 TX      */
113 
        ICR38 = 31;                                                                     /* Input Capture 0                      */
114 
                                                                                                /* Input Capture 1                      */
115 
        ICR39 = 31;                                                                     /* Input Capture 2                      */
116 
                                                                                                /* Input Capture 3                      */
117 
        ICR40 = 31;                                                                     /* Input Capture 4                      */
118 
                                                                                                /* Input Capture 5                      */
119 
        ICR41 = 31;                                                                     /* Input Capture 6                      */
120 
                                                                                                /* Input Capture 7                      */
121 
        ICR42 = 31;                                                                     /* Output Compare 0                     */
122 
                                                                                                /* Output Compare 1                     */
123 
        ICR43 = 31;                                                                     /* Output Compare 2                     */
124 
                                                                                                /* Output Compare 3                     */
125 
        ICR44 = 31;                                                                     /* Output Compare 4                     */
126 
                                                                                                /* Output Compare 5                     */
127 
        ICR45 = 31;                                                                     /* Output Compare 6                     */
128 
                                                                                                /* Output Compare 7                     */
129 
        ICR46 = 31;                                                                     /* Sound Generator                      */
130 
                                                                                                /* Phase Frequ. Modulator       */
131 
        ICR47 = 31;                                                                     /* System Reserved                      */
132 
                                                                                                /* System Reserved                      */
133 
        ICR48 = 31;                                                                     /* Prog. Pulse Gen. 0           */
134 
                                                                                                /* Prog. Pulse Gen. 1           */
135 
        ICR49 = 31;                                                                     /* Prog. Pulse Gen. 2           */
136 
                                                                                                /* Prog. Pulse Gen. 3           */
137 
        ICR50 = 31;                                                                     /* Prog. Pulse Gen. 4           */
138 
                                                                                                /* Prog. Pulse Gen. 5           */
139 
        ICR51 = 31;                                                                     /* Prog. Pulse Gen. 6           */
140 
                                                                                                /* Prog. Pulse Gen. 7           */
141 
        ICR52 = 31;                                                                     /* Prog. Pulse Gen. 8           */
142 
                                                                                                /* Prog. Pulse Gen. 9           */
143 
        ICR53 = 31;                                                                     /* Prog. Pulse Gen. 10          */
144 
                                                                                                /* Prog. Pulse Gen. 11          */
145 
        ICR54 = 31;                                                                     /* Prog. Pulse Gen. 12          */
146 
                                                                                                /* Prog. Pulse Gen. 13          */
147 
        ICR55 = 31;                                                                     /* Prog. Pulse Gen. 14          */
148 
                                                                                                /* Prog. Pulse Gen. 15          */
149 
        ICR56 = 31;                                                                     /* Up/Down Counter 0            */
150 
                                                                                                /* Up/Down Counter 1            */
151 
        ICR57 = 31;                                                                     /* Up/Down Counter 2            */
152 
                                                                                                /* Up/Down Counter 3            */
153 
        ICR58 = 31;                                                                     /* Real Time Clock                      */
154 
                                                                                                /* Calibration Unit                     */
155 
        ICR59 = 31;                                                                     /* A/D Converter 0                      */
156 
                                                                                                /* -                                            */
157 
        ICR60 = 31;                                                                     /* Alarm Comperator 0           */
158 
                                                                                                /* Alarm Comperator 1           */
159 
        ICR61 = 31;                                                                     /* Low Volage Detector          */
160 
                                                                                                /* SMC Zero Point 0-5           */
161 
        ICR62 = 31;                                                                     /* Timebase Overflow            */
162 
                                                                                                /* PLL Clock Gear                       */
163 
        ICR63 = 31;                                                                     /* DMA Controller                       */
164 
                                                                                                /* Main/Sub OSC stability wait  */
165 
}
166 
 
167 
 
168 
/*------------------------------------------------------------------------
169 
  Prototypes
170 
 
171 
  Add your own prototypes here. Each vector definition needs is proto-
172 
  type. Either do it here or include a header file containing them.
173 
-------------------------------------------------------------------------*/
174 
__interrupt void DefaultIRQHandler (void);
175 
extern __interrupt void ReloadTimer0_IRQHandler ( void );
176 
extern __interrupt void vPortYield ( void );
177 
extern __interrupt void vPortYieldDelayed (void);
178 
 
179 
extern __interrupt void UART2_RxISR(void);
180 
extern __interrupt void UART2_TxISR(void);
181 
extern __interrupt void UART5_RxISR(void);
182 
 
183 
/*------------------------------------------------------------------------
184 
   Vector definiton
185 
 
186 
   Use following statements to define vectors. All resource related
187 
   vectors are predefined. Remaining software interrupts can be added here
188 
   as well.
189 
------------------------------------------------------------------------*/
190 
#pragma intvect 0xBFF8                  0         /* (fixed) reset vector                */
191 
#pragma intvect 0x06000000              1        /* (fixed) Mode Byte                   */
192 
 
193 
#pragma intvect DefaultIRQHandler 15    /* Non Maskable Interrupt       */
194 
#pragma intvect DefaultIRQHandler 16    /* External Interrupt 0         */
195 
#pragma intvect DefaultIRQHandler 17    /* External Interrupt 1         */
196 
 
197 
#pragma intvect DefaultIRQHandler 18    /* External Interrupt 2         */
198 
 
199 
#pragma intvect DefaultIRQHandler 19    /* External Interrupt 3         */
200 
#pragma intvect DefaultIRQHandler 20    /* External Interrupt 4         */
201 
#pragma intvect DefaultIRQHandler 21    /* External Interrupt 5         */
202 
#pragma intvect DefaultIRQHandler 22    /* External Interrupt 6         */
203 
#pragma intvect DefaultIRQHandler 23    /* External Interrupt 7         */
204 
#pragma intvect DefaultIRQHandler 24    /* External Interrupt 8         */
205 
#pragma intvect DefaultIRQHandler 25    /* External Interrupt 9         */
206 
#pragma intvect DefaultIRQHandler 26    /* External Interrupt 10        */
207 
#pragma intvect DefaultIRQHandler 27    /* External Interrupt 11        */
208 
#pragma intvect DefaultIRQHandler 28    /* External Interrupt 12        */
209 
#pragma intvect DefaultIRQHandler 29    /* External Interrupt 13        */
210 
#pragma intvect DefaultIRQHandler 30    /* External Interrupt 14        */
211 
#pragma intvect DefaultIRQHandler 31    /* External Interrupt 15        */
212 
 
213 
#pragma intvect ReloadTimer0_IRQHandler 32      /* Reload Timer 0               */
214 
 
215 
#pragma intvect DefaultIRQHandler 33    /* Reload Timer 1                       */
216 
#pragma intvect DefaultIRQHandler 34    /* Reload Timer 2                       */
217 
#pragma intvect DefaultIRQHandler 35    /* Reload Timer 3                       */
218 
#pragma intvect DefaultIRQHandler 36    /* Reload Timer 4                       */
219 
#pragma intvect DefaultIRQHandler 37    /* Reload Timer 5                       */
220 
#pragma intvect DefaultIRQHandler 38    /* Reload Timer 6                       */
221 
#pragma intvect DefaultIRQHandler 39    /* Reload Timer 7                       */
222 
#pragma intvect DefaultIRQHandler 40    /* Free Run Timer 0                     */
223 
#pragma intvect DefaultIRQHandler 41    /* Free Run Timer 1                     */
224 
#pragma intvect DefaultIRQHandler 42    /* Free Run Timer 2                     */
225 
#pragma intvect DefaultIRQHandler 43    /* Free Run Timer 3                     */
226 
#pragma intvect DefaultIRQHandler 44    /* Free Run Timer 4                     */
227 
#pragma intvect DefaultIRQHandler 45    /* Free Run Timer 5                     */
228 
#pragma intvect DefaultIRQHandler 46    /* Free Run Timer 6                     */
229 
#pragma intvect DefaultIRQHandler 47    /* Free Run Timer 7                     */
230 
#pragma intvect DefaultIRQHandler 48    /* CAN 0                                        */
231 
#pragma intvect DefaultIRQHandler 49    /* CAN 1                                        */
232 
#pragma intvect DefaultIRQHandler 50    /* CAN 2                                        */
233 
#pragma intvect DefaultIRQHandler 51    /* CAN 3                                        */
234 
#pragma intvect DefaultIRQHandler 52    /* CAN 4                                        */
235 
#pragma intvect DefaultIRQHandler 53    /* CAN 5                                        */
236 
#pragma intvect DefaultIRQHandler 54    /* USART (LIN) 0 RX                     */
237 
#pragma intvect DefaultIRQHandler 55    /* USART (LIN) 0 TX                     */
238 
#pragma intvect DefaultIRQHandler 56    /* USART (LIN) 1 RX                     */
239 
#pragma intvect DefaultIRQHandler 57    /* USART (LIN) 1 TX                     */
240 
 
241 
#pragma intvect UART2_RxISR       58    /* USART (LIN) 2 RX                     */
242 
#pragma intvect UART2_TxISR       59    /* USART (LIN) 2 TX                     */
243 
 
244 
#pragma intvect DefaultIRQHandler 60    /* USART (LIN) 3 RX                     */
245 
#pragma intvect DefaultIRQHandler 61    /* USART (LIN) 3 TX                     */
246 
#pragma intvect DefaultIRQHandler 62    /* System Reserved                      */
247 
 
248 
#pragma intvect vPortYieldDelayed 63    /* Delayed Interrupt            */
249 
 
250 
#pragma intvect vPortYield              64              /* INT 64                                       */
251 
 
252 
#pragma intvect DefaultIRQHandler 65    /* System Reserved                      */
253 
#pragma intvect DefaultIRQHandler 66    /* USART (LIN, FIFO) 4 RX       */
254 
#pragma intvect DefaultIRQHandler 67    /* USART (LIN, FIFO) 4 TX       */
255 
 
256 
#pragma intvect UART5_RxISR        68           /* USART (LIN, FIFO) 5 RX       */
257 
 
258 
#pragma intvect DefaultIRQHandler 69    /* USART (LIN, FIFO) 5 TX       */
259 
#pragma intvect DefaultIRQHandler 70    /* USART (LIN, FIFO) 6 RX       */
260 
#pragma intvect DefaultIRQHandler 71    /* USART (LIN, FIFO) 6 TX       */
261 
#pragma intvect DefaultIRQHandler 72    /* USART (LIN, FIFO) 7 RX       */
262 
#pragma intvect DefaultIRQHandler 73    /* USART (LIN, FIFO) 7 TX       */
263 
#pragma intvect DefaultIRQHandler 74    /* I2C 0 / I2C 2                        */
264 
#pragma intvect DefaultIRQHandler 75    /* I2C 1 / I2C 3                        */
265 
#pragma intvect DefaultIRQHandler 76    /* USART (LIN, FIFO) 8 RX       */
266 
#pragma intvect DefaultIRQHandler 77    /* USART (LIN, FIFO) 8 TX       */
267 
#pragma intvect DefaultIRQHandler 78    /* USART (LIN, FIFO) 9 RX       */
268 
#pragma intvect DefaultIRQHandler 79    /* USART (LIN, FIFO) 9 TX       */
269 
#pragma intvect DefaultIRQHandler 80    /* USART (LIN, FIFO) 10 RX      */
270 
#pragma intvect DefaultIRQHandler 81    /* USART (LIN, FIFO) 10 TX      */
271 
#pragma intvect DefaultIRQHandler 82    /* USART (LIN, FIFO) 11 RX      */
272 
#pragma intvect DefaultIRQHandler 83    /* USART (LIN, FIFO) 11 TX      */
273 
#pragma intvect DefaultIRQHandler 84    /* USART (LIN, FIFO) 12 RX      */
274 
#pragma intvect DefaultIRQHandler 85    /* USART (LIN, FIFO) 12 TX      */
275 
#pragma intvect DefaultIRQHandler 86    /* USART (LIN, FIFO) 13 RX      */
276 
#pragma intvect DefaultIRQHandler 87    /* USART (LIN, FIFO) 13 TX      */
277 
#pragma intvect DefaultIRQHandler 88    /* USART (LIN, FIFO) 14 RX      */
278 
#pragma intvect DefaultIRQHandler 89    /* USART (LIN, FIFO) 14 TX      */
279 
#pragma intvect DefaultIRQHandler 90    /* USART (LIN, FIFO) 15 RX      */
280 
#pragma intvect DefaultIRQHandler 91    /* USART (LIN, FIFO) 15 TX      */
281 
#pragma intvect DefaultIRQHandler 92    /* Input Capture 0                      */
282 
#pragma intvect DefaultIRQHandler 93    /* Input Capture 1                      */
283 
#pragma intvect DefaultIRQHandler 94    /* Input Capture 2                      */
284 
#pragma intvect DefaultIRQHandler 95    /* Input Capture 3                      */
285 
#pragma intvect DefaultIRQHandler 96    /* Input Capture 4                      */
286 
#pragma intvect DefaultIRQHandler 97    /* Input Capture 5                      */
287 
#pragma intvect DefaultIRQHandler 98    /* Input Capture 6                      */
288 
#pragma intvect DefaultIRQHandler 99    /* Input Capture 7                      */
289 
#pragma intvect DefaultIRQHandler 100   /* Output Compare 0                     */
290 
#pragma intvect DefaultIRQHandler 101   /* Output Compare 1                     */
291 
#pragma intvect DefaultIRQHandler 102   /* Output Compare 2                     */
292 
#pragma intvect DefaultIRQHandler 103   /* Output Compare 3                     */
293 
#pragma intvect DefaultIRQHandler 104   /* Output Compare 4                     */
294 
#pragma intvect DefaultIRQHandler 105   /* Output Compare 5                     */
295 
#pragma intvect DefaultIRQHandler 106   /* Output Compare 6                     */
296 
#pragma intvect DefaultIRQHandler 107   /* Output Compare 7                     */
297 
#pragma intvect DefaultIRQHandler 108   /* Sound Generator                      */
298 
#pragma intvect DefaultIRQHandler 109   /* Phase Frequ. Modulator       */
299 
#pragma intvect DefaultIRQHandler 110   /* System Reserved                      */
300 
#pragma intvect DefaultIRQHandler 111   /* System Reserved                      */
301 
#pragma intvect DefaultIRQHandler 112   /* Prog. Pulse Gen. 0           */
302 
#pragma intvect DefaultIRQHandler 113   /* Prog. Pulse Gen. 1           */
303 
#pragma intvect DefaultIRQHandler 114   /* Prog. Pulse Gen. 2           */
304 
#pragma intvect DefaultIRQHandler 115   /* Prog. Pulse Gen. 3           */
305 
#pragma intvect DefaultIRQHandler 116   /* Prog. Pulse Gen. 4           */
306 
#pragma intvect DefaultIRQHandler 117   /* Prog. Pulse Gen. 5           */
307 
#pragma intvect DefaultIRQHandler 118   /* Prog. Pulse Gen. 6           */
308 
#pragma intvect DefaultIRQHandler 119   /* Prog. Pulse Gen. 7           */
309 
#pragma intvect DefaultIRQHandler 120   /* Prog. Pulse Gen. 8           */
310 
#pragma intvect DefaultIRQHandler 121   /* Prog. Pulse Gen. 9           */
311 
#pragma intvect DefaultIRQHandler 122   /* Prog. Pulse Gen. 10          */
312 
#pragma intvect DefaultIRQHandler 123   /* Prog. Pulse Gen. 11          */
313 
#pragma intvect DefaultIRQHandler 124   /* Prog. Pulse Gen. 12          */
314 
#pragma intvect DefaultIRQHandler 125   /* Prog. Pulse Gen. 13          */
315 
#pragma intvect DefaultIRQHandler 126   /* Prog. Pulse Gen. 14          */
316 
#pragma intvect DefaultIRQHandler 127   /* Prog. Pulse Gen. 15          */
317 
#pragma intvect DefaultIRQHandler 128   /* Up/Down Counter 0            */
318 
#pragma intvect DefaultIRQHandler 129   /* Up/Down Counter 1            */
319 
#pragma intvect DefaultIRQHandler 130   /* Up/Down Counter 2            */
320 
#pragma intvect DefaultIRQHandler 131   /* Up/Down Counter 3            */
321 
#pragma intvect DefaultIRQHandler 132   /* Real Time Clock                      */
322 
#pragma intvect DefaultIRQHandler 133   /* Calibration Unit                     */
323 
#pragma intvect DefaultIRQHandler 134   /* A/D Converter 0                      */
324 
#pragma intvect DefaultIRQHandler 135   /* -                                            */
325 
#pragma intvect DefaultIRQHandler 136   /* Alarm Comperator 0           */
326 
#pragma intvect DefaultIRQHandler 137   /* Alarm Comperator 1           */
327 
#pragma intvect DefaultIRQHandler 138   /* Low Volage Detector          */
328 
#pragma intvect DefaultIRQHandler 139   /* SMC Zero Point 0-5           */
329 
#pragma intvect DefaultIRQHandler 140   /* Timebase Overflow            */
330 
#pragma intvect DefaultIRQHandler 141   /* PLL Clock Gear                       */
331 
#pragma intvect DefaultIRQHandler 142   /* DMA Controller                       */
332 
#pragma intvect DefaultIRQHandler 143   /* Main/Sub OSC stability wait  */
333 
#pragma intvect 0xFFFFFFFF              144   /* Boot Sec. Vector (MB91V460A) */
334 
 
335 
/*------------------------------------------------------------------------
336 
  DefaultIRQHandler()
337 
 
338 
  This function is a placeholder for all vector definitions. Either use
339 
  your own placeholder or add necessary code here.
340 
-------------------------------------------------------------------------*/
341 
__interrupt
342 
void DefaultIRQHandler (void)
343 
{
344 
        /* RB_SYNC; */                                          /* Synchronisation with R-Bus   */
345 
                                                                                /* May be required, if there is */
346 
                                                                                /* no R-Bus access after the    */
347 
                                                                                /* reset of the interrupt flag  */
348 
 
349 
        __DI();                                                         /* disable interrupts              */
350 
        while(1)
351 
        {
352 
                Kick_Watchdog();                                /* feed hardware watchdog          */
353 
        }
354 
                                                                                /* halt system */
355 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.