URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MB91460_Softune/] [SRC/] [vectors.h] - Blame information for rev 820

Go to most recent revision | Details | Compare with Previous | View Log


/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.                                             */
/*                 (C) Fujitsu Microelectronics Europe GmbH                  */
/*----------------------------------------------------------------------------
  VECTORS.h
 
 
  06.10.06  1.00   UMa    Initial Version
-----------------------------------------------------------------------------*/
 
#ifndef VECTORS_H
#define VECTORS_H
 
void InitIrqLevels( void );
 
#endif
 

Line No.	Rev	Author	Line
1	584	jeremybenn	`/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */`
2			`/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */`
3			`/* ELIGIBILITY FOR ANY PURPOSES. */`
4			`/* (C) Fujitsu Microelectronics Europe GmbH */`
5			`/*----------------------------------------------------------------------------`
6			`VECTORS.h`
7
8
9			`06.10.06 1.00 UMa Initial Version`
10			`-----------------------------------------------------------------------------*/`
11
12			`#ifndef VECTORS_H`
13			`#define VECTORS_H`
14
15			`void InitIrqLevels( void );`
16
17			`#endif`
18

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MB91460_Softune/] [SRC/] [vectors.h] - Blame information for rev 820